Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	204	1			T1	1		T18	1		T5	1
index[0x1]	189	1			T1	4		T6	1		T43	1
index[0x2]	199	1			T18	1		T5	2		T48	1
index[0x3]	175	1			T5	7		T11	1		T68	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	217	1			T1	1		T18	2		T19	1
lens_less_than_1000[1]	136	1			T1	1		T6	1		T50	1
lens_less_than_1000[2]	128	1			T1	2		T5	1		T34	1
lens_less_than_1000[3]	92	1			T5	5		T38	1		T69	1
lens_less_than_1000[4]	58	1			T1	1		T5	1		T48	1
lens_less_than_1000[5]	49	1			T5	1		T43	1		T35	1
lens_less_than_1000[6]	39	1			T5	1		T295	1		T296	1
lens_less_than_1000[7]	14	1			T72	1		T77	1		T297	1
lens_less_than_1000[8]	15	1			T5	1		T24	3		T56	1
lens_less_than_1000[9]	6	1			T85	1		T298	1		T299	3
len_2	13	1			T68	1		T24	1		T132	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	63	1			T18	1		T19	1		T11	1
index[0x0]	lens_less_than_1000[1]	40	1			T1	1		T52	1		T36	1
index[0x0]	lens_less_than_1000[2]	32	1			T106	1		T123	1		T25	2
index[0x0]	lens_less_than_1000[3]	26	1			T261	1		T54	1		T56	1
index[0x0]	lens_less_than_1000[4]	16	1			T5	1		T51	1		T24	1
index[0x0]	lens_less_than_1000[5]	8	1			T300	1		T59	1		T113	1
index[0x0]	lens_less_than_1000[6]	9	1			T301	1		T302	1		T105	6
index[0x0]	lens_less_than_1000[7]	4	1			T72	1		T77	1		T205	1
index[0x0]	lens_less_than_1000[8]	4	1			T24	1		T270	1		T105	1
index[0x0]	len_2	2	1			T303	1		T121	1		-	-
index[0x1]	lens_less_than_1000[0]	52	1			T1	1		T52	1		T34	1
index[0x1]	lens_less_than_1000[1]	34	1			T6	1		T50	1		T106	1
index[0x1]	lens_less_than_1000[2]	31	1			T1	2		T38	1		T40	2
index[0x1]	lens_less_than_1000[3]	19	1			T73	1		T92	1		T268	1
index[0x1]	lens_less_than_1000[4]	17	1			T1	1		T24	1		T77	1
index[0x1]	lens_less_than_1000[5]	17	1			T43	1		T35	1		T112	1
index[0x1]	lens_less_than_1000[6]	7	1			T295	1		T296	1		T304	1
index[0x1]	lens_less_than_1000[7]	3	1			T58	2		T305	1		-	-
index[0x1]	lens_less_than_1000[8]	5	1			T24	1		T306	1		T307	1
index[0x1]	lens_less_than_1000[9]	3	1			T85	1		T299	2		-	-
index[0x1]	len_2	1	1			T132	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	52	1			T18	1		T28	1		T68	1
index[0x2]	lens_less_than_1000[1]	30	1			T34	1		T77	1		T308	1
index[0x2]	lens_less_than_1000[2]	41	1			T35	1		T74	1		T272	1
index[0x2]	lens_less_than_1000[3]	26	1			T38	1		T69	1		T54	1
index[0x2]	lens_less_than_1000[4]	11	1			T48	1		T309	1		T281	1
index[0x2]	lens_less_than_1000[5]	15	1			T5	1		T40	1		T259	2
index[0x2]	lens_less_than_1000[6]	12	1			T5	1		T58	3		T310	1
index[0x2]	lens_less_than_1000[7]	1	1			T86	1		-	-		-	-
index[0x2]	lens_less_than_1000[8]	4	1			T56	1		T311	1		T312	1
index[0x2]	lens_less_than_1000[9]	1	1			T283	1		-	-		-	-
index[0x2]	len_2	6	1			T68	1		T24	1		T132	1
index[0x3]	lens_less_than_1000[0]	50	1			T11	1		T68	2		T34	1
index[0x3]	lens_less_than_1000[1]	32	1			T108	1		T240	1		T79	2
index[0x3]	lens_less_than_1000[2]	24	1			T5	1		T34	1		T80	1
index[0x3]	lens_less_than_1000[3]	21	1			T5	5		T313	1		T281	1
index[0x3]	lens_less_than_1000[4]	14	1			T278	1		T89	1		T314	1
index[0x3]	lens_less_than_1000[5]	9	1			T29	3		T269	1		T315	1
index[0x3]	lens_less_than_1000[6]	11	1			T272	1		T86	1		T316	1
index[0x3]	lens_less_than_1000[7]	6	1			T297	1		T317	1		T64	1
index[0x3]	lens_less_than_1000[8]	2	1			T5	1		T24	1		-	-
index[0x3]	lens_less_than_1000[9]	2	1			T298	1		T299	1		-	-
index[0x3]	len_2	4	1			T303	2		T318	1		T121	1