Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T1	2		T3	1		T5	4
class_index[0x1]	47	1			T4	1		T35	1		T72	1
class_index[0x2]	70	1			T5	1		T66	1		T69	1
class_index[0x3]	41	1			T1	1		T4	1		T68	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	90	1			T3	1		T4	2		T69	1
intr_timeout_cnt[1]	57	1			T72	2		T79	1		T124	2
intr_timeout_cnt[2]	18	1			T1	1		T5	4		T74	1
intr_timeout_cnt[3]	10	1			T66	1		T83	1		T130	1
intr_timeout_cnt[4]	10	1			T30	1		T84	1		T282	3
intr_timeout_cnt[5]	9	1			T1	2		T82	1		T88	1
intr_timeout_cnt[6]	12	1			T5	1		T130	1		T115	1
intr_timeout_cnt[7]	7	1			T35	1		T78	1		T80	1
intr_timeout_cnt[8]	6	1			T68	1		T54	2		T277	1
intr_timeout_cnt[9]	1	1			T283	1		-	-		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	18	1			T3	1		T77	2		T81	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T72	2		T27	1		T284	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T5	4		T246	1		T118	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T285	1		T286	1		T263	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T84	1		T282	3		T287	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T1	2		T82	1		T121	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T130	1		T288	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T78	1		T83	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T277	1		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	28	1			T4	1		T72	1		T74	1
class_index[0x1]	intr_timeout_cnt[1]	8	1			T79	1		T84	2		T286	1
class_index[0x1]	intr_timeout_cnt[2]	3	1			T58	1		T131	1		T263	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T83	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T88	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T289	1		T290	2		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T35	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T54	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T283	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	28	1			T69	1		T73	1		T78	1
class_index[0x2]	intr_timeout_cnt[1]	19	1			T25	2		T57	1		T26	5
class_index[0x2]	intr_timeout_cnt[2]	4	1			T25	1		T130	1		T198	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T66	1		T86	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	3	1			T30	1		T291	1		T292	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T62	1		T293	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	6	1			T5	1		T115	1		T62	4
class_index[0x2]	intr_timeout_cnt[7]	4	1			T80	1		T82	1		T287	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T54	1		T262	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	16	1			T4	1		T25	1		T56	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T124	2		T54	1		T131	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T1	1		T74	1		T288	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T130	1		T285	1		T246	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T104	1		T118	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T294	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T94	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T68	1		-	-		-	-