Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	348017	1			T1	1815		T2	9		T3	35
all_values[1]	348017	1			T1	1815		T2	9		T3	35
all_values[2]	348017	1			T1	1815		T2	9		T3	35
all_values[3]	348017	1			T1	1815		T2	9		T3	35

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692265

1

T1

3564

T2

12

T3

67

auto[1]

699803

1

T1

3696

T2

24

T3

73

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

822518

1

T1

4261

T2

21

T3

130

auto[1]

569550

1

T1

2999

T2

15

T3

10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	101203	1			T1	529		T2	3		T3	12
all_values[0]	auto[0]	auto[1]	71911	1			T1	339		T2	1		T3	7
all_values[0]	auto[1]	auto[0]	102712	1			T1	554		T2	3		T3	13
all_values[0]	auto[1]	auto[1]	72191	1			T1	393		T2	2		T3	3
all_values[1]	auto[0]	auto[0]	102075	1			T1	519		T2	2		T3	17
all_values[1]	auto[0]	auto[1]	70915	1			T1	404		T2	2		T4	39
all_values[1]	auto[1]	auto[0]	103939	1			T1	501		T2	3		T3	18
all_values[1]	auto[1]	auto[1]	71088	1			T1	391		T2	2		T6	2
all_values[2]	auto[0]	auto[0]	102368	1			T1	536		T2	1		T3	16
all_values[2]	auto[0]	auto[1]	70114	1			T1	337		T2	1		T4	44
all_values[2]	auto[1]	auto[0]	104925	1			T1	587		T2	4		T3	19
all_values[2]	auto[1]	auto[1]	70610	1			T1	355		T2	3		T6	9
all_values[3]	auto[0]	auto[0]	102106	1			T1	506		T2	1		T3	15
all_values[3]	auto[0]	auto[1]	71573	1			T1	394		T2	1		T4	39
all_values[3]	auto[1]	auto[0]	103190	1			T1	529		T2	4		T3	20
all_values[3]	auto[1]	auto[1]	71148	1			T1	386		T2	3		T6	11