Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	348017	1			T1	1815		T2	9		T3	35
all_pins[1]	348017	1			T1	1815		T2	9		T3	35
all_pins[2]	348017	1			T1	1815		T2	9		T3	35
all_pins[3]	348017	1			T1	1815		T2	9		T3	35

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1107031	1			T1	5735		T2	26		T3	137
values[0x1]	285037	1			T1	1525		T2	10		T3	3
transitions[0x0=>0x1]	188458	1			T1	1030		T2	5		T3	3
transitions[0x1=>0x0]	188698	1			T1	1030		T2	5		T3	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	275826	1			T1	1422		T2	7		T3	32
all_pins[0]	values[0x1]	72191	1			T1	393		T2	2		T3	3
all_pins[0]	transitions[0x0=>0x1]	71586	1			T1	391		T2	2		T3	3
all_pins[0]	transitions[0x1=>0x0]	70783	1			T1	384		T2	3		T6	11
all_pins[1]	values[0x0]	276929	1			T1	1424		T2	7		T3	35
all_pins[1]	values[0x1]	71088	1			T1	391		T2	2		T6	2
all_pins[1]	transitions[0x0=>0x1]	39552	1			T1	232		T2	1		T6	2
all_pins[1]	transitions[0x1=>0x0]	40655	1			T1	234		T2	1		T3	3
all_pins[2]	values[0x0]	277407	1			T1	1460		T2	6		T3	35
all_pins[2]	values[0x1]	70610	1			T1	355		T2	3		T6	9
all_pins[2]	transitions[0x0=>0x1]	38404	1			T1	181		T2	1		T6	9
all_pins[2]	transitions[0x1=>0x0]	38882	1			T1	217		T6	2		T4	23
all_pins[3]	values[0x0]	276869	1			T1	1429		T2	6		T3	35
all_pins[3]	values[0x1]	71148	1			T1	386		T2	3		T6	11
all_pins[3]	transitions[0x0=>0x1]	38916	1			T1	226		T2	1		T6	11
all_pins[3]	transitions[0x1=>0x0]	38378	1			T1	195		T2	1		T6	9