Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	96020	1			T1	109		T15	568		T16	937
accum_cnt_1000	237110	1			T1	1230		T5	67		T11	1818
accum_cnt_100	25523	1			T1	169		T18	1		T5	106
accum_cnt_50	59542	1			T1	686		T4	170		T18	1
accum_cnt_10	180194	1			T1	935		T2	13		T3	27
accum_cnt_0	390446	1			T1	1580		T2	19		T3	85

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	256828	1			T1	1312		T2	8		T3	28
class_index[0x1]	256828	1			T1	1312		T2	8		T3	28
class_index[0x2]	256828	1			T1	1312		T2	8		T3	28
class_index[0x3]	256828	1			T1	1312		T2	8		T3	28

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22626	1			T16	270		T28	69		T38	509
class_index[0x0]	accum_cnt_1000	60989	1			T1	915		T5	50		T16	560
class_index[0x0]	accum_cnt_100	7077	1			T1	120		T5	52		T19	9
class_index[0x0]	accum_cnt_50	15812	1			T1	176		T4	26		T5	56
class_index[0x0]	accum_cnt_10	51877	1			T1	52		T3	27		T6	26
class_index[0x0]	accum_cnt_0	86859	1			T1	49		T2	8		T3	1
class_index[0x1]	accum_cnt_2000	23984	1			T1	109		T15	384		T16	371
class_index[0x1]	accum_cnt_1000	54538	1			T1	182		T11	985		T15	339
class_index[0x1]	accum_cnt_100	5337	1			T1	33		T5	17		T11	80
class_index[0x1]	accum_cnt_50	18009	1			T1	149		T4	78		T5	14
class_index[0x1]	accum_cnt_10	40972	1			T1	18		T2	1		T4	25
class_index[0x1]	accum_cnt_0	107786	1			T1	282		T2	7		T3	28
class_index[0x2]	accum_cnt_2000	27589	1			T15	34		T16	296		T29	437
class_index[0x2]	accum_cnt_1000	64576	1			T1	133		T5	14		T15	707
class_index[0x2]	accum_cnt_100	6289	1			T1	16		T18	1		T5	27
class_index[0x2]	accum_cnt_50	13686	1			T1	153		T4	20		T18	1
class_index[0x2]	accum_cnt_10	41298	1			T1	837		T2	6		T6	22
class_index[0x2]	accum_cnt_0	95845	1			T1	173		T2	2		T3	28
class_index[0x3]	accum_cnt_2000	21821	1			T15	150		T34	70		T261	85
class_index[0x3]	accum_cnt_1000	57007	1			T5	3		T11	833		T15	636
class_index[0x3]	accum_cnt_100	6820	1			T5	10		T11	152		T15	26
class_index[0x3]	accum_cnt_50	12035	1			T1	208		T4	46		T5	14
class_index[0x3]	accum_cnt_10	46047	1			T1	28		T2	6		T4	18
class_index[0x3]	accum_cnt_0	99956	1			T1	1076		T2	2		T3	28