Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8675	1			T1	17		T5	114		T34	169
alert[0x1]	8049	1			T1	5		T7	1		T34	382
alert[0x2]	6817	1			T1	894		T19	1		T34	24
alert[0x3]	5503	1			T1	18		T7	1		T68	4
alert[0x4]	3507	1			T1	271		T5	372		T19	9
alert[0x5]	7699	1			T1	102		T12	1		T77	92
alert[0x6]	5857	1			T1	775		T6	1		T7	1
alert[0x7]	11190	1			T1	1		T6	2		T49	1
alert[0x8]	5807	1			T34	2		T259	15		T107	2
alert[0x9]	4231	1			T19	35		T36	1		T129	26
alert[0xa]	8332	1			T19	1		T53	4		T77	43
alert[0xb]	9688	1			T1	338		T7	1		T5	5
alert[0xc]	5884	1			T1	7		T12	1		T53	1
alert[0xd]	12100	1			T36	7		T129	6		T295	1
alert[0xe]	4141	1			T19	9		T34	65		T12	1
alert[0xf]	3602	1			T1	26		T129	9		T92	12
alert[0x10]	2409	1			T7	1		T259	2		T129	208
alert[0x11]	6295	1			T1	5		T6	1		T34	334
alert[0x12]	6892	1			T1	105		T7	2		T68	2
alert[0x13]	8769	1			T7	1		T5	14		T12	1
alert[0x14]	15363	1			T1	1		T7	1		T12	1
alert[0x15]	12687	1			T1	674		T46	1		T34	49
alert[0x16]	6645	1			T1	27		T6	2		T34	11
alert[0x17]	6830	1			T1	690		T129	52		T77	22
alert[0x18]	11515	1			T1	544		T7	1		T259	1
alert[0x19]	16675	1			T1	63		T52	2		T34	49
alert[0x1a]	6324	1			T5	151		T259	2		T77	315
alert[0x1b]	6153	1			T6	1		T5	103		T36	5
alert[0x1c]	11670	1			T1	5		T7	1		T34	5
alert[0x1d]	7812	1			T1	5		T6	1		T49	1
alert[0x1e]	6666	1			T34	209		T321	1		T259	1
alert[0x1f]	4454	1			T5	48		T53	10		T129	11
alert[0x20]	7820	1			T11	1		T34	49		T126	12
alert[0x21]	6405	1			T66	1		T42	1		T321	1
alert[0x22]	7043	1			T1	1		T12	1		T53	1
alert[0x23]	10039	1			T7	1		T5	50		T80	2
alert[0x24]	10234	1			T1	5		T6	1		T5	211
alert[0x25]	9479	1			T36	3		T12	1		T259	23
alert[0x26]	11865	1			T1	10		T7	1		T5	864
alert[0x27]	5819	1			T7	1		T19	15		T34	1
alert[0x28]	5673	1			T1	5		T36	20		T259	3
alert[0x29]	8627	1			T1	246		T6	1		T38	2
alert[0x2a]	11288	1			T19	2		T34	48		T129	237
alert[0x2b]	7642	1			T6	1		T53	1		T129	653
alert[0x2c]	5860	1			T321	2		T80	3		T25	11
alert[0x2d]	3014	1			T49	1		T259	5		T295	1
alert[0x2e]	18398	1			T7	1		T19	1		T68	1
alert[0x2f]	4827	1			T1	7		T68	5		T34	70
alert[0x30]	9202	1			T6	1		T5	49		T34	276
alert[0x31]	6390	1			T1	1167		T259	8		T129	1302
alert[0x32]	3566	1			T7	1		T259	2		T53	3
alert[0x33]	5141	1			T5	99		T34	8		T30	44
alert[0x34]	7163	1			T1	1916		T19	2		T36	1
alert[0x35]	20477	1			T1	148		T5	818		T19	20
alert[0x36]	7203	1			T6	1		T5	99		T53	6
alert[0x37]	4375	1			T1	81		T5	51		T12	1
alert[0x38]	9174	1			T1	17		T36	2		T12	1
alert[0x39]	9571	1			T36	20		T129	42		T77	471
alert[0x3a]	4509	1			T19	6		T12	1		T77	9
alert[0x3b]	7644	1			T7	1		T34	108		T36	1
alert[0x3c]	3557	1			T36	1		T129	6		T77	130
alert[0x3d]	6791	1			T66	10		T34	2		T12	1
alert[0x3e]	6865	1			T129	40		T77	376		T125	1
alert[0x3f]	5596	1			T5	147		T36	9		T321	1
alert[0x40]	5912	1			T1	22		T34	1		T36	26

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	161616	1			T1	7		T6	1		T7	17
class_i[0x1]	148156	1			T1	7232		T6	2		T5	3195
class_i[0x2]	77284	1			T1	934		T6	9		T11	1
class_i[0x3]	118354	1			T1	25		T6	1		T34	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

504640

1

T1

8198

T5

3195

T19

103

alert_ping_fail

770

1

T6

13

T7

17

T11

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8658	1			T1	17		T5	114		T34	169
alert_integrity_fail	alert[0x1]	8040	1			T1	5		T34	382		T53	1
alert_integrity_fail	alert[0x2]	6806	1			T1	894		T19	1		T34	24
alert_integrity_fail	alert[0x3]	5492	1			T1	18		T68	4		T52	1
alert_integrity_fail	alert[0x4]	3491	1			T1	271		T5	372		T19	9
alert_integrity_fail	alert[0x5]	7685	1			T1	102		T77	92		T92	20
alert_integrity_fail	alert[0x6]	5844	1			T1	775		T46	1		T129	5
alert_integrity_fail	alert[0x7]	11172	1			T1	1		T129	28		T77	1343
alert_integrity_fail	alert[0x8]	5781	1			T34	2		T259	15		T129	12
alert_integrity_fail	alert[0x9]	4213	1			T19	35		T36	1		T129	26
alert_integrity_fail	alert[0xa]	8320	1			T19	1		T53	4		T77	43
alert_integrity_fail	alert[0xb]	9677	1			T1	338		T5	5		T19	2
alert_integrity_fail	alert[0xc]	5876	1			T1	7		T53	1		T129	10
alert_integrity_fail	alert[0xd]	12089	1			T36	7		T129	6		T77	110
alert_integrity_fail	alert[0xe]	4136	1			T19	9		T34	65		T53	6
alert_integrity_fail	alert[0xf]	3592	1			T1	26		T129	9		T92	12
alert_integrity_fail	alert[0x10]	2395	1			T259	2		T129	208		T77	1
alert_integrity_fail	alert[0x11]	6283	1			T1	5		T34	334		T259	4
alert_integrity_fail	alert[0x12]	6877	1			T1	105		T68	2		T36	17
alert_integrity_fail	alert[0x13]	8751	1			T5	14		T129	82		T77	12
alert_integrity_fail	alert[0x14]	15349	1			T1	1		T129	34		T77	11
alert_integrity_fail	alert[0x15]	12678	1			T1	674		T46	1		T34	49
alert_integrity_fail	alert[0x16]	6627	1			T1	27		T34	11		T30	1
alert_integrity_fail	alert[0x17]	6816	1			T1	690		T129	52		T77	22
alert_integrity_fail	alert[0x18]	11507	1			T1	544		T259	1		T30	3
alert_integrity_fail	alert[0x19]	16662	1			T1	63		T52	2		T34	49
alert_integrity_fail	alert[0x1a]	6314	1			T5	151		T259	2		T77	315
alert_integrity_fail	alert[0x1b]	6141	1			T5	103		T36	5		T30	1
alert_integrity_fail	alert[0x1c]	11654	1			T1	5		T34	5		T259	5
alert_integrity_fail	alert[0x1d]	7803	1			T1	5		T34	68		T53	5
alert_integrity_fail	alert[0x1e]	6653	1			T34	209		T259	1		T129	441
alert_integrity_fail	alert[0x1f]	4434	1			T5	48		T53	10		T129	11
alert_integrity_fail	alert[0x20]	7807	1			T34	49		T126	12		T25	7
alert_integrity_fail	alert[0x21]	6394	1			T66	1		T259	11		T92	204
alert_integrity_fail	alert[0x22]	7028	1			T1	1		T53	1		T30	3
alert_integrity_fail	alert[0x23]	10030	1			T5	50		T80	2		T92	975
alert_integrity_fail	alert[0x24]	10225	1			T1	5		T5	211		T68	1
alert_integrity_fail	alert[0x25]	9473	1			T36	3		T259	23		T53	1
alert_integrity_fail	alert[0x26]	11846	1			T1	10		T5	864		T52	1
alert_integrity_fail	alert[0x27]	5805	1			T19	15		T34	1		T129	12
alert_integrity_fail	alert[0x28]	5663	1			T1	5		T36	20		T259	3
alert_integrity_fail	alert[0x29]	8613	1			T1	246		T38	2		T53	2
alert_integrity_fail	alert[0x2a]	11278	1			T19	2		T34	48		T129	237
alert_integrity_fail	alert[0x2b]	7633	1			T53	1		T129	653		T92	297
alert_integrity_fail	alert[0x2c]	5846	1			T80	3		T25	11		T99	89
alert_integrity_fail	alert[0x2d]	2997	1			T259	5		T126	628		T25	368
alert_integrity_fail	alert[0x2e]	18391	1			T19	1		T68	1		T34	26
alert_integrity_fail	alert[0x2f]	4813	1			T1	7		T68	5		T34	70
alert_integrity_fail	alert[0x30]	9189	1			T5	49		T34	276		T77	80
alert_integrity_fail	alert[0x31]	6377	1			T1	1167		T259	8		T129	1302
alert_integrity_fail	alert[0x32]	3553	1			T259	2		T53	3		T92	97
alert_integrity_fail	alert[0x33]	5131	1			T5	99		T34	8		T30	44
alert_integrity_fail	alert[0x34]	7153	1			T1	1916		T19	2		T36	1
alert_integrity_fail	alert[0x35]	20469	1			T1	148		T5	818		T19	20
alert_integrity_fail	alert[0x36]	7193	1			T5	99		T53	6		T77	1472
alert_integrity_fail	alert[0x37]	4367	1			T1	81		T5	51		T129	158
alert_integrity_fail	alert[0x38]	9164	1			T1	17		T36	2		T126	104
alert_integrity_fail	alert[0x39]	9563	1			T36	20		T129	42		T77	471
alert_integrity_fail	alert[0x3a]	4501	1			T19	6		T77	9		T112	4
alert_integrity_fail	alert[0x3b]	7636	1			T34	108		T36	1		T53	29
alert_integrity_fail	alert[0x3c]	3546	1			T36	1		T129	6		T77	130
alert_integrity_fail	alert[0x3d]	6784	1			T66	10		T34	2		T129	11
alert_integrity_fail	alert[0x3e]	6861	1			T129	40		T77	376		T25	559
alert_integrity_fail	alert[0x3f]	5589	1			T5	147		T36	9		T30	2
alert_integrity_fail	alert[0x40]	5906	1			T1	22		T34	1		T36	26
alert_ping_fail	alert[0x0]	17	1			T106	1		T295	1		T125	2
alert_ping_fail	alert[0x1]	9	1			T7	1		T306	1		T322	1
alert_ping_fail	alert[0x2]	11	1			T125	1		T323	2		T254	1
alert_ping_fail	alert[0x3]	11	1			T7	1		T123	2		T324	1
alert_ping_fail	alert[0x4]	16	1			T12	1		T125	2		T325	2
alert_ping_fail	alert[0x5]	14	1			T12	1		T297	1		T326	1
alert_ping_fail	alert[0x6]	13	1			T6	1		T7	1		T324	1
alert_ping_fail	alert[0x7]	18	1			T6	2		T49	1		T321	1
alert_ping_fail	alert[0x8]	26	1			T107	2		T295	1		T125	2
alert_ping_fail	alert[0x9]	18	1			T325	1		T306	2		T322	1
alert_ping_fail	alert[0xa]	12	1			T323	1		T327	1		T328	1
alert_ping_fail	alert[0xb]	11	1			T7	1		T12	1		T325	1
alert_ping_fail	alert[0xc]	8	1			T12	1		T329	2		T330	2
alert_ping_fail	alert[0xd]	11	1			T295	1		T267	1		T331	1
alert_ping_fail	alert[0xe]	5	1			T12	1		T327	1		T332	1
alert_ping_fail	alert[0xf]	10	1			T322	1		T333	1		T331	1
alert_ping_fail	alert[0x10]	14	1			T7	1		T295	1		T325	1
alert_ping_fail	alert[0x11]	12	1			T6	1		T321	2		T326	1
alert_ping_fail	alert[0x12]	15	1			T7	2		T125	1		T297	1
alert_ping_fail	alert[0x13]	18	1			T7	1		T12	1		T106	1
alert_ping_fail	alert[0x14]	14	1			T7	1		T12	1		T123	1
alert_ping_fail	alert[0x15]	9	1			T321	1		T123	1		T267	1
alert_ping_fail	alert[0x16]	18	1			T6	2		T42	1		T317	2
alert_ping_fail	alert[0x17]	14	1			T325	1		T322	2		T331	1
alert_ping_fail	alert[0x18]	8	1			T7	1		T295	1		T297	1
alert_ping_fail	alert[0x19]	13	1			T12	1		T323	1		T306	1
alert_ping_fail	alert[0x1a]	10	1			T125	1		T297	1		T329	1
alert_ping_fail	alert[0x1b]	12	1			T6	1		T12	1		T297	1
alert_ping_fail	alert[0x1c]	16	1			T7	1		T297	1		T324	1
alert_ping_fail	alert[0x1d]	9	1			T6	1		T49	1		T331	2
alert_ping_fail	alert[0x1e]	13	1			T321	1		T324	1		T254	2
alert_ping_fail	alert[0x1f]	20	1			T295	1		T334	1		T267	1
alert_ping_fail	alert[0x20]	13	1			T11	1		T297	1		T323	1
alert_ping_fail	alert[0x21]	11	1			T42	1		T321	1		T297	1
alert_ping_fail	alert[0x22]	15	1			T12	1		T306	1		T324	1
alert_ping_fail	alert[0x23]	9	1			T7	1		T322	1		T326	2
alert_ping_fail	alert[0x24]	9	1			T6	1		T12	1		T125	1
alert_ping_fail	alert[0x25]	6	1			T12	1		T297	1		T306	1
alert_ping_fail	alert[0x26]	19	1			T7	1		T321	1		T297	1
alert_ping_fail	alert[0x27]	14	1			T7	1		T326	1		T324	2
alert_ping_fail	alert[0x28]	10	1			T295	1		T306	1		T324	1
alert_ping_fail	alert[0x29]	14	1			T6	1		T12	2		T295	2
alert_ping_fail	alert[0x2a]	10	1			T267	1		T306	1		T333	1
alert_ping_fail	alert[0x2b]	9	1			T6	1		T323	1		T322	1
alert_ping_fail	alert[0x2c]	14	1			T321	2		T322	1		T335	2
alert_ping_fail	alert[0x2d]	17	1			T49	1		T295	1		T123	1
alert_ping_fail	alert[0x2e]	7	1			T7	1		T325	1		T297	1
alert_ping_fail	alert[0x2f]	14	1			T123	1		T322	1		T333	2
alert_ping_fail	alert[0x30]	13	1			T6	1		T321	1		T123	1
alert_ping_fail	alert[0x31]	13	1			T125	1		T326	1		T324	1
alert_ping_fail	alert[0x32]	13	1			T7	1		T331	1		T254	1
alert_ping_fail	alert[0x33]	10	1			T333	1		T336	1		T337	1
alert_ping_fail	alert[0x34]	10	1			T267	1		T322	1		T330	1
alert_ping_fail	alert[0x35]	8	1			T295	1		T267	1		T336	1
alert_ping_fail	alert[0x36]	10	1			T6	1		T331	1		T248	1
alert_ping_fail	alert[0x37]	8	1			T12	1		T125	1		T326	1
alert_ping_fail	alert[0x38]	10	1			T12	1		T321	1		T267	1
alert_ping_fail	alert[0x39]	8	1			T297	1		T322	1		T324	1
alert_ping_fail	alert[0x3a]	8	1			T12	1		T306	1		T324	1
alert_ping_fail	alert[0x3b]	8	1			T7	1		T321	1		T267	1
alert_ping_fail	alert[0x3c]	11	1			T331	2		T329	2		T338	1
alert_ping_fail	alert[0x3d]	7	1			T12	1		T323	1		T329	1
alert_ping_fail	alert[0x3e]	4	1			T125	1		T339	1		T340	1
alert_ping_fail	alert[0x3f]	7	1			T321	1		T295	1		T336	1
alert_ping_fail	alert[0x40]	6	1			T12	1		T306	1		T322	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	161444	1			T1	7		T19	103		T46	2
alert_integrity_fail	class_i[0x1]	147942	1			T1	7232		T5	3195		T66	10
alert_integrity_fail	class_i[0x2]	77112	1			T1	934		T66	1		T68	9
alert_integrity_fail	class_i[0x3]	118142	1			T1	25		T34	2		T36	5
alert_ping_fail	class_i[0x0]	172	1			T6	1		T7	17		T321	1
alert_ping_fail	class_i[0x1]	214	1			T6	2		T42	2		T12	1
alert_ping_fail	class_i[0x2]	172	1			T6	9		T11	1		T49	3
alert_ping_fail	class_i[0x3]	212	1			T6	1		T12	18		T321	1