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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.99 98.72 97.09 100.00 100.00 99.38 99.56


Total test records in report: 830
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T190 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3720426006 Jul 26 05:45:14 PM PDT 24 Jul 26 05:45:17 PM PDT 24 134716864 ps
T775 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3343312183 Jul 26 05:45:44 PM PDT 24 Jul 26 05:45:52 PM PDT 24 404332732 ps
T776 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2006861243 Jul 26 05:45:13 PM PDT 24 Jul 26 05:45:21 PM PDT 24 148858953 ps
T777 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.648094709 Jul 26 05:45:31 PM PDT 24 Jul 26 05:45:36 PM PDT 24 51629968 ps
T778 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1693368239 Jul 26 05:45:19 PM PDT 24 Jul 26 05:45:43 PM PDT 24 526103868 ps
T779 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1678294677 Jul 26 05:45:16 PM PDT 24 Jul 26 05:45:21 PM PDT 24 125949668 ps
T780 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2080060173 Jul 26 05:45:15 PM PDT 24 Jul 26 05:45:28 PM PDT 24 351803498 ps
T155 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3202745141 Jul 26 05:45:44 PM PDT 24 Jul 26 05:49:10 PM PDT 24 11247027044 ps
T183 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.124721808 Jul 26 05:45:35 PM PDT 24 Jul 26 05:45:39 PM PDT 24 172574764 ps
T781 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1944086252 Jul 26 05:45:31 PM PDT 24 Jul 26 05:45:40 PM PDT 24 99803501 ps
T782 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1875586215 Jul 26 05:45:44 PM PDT 24 Jul 26 05:45:46 PM PDT 24 12463628 ps
T783 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1434777595 Jul 26 05:45:45 PM PDT 24 Jul 26 05:45:47 PM PDT 24 6694549 ps
T161 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3575975414 Jul 26 05:45:39 PM PDT 24 Jul 26 05:49:15 PM PDT 24 1632897186 ps
T166 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3649185598 Jul 26 05:45:34 PM PDT 24 Jul 26 05:55:14 PM PDT 24 21088419434 ps
T169 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1818124342 Jul 26 05:45:39 PM PDT 24 Jul 26 05:55:41 PM PDT 24 42741324114 ps
T784 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3528986282 Jul 26 05:45:48 PM PDT 24 Jul 26 05:45:50 PM PDT 24 10715168 ps
T785 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2176103115 Jul 26 05:45:16 PM PDT 24 Jul 26 05:45:29 PM PDT 24 628662484 ps
T786 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2758082986 Jul 26 05:45:29 PM PDT 24 Jul 26 05:45:31 PM PDT 24 10841777 ps
T787 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1189608295 Jul 26 05:45:41 PM PDT 24 Jul 26 05:46:02 PM PDT 24 172465309 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1936572494 Jul 26 05:45:22 PM PDT 24 Jul 26 05:45:23 PM PDT 24 10131521 ps
T789 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1920052105 Jul 26 05:45:41 PM PDT 24 Jul 26 05:45:50 PM PDT 24 94326352 ps
T790 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2467367458 Jul 26 05:45:27 PM PDT 24 Jul 26 05:46:05 PM PDT 24 2535270321 ps
T791 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1251439450 Jul 26 05:45:49 PM PDT 24 Jul 26 05:45:51 PM PDT 24 6788988 ps
T792 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2584634683 Jul 26 05:45:30 PM PDT 24 Jul 26 05:45:40 PM PDT 24 253173638 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3972601010 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:21 PM PDT 24 269774638 ps
T794 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2446811770 Jul 26 05:45:47 PM PDT 24 Jul 26 05:45:50 PM PDT 24 21563987 ps
T157 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1369925941 Jul 26 05:45:14 PM PDT 24 Jul 26 05:48:49 PM PDT 24 7482262712 ps
T795 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3407234197 Jul 26 05:45:36 PM PDT 24 Jul 26 05:45:56 PM PDT 24 249267463 ps
T796 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3634355092 Jul 26 05:45:20 PM PDT 24 Jul 26 05:46:34 PM PDT 24 2155067920 ps
T797 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3576806855 Jul 26 05:45:25 PM PDT 24 Jul 26 05:45:30 PM PDT 24 107253094 ps
T184 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.744181823 Jul 26 05:45:33 PM PDT 24 Jul 26 05:46:11 PM PDT 24 326111305 ps
T798 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.120251703 Jul 26 05:45:49 PM PDT 24 Jul 26 05:45:51 PM PDT 24 7600493 ps
T799 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3608511468 Jul 26 05:45:26 PM PDT 24 Jul 26 05:45:31 PM PDT 24 222042112 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1000549513 Jul 26 05:45:16 PM PDT 24 Jul 26 05:45:23 PM PDT 24 97472744 ps
T158 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4138192529 Jul 26 05:45:09 PM PDT 24 Jul 26 06:03:50 PM PDT 24 15769164977 ps
T801 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3096369428 Jul 26 05:45:35 PM PDT 24 Jul 26 05:45:43 PM PDT 24 195514329 ps
T802 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.331443151 Jul 26 05:45:42 PM PDT 24 Jul 26 05:45:45 PM PDT 24 6473608 ps
T803 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1286468310 Jul 26 05:45:04 PM PDT 24 Jul 26 05:45:06 PM PDT 24 12287973 ps
T804 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1238592767 Jul 26 05:45:36 PM PDT 24 Jul 26 05:45:41 PM PDT 24 117525262 ps
T805 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1716836971 Jul 26 05:45:40 PM PDT 24 Jul 26 05:45:44 PM PDT 24 34112955 ps
T191 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.569989165 Jul 26 05:45:48 PM PDT 24 Jul 26 05:46:27 PM PDT 24 464350853 ps
T806 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.661177275 Jul 26 05:45:49 PM PDT 24 Jul 26 05:45:58 PM PDT 24 116294980 ps
T807 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2714452408 Jul 26 05:45:51 PM PDT 24 Jul 26 05:45:52 PM PDT 24 32697518 ps
T170 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1471167476 Jul 26 05:45:36 PM PDT 24 Jul 26 05:50:31 PM PDT 24 8246853132 ps
T808 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.108847275 Jul 26 05:45:14 PM PDT 24 Jul 26 05:45:19 PM PDT 24 198229088 ps
T809 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.206200951 Jul 26 05:45:35 PM PDT 24 Jul 26 05:45:37 PM PDT 24 10313671 ps
T180 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2207714749 Jul 26 05:45:13 PM PDT 24 Jul 26 05:45:17 PM PDT 24 54440753 ps
T810 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.986291333 Jul 26 05:45:34 PM PDT 24 Jul 26 05:46:06 PM PDT 24 2346511893 ps
T159 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3569546286 Jul 26 05:45:44 PM PDT 24 Jul 26 05:48:51 PM PDT 24 5050078351 ps
T811 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3111723175 Jul 26 05:45:34 PM PDT 24 Jul 26 05:45:39 PM PDT 24 44334640 ps
T812 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1353391122 Jul 26 05:45:38 PM PDT 24 Jul 26 05:45:59 PM PDT 24 336779248 ps
T813 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.994829341 Jul 26 05:45:31 PM PDT 24 Jul 26 05:45:44 PM PDT 24 96957485 ps
T814 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1333397828 Jul 26 05:45:46 PM PDT 24 Jul 26 05:45:48 PM PDT 24 8983585 ps
T815 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2304590402 Jul 26 05:45:38 PM PDT 24 Jul 26 05:45:46 PM PDT 24 461103621 ps
T197 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1290080816 Jul 26 05:45:38 PM PDT 24 Jul 26 05:45:42 PM PDT 24 304192953 ps
T163 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.485269268 Jul 26 05:45:47 PM PDT 24 Jul 26 06:06:14 PM PDT 24 68546322053 ps
T816 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2681496467 Jul 26 05:45:43 PM PDT 24 Jul 26 05:45:45 PM PDT 24 16881994 ps
T196 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.556049207 Jul 26 05:45:11 PM PDT 24 Jul 26 05:45:51 PM PDT 24 2377762841 ps
T369 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1879293070 Jul 26 05:45:34 PM PDT 24 Jul 26 05:53:24 PM PDT 24 28599942782 ps
T162 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2889866598 Jul 26 05:45:12 PM PDT 24 Jul 26 05:48:11 PM PDT 24 4839847517 ps
T167 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4206425016 Jul 26 05:45:30 PM PDT 24 Jul 26 05:57:21 PM PDT 24 18699996433 ps
T817 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3705174679 Jul 26 05:45:14 PM PDT 24 Jul 26 05:45:24 PM PDT 24 272332649 ps
T818 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1562965083 Jul 26 05:45:49 PM PDT 24 Jul 26 05:45:51 PM PDT 24 25534367 ps
T819 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2649375622 Jul 26 05:45:45 PM PDT 24 Jul 26 05:45:46 PM PDT 24 8734299 ps
T820 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.372278956 Jul 26 05:45:49 PM PDT 24 Jul 26 05:45:51 PM PDT 24 8353747 ps
T370 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1238348602 Jul 26 05:45:10 PM PDT 24 Jul 26 05:53:39 PM PDT 24 14113671478 ps
T821 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3607976408 Jul 26 05:45:49 PM PDT 24 Jul 26 05:45:51 PM PDT 24 11013137 ps
T822 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3865629203 Jul 26 05:45:47 PM PDT 24 Jul 26 05:46:02 PM PDT 24 294897110 ps
T823 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.411668352 Jul 26 05:45:07 PM PDT 24 Jul 26 05:48:54 PM PDT 24 12769939834 ps
T824 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3791022718 Jul 26 05:45:37 PM PDT 24 Jul 26 05:45:55 PM PDT 24 257423886 ps
T825 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.187910799 Jul 26 05:45:14 PM PDT 24 Jul 26 05:45:18 PM PDT 24 21845672 ps
T826 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3251812926 Jul 26 05:45:12 PM PDT 24 Jul 26 05:45:21 PM PDT 24 252945441 ps
T827 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2922173853 Jul 26 05:45:35 PM PDT 24 Jul 26 05:45:40 PM PDT 24 396683226 ps
T165 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2553355464 Jul 26 05:45:48 PM PDT 24 Jul 26 05:50:25 PM PDT 24 3785980581 ps
T168 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.232197033 Jul 26 05:45:26 PM PDT 24 Jul 26 05:51:18 PM PDT 24 7249440035 ps
T171 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3274897683 Jul 26 05:45:46 PM PDT 24 Jul 26 05:48:52 PM PDT 24 11292008746 ps
T828 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3262846346 Jul 26 05:45:14 PM PDT 24 Jul 26 05:45:20 PM PDT 24 478455740 ps
T829 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.604393573 Jul 26 05:45:12 PM PDT 24 Jul 26 05:47:46 PM PDT 24 1107547431 ps
T189 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2843960011 Jul 26 05:45:38 PM PDT 24 Jul 26 05:45:47 PM PDT 24 180810595 ps
T830 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.459430712 Jul 26 05:45:48 PM PDT 24 Jul 26 05:45:50 PM PDT 24 45191343 ps

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2821292244
Short name T1
Test name
Test status
Simulation time 111366475937 ps
CPU time 3654.97 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 06:05:28 PM PDT 24
Peak memory 305812 kb
Host smart-dd592f1c-4f31-496b-bc25-ed7a8a98b1af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821292244 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2821292244
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3693276691
Short name T9
Test name
Test status
Simulation time 1555669124 ps
CPU time 21.77 seconds
Started Jul 26 05:03:13 PM PDT 24
Finished Jul 26 05:03:35 PM PDT 24
Peak memory 269964 kb
Host smart-611cf579-c343-4c7e-9bd1-1b98edd7a330
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3693276691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3693276691
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.453117111
Short name T134
Test name
Test status
Simulation time 69141919351 ps
CPU time 1233.77 seconds
Started Jul 26 05:45:20 PM PDT 24
Finished Jul 26 06:05:54 PM PDT 24
Peak memory 273536 kb
Host smart-15697667-d085-4540-9120-d5a9f28e71d6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453117111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.453117111
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3719635081
Short name T17
Test name
Test status
Simulation time 3645013318 ps
CPU time 37.39 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:04:08 PM PDT 24
Peak memory 248872 kb
Host smart-127c4dbc-331b-4d32-98d7-154ba606ed17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3719635081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3719635081
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.162086451
Short name T60
Test name
Test status
Simulation time 140735332864 ps
CPU time 4768.19 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 06:22:52 PM PDT 24
Peak memory 297976 kb
Host smart-964715f7-1ca1-4598-b01b-ad5caebe3f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162086451 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.162086451
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3346036363
Short name T173
Test name
Test status
Simulation time 496155639 ps
CPU time 36.69 seconds
Started Jul 26 05:45:37 PM PDT 24
Finished Jul 26 05:46:14 PM PDT 24
Peak memory 245992 kb
Host smart-e2684cf1-a50a-451d-8dd8-d0328544cf48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3346036363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3346036363
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.183139091
Short name T56
Test name
Test status
Simulation time 144248257168 ps
CPU time 7137.11 seconds
Started Jul 26 05:04:01 PM PDT 24
Finished Jul 26 07:02:59 PM PDT 24
Peak memory 354696 kb
Host smart-4b934f8b-ed9e-4f45-a423-b295e80974c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183139091 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.183139091
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.912095555
Short name T5
Test name
Test status
Simulation time 17156464707 ps
CPU time 1349.92 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:26:15 PM PDT 24
Peak memory 289256 kb
Host smart-ede6ac33-d3e3-4e42-8cce-e8f08be798c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912095555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.912095555
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1452871791
Short name T123
Test name
Test status
Simulation time 49825605925 ps
CPU time 2630.57 seconds
Started Jul 26 05:04:35 PM PDT 24
Finished Jul 26 05:48:26 PM PDT 24
Peak memory 289444 kb
Host smart-7a73f481-d8f9-4dfe-b318-2ffc19bced36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452871791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1452871791
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1594734892
Short name T149
Test name
Test status
Simulation time 2021958893 ps
CPU time 198.28 seconds
Started Jul 26 05:45:24 PM PDT 24
Finished Jul 26 05:48:42 PM PDT 24
Peak memory 265432 kb
Host smart-b325fcbe-a46f-4300-a618-697bad1cfc91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1594734892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1594734892
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3689608408
Short name T26
Test name
Test status
Simulation time 4585584367 ps
CPU time 261.98 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:07:51 PM PDT 24
Peak memory 256972 kb
Host smart-365914f1-bf4d-46ae-97de-dec4bb91828c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689608408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3689608408
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.296324739
Short name T99
Test name
Test status
Simulation time 20960188869 ps
CPU time 1273.98 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:24:37 PM PDT 24
Peak memory 273232 kb
Host smart-fd6f4229-bbf2-4715-875a-f5e22f51be2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296324739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.296324739
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1369925941
Short name T157
Test name
Test status
Simulation time 7482262712 ps
CPU time 214.82 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:48:49 PM PDT 24
Peak memory 273116 kb
Host smart-18518795-a94b-4163-8e02-05dc5a47b4c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1369925941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1369925941
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2228736308
Short name T11
Test name
Test status
Simulation time 177969894419 ps
CPU time 2131.67 seconds
Started Jul 26 05:03:49 PM PDT 24
Finished Jul 26 05:39:21 PM PDT 24
Peak memory 284672 kb
Host smart-d4e83ba3-b606-4550-bdd4-241655ce1ba0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228736308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2228736308
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2443776382
Short name T89
Test name
Test status
Simulation time 20210617989 ps
CPU time 2020.61 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:38:03 PM PDT 24
Peak memory 298168 kb
Host smart-bce62758-56de-491a-8a1b-e9ee3eb7aab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443776382 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2443776382
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1087612873
Short name T143
Test name
Test status
Simulation time 15180770356 ps
CPU time 1072.7 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 06:03:40 PM PDT 24
Peak memory 266452 kb
Host smart-9899a293-5751-4b78-a4a3-6e8a8045a85a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087612873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1087612873
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1572641287
Short name T297
Test name
Test status
Simulation time 10166598496 ps
CPU time 436.19 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:10:59 PM PDT 24
Peak memory 248780 kb
Host smart-b4dbec3a-5262-440b-8c30-1e31a9be7979
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572641287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1572641287
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1026028360
Short name T175
Test name
Test status
Simulation time 20124280 ps
CPU time 1.45 seconds
Started Jul 26 05:45:46 PM PDT 24
Finished Jul 26 05:45:47 PM PDT 24
Peak memory 236480 kb
Host smart-8b61c9df-6153-4cbb-aaf0-35659f3280fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1026028360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1026028360
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3825860434
Short name T77
Test name
Test status
Simulation time 110689112353 ps
CPU time 1987.46 seconds
Started Jul 26 05:03:08 PM PDT 24
Finished Jul 26 05:36:15 PM PDT 24
Peak memory 286364 kb
Host smart-1b823897-740a-41e0-8045-38962dfb30fc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825860434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3825860434
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2484565719
Short name T142
Test name
Test status
Simulation time 12270626729 ps
CPU time 929.15 seconds
Started Jul 26 05:45:26 PM PDT 24
Finished Jul 26 06:00:56 PM PDT 24
Peak memory 273396 kb
Host smart-329468f0-0f6e-4967-9d29-6ba0963e18fc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484565719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2484565719
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1045906125
Short name T272
Test name
Test status
Simulation time 145394871081 ps
CPU time 2235.35 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:41:01 PM PDT 24
Peak memory 272672 kb
Host smart-b3bb3647-7fb4-4c4c-8d1a-91855e12433d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045906125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1045906125
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1295866507
Short name T144
Test name
Test status
Simulation time 121027222982 ps
CPU time 1051.76 seconds
Started Jul 26 05:45:34 PM PDT 24
Finished Jul 26 06:03:06 PM PDT 24
Peak memory 265328 kb
Host smart-ef008c2a-8c4a-4e17-8d1d-08202ffcf389
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295866507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1295866507
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.738826339
Short name T331
Test name
Test status
Simulation time 37973838615 ps
CPU time 723.97 seconds
Started Jul 26 05:03:49 PM PDT 24
Finished Jul 26 05:15:53 PM PDT 24
Peak memory 255888 kb
Host smart-f9dd9f16-daec-4fbe-adc3-b02d1f87c3d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738826339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.738826339
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2089169235
Short name T106
Test name
Test status
Simulation time 161061717024 ps
CPU time 2365.24 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 285264 kb
Host smart-a36e5df5-918a-4933-855d-e86b65eb3159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089169235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2089169235
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3400406903
Short name T160
Test name
Test status
Simulation time 4206101883 ps
CPU time 322.27 seconds
Started Jul 26 05:45:32 PM PDT 24
Finished Jul 26 05:50:55 PM PDT 24
Peak memory 272032 kb
Host smart-d1589fac-7959-4d94-966b-d99685f2a647
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3400406903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3400406903
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1057024986
Short name T34
Test name
Test status
Simulation time 27305787254 ps
CPU time 1799.19 seconds
Started Jul 26 05:04:44 PM PDT 24
Finished Jul 26 05:34:43 PM PDT 24
Peak memory 283660 kb
Host smart-963e9d3e-a588-4aca-90ac-ff865cd6c1cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057024986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1057024986
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2262017179
Short name T12
Test name
Test status
Simulation time 12530025439 ps
CPU time 489.43 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:11:55 PM PDT 24
Peak memory 248836 kb
Host smart-daddc823-23d7-4030-acce-55fd725e6736
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262017179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2262017179
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2878722202
Short name T54
Test name
Test status
Simulation time 13255376849 ps
CPU time 154.99 seconds
Started Jul 26 05:04:52 PM PDT 24
Finished Jul 26 05:07:27 PM PDT 24
Peak memory 257108 kb
Host smart-e2c160b6-f32d-4dfc-8925-082baba79efb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878722202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2878722202
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.783423414
Short name T328
Test name
Test status
Simulation time 46459671105 ps
CPU time 2070.06 seconds
Started Jul 26 05:04:27 PM PDT 24
Finished Jul 26 05:38:58 PM PDT 24
Peak memory 284724 kb
Host smart-00da3a0d-0119-4513-a037-d80419664994
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783423414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.783423414
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2446819591
Short name T510
Test name
Test status
Simulation time 49431431202 ps
CPU time 513.29 seconds
Started Jul 26 05:03:00 PM PDT 24
Finished Jul 26 05:11:34 PM PDT 24
Peak memory 255788 kb
Host smart-08cd907f-3fbc-4290-a0ae-af7719a8b215
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446819591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2446819591
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.124359990
Short name T105
Test name
Test status
Simulation time 31563409870 ps
CPU time 1535.67 seconds
Started Jul 26 05:04:02 PM PDT 24
Finished Jul 26 05:29:38 PM PDT 24
Peak memory 289848 kb
Host smart-15b06d7e-949f-4f20-8624-1d39b60a6c67
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124359990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.124359990
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1471167476
Short name T170
Test name
Test status
Simulation time 8246853132 ps
CPU time 294.5 seconds
Started Jul 26 05:45:36 PM PDT 24
Finished Jul 26 05:50:31 PM PDT 24
Peak memory 265348 kb
Host smart-741ffa5b-b0c3-40cc-979b-59415fdd7eb9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471167476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1471167476
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3247355986
Short name T573
Test name
Test status
Simulation time 49370087160 ps
CPU time 1346.37 seconds
Started Jul 26 05:03:26 PM PDT 24
Finished Jul 26 05:25:52 PM PDT 24
Peak memory 273020 kb
Host smart-1c708caa-5ca9-4f69-bcfe-5915608d636b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247355986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3247355986
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.4111966006
Short name T83
Test name
Test status
Simulation time 38223730729 ps
CPU time 1304.98 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:25:10 PM PDT 24
Peak memory 289452 kb
Host smart-5615be82-846f-49bb-84c5-42710597d496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111966006 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.4111966006
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4206425016
Short name T167
Test name
Test status
Simulation time 18699996433 ps
CPU time 710.51 seconds
Started Jul 26 05:45:30 PM PDT 24
Finished Jul 26 05:57:21 PM PDT 24
Peak memory 265404 kb
Host smart-d821ba96-33df-4107-b5c7-964cf915b5eb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206425016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.4206425016
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2479342128
Short name T683
Test name
Test status
Simulation time 13862627519 ps
CPU time 550.48 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:12:55 PM PDT 24
Peak memory 257036 kb
Host smart-9587a661-0d39-492c-8f13-9fb8e74e23bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479342128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2479342128
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1735097068
Short name T350
Test name
Test status
Simulation time 118848354541 ps
CPU time 3441.38 seconds
Started Jul 26 05:04:24 PM PDT 24
Finished Jul 26 06:01:46 PM PDT 24
Peak memory 288904 kb
Host smart-9f5c38b2-2c05-439c-8bf2-76fb2d3f7d38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735097068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1735097068
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.124721808
Short name T183
Test name
Test status
Simulation time 172574764 ps
CPU time 3.8 seconds
Started Jul 26 05:45:35 PM PDT 24
Finished Jul 26 05:45:39 PM PDT 24
Peak memory 237496 kb
Host smart-ac956292-042e-43b9-886d-c0a18c66ac69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=124721808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.124721808
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1438214193
Short name T148
Test name
Test status
Simulation time 18226457307 ps
CPU time 506.28 seconds
Started Jul 26 05:45:16 PM PDT 24
Finished Jul 26 05:53:42 PM PDT 24
Peak memory 269144 kb
Host smart-f1aac239-b843-4169-a7a3-aaf1a7f91168
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438214193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1438214193
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.981456040
Short name T303
Test name
Test status
Simulation time 29766569022 ps
CPU time 1055.4 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:21:02 PM PDT 24
Peak memory 283916 kb
Host smart-736b0a0f-f452-487e-ab30-6381baaa2d0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981456040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.981456040
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4042803267
Short name T283
Test name
Test status
Simulation time 939912184 ps
CPU time 28.35 seconds
Started Jul 26 05:04:14 PM PDT 24
Finished Jul 26 05:04:42 PM PDT 24
Peak memory 255968 kb
Host smart-08304507-b2f0-4620-a4d9-a4d43abdfca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40428
03267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4042803267
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2169237150
Short name T31
Test name
Test status
Simulation time 209758073651 ps
CPU time 2885.59 seconds
Started Jul 26 05:21:46 PM PDT 24
Finished Jul 26 06:09:52 PM PDT 24
Peak memory 289004 kb
Host smart-4c6ca66f-c16b-4cc2-814c-17256ca51329
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169237150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2169237150
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3575975414
Short name T161
Test name
Test status
Simulation time 1632897186 ps
CPU time 215.92 seconds
Started Jul 26 05:45:39 PM PDT 24
Finished Jul 26 05:49:15 PM PDT 24
Peak memory 273044 kb
Host smart-6213b22c-2c56-450f-934c-7fcc922a7575
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3575975414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3575975414
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.860322376
Short name T742
Test name
Test status
Simulation time 13707224 ps
CPU time 1.75 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 237484 kb
Host smart-03c416ee-8642-49ad-a2ba-21caee866e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=860322376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.860322376
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3485673813
Short name T368
Test name
Test status
Simulation time 23782715373 ps
CPU time 345.42 seconds
Started Jul 26 05:45:23 PM PDT 24
Finished Jul 26 05:51:08 PM PDT 24
Peak memory 236656 kb
Host smart-48656f74-0ef6-4f3a-8842-5e10fdf4f68c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3485673813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3485673813
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3145236934
Short name T130
Test name
Test status
Simulation time 1171351367 ps
CPU time 36.38 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:04:01 PM PDT 24
Peak memory 256824 kb
Host smart-e6628fa3-0f61-4ca4-8e13-e24eba9ddef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31452
36934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3145236934
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1994961469
Short name T287
Test name
Test status
Simulation time 50854424 ps
CPU time 8.48 seconds
Started Jul 26 05:03:56 PM PDT 24
Finished Jul 26 05:04:04 PM PDT 24
Peak memory 248352 kb
Host smart-b357d5c2-6aa7-4f25-a563-e6e096c08678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19949
61469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1994961469
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.768620044
Short name T322
Test name
Test status
Simulation time 49831057681 ps
CPU time 539.72 seconds
Started Jul 26 05:04:34 PM PDT 24
Finished Jul 26 05:13:34 PM PDT 24
Peak memory 248784 kb
Host smart-31bf482e-d0de-4794-b7e6-afeb455e6ae2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768620044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.768620044
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.4094619861
Short name T341
Test name
Test status
Simulation time 122188951195 ps
CPU time 1765.66 seconds
Started Jul 26 05:04:52 PM PDT 24
Finished Jul 26 05:34:18 PM PDT 24
Peak memory 273184 kb
Host smart-5d6d1f89-5a7a-4eee-8d23-e471e0b66158
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094619861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.4094619861
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2043931159
Short name T263
Test name
Test status
Simulation time 30262261847 ps
CPU time 1924.61 seconds
Started Jul 26 05:04:51 PM PDT 24
Finished Jul 26 05:36:56 PM PDT 24
Peak memory 289096 kb
Host smart-98a1b059-5ebd-4662-bbe0-578ca2b8b05e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043931159 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2043931159
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1997578467
Short name T227
Test name
Test status
Simulation time 31285844 ps
CPU time 3.08 seconds
Started Jul 26 05:02:58 PM PDT 24
Finished Jul 26 05:03:02 PM PDT 24
Peak memory 248956 kb
Host smart-b9b1745a-db98-4a55-b56f-5812a58b71ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1997578467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1997578467
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3050463405
Short name T231
Test name
Test status
Simulation time 42635066 ps
CPU time 3.94 seconds
Started Jul 26 05:03:49 PM PDT 24
Finished Jul 26 05:03:53 PM PDT 24
Peak memory 249040 kb
Host smart-3ca6f2f2-27d4-47b4-968b-030b669d5289
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3050463405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3050463405
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.487227376
Short name T234
Test name
Test status
Simulation time 39986847 ps
CPU time 3.57 seconds
Started Jul 26 05:03:29 PM PDT 24
Finished Jul 26 05:03:32 PM PDT 24
Peak memory 249132 kb
Host smart-093a0a95-4d70-4118-afb5-66c17bb49362
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=487227376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.487227376
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1781143055
Short name T222
Test name
Test status
Simulation time 161931692 ps
CPU time 4.04 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:03:29 PM PDT 24
Peak memory 249088 kb
Host smart-8b469787-234e-40d0-9e7e-ac1245412b13
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1781143055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1781143055
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1621283257
Short name T305
Test name
Test status
Simulation time 585362286603 ps
CPU time 3622.69 seconds
Started Jul 26 05:03:18 PM PDT 24
Finished Jul 26 06:03:41 PM PDT 24
Peak memory 305568 kb
Host smart-2027c738-b082-47be-bbfc-0ac5873ba030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621283257 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1621283257
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3299652803
Short name T251
Test name
Test status
Simulation time 15767960634 ps
CPU time 1336.12 seconds
Started Jul 26 05:03:22 PM PDT 24
Finished Jul 26 05:25:39 PM PDT 24
Peak memory 289564 kb
Host smart-122146c0-da90-4660-a8cc-cfcbca3becae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299652803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3299652803
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.599202914
Short name T307
Test name
Test status
Simulation time 68526250651 ps
CPU time 1586.35 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:29:54 PM PDT 24
Peak memory 288832 kb
Host smart-042ed3c9-fc88-42db-8882-973f3b02ee20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599202914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.599202914
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1140549624
Short name T86
Test name
Test status
Simulation time 122639041377 ps
CPU time 2260.74 seconds
Started Jul 26 05:03:57 PM PDT 24
Finished Jul 26 05:41:38 PM PDT 24
Peak memory 322748 kb
Host smart-7669f58c-a030-48cd-b74b-a1a2a3d21f9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140549624 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1140549624
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3490724048
Short name T299
Test name
Test status
Simulation time 22880387010 ps
CPU time 1480.35 seconds
Started Jul 26 05:03:15 PM PDT 24
Finished Jul 26 05:27:55 PM PDT 24
Peak memory 273380 kb
Host smart-2dfee4ba-ada3-4ced-8e50-47dabc2b323f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490724048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3490724048
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3739113708
Short name T188
Test name
Test status
Simulation time 63594627 ps
CPU time 3.25 seconds
Started Jul 26 05:45:33 PM PDT 24
Finished Jul 26 05:45:36 PM PDT 24
Peak memory 237712 kb
Host smart-3780caf8-5d87-4f6b-aca6-a3dc841ebb47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3739113708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3739113708
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.232197033
Short name T168
Test name
Test status
Simulation time 7249440035 ps
CPU time 351.65 seconds
Started Jul 26 05:45:26 PM PDT 24
Finished Jul 26 05:51:18 PM PDT 24
Peak memory 265400 kb
Host smart-d17c65a0-e93f-4372-ac9a-8ab40d866cde
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232197033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.232197033
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2967596021
Short name T21
Test name
Test status
Simulation time 285826163304 ps
CPU time 6747.4 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 06:55:59 PM PDT 24
Peak memory 370512 kb
Host smart-03aed1ae-9588-4082-9273-24c07bfc42e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967596021 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2967596021
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.488959537
Short name T720
Test name
Test status
Simulation time 10126077 ps
CPU time 1.44 seconds
Started Jul 26 05:45:32 PM PDT 24
Finished Jul 26 05:45:33 PM PDT 24
Peak memory 237324 kb
Host smart-b80ee319-d2d6-4fd0-b6cf-e7cf8250f15f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=488959537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.488959537
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3118802112
Short name T347
Test name
Test status
Simulation time 111713902647 ps
CPU time 1781.56 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:33:07 PM PDT 24
Peak memory 283012 kb
Host smart-65e73465-b8e9-46d2-aae3-ee91e888aee4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118802112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3118802112
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2554102266
Short name T293
Test name
Test status
Simulation time 1043320700 ps
CPU time 63.91 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:04:28 PM PDT 24
Peak memory 256496 kb
Host smart-75151865-0adc-4a70-81a0-fa3f779d9de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25541
02266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2554102266
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1389478157
Short name T526
Test name
Test status
Simulation time 6669464491 ps
CPU time 138.69 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:05:42 PM PDT 24
Peak memory 256112 kb
Host smart-58089ac2-f483-4999-b616-124c7f87825c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389478157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1389478157
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1051924813
Short name T291
Test name
Test status
Simulation time 808459270 ps
CPU time 8.89 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:03:41 PM PDT 24
Peak memory 254420 kb
Host smart-b16c197c-d0e9-4318-9700-d30deacfb6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10519
24813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1051924813
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3127618669
Short name T559
Test name
Test status
Simulation time 30356785296 ps
CPU time 1158.94 seconds
Started Jul 26 05:03:19 PM PDT 24
Finished Jul 26 05:22:38 PM PDT 24
Peak memory 281580 kb
Host smart-e3267901-03e4-4a63-9116-6f90b148a6d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127618669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3127618669
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.889274699
Short name T94
Test name
Test status
Simulation time 28522747658 ps
CPU time 3129.68 seconds
Started Jul 26 05:03:59 PM PDT 24
Finished Jul 26 05:56:09 PM PDT 24
Peak memory 322732 kb
Host smart-454fd316-f348-40f2-87d4-9e43cd5c74b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889274699 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.889274699
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.554059619
Short name T35
Test name
Test status
Simulation time 415236406 ps
CPU time 28.7 seconds
Started Jul 26 05:03:57 PM PDT 24
Finished Jul 26 05:04:26 PM PDT 24
Peak memory 248552 kb
Host smart-8512a021-1076-49b8-b063-88b4b9b30dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55405
9619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.554059619
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1847639641
Short name T118
Test name
Test status
Simulation time 1085831423 ps
CPU time 22.9 seconds
Started Jul 26 05:03:58 PM PDT 24
Finished Jul 26 05:04:21 PM PDT 24
Peak memory 248248 kb
Host smart-13dcc12c-0ca8-4001-8fa5-9a5816a9d861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18476
39641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1847639641
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2708965423
Short name T132
Test name
Test status
Simulation time 28144400825 ps
CPU time 520.89 seconds
Started Jul 26 05:03:55 PM PDT 24
Finished Jul 26 05:12:36 PM PDT 24
Peak memory 265196 kb
Host smart-8c6d4ca5-6219-4097-9f29-f0ba7ce24aaa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708965423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2708965423
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.372451996
Short name T294
Test name
Test status
Simulation time 999363502 ps
CPU time 54.05 seconds
Started Jul 26 05:03:59 PM PDT 24
Finished Jul 26 05:04:53 PM PDT 24
Peak memory 256408 kb
Host smart-49e41283-00b1-4c99-adbd-9f675cb7ccd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37245
1996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.372451996
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.37536498
Short name T68
Test name
Test status
Simulation time 423996257 ps
CPU time 29.23 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:04:42 PM PDT 24
Peak memory 256500 kb
Host smart-3d8ccd60-5bd7-4af5-bb97-7fdbd0b39714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37536
498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.37536498
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2536291937
Short name T88
Test name
Test status
Simulation time 44884585846 ps
CPU time 2692.14 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:49:06 PM PDT 24
Peak memory 287828 kb
Host smart-80a91dac-c203-47f3-9cab-ec1ac73a8173
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536291937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2536291937
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.35164917
Short name T289
Test name
Test status
Simulation time 239870935761 ps
CPU time 3481.43 seconds
Started Jul 26 05:04:24 PM PDT 24
Finished Jul 26 06:02:26 PM PDT 24
Peak memory 289456 kb
Host smart-d68c4066-e669-42f4-8193-9e238d988194
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35164917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_hand
ler_stress_all.35164917
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1651935287
Short name T90
Test name
Test status
Simulation time 1747517820 ps
CPU time 66.76 seconds
Started Jul 26 05:03:00 PM PDT 24
Finished Jul 26 05:04:07 PM PDT 24
Peak memory 248628 kb
Host smart-36487b74-28c3-4201-9fee-608de33f31b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16519
35287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1651935287
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.237969205
Short name T407
Test name
Test status
Simulation time 442160575 ps
CPU time 34.93 seconds
Started Jul 26 05:03:19 PM PDT 24
Finished Jul 26 05:03:54 PM PDT 24
Peak memory 256124 kb
Host smart-cd031fe7-4c36-420c-a81a-441b56a0a163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23796
9205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.237969205
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.420042243
Short name T141
Test name
Test status
Simulation time 7707127916 ps
CPU time 278.03 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:50:17 PM PDT 24
Peak memory 265408 kb
Host smart-d859c70a-5053-4526-a9d1-71aa4eb76f3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=420042243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.420042243
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4240992837
Short name T140
Test name
Test status
Simulation time 4030647316 ps
CPU time 312.83 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:50:21 PM PDT 24
Peak memory 265452 kb
Host smart-495a155b-49c0-4712-9ede-ab6b2d868060
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4240992837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.4240992837
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.712909999
Short name T136
Test name
Test status
Simulation time 14654071297 ps
CPU time 306.38 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:50:54 PM PDT 24
Peak memory 265328 kb
Host smart-92e132e6-f025-4d16-9d3c-77a9b27b5983
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=712909999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.712909999
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.202201292
Short name T182
Test name
Test status
Simulation time 379845075 ps
CPU time 3.69 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:42 PM PDT 24
Peak memory 237476 kb
Host smart-d1b89c5b-06fd-492a-8276-f25507c01c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=202201292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.202201292
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2207714749
Short name T180
Test name
Test status
Simulation time 54440753 ps
CPU time 4.23 seconds
Started Jul 26 05:45:13 PM PDT 24
Finished Jul 26 05:45:17 PM PDT 24
Peak memory 237464 kb
Host smart-b4490e61-231e-4cf2-8e96-325029788e23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2207714749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2207714749
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1601549212
Short name T181
Test name
Test status
Simulation time 42108467 ps
CPU time 3.2 seconds
Started Jul 26 05:45:25 PM PDT 24
Finished Jul 26 05:45:29 PM PDT 24
Peak memory 237880 kb
Host smart-774d7fbc-22b5-4e1b-b709-660cf837fb19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1601549212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1601549212
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2035087021
Short name T187
Test name
Test status
Simulation time 38549252 ps
CPU time 3.32 seconds
Started Jul 26 05:45:29 PM PDT 24
Finished Jul 26 05:45:33 PM PDT 24
Peak memory 236572 kb
Host smart-4c8a4aba-9bfc-42b7-b5a4-237c5ed847a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2035087021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2035087021
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3569546286
Short name T159
Test name
Test status
Simulation time 5050078351 ps
CPU time 186.51 seconds
Started Jul 26 05:45:44 PM PDT 24
Finished Jul 26 05:48:51 PM PDT 24
Peak memory 265448 kb
Host smart-bbffbe7d-5624-4984-bab9-c98cd1104755
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3569546286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3569546286
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.419999539
Short name T179
Test name
Test status
Simulation time 172534838 ps
CPU time 20.14 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:46:08 PM PDT 24
Peak memory 245748 kb
Host smart-d05bf6a9-90ea-45b0-ad2e-db3eeae17ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=419999539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.419999539
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.569989165
Short name T191
Test name
Test status
Simulation time 464350853 ps
CPU time 37.97 seconds
Started Jul 26 05:45:48 PM PDT 24
Finished Jul 26 05:46:27 PM PDT 24
Peak memory 240472 kb
Host smart-b4a7d596-d9f2-457c-86eb-17bdd0fdfcbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=569989165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.569989165
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3931329281
Short name T185
Test name
Test status
Simulation time 39761955 ps
CPU time 2.18 seconds
Started Jul 26 05:45:13 PM PDT 24
Finished Jul 26 05:45:15 PM PDT 24
Peak memory 237416 kb
Host smart-89965b06-fa72-40df-a3ff-09c7914fa576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3931329281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3931329281
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4064321142
Short name T186
Test name
Test status
Simulation time 85838761 ps
CPU time 4 seconds
Started Jul 26 05:45:29 PM PDT 24
Finished Jul 26 05:45:34 PM PDT 24
Peak memory 236584 kb
Host smart-51fb5ce2-e9d0-43f2-bbc9-86290ad2c7bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4064321142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4064321142
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.556049207
Short name T196
Test name
Test status
Simulation time 2377762841 ps
CPU time 39.75 seconds
Started Jul 26 05:45:11 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 240532 kb
Host smart-5bda8b9b-a6d1-40c3-bef8-a3ae94c21911
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=556049207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.556049207
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2620006041
Short name T172
Test name
Test status
Simulation time 556642194 ps
CPU time 35.14 seconds
Started Jul 26 05:45:37 PM PDT 24
Finished Jul 26 05:46:12 PM PDT 24
Peak memory 240372 kb
Host smart-8f5323ce-583a-461b-a367-c71cde709735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2620006041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2620006041
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1290080816
Short name T197
Test name
Test status
Simulation time 304192953 ps
CPU time 4.04 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:42 PM PDT 24
Peak memory 237740 kb
Host smart-1d2ed2d2-3341-4bcf-a43b-9d590eef2423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1290080816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1290080816
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2843960011
Short name T189
Test name
Test status
Simulation time 180810595 ps
CPU time 8.57 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:47 PM PDT 24
Peak memory 237440 kb
Host smart-618a8365-6f09-4273-bb46-5ba7d0b32fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2843960011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2843960011
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.648074497
Short name T192
Test name
Test status
Simulation time 536397980 ps
CPU time 20.66 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:46:08 PM PDT 24
Peak memory 237472 kb
Host smart-bc3a42e4-9269-4d56-bcda-d5d3c8b51f93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=648074497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.648074497
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3720426006
Short name T190
Test name
Test status
Simulation time 134716864 ps
CPU time 3.02 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:45:17 PM PDT 24
Peak memory 237324 kb
Host smart-e1185179-eb4b-458e-bf48-d138d54fdc90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3720426006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3720426006
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.744181823
Short name T184
Test name
Test status
Simulation time 326111305 ps
CPU time 38.45 seconds
Started Jul 26 05:45:33 PM PDT 24
Finished Jul 26 05:46:11 PM PDT 24
Peak memory 240372 kb
Host smart-e6165074-7473-4541-8c38-5773283d4034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=744181823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.744181823
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2307071541
Short name T178
Test name
Test status
Simulation time 306189458 ps
CPU time 50.1 seconds
Started Jul 26 05:45:25 PM PDT 24
Finished Jul 26 05:46:15 PM PDT 24
Peak memory 237560 kb
Host smart-4df670af-d687-4ee1-939b-bf3e7ce34ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2307071541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2307071541
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.959911876
Short name T174
Test name
Test status
Simulation time 26215346 ps
CPU time 2.53 seconds
Started Jul 26 05:45:30 PM PDT 24
Finished Jul 26 05:45:32 PM PDT 24
Peak memory 237468 kb
Host smart-cb4ad971-de51-407c-9091-617402cb6ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=959911876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.959911876
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2308687862
Short name T725
Test name
Test status
Simulation time 5945621714 ps
CPU time 256.36 seconds
Started Jul 26 05:45:10 PM PDT 24
Finished Jul 26 05:49:27 PM PDT 24
Peak memory 240596 kb
Host smart-5de973c4-ca5c-4f59-9b70-79aebe178fac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2308687862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2308687862
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.411668352
Short name T823
Test name
Test status
Simulation time 12769939834 ps
CPU time 227.44 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:48:54 PM PDT 24
Peak memory 236728 kb
Host smart-cfa07b08-e530-4223-9db7-a46b51f67d93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=411668352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.411668352
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.472036661
Short name T767
Test name
Test status
Simulation time 26631037 ps
CPU time 4.16 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 248580 kb
Host smart-5f656e45-d292-45ad-bf8c-293143958ba2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=472036661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.472036661
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3251812926
Short name T826
Test name
Test status
Simulation time 252945441 ps
CPU time 9.05 seconds
Started Jul 26 05:45:12 PM PDT 24
Finished Jul 26 05:45:21 PM PDT 24
Peak memory 256776 kb
Host smart-14c52988-81ad-4ea2-9f1c-72c4b6ef8208
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251812926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3251812926
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1482599426
Short name T771
Test name
Test status
Simulation time 111638195 ps
CPU time 4.83 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:12 PM PDT 24
Peak memory 240396 kb
Host smart-10262594-aa77-49c0-888a-99fa8e111729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1482599426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1482599426
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4152461126
Short name T367
Test name
Test status
Simulation time 52558061 ps
CPU time 1.31 seconds
Started Jul 26 05:45:17 PM PDT 24
Finished Jul 26 05:45:18 PM PDT 24
Peak memory 237360 kb
Host smart-c1ab54e5-224f-4b05-9c72-29ae3f8e5340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4152461126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4152461126
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3972601010
Short name T793
Test name
Test status
Simulation time 269774638 ps
CPU time 18.9 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:21 PM PDT 24
Peak memory 245628 kb
Host smart-645edef3-ddba-4c3d-ae3d-1f834220c37f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3972601010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3972601010
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1238348602
Short name T370
Test name
Test status
Simulation time 14113671478 ps
CPU time 509.38 seconds
Started Jul 26 05:45:10 PM PDT 24
Finished Jul 26 05:53:39 PM PDT 24
Peak memory 265328 kb
Host smart-d9f9164e-39e6-4967-a590-c5d6504c51d5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238348602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1238348602
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1000549513
Short name T800
Test name
Test status
Simulation time 97472744 ps
CPU time 7.32 seconds
Started Jul 26 05:45:16 PM PDT 24
Finished Jul 26 05:45:23 PM PDT 24
Peak memory 248616 kb
Host smart-47a0ae13-bb63-46c9-94a4-8dff8e5c7822
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1000549513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1000549513
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2700083335
Short name T724
Test name
Test status
Simulation time 4206181744 ps
CPU time 152.03 seconds
Started Jul 26 05:45:10 PM PDT 24
Finished Jul 26 05:47:42 PM PDT 24
Peak memory 241568 kb
Host smart-2f7a5e92-1453-4060-872f-cfa2be819861
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2700083335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2700083335
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3436311355
Short name T729
Test name
Test status
Simulation time 3405593224 ps
CPU time 196.95 seconds
Started Jul 26 05:45:10 PM PDT 24
Finished Jul 26 05:48:28 PM PDT 24
Peak memory 237564 kb
Host smart-b14eff20-1389-425d-9208-a6d9c8d2a98a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3436311355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3436311355
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4060196351
Short name T756
Test name
Test status
Simulation time 54815708 ps
CPU time 5.13 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:13 PM PDT 24
Peak memory 240428 kb
Host smart-3a8ec473-ab7c-4ea9-857b-cf4f8cc8f907
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4060196351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4060196351
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3705174679
Short name T817
Test name
Test status
Simulation time 272332649 ps
CPU time 9.76 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:45:24 PM PDT 24
Peak memory 254180 kb
Host smart-557b420a-878d-41b1-8b0a-028a7bba64ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705174679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3705174679
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.296824375
Short name T753
Test name
Test status
Simulation time 67100414 ps
CPU time 6.04 seconds
Started Jul 26 05:45:12 PM PDT 24
Finished Jul 26 05:45:18 PM PDT 24
Peak memory 237428 kb
Host smart-0ab5e799-e7cf-4474-a629-675ebf5038ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=296824375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.296824375
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3900756724
Short name T361
Test name
Test status
Simulation time 14162128 ps
CPU time 1.31 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:45:15 PM PDT 24
Peak memory 237472 kb
Host smart-ce9c21b7-1a4f-40f7-ae2e-4491ef8d38a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3900756724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3900756724
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2805220371
Short name T730
Test name
Test status
Simulation time 2913831459 ps
CPU time 23.5 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:45:37 PM PDT 24
Peak memory 245816 kb
Host smart-4f6c995c-8e70-48a8-a5e7-93eea0f4cbcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2805220371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2805220371
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4281664255
Short name T154
Test name
Test status
Simulation time 44220144720 ps
CPU time 589.14 seconds
Started Jul 26 05:45:16 PM PDT 24
Finished Jul 26 05:55:05 PM PDT 24
Peak memory 265364 kb
Host smart-3eec8719-eeed-4616-bfe9-706436e8872c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281664255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4281664255
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1570907618
Short name T751
Test name
Test status
Simulation time 21548091 ps
CPU time 3.54 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:13 PM PDT 24
Peak memory 251872 kb
Host smart-9c45ec40-c86b-4cc6-bb6c-270cb7bbb06a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1570907618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1570907618
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3722307476
Short name T193
Test name
Test status
Simulation time 73002496 ps
CPU time 5.88 seconds
Started Jul 26 05:45:44 PM PDT 24
Finished Jul 26 05:45:50 PM PDT 24
Peak memory 240404 kb
Host smart-0661b997-ffe0-4af4-b4ab-fbc73776e8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722307476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3722307476
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.681233263
Short name T195
Test name
Test status
Simulation time 396476745 ps
CPU time 7.86 seconds
Started Jul 26 05:45:39 PM PDT 24
Finished Jul 26 05:45:47 PM PDT 24
Peak memory 237428 kb
Host smart-fa0a16d9-8bbe-449b-ad93-5ffd8b8281d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=681233263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.681233263
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.331443151
Short name T802
Test name
Test status
Simulation time 6473608 ps
CPU time 1.55 seconds
Started Jul 26 05:45:42 PM PDT 24
Finished Jul 26 05:45:45 PM PDT 24
Peak memory 237408 kb
Host smart-54229c75-99cf-4ec0-bd15-d3c4452a3af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=331443151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.331443151
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1156997797
Short name T214
Test name
Test status
Simulation time 1205102388 ps
CPU time 19.82 seconds
Started Jul 26 05:45:39 PM PDT 24
Finished Jul 26 05:45:59 PM PDT 24
Peak memory 240388 kb
Host smart-fe387b14-5af2-45f6-b788-390723240de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1156997797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1156997797
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1818124342
Short name T169
Test name
Test status
Simulation time 42741324114 ps
CPU time 602 seconds
Started Jul 26 05:45:39 PM PDT 24
Finished Jul 26 05:55:41 PM PDT 24
Peak memory 269084 kb
Host smart-41749317-a2a4-42d6-994e-b111633e8325
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818124342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1818124342
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2889806703
Short name T739
Test name
Test status
Simulation time 1327227189 ps
CPU time 8.76 seconds
Started Jul 26 05:45:40 PM PDT 24
Finished Jul 26 05:45:48 PM PDT 24
Peak memory 248756 kb
Host smart-02f36df3-e72f-4b2f-bf08-f73924b099f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2889806703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2889806703
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1238592767
Short name T804
Test name
Test status
Simulation time 117525262 ps
CPU time 5.18 seconds
Started Jul 26 05:45:36 PM PDT 24
Finished Jul 26 05:45:41 PM PDT 24
Peak memory 242048 kb
Host smart-bdbdb0d4-0391-4e39-aef2-59fa34de5e73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238592767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1238592767
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.911382025
Short name T769
Test name
Test status
Simulation time 20468383 ps
CPU time 3.16 seconds
Started Jul 26 05:45:36 PM PDT 24
Finished Jul 26 05:45:39 PM PDT 24
Peak memory 237476 kb
Host smart-27b3f2c7-a360-4b13-b6bb-d101428abd6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=911382025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.911382025
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1189608295
Short name T787
Test name
Test status
Simulation time 172465309 ps
CPU time 20.55 seconds
Started Jul 26 05:45:41 PM PDT 24
Finished Jul 26 05:46:02 PM PDT 24
Peak memory 248572 kb
Host smart-925f8735-7eb6-474d-a0b1-982be11e735c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1189608295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1189608295
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3202745141
Short name T155
Test name
Test status
Simulation time 11247027044 ps
CPU time 205.6 seconds
Started Jul 26 05:45:44 PM PDT 24
Finished Jul 26 05:49:10 PM PDT 24
Peak memory 265340 kb
Host smart-67de634e-2605-4a47-8ada-2e30d394d9a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3202745141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3202745141
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2157545497
Short name T150
Test name
Test status
Simulation time 25730987864 ps
CPU time 511.65 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:54:20 PM PDT 24
Peak memory 265348 kb
Host smart-64365725-2693-4a3e-9523-a3dd6eb8e362
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157545497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2157545497
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2179885501
Short name T773
Test name
Test status
Simulation time 27943199 ps
CPU time 4.21 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:43 PM PDT 24
Peak memory 248672 kb
Host smart-320fcbc3-7136-43c7-82af-9208623de5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2179885501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2179885501
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.273271148
Short name T717
Test name
Test status
Simulation time 307145877 ps
CPU time 7.31 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:46 PM PDT 24
Peak memory 240896 kb
Host smart-a68fef56-4257-403d-a039-374aa9d3424a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273271148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.273271148
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4055305987
Short name T217
Test name
Test status
Simulation time 101804103 ps
CPU time 8.82 seconds
Started Jul 26 05:45:40 PM PDT 24
Finished Jul 26 05:45:49 PM PDT 24
Peak memory 236572 kb
Host smart-15c877cd-4a74-4374-a24d-dc581e51db3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4055305987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.4055305987
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.459430712
Short name T830
Test name
Test status
Simulation time 45191343 ps
CPU time 1.49 seconds
Started Jul 26 05:45:48 PM PDT 24
Finished Jul 26 05:45:50 PM PDT 24
Peak memory 236468 kb
Host smart-66adb292-02f9-4ea4-9b4c-22483d6be76f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=459430712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.459430712
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1728879390
Short name T768
Test name
Test status
Simulation time 294894639 ps
CPU time 21.71 seconds
Started Jul 26 05:45:35 PM PDT 24
Finished Jul 26 05:45:57 PM PDT 24
Peak memory 244740 kb
Host smart-d1b76b96-6b1d-4b79-8f3d-c1895b52b6f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1728879390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1728879390
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3649185598
Short name T166
Test name
Test status
Simulation time 21088419434 ps
CPU time 579.26 seconds
Started Jul 26 05:45:34 PM PDT 24
Finished Jul 26 05:55:14 PM PDT 24
Peak memory 265404 kb
Host smart-c603caf3-5f24-4135-92bc-92b1b73b3e2b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649185598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3649185598
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3111723175
Short name T811
Test name
Test status
Simulation time 44334640 ps
CPU time 4.56 seconds
Started Jul 26 05:45:34 PM PDT 24
Finished Jul 26 05:45:39 PM PDT 24
Peak memory 251468 kb
Host smart-e58c3dbe-dc7c-4a11-8bb2-83eba4ade891
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3111723175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3111723175
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2308925642
Short name T765
Test name
Test status
Simulation time 263471553 ps
CPU time 10.89 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:49 PM PDT 24
Peak memory 252284 kb
Host smart-4b7acd8a-9768-49b2-b4cd-d26b79e43c08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308925642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2308925642
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2247523942
Short name T208
Test name
Test status
Simulation time 117927878 ps
CPU time 6.74 seconds
Started Jul 26 05:45:31 PM PDT 24
Finished Jul 26 05:45:38 PM PDT 24
Peak memory 237472 kb
Host smart-9689a80a-f781-446d-a77a-67f4ea295137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2247523942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2247523942
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.206200951
Short name T809
Test name
Test status
Simulation time 10313671 ps
CPU time 1.4 seconds
Started Jul 26 05:45:35 PM PDT 24
Finished Jul 26 05:45:37 PM PDT 24
Peak memory 237428 kb
Host smart-bbe86d0f-70fd-4c82-aa7e-7987179c45ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=206200951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.206200951
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.47422337
Short name T215
Test name
Test status
Simulation time 176325801 ps
CPU time 26.17 seconds
Started Jul 26 05:45:41 PM PDT 24
Finished Jul 26 05:46:07 PM PDT 24
Peak memory 245680 kb
Host smart-1970adcd-190d-49b0-99ce-3b77b96f3583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=47422337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outs
tanding.47422337
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1879293070
Short name T369
Test name
Test status
Simulation time 28599942782 ps
CPU time 469.34 seconds
Started Jul 26 05:45:34 PM PDT 24
Finished Jul 26 05:53:24 PM PDT 24
Peak memory 270644 kb
Host smart-0116698f-42f8-4495-82ad-ac0d87902008
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879293070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1879293070
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.718531309
Short name T752
Test name
Test status
Simulation time 467244074 ps
CPU time 14.18 seconds
Started Jul 26 05:45:35 PM PDT 24
Finished Jul 26 05:45:49 PM PDT 24
Peak memory 248836 kb
Host smart-b896679a-4114-4744-ad61-691ebcebdde4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=718531309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.718531309
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2259803103
Short name T735
Test name
Test status
Simulation time 208055810 ps
CPU time 10.88 seconds
Started Jul 26 05:45:37 PM PDT 24
Finished Jul 26 05:45:48 PM PDT 24
Peak memory 256628 kb
Host smart-35683a67-aa02-4b30-bc74-b25efee733b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259803103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2259803103
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.476359311
Short name T209
Test name
Test status
Simulation time 72506885 ps
CPU time 5.55 seconds
Started Jul 26 05:45:43 PM PDT 24
Finished Jul 26 05:45:49 PM PDT 24
Peak memory 237452 kb
Host smart-45854ef9-4f14-46f6-b17d-58a8d9b4a322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=476359311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.476359311
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.207160794
Short name T755
Test name
Test status
Simulation time 360204100 ps
CPU time 25.79 seconds
Started Jul 26 05:45:34 PM PDT 24
Finished Jul 26 05:46:00 PM PDT 24
Peak memory 245688 kb
Host smart-7a885180-b5bb-417e-b815-cde8670ccd13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=207160794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.207160794
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3961667721
Short name T152
Test name
Test status
Simulation time 16280736175 ps
CPU time 686.46 seconds
Started Jul 26 05:45:42 PM PDT 24
Finished Jul 26 05:57:09 PM PDT 24
Peak memory 273196 kb
Host smart-f2220bcd-9b33-47b2-8420-17b93f3694f6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961667721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3961667721
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3269133048
Short name T732
Test name
Test status
Simulation time 330132411 ps
CPU time 23.24 seconds
Started Jul 26 05:45:36 PM PDT 24
Finished Jul 26 05:45:59 PM PDT 24
Peak memory 248504 kb
Host smart-c428ef85-8797-489a-8ae8-f8490fae956b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3269133048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3269133048
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2922173853
Short name T827
Test name
Test status
Simulation time 396683226 ps
CPU time 5.84 seconds
Started Jul 26 05:45:35 PM PDT 24
Finished Jul 26 05:45:40 PM PDT 24
Peak memory 252236 kb
Host smart-a2c7663d-5dee-454b-b745-f286a42980cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922173853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2922173853
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1920052105
Short name T789
Test name
Test status
Simulation time 94326352 ps
CPU time 8.31 seconds
Started Jul 26 05:45:41 PM PDT 24
Finished Jul 26 05:45:50 PM PDT 24
Peak memory 237424 kb
Host smart-cee9253f-74c4-4d5e-998e-54f7998c9b7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1920052105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1920052105
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.55015229
Short name T360
Test name
Test status
Simulation time 11918071 ps
CPU time 1.67 seconds
Started Jul 26 05:45:37 PM PDT 24
Finished Jul 26 05:45:39 PM PDT 24
Peak memory 236552 kb
Host smart-f3d81803-29b4-4eb8-8c96-6d3f478c250b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=55015229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.55015229
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1353391122
Short name T812
Test name
Test status
Simulation time 336779248 ps
CPU time 21.26 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:59 PM PDT 24
Peak memory 248620 kb
Host smart-6c9e869a-1990-440d-bb3b-868ab72e06db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1353391122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1353391122
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2630669316
Short name T137
Test name
Test status
Simulation time 4776234800 ps
CPU time 105.46 seconds
Started Jul 26 05:45:48 PM PDT 24
Finished Jul 26 05:47:34 PM PDT 24
Peak memory 265448 kb
Host smart-069a33c0-6ba3-46ff-9481-9967431e3e67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2630669316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2630669316
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.585667179
Short name T145
Test name
Test status
Simulation time 44529036227 ps
CPU time 473.31 seconds
Started Jul 26 05:45:39 PM PDT 24
Finished Jul 26 05:53:32 PM PDT 24
Peak memory 265360 kb
Host smart-1ffb9fee-86b8-4497-b52b-15c8b2485571
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585667179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.585667179
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.986291333
Short name T810
Test name
Test status
Simulation time 2346511893 ps
CPU time 31.79 seconds
Started Jul 26 05:45:34 PM PDT 24
Finished Jul 26 05:46:06 PM PDT 24
Peak memory 254844 kb
Host smart-23a4781b-0159-49b0-abd6-66694f5c3c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=986291333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.986291333
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3096369428
Short name T801
Test name
Test status
Simulation time 195514329 ps
CPU time 7.67 seconds
Started Jul 26 05:45:35 PM PDT 24
Finished Jul 26 05:45:43 PM PDT 24
Peak memory 239432 kb
Host smart-609ab697-9480-43a8-b7fe-700aa79b035e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096369428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3096369428
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2304590402
Short name T815
Test name
Test status
Simulation time 461103621 ps
CPU time 8.04 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:46 PM PDT 24
Peak memory 236604 kb
Host smart-8a9f9f45-6ba8-4e9f-90ec-56b9466ab1c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2304590402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2304590402
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2681496467
Short name T816
Test name
Test status
Simulation time 16881994 ps
CPU time 1.78 seconds
Started Jul 26 05:45:43 PM PDT 24
Finished Jul 26 05:45:45 PM PDT 24
Peak memory 235548 kb
Host smart-b3060011-6525-4394-af53-bfa2fd6ee5ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2681496467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2681496467
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3407234197
Short name T795
Test name
Test status
Simulation time 249267463 ps
CPU time 19.74 seconds
Started Jul 26 05:45:36 PM PDT 24
Finished Jul 26 05:45:56 PM PDT 24
Peak memory 240360 kb
Host smart-2b0bf555-96e5-4bfa-88bc-88ca93d2e461
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3407234197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3407234197
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3274897683
Short name T171
Test name
Test status
Simulation time 11292008746 ps
CPU time 185.48 seconds
Started Jul 26 05:45:46 PM PDT 24
Finished Jul 26 05:48:52 PM PDT 24
Peak memory 265464 kb
Host smart-86bcc7b3-e641-4c5e-ab43-7ea4ca026c7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3274897683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3274897683
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2534858059
Short name T741
Test name
Test status
Simulation time 407335434 ps
CPU time 17.16 seconds
Started Jul 26 05:45:41 PM PDT 24
Finished Jul 26 05:45:58 PM PDT 24
Peak memory 254416 kb
Host smart-e1c140df-68ad-43c8-9201-68dbdb49cc5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2534858059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2534858059
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1354094843
Short name T733
Test name
Test status
Simulation time 162502319 ps
CPU time 6.81 seconds
Started Jul 26 05:45:39 PM PDT 24
Finished Jul 26 05:45:45 PM PDT 24
Peak memory 238888 kb
Host smart-a8d2764f-6092-49bb-baca-b11193e46711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354094843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1354094843
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.768837665
Short name T737
Test name
Test status
Simulation time 30199548 ps
CPU time 3.78 seconds
Started Jul 26 05:45:37 PM PDT 24
Finished Jul 26 05:45:41 PM PDT 24
Peak memory 240372 kb
Host smart-127c1b2c-63ac-4f15-972d-aab9edfbdad9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=768837665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.768837665
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3236546749
Short name T721
Test name
Test status
Simulation time 10027269 ps
CPU time 1.51 seconds
Started Jul 26 05:45:35 PM PDT 24
Finished Jul 26 05:45:36 PM PDT 24
Peak memory 237088 kb
Host smart-ba9959b0-c1ab-4dba-adfa-7156288d4ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3236546749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3236546749
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3791022718
Short name T824
Test name
Test status
Simulation time 257423886 ps
CPU time 17.77 seconds
Started Jul 26 05:45:37 PM PDT 24
Finished Jul 26 05:45:55 PM PDT 24
Peak memory 240388 kb
Host smart-1ce571e7-278d-4000-9e10-c94a5b4c5086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3791022718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3791022718
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3199032253
Short name T153
Test name
Test status
Simulation time 1594725723 ps
CPU time 88.57 seconds
Started Jul 26 05:45:39 PM PDT 24
Finished Jul 26 05:47:08 PM PDT 24
Peak memory 267996 kb
Host smart-cf86fe77-10c8-452b-a6c0-c83dfeb7e821
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3199032253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3199032253
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.93316082
Short name T274
Test name
Test status
Simulation time 2002288652 ps
CPU time 30.86 seconds
Started Jul 26 05:45:37 PM PDT 24
Finished Jul 26 05:46:08 PM PDT 24
Peak memory 248676 kb
Host smart-b0207396-316a-478f-9836-2cff86d3e993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=93316082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.93316082
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.661177275
Short name T806
Test name
Test status
Simulation time 116294980 ps
CPU time 8.05 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:58 PM PDT 24
Peak memory 256796 kb
Host smart-61b0c48f-94c0-4f3b-9064-57b7c593b409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661177275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.661177275
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.4096002803
Short name T726
Test name
Test status
Simulation time 21150532 ps
CPU time 3.35 seconds
Started Jul 26 05:45:50 PM PDT 24
Finished Jul 26 05:45:54 PM PDT 24
Peak memory 239216 kb
Host smart-308c6fff-a67b-4a81-b6b2-8ae7b9152736
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4096002803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.4096002803
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2446811770
Short name T794
Test name
Test status
Simulation time 21563987 ps
CPU time 1.39 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:45:50 PM PDT 24
Peak memory 237432 kb
Host smart-44196b91-b11e-40b0-a2a5-d7f250b8949b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2446811770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2446811770
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1173804621
Short name T758
Test name
Test status
Simulation time 92871574 ps
CPU time 10.5 seconds
Started Jul 26 05:45:46 PM PDT 24
Finished Jul 26 05:45:58 PM PDT 24
Peak memory 244760 kb
Host smart-d5ceff53-54e3-4527-9314-1b0b6ca1710e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1173804621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1173804621
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2553355464
Short name T165
Test name
Test status
Simulation time 3785980581 ps
CPU time 275.83 seconds
Started Jul 26 05:45:48 PM PDT 24
Finished Jul 26 05:50:25 PM PDT 24
Peak memory 265616 kb
Host smart-7c19e9b2-da44-47ef-badc-e351e1f6e404
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2553355464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2553355464
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1098122265
Short name T749
Test name
Test status
Simulation time 1245398200 ps
CPU time 12.36 seconds
Started Jul 26 05:45:39 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 248596 kb
Host smart-2a2dd3fb-f29b-4168-8c4d-3f98fb2c6ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1098122265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1098122265
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1523785777
Short name T770
Test name
Test status
Simulation time 392772483 ps
CPU time 7.63 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:45:56 PM PDT 24
Peak memory 239512 kb
Host smart-a9a92230-9b87-4e51-8d43-469e52cb1504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523785777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1523785777
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3343312183
Short name T775
Test name
Test status
Simulation time 404332732 ps
CPU time 8.14 seconds
Started Jul 26 05:45:44 PM PDT 24
Finished Jul 26 05:45:52 PM PDT 24
Peak memory 236584 kb
Host smart-a3e9840d-b6d7-4cbd-8ce7-50b5b6223a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3343312183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3343312183
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2166509307
Short name T744
Test name
Test status
Simulation time 6710884 ps
CPU time 1.45 seconds
Started Jul 26 05:45:44 PM PDT 24
Finished Jul 26 05:45:45 PM PDT 24
Peak memory 237492 kb
Host smart-978ba40f-ac12-40f2-9835-ff754a0e0279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2166509307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2166509307
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3865629203
Short name T822
Test name
Test status
Simulation time 294897110 ps
CPU time 14.64 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:46:02 PM PDT 24
Peak memory 240460 kb
Host smart-4205e90e-8bee-40ea-aa89-e7581e5ec5ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3865629203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3865629203
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.485269268
Short name T163
Test name
Test status
Simulation time 68546322053 ps
CPU time 1226.8 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 06:06:14 PM PDT 24
Peak memory 273624 kb
Host smart-622678db-a2f2-49fa-9301-1a397cb749be
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485269268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.485269268
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2182541765
Short name T734
Test name
Test status
Simulation time 205054206 ps
CPU time 13.7 seconds
Started Jul 26 05:45:42 PM PDT 24
Finished Jul 26 05:45:57 PM PDT 24
Peak memory 253816 kb
Host smart-0bff3d7b-c7de-409f-a4bd-cd2d1d2bf1ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2182541765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2182541765
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3634355092
Short name T796
Test name
Test status
Simulation time 2155067920 ps
CPU time 73.71 seconds
Started Jul 26 05:45:20 PM PDT 24
Finished Jul 26 05:46:34 PM PDT 24
Peak memory 237500 kb
Host smart-8b3e5a5f-ecf6-42bd-9d86-0938ae3d200f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3634355092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3634355092
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.359577806
Short name T746
Test name
Test status
Simulation time 4479085083 ps
CPU time 258.68 seconds
Started Jul 26 05:45:15 PM PDT 24
Finished Jul 26 05:49:34 PM PDT 24
Peak memory 237608 kb
Host smart-86d770b5-db95-44c6-9013-64146efeea1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=359577806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.359577806
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.108847275
Short name T808
Test name
Test status
Simulation time 198229088 ps
CPU time 4.94 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:45:19 PM PDT 24
Peak memory 248548 kb
Host smart-0160697d-26a4-423f-a5f1-eb69a797e935
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=108847275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.108847275
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2176103115
Short name T785
Test name
Test status
Simulation time 628662484 ps
CPU time 12.76 seconds
Started Jul 26 05:45:16 PM PDT 24
Finished Jul 26 05:45:29 PM PDT 24
Peak memory 252520 kb
Host smart-68cafb3c-7020-45e3-a9b7-5df1e341bee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176103115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2176103115
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3001746478
Short name T745
Test name
Test status
Simulation time 65980708 ps
CPU time 3.76 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:45:18 PM PDT 24
Peak memory 237436 kb
Host smart-f6ab893c-744b-4db6-a211-044001727f1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3001746478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3001746478
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4272731088
Short name T761
Test name
Test status
Simulation time 6431572 ps
CPU time 1.43 seconds
Started Jul 26 05:45:20 PM PDT 24
Finished Jul 26 05:45:22 PM PDT 24
Peak memory 236444 kb
Host smart-d35bfe3e-9732-440b-b4bb-f69e8b826ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4272731088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4272731088
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1243082380
Short name T722
Test name
Test status
Simulation time 306868684 ps
CPU time 20.89 seconds
Started Jul 26 05:45:12 PM PDT 24
Finished Jul 26 05:45:33 PM PDT 24
Peak memory 244764 kb
Host smart-2406d677-d178-45a9-a75d-213c7b40dcdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1243082380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1243082380
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1249824682
Short name T147
Test name
Test status
Simulation time 3181504899 ps
CPU time 101.93 seconds
Started Jul 26 05:45:13 PM PDT 24
Finished Jul 26 05:46:55 PM PDT 24
Peak memory 265496 kb
Host smart-1acf0e2b-1681-4a7f-9c73-7e77fc7a98e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1249824682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1249824682
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4138192529
Short name T158
Test name
Test status
Simulation time 15769164977 ps
CPU time 1120.7 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 06:03:50 PM PDT 24
Peak memory 266428 kb
Host smart-686dfe33-a13f-405f-9ede-894f6765b674
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138192529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4138192529
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3262846346
Short name T828
Test name
Test status
Simulation time 478455740 ps
CPU time 6.46 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:45:20 PM PDT 24
Peak memory 252484 kb
Host smart-dbfe71c8-f0a7-4157-bc95-f0145fcc03cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3262846346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3262846346
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.782630734
Short name T177
Test name
Test status
Simulation time 12240703 ps
CPU time 1.4 seconds
Started Jul 26 05:45:50 PM PDT 24
Finished Jul 26 05:45:52 PM PDT 24
Peak memory 237460 kb
Host smart-0d0b6484-eb5f-46da-b453-54ca27824dcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=782630734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.782630734
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1251439450
Short name T791
Test name
Test status
Simulation time 6788988 ps
CPU time 1.46 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 237432 kb
Host smart-bf98090e-54c9-4d9f-ad6b-e11cd786028e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1251439450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1251439450
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1333397828
Short name T814
Test name
Test status
Simulation time 8983585 ps
CPU time 1.32 seconds
Started Jul 26 05:45:46 PM PDT 24
Finished Jul 26 05:45:48 PM PDT 24
Peak memory 237372 kb
Host smart-cb786508-4e7e-47a6-97cc-99bdd3066bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1333397828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1333397828
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2602949546
Short name T363
Test name
Test status
Simulation time 8283839 ps
CPU time 1.53 seconds
Started Jul 26 05:45:48 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 237448 kb
Host smart-a834a796-e486-4983-bc87-392b657e2b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2602949546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2602949546
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.330827632
Short name T728
Test name
Test status
Simulation time 10726081 ps
CPU time 1.27 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 237468 kb
Host smart-9bad4083-c878-4ec4-a78f-48886aa2aec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=330827632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.330827632
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2386007787
Short name T366
Test name
Test status
Simulation time 6310939 ps
CPU time 1.47 seconds
Started Jul 26 05:45:45 PM PDT 24
Finished Jul 26 05:45:47 PM PDT 24
Peak memory 237500 kb
Host smart-f0027054-d59d-4ce4-9aee-4a262f372b1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2386007787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2386007787
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3607976408
Short name T821
Test name
Test status
Simulation time 11013137 ps
CPU time 1.31 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 235488 kb
Host smart-5dd481f4-3ed0-4bfc-ace5-09bbb6f84fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3607976408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3607976408
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3064610820
Short name T258
Test name
Test status
Simulation time 7524549 ps
CPU time 1.48 seconds
Started Jul 26 05:45:46 PM PDT 24
Finished Jul 26 05:45:48 PM PDT 24
Peak memory 237448 kb
Host smart-d9ae57d1-ea29-4ccc-8950-b09745477926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3064610820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3064610820
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.185835239
Short name T359
Test name
Test status
Simulation time 13995467 ps
CPU time 1.38 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 237468 kb
Host smart-3948cb9f-9700-42a3-a2ff-a80fcbfa221c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=185835239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.185835239
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.604393573
Short name T829
Test name
Test status
Simulation time 1107547431 ps
CPU time 153.65 seconds
Started Jul 26 05:45:12 PM PDT 24
Finished Jul 26 05:47:46 PM PDT 24
Peak memory 240392 kb
Host smart-d657d0be-8408-41ed-8ee2-456291927185
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=604393573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.604393573
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3151863273
Short name T736
Test name
Test status
Simulation time 9603249895 ps
CPU time 201.58 seconds
Started Jul 26 05:45:24 PM PDT 24
Finished Jul 26 05:48:45 PM PDT 24
Peak memory 237452 kb
Host smart-af6c47a5-3280-4940-a361-8f17df074068
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3151863273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3151863273
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.187910799
Short name T825
Test name
Test status
Simulation time 21845672 ps
CPU time 3.75 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:45:18 PM PDT 24
Peak memory 240336 kb
Host smart-7180732d-5b47-4c50-a845-693b7034311e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=187910799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.187910799
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2006861243
Short name T776
Test name
Test status
Simulation time 148858953 ps
CPU time 7.6 seconds
Started Jul 26 05:45:13 PM PDT 24
Finished Jul 26 05:45:21 PM PDT 24
Peak memory 251760 kb
Host smart-408c8ea4-089b-4972-8051-e8803d8a442d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006861243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2006861243
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2434685212
Short name T774
Test name
Test status
Simulation time 61542291 ps
CPU time 3.66 seconds
Started Jul 26 05:45:15 PM PDT 24
Finished Jul 26 05:45:19 PM PDT 24
Peak memory 240332 kb
Host smart-93d2f37e-f90b-424a-b999-c0508d36228b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2434685212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2434685212
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1286468310
Short name T803
Test name
Test status
Simulation time 12287973 ps
CPU time 1.4 seconds
Started Jul 26 05:45:04 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 237692 kb
Host smart-f26116e6-f164-46cc-ba21-b3c4da1a4489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1286468310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1286468310
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2010151865
Short name T216
Test name
Test status
Simulation time 1365222229 ps
CPU time 45.5 seconds
Started Jul 26 05:45:11 PM PDT 24
Finished Jul 26 05:45:56 PM PDT 24
Peak memory 245676 kb
Host smart-2a045ac2-ff83-4653-96a4-ef778aad9795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2010151865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2010151865
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.634007996
Short name T146
Test name
Test status
Simulation time 1455791848 ps
CPU time 94.83 seconds
Started Jul 26 05:45:14 PM PDT 24
Finished Jul 26 05:46:49 PM PDT 24
Peak memory 265296 kb
Host smart-098aadc0-b19f-4568-a953-1aac15997967
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=634007996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.634007996
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1664083482
Short name T740
Test name
Test status
Simulation time 398172016 ps
CPU time 25.92 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:35 PM PDT 24
Peak memory 248664 kb
Host smart-f5938142-5039-4da6-9fe4-fd0d6b1df3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1664083482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1664083482
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1344068236
Short name T772
Test name
Test status
Simulation time 45864614 ps
CPU time 1.51 seconds
Started Jul 26 05:45:44 PM PDT 24
Finished Jul 26 05:45:46 PM PDT 24
Peak memory 237336 kb
Host smart-4419e7c8-f17f-40a6-8413-f439d1341c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1344068236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1344068236
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.120251703
Short name T798
Test name
Test status
Simulation time 7600493 ps
CPU time 1.43 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 237468 kb
Host smart-159a0029-233a-4a33-8503-37a769f0fb63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=120251703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.120251703
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2714452408
Short name T807
Test name
Test status
Simulation time 32697518 ps
CPU time 1.3 seconds
Started Jul 26 05:45:51 PM PDT 24
Finished Jul 26 05:45:52 PM PDT 24
Peak memory 237344 kb
Host smart-e7a69aac-5dcc-4567-93c7-ada3ffab6988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2714452408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2714452408
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2649375622
Short name T819
Test name
Test status
Simulation time 8734299 ps
CPU time 1.38 seconds
Started Jul 26 05:45:45 PM PDT 24
Finished Jul 26 05:45:46 PM PDT 24
Peak memory 237500 kb
Host smart-20292c74-2343-4302-92fd-8bf915767da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2649375622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2649375622
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2258017378
Short name T719
Test name
Test status
Simulation time 10208430 ps
CPU time 1.33 seconds
Started Jul 26 05:45:48 PM PDT 24
Finished Jul 26 05:45:50 PM PDT 24
Peak memory 237372 kb
Host smart-414f27a9-a529-4331-a7b1-c28aede2011b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2258017378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2258017378
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3159078847
Short name T762
Test name
Test status
Simulation time 13017933 ps
CPU time 1.62 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:45:49 PM PDT 24
Peak memory 237436 kb
Host smart-ace55b7c-0bc1-4aed-b6c4-5f9a4c9cd9f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3159078847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3159078847
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2749851931
Short name T760
Test name
Test status
Simulation time 40057675 ps
CPU time 1.48 seconds
Started Jul 26 05:45:45 PM PDT 24
Finished Jul 26 05:45:47 PM PDT 24
Peak memory 236524 kb
Host smart-08b280df-966d-4855-b9c3-7bee193c0e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2749851931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2749851931
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1434777595
Short name T783
Test name
Test status
Simulation time 6694549 ps
CPU time 1.45 seconds
Started Jul 26 05:45:45 PM PDT 24
Finished Jul 26 05:45:47 PM PDT 24
Peak memory 237432 kb
Host smart-30b2bc86-b7e9-4477-b5f0-27b688f46f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1434777595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1434777595
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4265060667
Short name T764
Test name
Test status
Simulation time 10338809 ps
CPU time 1.25 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:45:49 PM PDT 24
Peak memory 236572 kb
Host smart-b801ee3a-faef-4743-9a65-a7276471cee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4265060667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4265060667
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.324152153
Short name T718
Test name
Test status
Simulation time 15380833 ps
CPU time 1.28 seconds
Started Jul 26 05:45:51 PM PDT 24
Finished Jul 26 05:45:53 PM PDT 24
Peak memory 237500 kb
Host smart-509d53a0-6a29-4a3a-9126-ac7842c6dcad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=324152153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.324152153
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2562072995
Short name T194
Test name
Test status
Simulation time 4296529014 ps
CPU time 148.85 seconds
Started Jul 26 05:45:17 PM PDT 24
Finished Jul 26 05:47:46 PM PDT 24
Peak memory 237592 kb
Host smart-1c6afcd5-8176-4e33-a64b-dd3f7a58fb0a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2562072995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2562072995
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3608511468
Short name T799
Test name
Test status
Simulation time 222042112 ps
CPU time 5.46 seconds
Started Jul 26 05:45:26 PM PDT 24
Finished Jul 26 05:45:31 PM PDT 24
Peak memory 240420 kb
Host smart-96c8c0c0-8fe6-4224-b443-b43297f58ddf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3608511468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3608511468
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.673972026
Short name T763
Test name
Test status
Simulation time 85629326 ps
CPU time 7.52 seconds
Started Jul 26 05:45:11 PM PDT 24
Finished Jul 26 05:45:19 PM PDT 24
Peak memory 241036 kb
Host smart-e3b0d703-638e-49d4-b1dd-a01f963a8766
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673972026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.673972026
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1210924387
Short name T738
Test name
Test status
Simulation time 187767957 ps
CPU time 4.43 seconds
Started Jul 26 05:45:36 PM PDT 24
Finished Jul 26 05:45:41 PM PDT 24
Peak memory 236512 kb
Host smart-3373a903-39c4-4db4-b46d-f76a0dd02250
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1210924387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1210924387
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1936572494
Short name T788
Test name
Test status
Simulation time 10131521 ps
CPU time 1.26 seconds
Started Jul 26 05:45:22 PM PDT 24
Finished Jul 26 05:45:23 PM PDT 24
Peak memory 237500 kb
Host smart-24056377-6ba5-4a89-82dd-b41931c7502d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1936572494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1936572494
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2080060173
Short name T780
Test name
Test status
Simulation time 351803498 ps
CPU time 12.66 seconds
Started Jul 26 05:45:15 PM PDT 24
Finished Jul 26 05:45:28 PM PDT 24
Peak memory 245524 kb
Host smart-3a28dea1-adcd-4ff3-8977-3898bc9214fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2080060173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2080060173
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.994829341
Short name T813
Test name
Test status
Simulation time 96957485 ps
CPU time 12.83 seconds
Started Jul 26 05:45:31 PM PDT 24
Finished Jul 26 05:45:44 PM PDT 24
Peak memory 248172 kb
Host smart-98ea69d2-3e19-4a21-808e-64bbbf64ac0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=994829341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.994829341
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2529473788
Short name T364
Test name
Test status
Simulation time 11757361 ps
CPU time 1.45 seconds
Started Jul 26 05:45:48 PM PDT 24
Finished Jul 26 05:45:50 PM PDT 24
Peak memory 236556 kb
Host smart-5f37fbc0-7feb-4b4f-ad74-b1242ada924a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2529473788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2529473788
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.27917186
Short name T176
Test name
Test status
Simulation time 10160741 ps
CPU time 1.27 seconds
Started Jul 26 05:45:48 PM PDT 24
Finished Jul 26 05:45:50 PM PDT 24
Peak memory 236428 kb
Host smart-c5fc8d41-faa8-457d-94f1-e8c9548837d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=27917186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.27917186
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3528986282
Short name T784
Test name
Test status
Simulation time 10715168 ps
CPU time 1.59 seconds
Started Jul 26 05:45:48 PM PDT 24
Finished Jul 26 05:45:50 PM PDT 24
Peak memory 236572 kb
Host smart-ce94490b-8a70-4a31-9b88-49341468887d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3528986282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3528986282
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1875586215
Short name T782
Test name
Test status
Simulation time 12463628 ps
CPU time 1.49 seconds
Started Jul 26 05:45:44 PM PDT 24
Finished Jul 26 05:45:46 PM PDT 24
Peak memory 236620 kb
Host smart-58db75c2-9f2f-457d-8167-e69391aa095c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1875586215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1875586215
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1729215575
Short name T750
Test name
Test status
Simulation time 21000851 ps
CPU time 1.4 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 237428 kb
Host smart-9ee2fd80-a8af-41c4-b844-6c13751d1f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1729215575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1729215575
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1562965083
Short name T818
Test name
Test status
Simulation time 25534367 ps
CPU time 1.57 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 236476 kb
Host smart-ff8acf91-042e-422e-92cb-a34406992121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1562965083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1562965083
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.973032685
Short name T723
Test name
Test status
Simulation time 14273282 ps
CPU time 1.4 seconds
Started Jul 26 05:45:47 PM PDT 24
Finished Jul 26 05:45:49 PM PDT 24
Peak memory 237432 kb
Host smart-4ca38c26-daef-4408-abbf-94117e03e599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=973032685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.973032685
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.372278956
Short name T820
Test name
Test status
Simulation time 8353747 ps
CPU time 1.38 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 237432 kb
Host smart-9ea73740-db5f-44d6-a491-e6eaa1cbebfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=372278956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.372278956
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2309720573
Short name T759
Test name
Test status
Simulation time 25642097 ps
CPU time 1.53 seconds
Started Jul 26 05:45:49 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 236516 kb
Host smart-e26ae53a-88ed-4297-ab26-2f08a782cad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2309720573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2309720573
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1928390896
Short name T747
Test name
Test status
Simulation time 7807953 ps
CPU time 1.62 seconds
Started Jul 26 05:45:56 PM PDT 24
Finished Jul 26 05:45:58 PM PDT 24
Peak memory 237428 kb
Host smart-a78cd948-12b2-4cdf-a39d-6808286f9716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1928390896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1928390896
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3576806855
Short name T797
Test name
Test status
Simulation time 107253094 ps
CPU time 5 seconds
Started Jul 26 05:45:25 PM PDT 24
Finished Jul 26 05:45:30 PM PDT 24
Peak memory 240872 kb
Host smart-acbad805-e2c2-4f3b-ad17-bde113b61221
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576806855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3576806855
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1678294677
Short name T779
Test name
Test status
Simulation time 125949668 ps
CPU time 5.33 seconds
Started Jul 26 05:45:16 PM PDT 24
Finished Jul 26 05:45:21 PM PDT 24
Peak memory 240332 kb
Host smart-1d3bf4a9-0194-40f2-850e-05eb90d94a85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1678294677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1678294677
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2758082986
Short name T786
Test name
Test status
Simulation time 10841777 ps
CPU time 1.64 seconds
Started Jul 26 05:45:29 PM PDT 24
Finished Jul 26 05:45:31 PM PDT 24
Peak memory 237500 kb
Host smart-14700ecf-260f-400d-a87d-3e587d213d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2758082986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2758082986
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3010182812
Short name T213
Test name
Test status
Simulation time 2858763944 ps
CPU time 39.45 seconds
Started Jul 26 05:45:27 PM PDT 24
Finished Jul 26 05:46:06 PM PDT 24
Peak memory 245756 kb
Host smart-13b98dda-ae47-494b-b86e-b0f2cd8a6313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3010182812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3010182812
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2889866598
Short name T162
Test name
Test status
Simulation time 4839847517 ps
CPU time 178.15 seconds
Started Jul 26 05:45:12 PM PDT 24
Finished Jul 26 05:48:11 PM PDT 24
Peak memory 257252 kb
Host smart-bb48764f-ef5b-4071-841b-440c7d7b0f36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2889866598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2889866598
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.443116029
Short name T164
Test name
Test status
Simulation time 16281835436 ps
CPU time 583.28 seconds
Started Jul 26 05:45:22 PM PDT 24
Finished Jul 26 05:55:05 PM PDT 24
Peak memory 272532 kb
Host smart-6d189794-add9-45d5-b64d-f98ea1aaae16
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443116029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.443116029
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3516420649
Short name T754
Test name
Test status
Simulation time 214117340 ps
CPU time 8.16 seconds
Started Jul 26 05:45:30 PM PDT 24
Finished Jul 26 05:45:38 PM PDT 24
Peak memory 254224 kb
Host smart-8f4635ac-476d-4134-9568-5dc6e4c1acac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3516420649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3516420649
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2388711775
Short name T731
Test name
Test status
Simulation time 154205226 ps
CPU time 10.42 seconds
Started Jul 26 05:45:29 PM PDT 24
Finished Jul 26 05:45:40 PM PDT 24
Peak memory 252052 kb
Host smart-050cf0f9-8f42-4eb2-aadd-4a2fc3264a97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388711775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2388711775
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1194805673
Short name T210
Test name
Test status
Simulation time 132597723 ps
CPU time 10.38 seconds
Started Jul 26 05:45:15 PM PDT 24
Finished Jul 26 05:45:31 PM PDT 24
Peak memory 237496 kb
Host smart-d6987385-64a4-43c9-8a39-ff3e6070698c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1194805673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1194805673
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3044734779
Short name T365
Test name
Test status
Simulation time 8067668 ps
CPU time 1.49 seconds
Started Jul 26 05:45:27 PM PDT 24
Finished Jul 26 05:45:29 PM PDT 24
Peak memory 236596 kb
Host smart-62b537d6-c4f2-4f01-912a-cbd0db33943b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3044734779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3044734779
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3189049790
Short name T727
Test name
Test status
Simulation time 672795422 ps
CPU time 20.49 seconds
Started Jul 26 05:45:31 PM PDT 24
Finished Jul 26 05:45:51 PM PDT 24
Peak memory 248624 kb
Host smart-230cd55c-ffbc-43ee-880e-8a5ad2e0c89b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3189049790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3189049790
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.477384383
Short name T138
Test name
Test status
Simulation time 2810625935 ps
CPU time 188.43 seconds
Started Jul 26 05:45:30 PM PDT 24
Finished Jul 26 05:48:39 PM PDT 24
Peak memory 267960 kb
Host smart-1b678a3e-2317-4319-845b-fb9561ce3b8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=477384383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.477384383
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1892771610
Short name T151
Test name
Test status
Simulation time 102570147363 ps
CPU time 559.88 seconds
Started Jul 26 05:45:17 PM PDT 24
Finished Jul 26 05:54:37 PM PDT 24
Peak memory 265392 kb
Host smart-bb89415b-068b-474d-9ec3-95e48615d35e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892771610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1892771610
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2584634683
Short name T792
Test name
Test status
Simulation time 253173638 ps
CPU time 9.5 seconds
Started Jul 26 05:45:30 PM PDT 24
Finished Jul 26 05:45:40 PM PDT 24
Peak memory 253720 kb
Host smart-874142d8-62b8-488a-bec4-f9dcc39dfcf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2584634683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2584634683
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3915714940
Short name T748
Test name
Test status
Simulation time 409661070 ps
CPU time 8.08 seconds
Started Jul 26 05:45:28 PM PDT 24
Finished Jul 26 05:45:36 PM PDT 24
Peak memory 240720 kb
Host smart-ccc7887c-dff0-460a-9bff-6e6c65816dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915714940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3915714940
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1944086252
Short name T781
Test name
Test status
Simulation time 99803501 ps
CPU time 8.83 seconds
Started Jul 26 05:45:31 PM PDT 24
Finished Jul 26 05:45:40 PM PDT 24
Peak memory 240424 kb
Host smart-5a8622fd-4598-4230-b198-c44d06c069e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1944086252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1944086252
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3308227961
Short name T743
Test name
Test status
Simulation time 28679426 ps
CPU time 1.33 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:39 PM PDT 24
Peak memory 237460 kb
Host smart-4f0a5096-13e1-407c-bb2a-43138bbd7916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3308227961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3308227961
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3196275442
Short name T212
Test name
Test status
Simulation time 315247341 ps
CPU time 17.56 seconds
Started Jul 26 05:45:28 PM PDT 24
Finished Jul 26 05:45:45 PM PDT 24
Peak memory 240404 kb
Host smart-b31a7124-3e8a-4dde-af95-9ee09e1f794e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3196275442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3196275442
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2877578009
Short name T135
Test name
Test status
Simulation time 4627658116 ps
CPU time 330.71 seconds
Started Jul 26 05:45:18 PM PDT 24
Finished Jul 26 05:50:49 PM PDT 24
Peak memory 265320 kb
Host smart-ea1edd8a-c733-4cd1-a062-ab6871d98962
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2877578009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2877578009
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2488205428
Short name T757
Test name
Test status
Simulation time 53784962 ps
CPU time 7.39 seconds
Started Jul 26 05:45:30 PM PDT 24
Finished Jul 26 05:45:37 PM PDT 24
Peak memory 248672 kb
Host smart-f1f04ada-edf7-4868-a9af-8a9b54705077
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2488205428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2488205428
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4286489637
Short name T218
Test name
Test status
Simulation time 412327621 ps
CPU time 8.76 seconds
Started Jul 26 05:45:29 PM PDT 24
Finished Jul 26 05:45:38 PM PDT 24
Peak memory 254884 kb
Host smart-a6992925-e61e-4676-a718-80081defedac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286489637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4286489637
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1716836971
Short name T805
Test name
Test status
Simulation time 34112955 ps
CPU time 3.44 seconds
Started Jul 26 05:45:40 PM PDT 24
Finished Jul 26 05:45:44 PM PDT 24
Peak memory 237400 kb
Host smart-a3e0f570-65a5-4224-8654-b09dd4bef47b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1716836971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1716836971
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.386414898
Short name T362
Test name
Test status
Simulation time 8414102 ps
CPU time 1.39 seconds
Started Jul 26 05:45:15 PM PDT 24
Finished Jul 26 05:45:16 PM PDT 24
Peak memory 236488 kb
Host smart-a739108e-a0fb-46cc-92ca-5b7c79ec495d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=386414898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.386414898
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2467367458
Short name T790
Test name
Test status
Simulation time 2535270321 ps
CPU time 37.41 seconds
Started Jul 26 05:45:27 PM PDT 24
Finished Jul 26 05:46:05 PM PDT 24
Peak memory 244892 kb
Host smart-02399162-90e1-4c9e-b444-954457b7e5f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2467367458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2467367458
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.59173760
Short name T156
Test name
Test status
Simulation time 2178420956 ps
CPU time 94.18 seconds
Started Jul 26 05:45:31 PM PDT 24
Finished Jul 26 05:47:05 PM PDT 24
Peak memory 265340 kb
Host smart-699868b9-0507-4c0b-bff3-983a4ef02dfd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59173760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors
.59173760
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1693368239
Short name T778
Test name
Test status
Simulation time 526103868 ps
CPU time 18.35 seconds
Started Jul 26 05:45:19 PM PDT 24
Finished Jul 26 05:45:43 PM PDT 24
Peak memory 248676 kb
Host smart-3f5714d2-b955-4be8-a668-58a394d431d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1693368239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1693368239
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1122855735
Short name T273
Test name
Test status
Simulation time 111855671 ps
CPU time 8.39 seconds
Started Jul 26 05:45:37 PM PDT 24
Finished Jul 26 05:45:46 PM PDT 24
Peak memory 240952 kb
Host smart-44522347-9fba-4138-9806-5fdc82cd95ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122855735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1122855735
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.648094709
Short name T777
Test name
Test status
Simulation time 51629968 ps
CPU time 5.08 seconds
Started Jul 26 05:45:31 PM PDT 24
Finished Jul 26 05:45:36 PM PDT 24
Peak memory 236604 kb
Host smart-788884d7-f0b3-44cb-acb7-d62e178a0148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=648094709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.648094709
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4277463511
Short name T766
Test name
Test status
Simulation time 14955038 ps
CPU time 1.44 seconds
Started Jul 26 05:45:34 PM PDT 24
Finished Jul 26 05:45:36 PM PDT 24
Peak memory 236544 kb
Host smart-6bdaaba3-e9f5-4b8a-bf62-f3780bda6f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4277463511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4277463511
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2708750427
Short name T211
Test name
Test status
Simulation time 181831577 ps
CPU time 23.42 seconds
Started Jul 26 05:45:44 PM PDT 24
Finished Jul 26 05:46:08 PM PDT 24
Peak memory 244768 kb
Host smart-d1b884b4-ea88-47e8-aa6a-0edceb275a1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2708750427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2708750427
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3365718997
Short name T139
Test name
Test status
Simulation time 1339729784 ps
CPU time 92.81 seconds
Started Jul 26 05:45:27 PM PDT 24
Finished Jul 26 05:47:00 PM PDT 24
Peak memory 265296 kb
Host smart-6a672b63-8463-46bf-9e32-9449f008236a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3365718997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3365718997
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1986636293
Short name T265
Test name
Test status
Simulation time 159564602 ps
CPU time 10.62 seconds
Started Jul 26 05:45:26 PM PDT 24
Finished Jul 26 05:45:37 PM PDT 24
Peak memory 248660 kb
Host smart-f12968c4-eb0e-437e-a2e0-9abcfd8c79ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1986636293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1986636293
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3653712277
Short name T422
Test name
Test status
Simulation time 30470238683 ps
CPU time 1753.64 seconds
Started Jul 26 05:03:12 PM PDT 24
Finished Jul 26 05:32:26 PM PDT 24
Peak memory 273380 kb
Host smart-a7a8c215-5c37-4b3f-9250-68f06e631cda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653712277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3653712277
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1821969192
Short name T385
Test name
Test status
Simulation time 119390383 ps
CPU time 8.06 seconds
Started Jul 26 05:02:58 PM PDT 24
Finished Jul 26 05:03:06 PM PDT 24
Peak memory 248692 kb
Host smart-ec3a73f8-ec6e-4af5-841b-c45c8da45cd8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1821969192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1821969192
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2255087198
Short name T429
Test name
Test status
Simulation time 7267712140 ps
CPU time 132.48 seconds
Started Jul 26 05:03:01 PM PDT 24
Finished Jul 26 05:05:14 PM PDT 24
Peak memory 256044 kb
Host smart-fb5ebb35-6dad-44ff-8738-7906c149f70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550
87198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2255087198
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3574383675
Short name T549
Test name
Test status
Simulation time 1748248146 ps
CPU time 46.76 seconds
Started Jul 26 05:02:56 PM PDT 24
Finished Jul 26 05:03:43 PM PDT 24
Peak memory 248420 kb
Host smart-5df24de9-0805-4562-859b-a7b40c729546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35743
83675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3574383675
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2527388966
Short name T572
Test name
Test status
Simulation time 30316016627 ps
CPU time 1169.31 seconds
Started Jul 26 05:03:14 PM PDT 24
Finished Jul 26 05:22:46 PM PDT 24
Peak memory 289736 kb
Host smart-7913e50a-7073-48a1-b7b1-9ab4ea56e85f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527388966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2527388966
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1525389262
Short name T511
Test name
Test status
Simulation time 43144424978 ps
CPU time 1397.82 seconds
Started Jul 26 05:02:55 PM PDT 24
Finished Jul 26 05:26:13 PM PDT 24
Peak memory 289604 kb
Host smart-0079c2bb-004a-4793-baea-75d5e93a0d93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525389262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1525389262
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1978807253
Short name T254
Test name
Test status
Simulation time 159670330386 ps
CPU time 517 seconds
Started Jul 26 05:02:56 PM PDT 24
Finished Jul 26 05:11:33 PM PDT 24
Peak memory 248632 kb
Host smart-f087806e-3231-4526-a870-9cff680a8d01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978807253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1978807253
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2126127734
Short name T389
Test name
Test status
Simulation time 468705806 ps
CPU time 15.42 seconds
Started Jul 26 05:03:02 PM PDT 24
Finished Jul 26 05:03:18 PM PDT 24
Peak memory 248700 kb
Host smart-15a7864f-eae5-464e-b455-f882fc898b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21261
27734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2126127734
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.556901784
Short name T96
Test name
Test status
Simulation time 1860520932 ps
CPU time 32.9 seconds
Started Jul 26 05:02:51 PM PDT 24
Finished Jul 26 05:03:24 PM PDT 24
Peak memory 256908 kb
Host smart-6c2e3b7e-7dec-4e59-8794-87d65dae25a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55690
1784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.556901784
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.630664913
Short name T33
Test name
Test status
Simulation time 797326084 ps
CPU time 12.23 seconds
Started Jul 26 05:02:58 PM PDT 24
Finished Jul 26 05:03:10 PM PDT 24
Peak memory 276608 kb
Host smart-dda61e37-cea4-4597-a3e3-1e8863ee078b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=630664913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.630664913
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3049823048
Short name T574
Test name
Test status
Simulation time 498251945 ps
CPU time 3.86 seconds
Started Jul 26 05:03:04 PM PDT 24
Finished Jul 26 05:03:08 PM PDT 24
Peak memory 249252 kb
Host smart-e21af956-cddb-409b-9b25-89eb804746b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30498
23048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3049823048
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.749375421
Short name T493
Test name
Test status
Simulation time 3715593279 ps
CPU time 29.17 seconds
Started Jul 26 05:03:04 PM PDT 24
Finished Jul 26 05:03:34 PM PDT 24
Peak memory 255996 kb
Host smart-7199750f-b27e-4a90-b6cd-443b71ba12f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74937
5421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.749375421
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2800794349
Short name T282
Test name
Test status
Simulation time 160706246572 ps
CPU time 4098.02 seconds
Started Jul 26 05:03:02 PM PDT 24
Finished Jul 26 06:11:20 PM PDT 24
Peak memory 338864 kb
Host smart-b0827bd1-00db-4a22-af54-10d1bbd71295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800794349 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2800794349
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1498047899
Short name T232
Test name
Test status
Simulation time 142434843 ps
CPU time 3.63 seconds
Started Jul 26 05:03:13 PM PDT 24
Finished Jul 26 05:03:16 PM PDT 24
Peak memory 249032 kb
Host smart-72014ccf-9aaa-4639-aa87-131921e34708
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1498047899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1498047899
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2716178012
Short name T102
Test name
Test status
Simulation time 64138666074 ps
CPU time 1132.31 seconds
Started Jul 26 05:03:15 PM PDT 24
Finished Jul 26 05:22:07 PM PDT 24
Peak memory 265168 kb
Host smart-e736f818-7d16-4507-8211-467bc4a8567f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716178012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2716178012
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3438668859
Short name T393
Test name
Test status
Simulation time 2021177668 ps
CPU time 26.44 seconds
Started Jul 26 05:03:08 PM PDT 24
Finished Jul 26 05:03:34 PM PDT 24
Peak memory 248652 kb
Host smart-99bc897e-7356-4a3e-88f3-9adc76e06476
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3438668859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3438668859
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2704666166
Short name T401
Test name
Test status
Simulation time 1238512147 ps
CPU time 55.24 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:04:01 PM PDT 24
Peak memory 256940 kb
Host smart-2858cfc0-c132-4f1c-a4d4-7f0d14e815aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27046
66166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2704666166
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.4080763282
Short name T695
Test name
Test status
Simulation time 254524156 ps
CPU time 21.73 seconds
Started Jul 26 05:03:10 PM PDT 24
Finished Jul 26 05:03:31 PM PDT 24
Peak memory 248572 kb
Host smart-135c190a-b3e4-478c-b5db-3e8e968692f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40807
63282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4080763282
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1241831449
Short name T542
Test name
Test status
Simulation time 7859996288 ps
CPU time 691.1 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:14:55 PM PDT 24
Peak memory 273476 kb
Host smart-012a1124-5d04-4d8f-b9e7-4d2f399dee51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241831449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1241831449
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1401051547
Short name T442
Test name
Test status
Simulation time 38597957247 ps
CPU time 2310.23 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:42:01 PM PDT 24
Peak memory 283208 kb
Host smart-03efad73-2a2e-40ed-9fd4-2245b40c1534
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401051547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1401051547
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2669438554
Short name T588
Test name
Test status
Simulation time 2721604305 ps
CPU time 115.01 seconds
Started Jul 26 05:03:13 PM PDT 24
Finished Jul 26 05:05:09 PM PDT 24
Peak memory 248828 kb
Host smart-8f91996b-1695-47ea-b0b6-5416df0e1130
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669438554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2669438554
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2973624923
Short name T524
Test name
Test status
Simulation time 268018636 ps
CPU time 21.54 seconds
Started Jul 26 05:03:21 PM PDT 24
Finished Jul 26 05:03:42 PM PDT 24
Peak memory 256080 kb
Host smart-d4fd2715-3190-4317-a8dd-6d6ade794899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29736
24923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2973624923
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3337031360
Short name T32
Test name
Test status
Simulation time 642873814 ps
CPU time 10.65 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:03:17 PM PDT 24
Peak memory 277484 kb
Host smart-8aab345a-d447-40c1-b1ce-d1a73a78a89a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3337031360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3337031360
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3800949822
Short name T496
Test name
Test status
Simulation time 953295765 ps
CPU time 49.34 seconds
Started Jul 26 05:03:11 PM PDT 24
Finished Jul 26 05:04:01 PM PDT 24
Peak memory 256312 kb
Host smart-c8f0c97f-782d-40db-bea4-08e9bc0764ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
49822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3800949822
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.216401943
Short name T592
Test name
Test status
Simulation time 4296185805 ps
CPU time 58.11 seconds
Started Jul 26 05:02:59 PM PDT 24
Finished Jul 26 05:03:57 PM PDT 24
Peak memory 256856 kb
Host smart-3f08705d-3ab4-479d-99ce-cfa85368ee3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21640
1943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.216401943
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.267793965
Short name T391
Test name
Test status
Simulation time 8394104592 ps
CPU time 892.14 seconds
Started Jul 26 05:03:08 PM PDT 24
Finished Jul 26 05:18:01 PM PDT 24
Peak memory 273108 kb
Host smart-3324b830-8012-4eed-aaa2-3fe52eefe633
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267793965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.267793965
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2337243371
Short name T643
Test name
Test status
Simulation time 181594853 ps
CPU time 10.24 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:03:34 PM PDT 24
Peak memory 248808 kb
Host smart-dcf21c15-a0b7-4fcc-9a03-0a0ba13275d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2337243371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2337243371
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1986481421
Short name T439
Test name
Test status
Simulation time 6246101283 ps
CPU time 362.66 seconds
Started Jul 26 05:03:11 PM PDT 24
Finished Jul 26 05:09:14 PM PDT 24
Peak memory 256872 kb
Host smart-fcbdcdb8-40f0-45ba-8425-792672f26384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19864
81421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1986481421
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1595783392
Short name T629
Test name
Test status
Simulation time 133627987 ps
CPU time 7.37 seconds
Started Jul 26 05:03:41 PM PDT 24
Finished Jul 26 05:03:49 PM PDT 24
Peak memory 254984 kb
Host smart-a06be2ed-5df3-4c78-97f2-bac50d476ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15957
83392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1595783392
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2779568764
Short name T354
Test name
Test status
Simulation time 38161085194 ps
CPU time 1121.58 seconds
Started Jul 26 05:03:38 PM PDT 24
Finished Jul 26 05:22:20 PM PDT 24
Peak memory 283476 kb
Host smart-c498e941-448f-4976-83a6-9872f7733537
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779568764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2779568764
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1161784500
Short name T600
Test name
Test status
Simulation time 156728559492 ps
CPU time 2316.4 seconds
Started Jul 26 05:03:35 PM PDT 24
Finished Jul 26 05:42:11 PM PDT 24
Peak memory 273536 kb
Host smart-620910ba-efeb-4f30-80a8-e9e8e9e75c92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161784500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1161784500
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2561390847
Short name T337
Test name
Test status
Simulation time 7370685765 ps
CPU time 158 seconds
Started Jul 26 05:03:22 PM PDT 24
Finished Jul 26 05:06:00 PM PDT 24
Peak memory 248612 kb
Host smart-93c8c785-446e-4bae-a1e8-b801860fb7da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561390847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2561390847
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.605771926
Short name T20
Test name
Test status
Simulation time 456712276 ps
CPU time 12.41 seconds
Started Jul 26 05:03:13 PM PDT 24
Finished Jul 26 05:03:26 PM PDT 24
Peak memory 248832 kb
Host smart-951804ee-95ae-4d6c-ba66-a1a20a97f646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60577
1926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.605771926
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4052036349
Short name T468
Test name
Test status
Simulation time 2621085658 ps
CPU time 41.98 seconds
Started Jul 26 05:03:11 PM PDT 24
Finished Jul 26 05:03:53 PM PDT 24
Peak memory 248780 kb
Host smart-9ad1e99a-840d-4257-bee0-68caa6d58895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40520
36349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4052036349
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.608755402
Short name T631
Test name
Test status
Simulation time 2837492541 ps
CPU time 38.24 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:04:04 PM PDT 24
Peak memory 249124 kb
Host smart-ab111cc9-9d82-4b8b-b07e-c1bd5252228b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60875
5402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.608755402
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3004070107
Short name T421
Test name
Test status
Simulation time 415837199 ps
CPU time 20.73 seconds
Started Jul 26 05:03:08 PM PDT 24
Finished Jul 26 05:03:29 PM PDT 24
Peak memory 256976 kb
Host smart-7b5b7cdd-6267-41ea-b229-ee6750d19629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30040
70107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3004070107
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2412590470
Short name T602
Test name
Test status
Simulation time 150186650425 ps
CPU time 2502.89 seconds
Started Jul 26 05:03:26 PM PDT 24
Finished Jul 26 05:45:09 PM PDT 24
Peak memory 289144 kb
Host smart-8dec0697-5bae-4823-a810-d5c359348544
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412590470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2412590470
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3128822041
Short name T224
Test name
Test status
Simulation time 38582436 ps
CPU time 3.72 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:03:31 PM PDT 24
Peak memory 249104 kb
Host smart-173fcfbf-4337-4d21-a1fb-f542ebd670f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3128822041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3128822041
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1075827832
Short name T398
Test name
Test status
Simulation time 10765071114 ps
CPU time 1284.58 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:24:49 PM PDT 24
Peak memory 289688 kb
Host smart-ce8f8b78-6fed-4ece-b691-4e3c6f66fd2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075827832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1075827832
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2327927753
Short name T485
Test name
Test status
Simulation time 1306968952 ps
CPU time 9.57 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:03:33 PM PDT 24
Peak memory 248732 kb
Host smart-992c96d9-ea72-401f-8c8a-02c2a1ca787b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2327927753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2327927753
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.885983923
Short name T554
Test name
Test status
Simulation time 9340036240 ps
CPU time 251.16 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:07:55 PM PDT 24
Peak memory 256372 kb
Host smart-d997a034-0f5c-44da-9e40-2c8a5a5367c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88598
3923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.885983923
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3963929549
Short name T715
Test name
Test status
Simulation time 218740060 ps
CPU time 28.77 seconds
Started Jul 26 05:03:38 PM PDT 24
Finished Jul 26 05:04:07 PM PDT 24
Peak memory 248756 kb
Host smart-aea25e84-6b01-44ee-a9a7-e541debb9a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39639
29549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3963929549
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1604515200
Short name T199
Test name
Test status
Simulation time 31263997913 ps
CPU time 685.56 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:14:56 PM PDT 24
Peak memory 271344 kb
Host smart-5b0fbb8d-b4e6-431b-8847-588cdc1f7c3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604515200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1604515200
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2911585743
Short name T465
Test name
Test status
Simulation time 27575252147 ps
CPU time 127.25 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:05:39 PM PDT 24
Peak memory 247892 kb
Host smart-382a33ed-b6f5-4d0c-9712-82957ad2f91f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911585743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2911585743
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.452024052
Short name T443
Test name
Test status
Simulation time 1629532667 ps
CPU time 45.37 seconds
Started Jul 26 05:03:41 PM PDT 24
Finished Jul 26 05:04:27 PM PDT 24
Peak memory 256200 kb
Host smart-760ff848-b899-4d2d-9c3a-3f68c4e1b6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45202
4052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.452024052
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2446714917
Short name T607
Test name
Test status
Simulation time 2600897447 ps
CPU time 47.7 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:04:33 PM PDT 24
Peak memory 248960 kb
Host smart-6bcaa123-7ede-4e27-8dcb-b685c69a4900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24467
14917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2446714917
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3174272179
Short name T101
Test name
Test status
Simulation time 788612393 ps
CPU time 58.19 seconds
Started Jul 26 05:03:21 PM PDT 24
Finished Jul 26 05:04:20 PM PDT 24
Peak memory 249920 kb
Host smart-52996f79-435f-4e80-932b-c09e58600e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31742
72179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3174272179
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1666990215
Short name T543
Test name
Test status
Simulation time 6112944042 ps
CPU time 47.41 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:04:15 PM PDT 24
Peak memory 256244 kb
Host smart-e389b0e0-583b-4385-8197-7c3e0a96d789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16669
90215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1666990215
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.725688394
Short name T436
Test name
Test status
Simulation time 32067484024 ps
CPU time 2067.15 seconds
Started Jul 26 05:03:20 PM PDT 24
Finished Jul 26 05:37:48 PM PDT 24
Peak memory 285820 kb
Host smart-d7aa7a3c-50b0-4869-91b9-4450922955d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725688394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.725688394
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3932709199
Short name T219
Test name
Test status
Simulation time 16148271 ps
CPU time 2.49 seconds
Started Jul 26 05:03:35 PM PDT 24
Finished Jul 26 05:03:37 PM PDT 24
Peak memory 249024 kb
Host smart-eaa13304-38a5-4bc4-9f4b-4bf5accee3fb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3932709199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3932709199
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2244360518
Short name T271
Test name
Test status
Simulation time 38500838275 ps
CPU time 2491.08 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:44:56 PM PDT 24
Peak memory 287312 kb
Host smart-0ebfa0dc-9e7d-436f-b42e-9a8e71b8392c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244360518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2244360518
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1282044003
Short name T239
Test name
Test status
Simulation time 1737614444 ps
CPU time 29.94 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:03:57 PM PDT 24
Peak memory 248788 kb
Host smart-54d2066f-6da4-427f-9d1a-f15b6688cd78
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1282044003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1282044003
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1642043049
Short name T509
Test name
Test status
Simulation time 2950993705 ps
CPU time 188.29 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:06:35 PM PDT 24
Peak memory 256164 kb
Host smart-073a8500-3a65-4e63-9538-47aca2f2da69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16420
43049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1642043049
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2624482321
Short name T373
Test name
Test status
Simulation time 157384816 ps
CPU time 10.14 seconds
Started Jul 26 05:03:29 PM PDT 24
Finished Jul 26 05:03:39 PM PDT 24
Peak memory 254500 kb
Host smart-cf5cbeb7-cec2-49c0-b39e-86f633732e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26244
82321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2624482321
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3830619581
Short name T349
Test name
Test status
Simulation time 16691569425 ps
CPU time 1511.72 seconds
Started Jul 26 05:03:35 PM PDT 24
Finished Jul 26 05:28:47 PM PDT 24
Peak memory 288264 kb
Host smart-bf4e2499-7817-49ae-9436-cbeb2efa82b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830619581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3830619581
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3746499795
Short name T655
Test name
Test status
Simulation time 35272041157 ps
CPU time 1884.77 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:34:48 PM PDT 24
Peak memory 273320 kb
Host smart-f26b8573-26c9-4f0a-bd15-4a0e204cfff7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746499795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3746499795
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.202771108
Short name T329
Test name
Test status
Simulation time 54431674207 ps
CPU time 585.08 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:13:15 PM PDT 24
Peak memory 248888 kb
Host smart-f2e50d3e-0cb3-40a4-8268-74fc7c3d924e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202771108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.202771108
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2171205383
Short name T681
Test name
Test status
Simulation time 167863562 ps
CPU time 12.7 seconds
Started Jul 26 05:03:21 PM PDT 24
Finished Jul 26 05:03:39 PM PDT 24
Peak memory 248648 kb
Host smart-e9e3f14f-8d95-415f-92e5-0c757881801a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21712
05383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2171205383
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.610657851
Short name T497
Test name
Test status
Simulation time 3105638223 ps
CPU time 15.06 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:03:45 PM PDT 24
Peak memory 256156 kb
Host smart-52c8c60b-aaa0-4cb6-a13d-63a4dd368b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61065
7851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.610657851
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2248878058
Short name T513
Test name
Test status
Simulation time 1985221414 ps
CPU time 34.32 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:04:19 PM PDT 24
Peak memory 256024 kb
Host smart-949d766e-39c8-464a-a40d-b84d55158d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22488
78058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2248878058
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2269382887
Short name T620
Test name
Test status
Simulation time 274551903 ps
CPU time 26.31 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:03:51 PM PDT 24
Peak memory 256528 kb
Host smart-aac3906b-bb66-4b20-bfc6-cbe016b2a753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22693
82887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2269382887
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3986317621
Short name T250
Test name
Test status
Simulation time 24480142684 ps
CPU time 1524.1 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:29:09 PM PDT 24
Peak memory 289416 kb
Host smart-6b151f78-5c0b-448f-9934-b14fcc379ff9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986317621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3986317621
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4278415613
Short name T236
Test name
Test status
Simulation time 33848534 ps
CPU time 2.54 seconds
Started Jul 26 05:03:26 PM PDT 24
Finished Jul 26 05:03:29 PM PDT 24
Peak memory 249124 kb
Host smart-d8dccc63-1313-4772-9644-aa3a4478efbd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4278415613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4278415613
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3741726335
Short name T91
Test name
Test status
Simulation time 12272901227 ps
CPU time 1227.65 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:23:51 PM PDT 24
Peak memory 284500 kb
Host smart-981bc13d-2302-47de-a63e-1c9f2bbec804
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741726335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3741726335
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1155673311
Short name T379
Test name
Test status
Simulation time 1749199344 ps
CPU time 19.59 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:03:52 PM PDT 24
Peak memory 248708 kb
Host smart-cffc2635-7a10-4bdb-b743-1592bcc68b3c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1155673311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1155673311
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3350799254
Short name T268
Test name
Test status
Simulation time 15764382642 ps
CPU time 157.63 seconds
Started Jul 26 05:03:22 PM PDT 24
Finished Jul 26 05:05:59 PM PDT 24
Peak memory 256908 kb
Host smart-a3b6fcb0-2592-4960-af3d-191e9d7e6008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33507
99254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3350799254
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2453839817
Short name T557
Test name
Test status
Simulation time 2085488517 ps
CPU time 39.29 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:04:06 PM PDT 24
Peak memory 255920 kb
Host smart-8e538255-11a7-43b5-b94c-a2d0fb1c1ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24538
39817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2453839817
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.48775608
Short name T302
Test name
Test status
Simulation time 7908265982 ps
CPU time 770.06 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:16:18 PM PDT 24
Peak memory 273220 kb
Host smart-4117829e-9925-43ad-aa8b-4d25f090b7af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48775608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.48775608
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.921048267
Short name T127
Test name
Test status
Simulation time 22149151684 ps
CPU time 1448.6 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:27:39 PM PDT 24
Peak memory 273008 kb
Host smart-d4058a81-f2b1-4580-8727-982cf217c4b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921048267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.921048267
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.394271735
Short name T323
Test name
Test status
Simulation time 12196964744 ps
CPU time 492.83 seconds
Started Jul 26 05:03:26 PM PDT 24
Finished Jul 26 05:11:39 PM PDT 24
Peak memory 248860 kb
Host smart-2fe2eb7d-7896-434e-97ba-9382f79fbcfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394271735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.394271735
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2501205237
Short name T238
Test name
Test status
Simulation time 324511756 ps
CPU time 22.09 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:03:50 PM PDT 24
Peak memory 256084 kb
Host smart-7768efab-376a-4097-8044-6443f646b2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25012
05237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2501205237
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.494781435
Short name T410
Test name
Test status
Simulation time 2842336846 ps
CPU time 38.85 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:04:03 PM PDT 24
Peak memory 248204 kb
Host smart-22330fc2-9017-4c70-b3c9-43694e1230a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49478
1435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.494781435
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3327751894
Short name T453
Test name
Test status
Simulation time 6818075548 ps
CPU time 36.39 seconds
Started Jul 26 05:03:36 PM PDT 24
Finished Jul 26 05:04:12 PM PDT 24
Peak memory 256984 kb
Host smart-33400dd9-3d2e-4a2b-8218-e26b407b12d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277
51894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3327751894
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1153383135
Short name T235
Test name
Test status
Simulation time 78306475 ps
CPU time 3.41 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:03:36 PM PDT 24
Peak memory 249052 kb
Host smart-fe8ca1a9-28cc-4419-ae3f-dfe27c6bc50e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1153383135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1153383135
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3341097295
Short name T129
Test name
Test status
Simulation time 99400937223 ps
CPU time 1619.75 seconds
Started Jul 26 05:03:22 PM PDT 24
Finished Jul 26 05:30:22 PM PDT 24
Peak memory 273372 kb
Host smart-31a848ac-eb34-4a4d-bddf-eb77cc89a16b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341097295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3341097295
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1472921638
Short name T596
Test name
Test status
Simulation time 1703832059 ps
CPU time 26.36 seconds
Started Jul 26 05:03:37 PM PDT 24
Finished Jul 26 05:04:03 PM PDT 24
Peak memory 248800 kb
Host smart-5069e9ad-9051-45eb-8702-6da60d835275
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1472921638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1472921638
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2308756614
Short name T514
Test name
Test status
Simulation time 32756704332 ps
CPU time 331.39 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:08:59 PM PDT 24
Peak memory 256360 kb
Host smart-8c3d7929-8652-4429-a61d-05e08303d63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23087
56614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2308756614
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3264841223
Short name T131
Test name
Test status
Simulation time 2556947708 ps
CPU time 43.23 seconds
Started Jul 26 05:03:46 PM PDT 24
Finished Jul 26 05:04:29 PM PDT 24
Peak memory 257080 kb
Host smart-ee6cc62c-c187-409a-82ea-be041de8ccfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32648
41223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3264841223
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.939317360
Short name T630
Test name
Test status
Simulation time 221455305480 ps
CPU time 3405.72 seconds
Started Jul 26 05:03:36 PM PDT 24
Finished Jul 26 06:00:23 PM PDT 24
Peak memory 288704 kb
Host smart-b1ab8489-e634-48b6-b76f-90a3d7f09e79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939317360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.939317360
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2839335439
Short name T458
Test name
Test status
Simulation time 10905376366 ps
CPU time 120.65 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:05:25 PM PDT 24
Peak memory 248724 kb
Host smart-be16b5cc-2ac4-409a-ac11-56b99db476db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839335439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2839335439
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.654538847
Short name T110
Test name
Test status
Simulation time 1039663106 ps
CPU time 58.43 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:04:25 PM PDT 24
Peak memory 256936 kb
Host smart-b8455b85-7c24-4f96-90ad-6cd235888938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65453
8847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.654538847
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1992549473
Short name T252
Test name
Test status
Simulation time 33598523 ps
CPU time 3.01 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:03:31 PM PDT 24
Peak memory 240116 kb
Host smart-219ad228-d37f-4b03-827b-c33297db88f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19925
49473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1992549473
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.4261279658
Short name T517
Test name
Test status
Simulation time 76637844 ps
CPU time 6.94 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:03:30 PM PDT 24
Peak memory 251712 kb
Host smart-c09af548-6cf2-4271-97ed-9bf6ec4a7a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42612
79658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.4261279658
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3581381499
Short name T494
Test name
Test status
Simulation time 37958870254 ps
CPU time 2197.93 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:40:03 PM PDT 24
Peak memory 289856 kb
Host smart-f0477518-cb54-40e0-97f6-e83ba24b63ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581381499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3581381499
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3693824357
Short name T58
Test name
Test status
Simulation time 312514890580 ps
CPU time 5597.41 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 06:36:48 PM PDT 24
Peak memory 322744 kb
Host smart-a4b36835-4815-483a-80af-d5fae416796d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693824357 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3693824357
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.984608148
Short name T225
Test name
Test status
Simulation time 14786868 ps
CPU time 2.25 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:03:32 PM PDT 24
Peak memory 249104 kb
Host smart-b8bc8b1a-3d8e-4ec4-961e-abbabeefbafa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=984608148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.984608148
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2716273415
Short name T383
Test name
Test status
Simulation time 637906408841 ps
CPU time 3082.74 seconds
Started Jul 26 05:03:37 PM PDT 24
Finished Jul 26 05:55:00 PM PDT 24
Peak memory 289000 kb
Host smart-305fbb50-12d6-4158-87b1-c6e52563c24d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716273415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2716273415
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3664288258
Short name T664
Test name
Test status
Simulation time 1978162172 ps
CPU time 24.95 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:04:08 PM PDT 24
Peak memory 248740 kb
Host smart-6bce5559-0601-4566-94da-4cd2232121d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3664288258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3664288258
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2142573084
Short name T51
Test name
Test status
Simulation time 3168057764 ps
CPU time 178.24 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:06:42 PM PDT 24
Peak memory 256520 kb
Host smart-742ce8e4-cd1d-4f5a-a0ac-77773e1a4e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21425
73084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2142573084
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3608970402
Short name T521
Test name
Test status
Simulation time 166586059 ps
CPU time 21.32 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:03:53 PM PDT 24
Peak memory 248372 kb
Host smart-5b845737-46a8-417a-aca0-582a11438d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36089
70402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3608970402
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1942825942
Short name T692
Test name
Test status
Simulation time 218606975205 ps
CPU time 3099.27 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:55:05 PM PDT 24
Peak memory 288920 kb
Host smart-0d07578e-e9f8-464a-baa0-52a695390c34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942825942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1942825942
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2925318023
Short name T325
Test name
Test status
Simulation time 7955163127 ps
CPU time 167.57 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:06:39 PM PDT 24
Peak memory 247600 kb
Host smart-aaf33557-6c5c-4866-bb86-737d8cf0adb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925318023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2925318023
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1634024862
Short name T519
Test name
Test status
Simulation time 305506352 ps
CPU time 23.52 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:03:48 PM PDT 24
Peak memory 256280 kb
Host smart-4148307b-54c2-4c6e-869d-81966ead07a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16340
24862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1634024862
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.945678652
Short name T408
Test name
Test status
Simulation time 1407579715 ps
CPU time 37.72 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:04:06 PM PDT 24
Peak memory 257008 kb
Host smart-c9a4f6e1-1dfe-43ff-95cc-5adec2c9897e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94567
8652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.945678652
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3310040303
Short name T372
Test name
Test status
Simulation time 796600470 ps
CPU time 48.34 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:04:13 PM PDT 24
Peak memory 256976 kb
Host smart-886b3bad-85f0-459e-8778-eec9aca9754d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33100
40303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3310040303
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3527777954
Short name T318
Test name
Test status
Simulation time 18788544518 ps
CPU time 1732.05 seconds
Started Jul 26 05:03:31 PM PDT 24
Finished Jul 26 05:32:23 PM PDT 24
Peak memory 298304 kb
Host smart-d72c8555-486a-4eca-8181-e9a571b21be2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527777954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3527777954
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3343718572
Short name T677
Test name
Test status
Simulation time 396413713019 ps
CPU time 1392.3 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:26:42 PM PDT 24
Peak memory 289524 kb
Host smart-d094bcc3-68f3-45b8-8251-c9839c8061a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343718572 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3343718572
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1718898044
Short name T97
Test name
Test status
Simulation time 51249737491 ps
CPU time 774.8 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:16:22 PM PDT 24
Peak memory 273280 kb
Host smart-2e9b16fa-0ecd-437f-83e0-652924e3f704
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718898044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1718898044
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2207308864
Short name T13
Test name
Test status
Simulation time 768360090 ps
CPU time 13.72 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:03:44 PM PDT 24
Peak memory 248804 kb
Host smart-de9fe33a-8cc7-416f-b85d-0289d864d239
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2207308864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2207308864
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1279215995
Short name T419
Test name
Test status
Simulation time 6938489653 ps
CPU time 101.42 seconds
Started Jul 26 05:03:36 PM PDT 24
Finished Jul 26 05:05:18 PM PDT 24
Peak memory 256608 kb
Host smart-246c8e3d-4117-4aab-b8aa-c35f5e2c3ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12792
15995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1279215995
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.324730421
Short name T606
Test name
Test status
Simulation time 170136294 ps
CPU time 8.32 seconds
Started Jul 26 05:03:36 PM PDT 24
Finished Jul 26 05:03:44 PM PDT 24
Peak memory 254660 kb
Host smart-20eb3b56-14a1-4de2-b7cf-5d7049b7b3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473
0421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.324730421
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2811949148
Short name T49
Test name
Test status
Simulation time 139986620398 ps
CPU time 2049.43 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:37:42 PM PDT 24
Peak memory 273308 kb
Host smart-428808ae-93a1-47e3-8ec2-056f2d754e6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811949148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2811949148
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.207425845
Short name T249
Test name
Test status
Simulation time 45903504 ps
CPU time 3.71 seconds
Started Jul 26 05:03:41 PM PDT 24
Finished Jul 26 05:03:45 PM PDT 24
Peak memory 248772 kb
Host smart-e6b2f8fd-94d9-4450-a08b-9c8e415efeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20742
5845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.207425845
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3854885999
Short name T482
Test name
Test status
Simulation time 204344318 ps
CPU time 14.07 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:03:57 PM PDT 24
Peak memory 248096 kb
Host smart-a8bdb43e-6dc7-4554-85d8-47105ca2adb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38548
85999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3854885999
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3656074919
Short name T285
Test name
Test status
Simulation time 1465066935 ps
CPU time 49.03 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:04:34 PM PDT 24
Peak memory 248236 kb
Host smart-a8b9d0c5-49aa-48f2-a83f-2c5c72b6089b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36560
74919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3656074919
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1214869834
Short name T534
Test name
Test status
Simulation time 1757463919 ps
CPU time 54.85 seconds
Started Jul 26 05:03:35 PM PDT 24
Finished Jul 26 05:04:30 PM PDT 24
Peak memory 256928 kb
Host smart-4e3bc6f8-afea-426a-af91-4c30a9f27763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12148
69834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1214869834
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3154776509
Short name T699
Test name
Test status
Simulation time 308739200915 ps
CPU time 3196.34 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:56:47 PM PDT 24
Peak memory 289552 kb
Host smart-ca27050c-530c-4e42-a535-e37d0c18d4c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154776509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3154776509
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2132762638
Short name T262
Test name
Test status
Simulation time 24942854858 ps
CPU time 1421.6 seconds
Started Jul 26 05:03:36 PM PDT 24
Finished Jul 26 05:27:18 PM PDT 24
Peak memory 285920 kb
Host smart-4852dcfe-1058-45f7-9442-334029a6029a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132762638 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2132762638
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3974519064
Short name T636
Test name
Test status
Simulation time 32024234823 ps
CPU time 1827.23 seconds
Started Jul 26 05:03:40 PM PDT 24
Finished Jul 26 05:34:08 PM PDT 24
Peak memory 273420 kb
Host smart-a0f83174-1f40-42bf-98c9-f38a2c25a300
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974519064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3974519064
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3600345574
Short name T504
Test name
Test status
Simulation time 113380450 ps
CPU time 7.43 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:03:32 PM PDT 24
Peak memory 248712 kb
Host smart-ae65c2c7-2d5e-46ab-8f06-8af88eb38359
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3600345574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3600345574
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3412456455
Short name T424
Test name
Test status
Simulation time 3545514744 ps
CPU time 111.71 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:05:36 PM PDT 24
Peak memory 256476 kb
Host smart-6755dde2-e089-4157-aab5-b5e70c02297a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34124
56455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3412456455
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4076087022
Short name T665
Test name
Test status
Simulation time 1096501245 ps
CPU time 69.16 seconds
Started Jul 26 05:03:48 PM PDT 24
Finished Jul 26 05:04:58 PM PDT 24
Peak memory 248836 kb
Host smart-eaa9783c-7e25-44f8-aae3-149f76ff68dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40760
87022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4076087022
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1012515965
Short name T107
Test name
Test status
Simulation time 10218678453 ps
CPU time 947.87 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:19:20 PM PDT 24
Peak memory 273112 kb
Host smart-01be2a1c-776b-43ff-8ac8-f0b9858f1033
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012515965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1012515965
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.528585082
Short name T15
Test name
Test status
Simulation time 6946882225 ps
CPU time 766.59 seconds
Started Jul 26 05:03:40 PM PDT 24
Finished Jul 26 05:16:27 PM PDT 24
Peak memory 273288 kb
Host smart-70984744-dd9e-4dae-a511-bedf6ac520a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528585082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.528585082
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1838179802
Short name T628
Test name
Test status
Simulation time 68994477751 ps
CPU time 454.06 seconds
Started Jul 26 05:03:36 PM PDT 24
Finished Jul 26 05:11:10 PM PDT 24
Peak memory 248884 kb
Host smart-846ef61f-2e49-43ef-9435-590521f80cc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838179802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1838179802
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.6079596
Short name T384
Test name
Test status
Simulation time 1879104704 ps
CPU time 26.85 seconds
Started Jul 26 05:03:33 PM PDT 24
Finished Jul 26 05:04:00 PM PDT 24
Peak memory 256148 kb
Host smart-213be82c-72e0-4318-b160-2a3044f690ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60795
96 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.6079596
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.4033409424
Short name T538
Test name
Test status
Simulation time 4085945557 ps
CPU time 61.71 seconds
Started Jul 26 05:03:26 PM PDT 24
Finished Jul 26 05:04:28 PM PDT 24
Peak memory 256808 kb
Host smart-3b23e39c-14f5-4b58-8f01-8ea9590c5f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40334
09424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4033409424
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3310056151
Short name T464
Test name
Test status
Simulation time 3200724300 ps
CPU time 56.91 seconds
Started Jul 26 05:03:46 PM PDT 24
Finished Jul 26 05:04:43 PM PDT 24
Peak memory 248900 kb
Host smart-e93ac8a8-8936-4c3a-949f-682f8444b682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33100
56151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3310056151
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2588707251
Short name T82
Test name
Test status
Simulation time 106251968780 ps
CPU time 1564.68 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:29:29 PM PDT 24
Peak memory 273116 kb
Host smart-6053a103-4476-43d7-a22c-b9fec795ee0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588707251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2588707251
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3894711220
Short name T228
Test name
Test status
Simulation time 47541256 ps
CPU time 4.02 seconds
Started Jul 26 05:03:40 PM PDT 24
Finished Jul 26 05:03:45 PM PDT 24
Peak memory 249120 kb
Host smart-ea2607b7-6014-4552-97a3-2573404df78f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3894711220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3894711220
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2160665119
Short name T540
Test name
Test status
Simulation time 158368087972 ps
CPU time 2386.94 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:43:20 PM PDT 24
Peak memory 289112 kb
Host smart-278cf826-9b4d-4494-b4fb-0c6f159eed50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160665119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2160665119
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3614257797
Short name T374
Test name
Test status
Simulation time 1947147398 ps
CPU time 111.71 seconds
Started Jul 26 05:03:31 PM PDT 24
Finished Jul 26 05:05:23 PM PDT 24
Peak memory 256068 kb
Host smart-c9e0d7d3-bbea-4697-9e90-a7345ed45aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36142
57797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3614257797
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2708307192
Short name T27
Test name
Test status
Simulation time 738181633 ps
CPU time 45.33 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:04:30 PM PDT 24
Peak memory 248336 kb
Host smart-f6825bcb-01fd-4570-955f-720f3be8114f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083
07192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2708307192
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.951493462
Short name T544
Test name
Test status
Simulation time 14279412401 ps
CPU time 1267.34 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:24:40 PM PDT 24
Peak memory 289824 kb
Host smart-e5a784c5-ceb9-4c4b-99db-ed6690eb705c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951493462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.951493462
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.37552611
Short name T591
Test name
Test status
Simulation time 25995308464 ps
CPU time 134.71 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:05:47 PM PDT 24
Peak memory 247900 kb
Host smart-714902c9-88c8-4aaa-ae93-45521e02d0ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37552611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.37552611
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1981113733
Short name T428
Test name
Test status
Simulation time 767619050 ps
CPU time 41.11 seconds
Started Jul 26 05:03:41 PM PDT 24
Finished Jul 26 05:04:22 PM PDT 24
Peak memory 256256 kb
Host smart-1fde39c8-7767-4c5c-b2d0-d83777de74dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19811
13733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1981113733
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3120331725
Short name T65
Test name
Test status
Simulation time 3723472019 ps
CPU time 44.82 seconds
Started Jul 26 05:03:47 PM PDT 24
Finished Jul 26 05:04:32 PM PDT 24
Peak memory 248556 kb
Host smart-80bdd5c0-2e2e-4dfa-b167-07696f77e61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31203
31725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3120331725
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1704729760
Short name T3
Test name
Test status
Simulation time 354457813 ps
CPU time 32.96 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:04:00 PM PDT 24
Peak memory 256944 kb
Host smart-b40c4a54-3fe3-48bf-a150-1349ee115a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17047
29760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1704729760
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.4107307924
Short name T690
Test name
Test status
Simulation time 16542710043 ps
CPU time 1495.56 seconds
Started Jul 26 05:03:35 PM PDT 24
Finished Jul 26 05:28:31 PM PDT 24
Peak memory 289288 kb
Host smart-bd4e2a2a-b296-4d0b-85f5-62ca5dda4da3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107307924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.4107307924
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2847587117
Short name T223
Test name
Test status
Simulation time 40400129 ps
CPU time 2.63 seconds
Started Jul 26 05:03:53 PM PDT 24
Finished Jul 26 05:03:56 PM PDT 24
Peak memory 249124 kb
Host smart-8d30a6a7-b5eb-4846-96ab-ea2e806ae32d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2847587117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2847587117
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2370516062
Short name T558
Test name
Test status
Simulation time 118077740759 ps
CPU time 2153.01 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:39:38 PM PDT 24
Peak memory 282284 kb
Host smart-6a128dab-33d0-4a0e-b279-7d24576c3c13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370516062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2370516062
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3772168242
Short name T387
Test name
Test status
Simulation time 1037375014 ps
CPU time 43.44 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:04:16 PM PDT 24
Peak memory 248716 kb
Host smart-bd415b16-c74b-47f1-ab3f-046f57348b62
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3772168242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3772168242
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1441451211
Short name T637
Test name
Test status
Simulation time 502494878 ps
CPU time 15.75 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:03:43 PM PDT 24
Peak memory 248120 kb
Host smart-07ea3626-d9a1-41e3-a744-01a122d25462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14414
51211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1441451211
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2796221578
Short name T41
Test name
Test status
Simulation time 4410944846 ps
CPU time 46.15 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:04:30 PM PDT 24
Peak memory 249076 kb
Host smart-9d1c634e-5fec-4cf8-a619-1c6bf0ff3afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27962
21578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2796221578
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.912642781
Short name T598
Test name
Test status
Simulation time 26101758052 ps
CPU time 1435.94 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:27:28 PM PDT 24
Peak memory 273356 kb
Host smart-9b0b9626-18f5-4745-9236-0e922220224d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912642781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.912642781
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.93256865
Short name T247
Test name
Test status
Simulation time 13887561049 ps
CPU time 1058.17 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:21:11 PM PDT 24
Peak memory 281572 kb
Host smart-a2d3a540-cedb-410e-896c-ff44df751b98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93256865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.93256865
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.803510357
Short name T707
Test name
Test status
Simulation time 8423507257 ps
CPU time 359.43 seconds
Started Jul 26 05:03:35 PM PDT 24
Finished Jul 26 05:09:35 PM PDT 24
Peak memory 247412 kb
Host smart-2f48f1e3-dd4f-45cb-9b34-3b806c298cec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803510357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.803510357
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.470187230
Short name T377
Test name
Test status
Simulation time 8102597741 ps
CPU time 67.29 seconds
Started Jul 26 05:03:49 PM PDT 24
Finished Jul 26 05:04:57 PM PDT 24
Peak memory 257240 kb
Host smart-4478c75d-03cd-4443-bff2-7e1420ec7c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47018
7230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.470187230
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.4228849028
Short name T431
Test name
Test status
Simulation time 1734803748 ps
CPU time 51.32 seconds
Started Jul 26 05:03:34 PM PDT 24
Finished Jul 26 05:04:25 PM PDT 24
Peak memory 256096 kb
Host smart-9fcdf7c3-dfb3-4c77-861f-d089b431f134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42288
49028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.4228849028
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.4058241202
Short name T704
Test name
Test status
Simulation time 648313982 ps
CPU time 50.48 seconds
Started Jul 26 05:03:29 PM PDT 24
Finished Jul 26 05:04:19 PM PDT 24
Peak memory 256872 kb
Host smart-1b2b6df0-7f2d-46bb-aea5-7d1fb8ae3808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40582
41202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.4058241202
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1400704996
Short name T45
Test name
Test status
Simulation time 68341713 ps
CPU time 3.75 seconds
Started Jul 26 05:03:12 PM PDT 24
Finished Jul 26 05:03:16 PM PDT 24
Peak memory 249124 kb
Host smart-3edd61a1-3d47-44c7-9306-c79f522e56f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1400704996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1400704996
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2289041981
Short name T38
Test name
Test status
Simulation time 63951667259 ps
CPU time 1033.02 seconds
Started Jul 26 05:03:07 PM PDT 24
Finished Jul 26 05:20:21 PM PDT 24
Peak memory 288604 kb
Host smart-fb75b8af-9e9c-422a-9165-65086d2513d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289041981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2289041981
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3488819199
Short name T14
Test name
Test status
Simulation time 598409097 ps
CPU time 10.45 seconds
Started Jul 26 05:03:15 PM PDT 24
Finished Jul 26 05:03:26 PM PDT 24
Peak memory 248612 kb
Host smart-d63a4273-d282-4e40-872b-5c6b48b5fe24
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3488819199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3488819199
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2072025045
Short name T50
Test name
Test status
Simulation time 17014267757 ps
CPU time 243.86 seconds
Started Jul 26 05:02:57 PM PDT 24
Finished Jul 26 05:07:01 PM PDT 24
Peak memory 256360 kb
Host smart-c1644b6a-9dd8-40da-b1c4-30d675054007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20720
25045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2072025045
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.954643695
Short name T679
Test name
Test status
Simulation time 204708648 ps
CPU time 14.3 seconds
Started Jul 26 05:03:10 PM PDT 24
Finished Jul 26 05:03:25 PM PDT 24
Peak memory 248352 kb
Host smart-9162527f-407e-46c3-b428-ad3893b3f7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95464
3695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.954643695
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1825729002
Short name T95
Test name
Test status
Simulation time 22145683080 ps
CPU time 1045.72 seconds
Started Jul 26 05:03:11 PM PDT 24
Finished Jul 26 05:20:37 PM PDT 24
Peak memory 268368 kb
Host smart-6a203c5e-f50a-4e1c-9a87-4a1800747f72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825729002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1825729002
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2807749075
Short name T339
Test name
Test status
Simulation time 9568611677 ps
CPU time 388.79 seconds
Started Jul 26 05:03:05 PM PDT 24
Finished Jul 26 05:09:34 PM PDT 24
Peak memory 248684 kb
Host smart-361464d6-3472-469e-ba2c-4b49bede8cb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807749075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2807749075
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.752148772
Short name T594
Test name
Test status
Simulation time 870084073 ps
CPU time 24.41 seconds
Started Jul 26 05:02:59 PM PDT 24
Finished Jul 26 05:03:23 PM PDT 24
Peak memory 256084 kb
Host smart-cb3e0676-5566-4498-80f6-e299405d6c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75214
8772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.752148772
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2980921037
Short name T253
Test name
Test status
Simulation time 64827949 ps
CPU time 4.67 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:03:11 PM PDT 24
Peak memory 240024 kb
Host smart-6dc0b832-5e97-4dbe-b659-9544786a5a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29809
21037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2980921037
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4035913177
Short name T8
Test name
Test status
Simulation time 602118541 ps
CPU time 12.26 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:03:18 PM PDT 24
Peak memory 271360 kb
Host smart-4bd3fae4-4e62-481b-a675-c00c72ab595a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4035913177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4035913177
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.750963998
Short name T278
Test name
Test status
Simulation time 364423744 ps
CPU time 21.99 seconds
Started Jul 26 05:03:22 PM PDT 24
Finished Jul 26 05:03:44 PM PDT 24
Peak memory 248696 kb
Host smart-11d6a0b5-68ad-4429-84b0-9af29fdb2872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75096
3998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.750963998
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3272359926
Short name T456
Test name
Test status
Simulation time 993874757 ps
CPU time 15.64 seconds
Started Jul 26 05:03:14 PM PDT 24
Finished Jul 26 05:03:30 PM PDT 24
Peak memory 255608 kb
Host smart-ccbdfea6-c5cf-4bfc-a4c7-0922e9330569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32723
59926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3272359926
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1031335523
Short name T240
Test name
Test status
Simulation time 7006678587 ps
CPU time 395.9 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:10:00 PM PDT 24
Peak memory 257076 kb
Host smart-40476031-4631-426a-ae8a-39e036f89d0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031335523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1031335523
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2888700312
Short name T292
Test name
Test status
Simulation time 294838997777 ps
CPU time 7853.24 seconds
Started Jul 26 05:03:10 PM PDT 24
Finished Jul 26 07:14:04 PM PDT 24
Peak memory 371292 kb
Host smart-091da7e7-d8d1-464d-8d6f-fc194564500d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888700312 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2888700312
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.4175600161
Short name T313
Test name
Test status
Simulation time 95994119998 ps
CPU time 1385.72 seconds
Started Jul 26 05:03:41 PM PDT 24
Finished Jul 26 05:26:47 PM PDT 24
Peak memory 273436 kb
Host smart-997755e8-eeb1-44bd-8a64-168f02e679f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175600161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.4175600161
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1053957689
Short name T376
Test name
Test status
Simulation time 1274441893 ps
CPU time 83.61 seconds
Started Jul 26 05:03:50 PM PDT 24
Finished Jul 26 05:05:14 PM PDT 24
Peak memory 256324 kb
Host smart-d16a2ef5-748f-4a40-90f7-b3ad1ead8a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10539
57689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1053957689
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.694748651
Short name T578
Test name
Test status
Simulation time 3554728115 ps
CPU time 19.96 seconds
Started Jul 26 05:03:36 PM PDT 24
Finished Jul 26 05:03:57 PM PDT 24
Peak memory 248484 kb
Host smart-b3e40f80-dc51-4e7e-a9e8-554f6dfc11bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69474
8651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.694748651
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1953990902
Short name T351
Test name
Test status
Simulation time 175631970006 ps
CPU time 2723.15 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:49:16 PM PDT 24
Peak memory 289616 kb
Host smart-c58f8e10-074b-4f07-af77-fbdcbab7370a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953990902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1953990902
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3077843126
Short name T87
Test name
Test status
Simulation time 73971073080 ps
CPU time 1594.09 seconds
Started Jul 26 05:03:49 PM PDT 24
Finished Jul 26 05:30:23 PM PDT 24
Peak memory 272788 kb
Host smart-0b7df6c6-8457-40da-9785-37d28905c08e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077843126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3077843126
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1023498342
Short name T501
Test name
Test status
Simulation time 1432862067 ps
CPU time 37.27 seconds
Started Jul 26 05:03:39 PM PDT 24
Finished Jul 26 05:04:16 PM PDT 24
Peak memory 256260 kb
Host smart-d123c2be-19c5-47ed-a3d1-93efbba15dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10234
98342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1023498342
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.4111748907
Short name T448
Test name
Test status
Simulation time 1370875270 ps
CPU time 39.69 seconds
Started Jul 26 05:03:32 PM PDT 24
Finished Jul 26 05:04:12 PM PDT 24
Peak memory 256416 kb
Host smart-72bb936b-bb69-4142-ac69-92306ecfbda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117
48907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.4111748907
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3235949402
Short name T505
Test name
Test status
Simulation time 204258198 ps
CPU time 4.67 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:03:49 PM PDT 24
Peak memory 239804 kb
Host smart-4fc6db55-85fa-406b-849f-ad9b2db54861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32359
49402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3235949402
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.246080376
Short name T635
Test name
Test status
Simulation time 639222264 ps
CPU time 31.48 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:04:17 PM PDT 24
Peak memory 256988 kb
Host smart-634888c2-a7f4-493e-9b07-8074017c335f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24608
0376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.246080376
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1207477946
Short name T671
Test name
Test status
Simulation time 33757726321 ps
CPU time 2107.44 seconds
Started Jul 26 05:03:39 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 286392 kb
Host smart-587825f5-4ac7-4e5e-b663-2cf62549cde1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207477946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1207477946
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1096183411
Short name T16
Test name
Test status
Simulation time 18623641725 ps
CPU time 923.8 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:19:09 PM PDT 24
Peak memory 273008 kb
Host smart-13c701e7-0c60-44b6-ab3c-01f49d3cf75d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096183411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1096183411
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.782026240
Short name T454
Test name
Test status
Simulation time 2212959194 ps
CPU time 97.6 seconds
Started Jul 26 05:03:42 PM PDT 24
Finished Jul 26 05:05:19 PM PDT 24
Peak memory 250956 kb
Host smart-b9256ad5-d90e-4502-8dc1-b89d62a2f156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78202
6240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.782026240
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1641452506
Short name T583
Test name
Test status
Simulation time 814116371 ps
CPU time 29.3 seconds
Started Jul 26 05:03:55 PM PDT 24
Finished Jul 26 05:04:24 PM PDT 24
Peak memory 248772 kb
Host smart-2f7c7085-2ce1-4fb0-ad18-e3441f8b65bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16414
52506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1641452506
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2353339273
Short name T342
Test name
Test status
Simulation time 817690093857 ps
CPU time 2389.27 seconds
Started Jul 26 05:03:41 PM PDT 24
Finished Jul 26 05:43:31 PM PDT 24
Peak memory 289372 kb
Host smart-2d0593a1-96f7-4b78-81cf-ce9813674033
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353339273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2353339273
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1522757278
Short name T634
Test name
Test status
Simulation time 36745594292 ps
CPU time 2564.02 seconds
Started Jul 26 05:03:54 PM PDT 24
Finished Jul 26 05:46:38 PM PDT 24
Peak memory 289492 kb
Host smart-0a38b7cb-b23b-434f-badf-eb1a715061b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522757278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1522757278
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.609573073
Short name T564
Test name
Test status
Simulation time 564205676 ps
CPU time 30.51 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:04:13 PM PDT 24
Peak memory 256908 kb
Host smart-d4fc6f7b-2f84-4932-9288-e2d876c5180a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60957
3073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.609573073
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2389498294
Short name T604
Test name
Test status
Simulation time 2245747255 ps
CPU time 71.77 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:05:04 PM PDT 24
Peak memory 248820 kb
Host smart-783e8f1a-df33-4e72-b814-003017676170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23894
98294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2389498294
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2821195374
Short name T18
Test name
Test status
Simulation time 250941858 ps
CPU time 10.41 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:03:55 PM PDT 24
Peak memory 254012 kb
Host smart-f7bc106c-ccbe-43b4-ac7d-fda6ca7044bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28211
95374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2821195374
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.217903492
Short name T563
Test name
Test status
Simulation time 110682794 ps
CPU time 9.5 seconds
Started Jul 26 05:03:46 PM PDT 24
Finished Jul 26 05:03:55 PM PDT 24
Peak memory 254924 kb
Host smart-326878e5-8531-47ca-8ac6-ee950a6c6d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21790
3492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.217903492
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3857565577
Short name T446
Test name
Test status
Simulation time 28357923503 ps
CPU time 1616.1 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:30:39 PM PDT 24
Peak memory 268660 kb
Host smart-1d8f73e0-d2e1-4b76-a05a-75a23da13ce2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857565577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3857565577
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2691305174
Short name T474
Test name
Test status
Simulation time 28063315616 ps
CPU time 1491.83 seconds
Started Jul 26 05:03:41 PM PDT 24
Finished Jul 26 05:28:33 PM PDT 24
Peak memory 289244 kb
Host smart-85bd118e-9a30-46d6-8134-0cbb719604c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691305174 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2691305174
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3750116864
Short name T119
Test name
Test status
Simulation time 22806257562 ps
CPU time 1311.98 seconds
Started Jul 26 05:03:50 PM PDT 24
Finished Jul 26 05:25:42 PM PDT 24
Peak memory 273340 kb
Host smart-fd50a873-0f30-4bcd-a802-b114950a8690
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750116864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3750116864
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2439024193
Short name T37
Test name
Test status
Simulation time 3535319629 ps
CPU time 187.23 seconds
Started Jul 26 05:03:40 PM PDT 24
Finished Jul 26 05:06:48 PM PDT 24
Peak memory 256544 kb
Host smart-c49f0d8f-920e-4868-b267-747d021e0332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24390
24193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2439024193
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.927969197
Short name T81
Test name
Test status
Simulation time 864108599 ps
CPU time 53.57 seconds
Started Jul 26 05:03:50 PM PDT 24
Finished Jul 26 05:04:43 PM PDT 24
Peak memory 248248 kb
Host smart-0d2ee8ed-f692-4847-9732-987a7b894fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92796
9197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.927969197
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3478158613
Short name T698
Test name
Test status
Simulation time 9677855632 ps
CPU time 1055.25 seconds
Started Jul 26 05:03:42 PM PDT 24
Finished Jul 26 05:21:17 PM PDT 24
Peak memory 273264 kb
Host smart-7a81406f-3178-4b46-8dda-42a6678d103c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478158613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3478158613
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3328954066
Short name T340
Test name
Test status
Simulation time 13471808633 ps
CPU time 546.24 seconds
Started Jul 26 05:03:34 PM PDT 24
Finished Jul 26 05:12:40 PM PDT 24
Peak memory 248824 kb
Host smart-c6901a93-66d4-4f95-8c40-947b8f4a1a46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328954066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3328954066
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3660548245
Short name T128
Test name
Test status
Simulation time 1767327743 ps
CPU time 26.05 seconds
Started Jul 26 05:03:46 PM PDT 24
Finished Jul 26 05:04:12 PM PDT 24
Peak memory 256140 kb
Host smart-1ae209b1-43b6-493d-be04-64a9d34005d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36605
48245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3660548245
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2671202928
Short name T697
Test name
Test status
Simulation time 247249249 ps
CPU time 20.21 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:04:13 PM PDT 24
Peak memory 256868 kb
Host smart-27427999-6168-49ba-8037-2e71ed8af785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26712
02928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2671202928
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.215282349
Short name T66
Test name
Test status
Simulation time 265667061 ps
CPU time 20.05 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:04:04 PM PDT 24
Peak memory 256316 kb
Host smart-b6324f09-b560-44f3-bbb1-cf4ca77ed3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21528
2349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.215282349
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1574878465
Short name T449
Test name
Test status
Simulation time 1071052995 ps
CPU time 16.61 seconds
Started Jul 26 05:03:41 PM PDT 24
Finished Jul 26 05:03:58 PM PDT 24
Peak memory 256972 kb
Host smart-7fd24ae7-8f4c-4f9e-89d7-a782d5611871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748
78465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1574878465
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1455919382
Short name T25
Test name
Test status
Simulation time 96788620532 ps
CPU time 2892.17 seconds
Started Jul 26 05:03:49 PM PDT 24
Finished Jul 26 05:52:02 PM PDT 24
Peak memory 289296 kb
Host smart-a586a334-2ee2-4d11-b264-faa4289d4e79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455919382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1455919382
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3167620477
Short name T207
Test name
Test status
Simulation time 49224331550 ps
CPU time 2340.58 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:42:44 PM PDT 24
Peak memory 301116 kb
Host smart-b414938e-aa92-40cc-b7cf-02101498077a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167620477 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3167620477
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3469460360
Short name T92
Test name
Test status
Simulation time 41213612522 ps
CPU time 2376.12 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:43:27 PM PDT 24
Peak memory 286468 kb
Host smart-e110f9c5-f301-407c-b808-c016d81fe477
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469460360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3469460360
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.175098663
Short name T423
Test name
Test status
Simulation time 1746062086 ps
CPU time 21.21 seconds
Started Jul 26 05:03:53 PM PDT 24
Finished Jul 26 05:04:14 PM PDT 24
Peak memory 256988 kb
Host smart-1cb5c2ff-f215-44af-b7f5-277ca5d2132b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17509
8663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.175098663
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1724761767
Short name T680
Test name
Test status
Simulation time 272889749 ps
CPU time 30.12 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:04:13 PM PDT 24
Peak memory 256508 kb
Host smart-2b1ee9c7-b70a-4989-8e56-da58928f202a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17247
61767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1724761767
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1455216602
Short name T561
Test name
Test status
Simulation time 83384792588 ps
CPU time 2314.13 seconds
Started Jul 26 05:03:57 PM PDT 24
Finished Jul 26 05:42:32 PM PDT 24
Peak memory 288880 kb
Host smart-94e9fed2-015e-4fa7-b5d7-fea6df527d2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455216602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1455216602
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2733211102
Short name T312
Test name
Test status
Simulation time 58581226697 ps
CPU time 1978.75 seconds
Started Jul 26 05:03:39 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 273260 kb
Host smart-58bf8fa1-2e91-4018-808b-194cf55beb86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733211102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2733211102
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3173119010
Short name T44
Test name
Test status
Simulation time 665312018 ps
CPU time 21.71 seconds
Started Jul 26 05:03:48 PM PDT 24
Finished Jul 26 05:04:10 PM PDT 24
Peak memory 248788 kb
Host smart-be11f554-f5c4-4e4b-af0a-f3f330a59434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31731
19010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3173119010
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.409939382
Short name T417
Test name
Test status
Simulation time 2818292567 ps
CPU time 46.2 seconds
Started Jul 26 05:03:42 PM PDT 24
Finished Jul 26 05:04:29 PM PDT 24
Peak memory 248704 kb
Host smart-72155b66-f071-49d3-853c-2026d3064c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40993
9382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.409939382
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.849212857
Short name T79
Test name
Test status
Simulation time 515120126 ps
CPU time 32.27 seconds
Started Jul 26 05:03:54 PM PDT 24
Finished Jul 26 05:04:27 PM PDT 24
Peak memory 256012 kb
Host smart-db1342f4-7a2d-4ffd-a79b-e0f9cd8762a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84921
2857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.849212857
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.947010931
Short name T202
Test name
Test status
Simulation time 196590908 ps
CPU time 10.31 seconds
Started Jul 26 05:03:53 PM PDT 24
Finished Jul 26 05:04:04 PM PDT 24
Peak memory 255488 kb
Host smart-40839459-1e0c-44f5-a28d-c98ff7cccdd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94701
0931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.947010931
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1782672046
Short name T284
Test name
Test status
Simulation time 24043930152 ps
CPU time 1416.98 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:27:21 PM PDT 24
Peak memory 272552 kb
Host smart-c2ec126d-c43e-4fe5-a26b-8bbb6a4c76d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782672046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1782672046
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.265417600
Short name T413
Test name
Test status
Simulation time 17339830366 ps
CPU time 1419.01 seconds
Started Jul 26 05:03:56 PM PDT 24
Finished Jul 26 05:27:35 PM PDT 24
Peak memory 289464 kb
Host smart-199036ed-99a8-49b4-915d-54c31fcb3a5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265417600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.265417600
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3616919488
Short name T201
Test name
Test status
Simulation time 1762264182 ps
CPU time 130.73 seconds
Started Jul 26 05:03:57 PM PDT 24
Finished Jul 26 05:06:08 PM PDT 24
Peak memory 256636 kb
Host smart-f15f6a52-cb34-4675-8888-5fff67a50c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36169
19488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3616919488
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1590895360
Short name T498
Test name
Test status
Simulation time 478605889 ps
CPU time 38.15 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:04:30 PM PDT 24
Peak memory 255472 kb
Host smart-6dfe44a0-d7ff-412b-a980-a6e7983633aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
95360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1590895360
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.597064534
Short name T358
Test name
Test status
Simulation time 24200031898 ps
CPU time 1477.67 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:28:22 PM PDT 24
Peak memory 287340 kb
Host smart-7d92fee3-cce0-4dd2-8ab6-878387465895
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597064534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.597064534
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.4182922700
Short name T426
Test name
Test status
Simulation time 129701278592 ps
CPU time 1117.05 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:22:28 PM PDT 24
Peak memory 273428 kb
Host smart-7d8e622e-d60f-409c-9959-4be3e065a10a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182922700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.4182922700
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.584777910
Short name T386
Test name
Test status
Simulation time 93915711 ps
CPU time 4.93 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:03:51 PM PDT 24
Peak memory 248772 kb
Host smart-d88460f1-48a0-44eb-83bb-9d375c79ec0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58477
7910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.584777910
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.836628728
Short name T506
Test name
Test status
Simulation time 54383657 ps
CPU time 2.95 seconds
Started Jul 26 05:03:46 PM PDT 24
Finished Jul 26 05:03:49 PM PDT 24
Peak memory 240624 kb
Host smart-2d41d26d-8680-4a94-bb3d-d9b7a6adf925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83662
8728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.836628728
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1995548560
Short name T288
Test name
Test status
Simulation time 490247247 ps
CPU time 29.79 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:04:22 PM PDT 24
Peak memory 248320 kb
Host smart-943535ba-5602-4361-b207-5d696fd94bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19955
48560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1995548560
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1184401313
Short name T371
Test name
Test status
Simulation time 140851132 ps
CPU time 8.64 seconds
Started Jul 26 05:03:39 PM PDT 24
Finished Jul 26 05:03:48 PM PDT 24
Peak memory 248736 kb
Host smart-1517a181-8824-4a35-80dd-3f8707fb2958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11844
01313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1184401313
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.655892044
Short name T577
Test name
Test status
Simulation time 228745040373 ps
CPU time 3259.28 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:58:12 PM PDT 24
Peak memory 289184 kb
Host smart-14bfa3a9-7b88-4d37-9eb7-2be6c2483a39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655892044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.655892044
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3475305320
Short name T477
Test name
Test status
Simulation time 52113940265 ps
CPU time 3620.2 seconds
Started Jul 26 05:03:59 PM PDT 24
Finished Jul 26 06:04:19 PM PDT 24
Peak memory 305596 kb
Host smart-1ffcae92-7164-4e30-873e-8845924c6e80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475305320 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3475305320
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3365336315
Short name T126
Test name
Test status
Simulation time 41028538136 ps
CPU time 1327.25 seconds
Started Jul 26 05:03:40 PM PDT 24
Finished Jul 26 05:25:48 PM PDT 24
Peak memory 272916 kb
Host smart-bc9a1e76-b347-4b61-b769-8a00f6b7b2dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365336315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3365336315
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2429061788
Short name T444
Test name
Test status
Simulation time 26909248244 ps
CPU time 312.94 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:08:56 PM PDT 24
Peak memory 256624 kb
Host smart-8d7ee89b-bff6-46c8-9164-893146a43718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24290
61788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2429061788
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3039748542
Short name T700
Test name
Test status
Simulation time 423430324 ps
CPU time 16.17 seconds
Started Jul 26 05:03:57 PM PDT 24
Finished Jul 26 05:04:13 PM PDT 24
Peak memory 255032 kb
Host smart-3fd11b58-5ff9-4fee-8763-1f387a62847c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30397
48542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3039748542
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3066004790
Short name T344
Test name
Test status
Simulation time 38653327566 ps
CPU time 1437.39 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:27:41 PM PDT 24
Peak memory 289476 kb
Host smart-39b3ada7-5d8c-4d61-93da-ae40bf6e8a34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066004790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3066004790
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.4078408746
Short name T520
Test name
Test status
Simulation time 56659672237 ps
CPU time 1732.31 seconds
Started Jul 26 05:03:58 PM PDT 24
Finished Jul 26 05:32:50 PM PDT 24
Peak memory 273316 kb
Host smart-36813a87-375c-49c1-8875-578a157ba178
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078408746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.4078408746
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.756346659
Short name T330
Test name
Test status
Simulation time 13858814523 ps
CPU time 576.27 seconds
Started Jul 26 05:03:58 PM PDT 24
Finished Jul 26 05:13:35 PM PDT 24
Peak memory 248880 kb
Host smart-12f431f0-b239-4b64-8d29-b270dc71d214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756346659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.756346659
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2879686365
Short name T470
Test name
Test status
Simulation time 1695852236 ps
CPU time 26.83 seconds
Started Jul 26 05:03:41 PM PDT 24
Finished Jul 26 05:04:08 PM PDT 24
Peak memory 256984 kb
Host smart-534ff7d6-9362-4155-8875-c31f63818234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28796
86365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2879686365
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.456231906
Short name T539
Test name
Test status
Simulation time 731853856 ps
CPU time 57.21 seconds
Started Jul 26 05:03:42 PM PDT 24
Finished Jul 26 05:04:40 PM PDT 24
Peak memory 256368 kb
Host smart-d7f3dec3-5d26-454b-b981-9f4143e8e8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45623
1906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.456231906
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1837133300
Short name T646
Test name
Test status
Simulation time 1307520512 ps
CPU time 27.89 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:04:20 PM PDT 24
Peak memory 256804 kb
Host smart-828defd4-5741-4e46-9a5d-4607207ba44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18371
33300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1837133300
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.730916224
Short name T281
Test name
Test status
Simulation time 84286278657 ps
CPU time 2497.29 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:45:21 PM PDT 24
Peak memory 284924 kb
Host smart-b52d02a5-b3ec-4bdb-8ea6-f1f2f8bee836
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730916224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.730916224
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2447721677
Short name T117
Test name
Test status
Simulation time 38772808487 ps
CPU time 2205.27 seconds
Started Jul 26 05:03:49 PM PDT 24
Finished Jul 26 05:40:35 PM PDT 24
Peak memory 283460 kb
Host smart-1837d7ad-c3fb-46b1-9801-963cd938aebc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447721677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2447721677
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.4136116766
Short name T406
Test name
Test status
Simulation time 740285498 ps
CPU time 49.89 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:04:50 PM PDT 24
Peak memory 256500 kb
Host smart-f8b842c4-9d4a-4fd3-b528-75bdd68e6510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41361
16766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.4136116766
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1804131536
Short name T479
Test name
Test status
Simulation time 230435494 ps
CPU time 14.96 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:04:08 PM PDT 24
Peak memory 248764 kb
Host smart-beebb641-98d6-46ea-9068-3036a79bb295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18041
31536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1804131536
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.4059657834
Short name T632
Test name
Test status
Simulation time 69781666553 ps
CPU time 2044.2 seconds
Started Jul 26 05:03:50 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 273388 kb
Host smart-20235e3e-0b63-4665-939f-deb981a38770
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059657834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4059657834
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.864347647
Short name T248
Test name
Test status
Simulation time 27470011473 ps
CPU time 593.59 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:13:37 PM PDT 24
Peak memory 248544 kb
Host smart-9ab9df88-4132-4509-8730-75044c020b09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864347647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.864347647
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1273977697
Short name T706
Test name
Test status
Simulation time 676329108 ps
CPU time 35.26 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:04:20 PM PDT 24
Peak memory 256872 kb
Host smart-07480f2b-4e71-401c-a792-8b91fc90085b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12739
77697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1273977697
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.636144344
Short name T71
Test name
Test status
Simulation time 238486367 ps
CPU time 10.59 seconds
Started Jul 26 05:03:48 PM PDT 24
Finished Jul 26 05:03:58 PM PDT 24
Peak memory 248080 kb
Host smart-81f20ce1-4b47-4de5-be5f-f55ee5674be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63614
4344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.636144344
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.954119755
Short name T503
Test name
Test status
Simulation time 88906130 ps
CPU time 9.3 seconds
Started Jul 26 05:03:47 PM PDT 24
Finished Jul 26 05:03:56 PM PDT 24
Peak memory 256100 kb
Host smart-4201f2d5-777e-4769-827e-47363563d321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95411
9755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.954119755
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1868351788
Short name T622
Test name
Test status
Simulation time 730820673 ps
CPU time 7.17 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:04:08 PM PDT 24
Peak memory 248824 kb
Host smart-208bf357-19ca-4267-9dd2-e9c897be1ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18683
51788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1868351788
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1272376035
Short name T52
Test name
Test status
Simulation time 31719936444 ps
CPU time 336.71 seconds
Started Jul 26 05:03:46 PM PDT 24
Finished Jul 26 05:09:23 PM PDT 24
Peak memory 265284 kb
Host smart-213db512-6aad-45f6-86f9-63942245575b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272376035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1272376035
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1588687422
Short name T476
Test name
Test status
Simulation time 9494664543 ps
CPU time 1081.23 seconds
Started Jul 26 05:03:47 PM PDT 24
Finished Jul 26 05:21:49 PM PDT 24
Peak memory 285740 kb
Host smart-d3d958a1-3d89-4b45-aba2-92094fa20b37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588687422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1588687422
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3834048489
Short name T269
Test name
Test status
Simulation time 6754723195 ps
CPU time 146.16 seconds
Started Jul 26 05:03:46 PM PDT 24
Finished Jul 26 05:06:12 PM PDT 24
Peak memory 257012 kb
Host smart-73aa3be1-bd53-4964-b77d-9b36123cb80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340
48489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3834048489
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2778330622
Short name T276
Test name
Test status
Simulation time 1139862431 ps
CPU time 44.4 seconds
Started Jul 26 05:03:55 PM PDT 24
Finished Jul 26 05:04:39 PM PDT 24
Peak memory 248580 kb
Host smart-74b1a8a2-9a03-40d2-a565-4018b6e30d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
30622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2778330622
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1211911915
Short name T70
Test name
Test status
Simulation time 170825540523 ps
CPU time 2461.6 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 289704 kb
Host smart-c725ddf5-401b-4267-af05-a9475828a46b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211911915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1211911915
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3026107192
Short name T595
Test name
Test status
Simulation time 68343362568 ps
CPU time 2358.96 seconds
Started Jul 26 05:03:55 PM PDT 24
Finished Jul 26 05:43:14 PM PDT 24
Peak memory 289404 kb
Host smart-57fd0ac0-2f76-4544-9fdb-4dc24b98c255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026107192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3026107192
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.206603720
Short name T333
Test name
Test status
Simulation time 36564349031 ps
CPU time 391.69 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:10:23 PM PDT 24
Peak memory 248644 kb
Host smart-cb53063e-0603-4284-8560-5d24571f114e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206603720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.206603720
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3818529165
Short name T445
Test name
Test status
Simulation time 814264514 ps
CPU time 52.15 seconds
Started Jul 26 05:03:49 PM PDT 24
Finished Jul 26 05:04:41 PM PDT 24
Peak memory 248792 kb
Host smart-c86ed3be-c459-453a-b950-69dac219803a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38185
29165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3818529165
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.120570805
Short name T667
Test name
Test status
Simulation time 696519763 ps
CPU time 15.65 seconds
Started Jul 26 05:03:48 PM PDT 24
Finished Jul 26 05:04:04 PM PDT 24
Peak memory 255076 kb
Host smart-4cfdde8a-cb60-4763-bc74-880ce6f2de23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12057
0805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.120570805
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1621682807
Short name T555
Test name
Test status
Simulation time 5342410081 ps
CPU time 26.12 seconds
Started Jul 26 05:03:43 PM PDT 24
Finished Jul 26 05:04:09 PM PDT 24
Peak memory 257020 kb
Host smart-a44e85bc-7f76-418e-8a0c-eb31e4451d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
82807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1621682807
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2705601064
Short name T404
Test name
Test status
Simulation time 72525031807 ps
CPU time 2245.41 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:41:11 PM PDT 24
Peak memory 288684 kb
Host smart-6898ebe0-4a5b-432c-bce4-146af061c3df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705601064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2705601064
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3610439595
Short name T206
Test name
Test status
Simulation time 20068936452 ps
CPU time 1103.19 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:22:07 PM PDT 24
Peak memory 266100 kb
Host smart-319fcf29-d64d-40c8-88b0-37dea6cf9c03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610439595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3610439595
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2324193338
Short name T462
Test name
Test status
Simulation time 3934693640 ps
CPU time 209.04 seconds
Started Jul 26 05:03:47 PM PDT 24
Finished Jul 26 05:07:16 PM PDT 24
Peak memory 257076 kb
Host smart-5e408249-9f8c-4226-ad37-09faa63550f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23241
93338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2324193338
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3339599719
Short name T528
Test name
Test status
Simulation time 6418677397 ps
CPU time 52.22 seconds
Started Jul 26 05:03:44 PM PDT 24
Finished Jul 26 05:04:36 PM PDT 24
Peak memory 248564 kb
Host smart-8545f4b7-3abe-452b-a510-9003874882e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33395
99719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3339599719
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2696019055
Short name T357
Test name
Test status
Simulation time 64696118656 ps
CPU time 1132.28 seconds
Started Jul 26 05:03:53 PM PDT 24
Finished Jul 26 05:22:45 PM PDT 24
Peak memory 273336 kb
Host smart-d1f2a401-9068-43cb-b839-55b76a28915e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696019055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2696019055
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2888098272
Short name T619
Test name
Test status
Simulation time 257184995620 ps
CPU time 2293.36 seconds
Started Jul 26 05:03:59 PM PDT 24
Finished Jul 26 05:42:13 PM PDT 24
Peak memory 288492 kb
Host smart-98d134cc-c9cb-4f37-9633-6b331c9fece3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888098272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2888098272
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4226033122
Short name T569
Test name
Test status
Simulation time 145830900357 ps
CPU time 454.56 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:11:25 PM PDT 24
Peak memory 248820 kb
Host smart-416304c4-bdc6-464e-82fc-050502c3b291
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226033122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4226033122
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2023966406
Short name T652
Test name
Test status
Simulation time 326801093 ps
CPU time 27.82 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:04:20 PM PDT 24
Peak memory 256212 kb
Host smart-81468177-cb89-469e-89ff-c24fdc27fb5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20239
66406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2023966406
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4274767431
Short name T266
Test name
Test status
Simulation time 1513993604 ps
CPU time 43.06 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:04:34 PM PDT 24
Peak memory 248608 kb
Host smart-7eda1a94-81e6-4be5-bdf1-070c644d75dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42747
67431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4274767431
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2495986081
Short name T53
Test name
Test status
Simulation time 693188497 ps
CPU time 45.38 seconds
Started Jul 26 05:03:45 PM PDT 24
Finished Jul 26 05:04:31 PM PDT 24
Peak memory 256376 kb
Host smart-eab231ac-9c20-4048-a357-11d521c9ff4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24959
86081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2495986081
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2216097924
Short name T414
Test name
Test status
Simulation time 322086565 ps
CPU time 23.94 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:04:15 PM PDT 24
Peak memory 256884 kb
Host smart-4abd5d8d-b203-455a-b421-c5c96f1ef817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22160
97924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2216097924
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.4218205496
Short name T286
Test name
Test status
Simulation time 14334793975 ps
CPU time 966.49 seconds
Started Jul 26 05:03:53 PM PDT 24
Finished Jul 26 05:20:00 PM PDT 24
Peak memory 270664 kb
Host smart-0ab2a8f8-a07f-4a4a-85aa-49105ad2e46d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218205496 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.4218205496
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2742243176
Short name T490
Test name
Test status
Simulation time 141339933507 ps
CPU time 2536.78 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:46:09 PM PDT 24
Peak memory 289772 kb
Host smart-25c621e6-36bb-4ae9-a95d-0492d257f5c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742243176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2742243176
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.903167421
Short name T654
Test name
Test status
Simulation time 7194385730 ps
CPU time 158.21 seconds
Started Jul 26 05:04:01 PM PDT 24
Finished Jul 26 05:06:40 PM PDT 24
Peak memory 256960 kb
Host smart-5de80da9-361c-4558-a280-db29ecaf2c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90316
7421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.903167421
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.568860130
Short name T567
Test name
Test status
Simulation time 226791906 ps
CPU time 8.2 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:03:59 PM PDT 24
Peak memory 248780 kb
Host smart-d906a90b-8c0e-4d4e-b1e6-956baa16320e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56886
0130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.568860130
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2417220806
Short name T487
Test name
Test status
Simulation time 56063317673 ps
CPU time 1620.26 seconds
Started Jul 26 05:03:59 PM PDT 24
Finished Jul 26 05:31:00 PM PDT 24
Peak memory 272684 kb
Host smart-d52aac55-c537-48a9-9e16-1f1139fd139e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417220806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2417220806
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1923788940
Short name T499
Test name
Test status
Simulation time 65770704667 ps
CPU time 1008.75 seconds
Started Jul 26 05:03:56 PM PDT 24
Finished Jul 26 05:20:45 PM PDT 24
Peak memory 273372 kb
Host smart-b7c16d5b-26ce-49b5-bb94-dfb5ab1e9e3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923788940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1923788940
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2468982615
Short name T332
Test name
Test status
Simulation time 12025786080 ps
CPU time 496.96 seconds
Started Jul 26 05:03:56 PM PDT 24
Finished Jul 26 05:12:13 PM PDT 24
Peak memory 248720 kb
Host smart-8c3f72ff-5786-4627-87e2-431e0a7f6fd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468982615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2468982615
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3640086384
Short name T614
Test name
Test status
Simulation time 328113423 ps
CPU time 35.81 seconds
Started Jul 26 05:03:55 PM PDT 24
Finished Jul 26 05:04:31 PM PDT 24
Peak memory 256120 kb
Host smart-6404ab83-d82c-4848-aa45-d0ba66784e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36400
86384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3640086384
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3917262410
Short name T608
Test name
Test status
Simulation time 543655804 ps
CPU time 40.64 seconds
Started Jul 26 05:03:54 PM PDT 24
Finished Jul 26 05:04:34 PM PDT 24
Peak memory 256176 kb
Host smart-4abd260b-990d-44b7-b671-2a60a13cf473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39172
62410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3917262410
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.27980586
Short name T587
Test name
Test status
Simulation time 321108449 ps
CPU time 24.12 seconds
Started Jul 26 05:03:58 PM PDT 24
Finished Jul 26 05:04:23 PM PDT 24
Peak memory 248752 kb
Host smart-afe4195a-5016-411a-bba5-eb3ffcb571ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27980
586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.27980586
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2208423097
Short name T256
Test name
Test status
Simulation time 296590402 ps
CPU time 32.33 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:04:33 PM PDT 24
Peak memory 256980 kb
Host smart-a12aacbd-00d1-4dfd-8a46-6103146fab2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22084
23097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2208423097
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1562747585
Short name T585
Test name
Test status
Simulation time 34106645495 ps
CPU time 2109.06 seconds
Started Jul 26 05:04:11 PM PDT 24
Finished Jul 26 05:39:21 PM PDT 24
Peak memory 289700 kb
Host smart-b1f692d7-9868-4e2d-8fce-65cd77a22e24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562747585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1562747585
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.244014589
Short name T229
Test name
Test status
Simulation time 162560281 ps
CPU time 3.53 seconds
Started Jul 26 05:03:13 PM PDT 24
Finished Jul 26 05:03:16 PM PDT 24
Peak memory 249008 kb
Host smart-b1e9d64a-8e78-4fe2-b800-354f00c932ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=244014589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.244014589
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.986333808
Short name T472
Test name
Test status
Simulation time 5520484005 ps
CPU time 25.74 seconds
Started Jul 26 05:02:58 PM PDT 24
Finished Jul 26 05:03:24 PM PDT 24
Peak memory 248688 kb
Host smart-1a50bc83-04ad-4ff8-be05-da42650b0ae5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=986333808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.986333808
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1510705166
Short name T108
Test name
Test status
Simulation time 2540042343 ps
CPU time 136.16 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:05:22 PM PDT 24
Peak memory 256328 kb
Host smart-3fac796f-bea2-4861-b886-a44b442dc14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15107
05166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1510705166
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1714062755
Short name T76
Test name
Test status
Simulation time 129014081 ps
CPU time 8.73 seconds
Started Jul 26 05:03:18 PM PDT 24
Finished Jul 26 05:03:27 PM PDT 24
Peak memory 248720 kb
Host smart-1645ef30-8e1b-4696-bccb-f4654e8fa363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17140
62755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1714062755
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2422521124
Short name T352
Test name
Test status
Simulation time 17423732042 ps
CPU time 1122.31 seconds
Started Jul 26 05:03:18 PM PDT 24
Finished Jul 26 05:22:01 PM PDT 24
Peak memory 271804 kb
Host smart-69798a95-52d2-440a-b3f2-87067be8dd0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422521124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2422521124
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1998534931
Short name T403
Test name
Test status
Simulation time 77828554159 ps
CPU time 2126.26 seconds
Started Jul 26 05:03:15 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 289344 kb
Host smart-75f15487-65a9-4c53-9eaf-ed911a20ce58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998534931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1998534931
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2018846179
Short name T296
Test name
Test status
Simulation time 1441946015 ps
CPU time 17.4 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:03:46 PM PDT 24
Peak memory 256012 kb
Host smart-23684cb1-c332-4b33-bed9-8048f225e91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20188
46179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2018846179
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.331862479
Short name T650
Test name
Test status
Simulation time 1081830946 ps
CPU time 39.9 seconds
Started Jul 26 05:03:12 PM PDT 24
Finished Jul 26 05:03:52 PM PDT 24
Peak memory 248228 kb
Host smart-dfbec1d0-037d-440a-abb2-49f02ee3d478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33186
2479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.331862479
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3727830543
Short name T19
Test name
Test status
Simulation time 538198029 ps
CPU time 34.85 seconds
Started Jul 26 05:03:02 PM PDT 24
Finished Jul 26 05:03:42 PM PDT 24
Peak memory 248628 kb
Host smart-0fb5d6a5-f23b-40b9-8a6e-2ee8a4f3c6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37278
30543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3727830543
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3847084687
Short name T415
Test name
Test status
Simulation time 581804941 ps
CPU time 28.31 seconds
Started Jul 26 05:03:00 PM PDT 24
Finished Jul 26 05:03:29 PM PDT 24
Peak memory 255936 kb
Host smart-3f644952-827b-46b5-a0f2-02e4c8d1811a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38470
84687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3847084687
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3199745020
Short name T59
Test name
Test status
Simulation time 71385950193 ps
CPU time 927.87 seconds
Started Jul 26 05:03:07 PM PDT 24
Finished Jul 26 05:18:40 PM PDT 24
Peak memory 282504 kb
Host smart-39600da3-a7c4-4970-8b6a-9f89994f46e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199745020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3199745020
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2912177422
Short name T264
Test name
Test status
Simulation time 20407316950 ps
CPU time 1319.92 seconds
Started Jul 26 05:03:05 PM PDT 24
Finished Jul 26 05:25:05 PM PDT 24
Peak memory 281832 kb
Host smart-6c279b9c-dcae-4fdc-b5d2-9a87cbca2da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912177422 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2912177422
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1009316331
Short name T571
Test name
Test status
Simulation time 38992737856 ps
CPU time 2256.95 seconds
Started Jul 26 05:03:57 PM PDT 24
Finished Jul 26 05:41:34 PM PDT 24
Peak memory 289508 kb
Host smart-25f62f93-c323-4e47-b135-55750243e6ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009316331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1009316331
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1475362073
Short name T642
Test name
Test status
Simulation time 9253352736 ps
CPU time 146.93 seconds
Started Jul 26 05:03:50 PM PDT 24
Finished Jul 26 05:06:17 PM PDT 24
Peak memory 256808 kb
Host smart-7997ea28-a5c5-4659-a1bf-c768123096b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14753
62073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1475362073
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1040531670
Short name T685
Test name
Test status
Simulation time 230773975 ps
CPU time 17.1 seconds
Started Jul 26 05:03:54 PM PDT 24
Finished Jul 26 05:04:11 PM PDT 24
Peak memory 256348 kb
Host smart-48e4935d-08e3-4650-bf79-5db04ba16270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405
31670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1040531670
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3016768847
Short name T345
Test name
Test status
Simulation time 108086923993 ps
CPU time 1737.32 seconds
Started Jul 26 05:03:57 PM PDT 24
Finished Jul 26 05:32:54 PM PDT 24
Peak memory 289704 kb
Host smart-7f260149-c827-45b1-bbff-d9702ae274b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016768847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3016768847
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3457593096
Short name T566
Test name
Test status
Simulation time 36972543039 ps
CPU time 894.78 seconds
Started Jul 26 05:03:59 PM PDT 24
Finished Jul 26 05:18:54 PM PDT 24
Peak memory 273280 kb
Host smart-e8a11cc4-bd67-433b-b2e4-68e6480c106f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457593096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3457593096
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.106054321
Short name T647
Test name
Test status
Simulation time 14720351090 ps
CPU time 316.11 seconds
Started Jul 26 05:03:55 PM PDT 24
Finished Jul 26 05:09:12 PM PDT 24
Peak memory 248820 kb
Host smart-a8b8fb96-9762-49f7-b483-c51fb0cea955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106054321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.106054321
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.82609027
Short name T531
Test name
Test status
Simulation time 964568114 ps
CPU time 53.12 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:04:53 PM PDT 24
Peak memory 256248 kb
Host smart-7a897080-8446-4e40-aaac-8c6f2c37423d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82609
027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.82609027
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3176347842
Short name T57
Test name
Test status
Simulation time 16132991920 ps
CPU time 51.48 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:04:43 PM PDT 24
Peak memory 248896 kb
Host smart-def8ee13-1cbf-4f79-b919-0c759c00b6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31763
47842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3176347842
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.52743902
Short name T36
Test name
Test status
Simulation time 15470678713 ps
CPU time 63.5 seconds
Started Jul 26 05:04:02 PM PDT 24
Finished Jul 26 05:05:06 PM PDT 24
Peak memory 256984 kb
Host smart-a45e3f85-9b56-4f05-addd-c87057f8c580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52743
902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.52743902
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.4122703667
Short name T696
Test name
Test status
Simulation time 679502881 ps
CPU time 43.33 seconds
Started Jul 26 05:03:56 PM PDT 24
Finished Jul 26 05:04:39 PM PDT 24
Peak memory 256840 kb
Host smart-1dca091e-d04b-48a8-8fc6-d3a448e7b409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41227
03667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.4122703667
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1239203953
Short name T121
Test name
Test status
Simulation time 24450818557 ps
CPU time 2831.49 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:51:04 PM PDT 24
Peak memory 322636 kb
Host smart-a0e668a5-c04b-424a-82eb-9cc20d7e1814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239203953 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1239203953
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2140207230
Short name T61
Test name
Test status
Simulation time 16678404870 ps
CPU time 1376.69 seconds
Started Jul 26 05:03:56 PM PDT 24
Finished Jul 26 05:26:53 PM PDT 24
Peak memory 289460 kb
Host smart-821cdd1f-9783-4c49-b339-6709782d547a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140207230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2140207230
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3089864818
Short name T279
Test name
Test status
Simulation time 1522349691 ps
CPU time 111.92 seconds
Started Jul 26 05:03:57 PM PDT 24
Finished Jul 26 05:05:49 PM PDT 24
Peak memory 256500 kb
Host smart-ea04687c-17aa-4e80-9e70-675fe3645314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30898
64818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3089864818
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4213892890
Short name T613
Test name
Test status
Simulation time 971089613 ps
CPU time 30.82 seconds
Started Jul 26 05:03:53 PM PDT 24
Finished Jul 26 05:04:24 PM PDT 24
Peak memory 248584 kb
Host smart-d011247c-f3a3-466e-b8a8-4240efab61cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42138
92890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4213892890
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.4008707152
Short name T348
Test name
Test status
Simulation time 50992173460 ps
CPU time 975.49 seconds
Started Jul 26 05:03:56 PM PDT 24
Finished Jul 26 05:20:12 PM PDT 24
Peak memory 281312 kb
Host smart-3564b5fb-1397-4377-8542-6f6d29caaaee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008707152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.4008707152
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3744806464
Short name T676
Test name
Test status
Simulation time 123754399522 ps
CPU time 2209.49 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:40:42 PM PDT 24
Peak memory 287760 kb
Host smart-90e8e19d-4fcf-48b9-959d-2b58292a81d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744806464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3744806464
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.4281576047
Short name T336
Test name
Test status
Simulation time 42932636427 ps
CPU time 490.98 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:12:03 PM PDT 24
Peak memory 248888 kb
Host smart-df0f06ca-3e1f-4ef0-b408-de5b8df1ae50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281576047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4281576047
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1631833086
Short name T450
Test name
Test status
Simulation time 929741806 ps
CPU time 16.62 seconds
Started Jul 26 05:04:09 PM PDT 24
Finished Jul 26 05:04:25 PM PDT 24
Peak memory 248688 kb
Host smart-f663b11b-bce1-4993-a7ed-aa84cf3498ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16318
33086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1631833086
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2705709300
Short name T418
Test name
Test status
Simulation time 128969918 ps
CPU time 11.28 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:04:12 PM PDT 24
Peak memory 248232 kb
Host smart-ffe5dd01-138d-4eee-a741-667c8d6a179f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27057
09300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2705709300
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1709146544
Short name T518
Test name
Test status
Simulation time 451292402 ps
CPU time 30.4 seconds
Started Jul 26 05:03:59 PM PDT 24
Finished Jul 26 05:04:30 PM PDT 24
Peak memory 256456 kb
Host smart-6d352837-1ddf-4e66-bded-51270179e80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17091
46544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1709146544
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1610195240
Short name T308
Test name
Test status
Simulation time 3405352649 ps
CPU time 35.85 seconds
Started Jul 26 05:03:58 PM PDT 24
Finished Jul 26 05:04:34 PM PDT 24
Peak memory 256884 kb
Host smart-81a90db4-4823-418f-99e6-8afd143bcf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16101
95240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1610195240
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.482015773
Short name T98
Test name
Test status
Simulation time 58142785660 ps
CPU time 1605.98 seconds
Started Jul 26 05:03:51 PM PDT 24
Finished Jul 26 05:30:37 PM PDT 24
Peak memory 301176 kb
Host smart-6d06904e-e5a9-46ed-8398-101b07e7fe31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482015773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.482015773
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4068198250
Short name T396
Test name
Test status
Simulation time 72640885427 ps
CPU time 1191.29 seconds
Started Jul 26 05:04:09 PM PDT 24
Finished Jul 26 05:24:01 PM PDT 24
Peak memory 289112 kb
Host smart-d86a33a2-f4ab-47ee-a72e-3b64e8c24052
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068198250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4068198250
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2428216444
Short name T478
Test name
Test status
Simulation time 19235228999 ps
CPU time 247.1 seconds
Started Jul 26 05:03:53 PM PDT 24
Finished Jul 26 05:08:01 PM PDT 24
Peak memory 251720 kb
Host smart-6db23800-b85f-416a-b81e-b152a95ebcb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24282
16444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2428216444
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1764426275
Short name T536
Test name
Test status
Simulation time 124018135 ps
CPU time 13.06 seconds
Started Jul 26 05:04:04 PM PDT 24
Finished Jul 26 05:04:17 PM PDT 24
Peak memory 248284 kb
Host smart-4afd8342-6f0d-4636-a8e3-a418a27a6852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17644
26275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1764426275
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3220179676
Short name T42
Test name
Test status
Simulation time 49276927207 ps
CPU time 1410.44 seconds
Started Jul 26 05:04:11 PM PDT 24
Finished Jul 26 05:27:42 PM PDT 24
Peak memory 272260 kb
Host smart-7bd389b8-2411-4e5f-be33-51bddaf763cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220179676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3220179676
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.990276340
Short name T648
Test name
Test status
Simulation time 786291885422 ps
CPU time 2589.06 seconds
Started Jul 26 05:04:10 PM PDT 24
Finished Jul 26 05:47:20 PM PDT 24
Peak memory 273432 kb
Host smart-ba0e1f6e-3013-4b63-a2fb-aca68e8b509b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990276340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.990276340
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.236382744
Short name T522
Test name
Test status
Simulation time 5354900612 ps
CPU time 218.58 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:07:39 PM PDT 24
Peak memory 248636 kb
Host smart-58050a45-3094-4a87-8e7d-fb8607f502c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236382744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.236382744
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2641001419
Short name T39
Test name
Test status
Simulation time 295137929 ps
CPU time 7.27 seconds
Started Jul 26 05:03:54 PM PDT 24
Finished Jul 26 05:04:01 PM PDT 24
Peak memory 248724 kb
Host smart-af99ea55-5df5-4a53-bd12-c9eb0db02dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26410
01419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2641001419
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3797298288
Short name T653
Test name
Test status
Simulation time 796116003 ps
CPU time 24.37 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:04:17 PM PDT 24
Peak memory 248272 kb
Host smart-8240c550-15af-4154-bf6e-1f58e3b89f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37972
98288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3797298288
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4179194749
Short name T100
Test name
Test status
Simulation time 4582938083 ps
CPU time 62.44 seconds
Started Jul 26 05:03:52 PM PDT 24
Finished Jul 26 05:04:55 PM PDT 24
Peak memory 256624 kb
Host smart-e1d3db12-cedf-4670-a65d-42dedd85e881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41791
94749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4179194749
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2080790502
Short name T593
Test name
Test status
Simulation time 516520387 ps
CPU time 26.59 seconds
Started Jul 26 05:03:55 PM PDT 24
Finished Jul 26 05:04:22 PM PDT 24
Peak memory 248720 kb
Host smart-db877155-957e-45d0-8b5c-ea7d39cc55eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20807
90502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2080790502
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3178877016
Short name T4
Test name
Test status
Simulation time 7280666109 ps
CPU time 207.44 seconds
Started Jul 26 05:04:01 PM PDT 24
Finished Jul 26 05:07:29 PM PDT 24
Peak memory 256020 kb
Host smart-93ad37d6-7b9e-45a3-aa25-402309782815
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178877016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3178877016
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2398934497
Short name T615
Test name
Test status
Simulation time 290903785713 ps
CPU time 4030.52 seconds
Started Jul 26 05:03:59 PM PDT 24
Finished Jul 26 06:11:10 PM PDT 24
Peak memory 335440 kb
Host smart-1d04da6d-7f9e-42c5-9a6f-12000cc510a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398934497 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2398934497
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4235413321
Short name T560
Test name
Test status
Simulation time 29274286734 ps
CPU time 695.27 seconds
Started Jul 26 05:04:09 PM PDT 24
Finished Jul 26 05:15:45 PM PDT 24
Peak memory 273328 kb
Host smart-3a4fd6a3-78c7-4a92-be18-19861a124708
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235413321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4235413321
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3265497830
Short name T409
Test name
Test status
Simulation time 32235165215 ps
CPU time 241.98 seconds
Started Jul 26 05:03:58 PM PDT 24
Finished Jul 26 05:08:01 PM PDT 24
Peak memory 256628 kb
Host smart-478ebe07-54d3-417c-b5c8-7dc6f4c1b3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32654
97830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3265497830
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3754913302
Short name T270
Test name
Test status
Simulation time 993278578 ps
CPU time 59.82 seconds
Started Jul 26 05:04:06 PM PDT 24
Finished Jul 26 05:05:06 PM PDT 24
Peak memory 256988 kb
Host smart-d4c50f44-58fc-4596-ac4c-34c0ee9ffe6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
13302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3754913302
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3610191604
Short name T343
Test name
Test status
Simulation time 45631409883 ps
CPU time 2788.8 seconds
Started Jul 26 05:04:04 PM PDT 24
Finished Jul 26 05:50:34 PM PDT 24
Peak memory 289108 kb
Host smart-700dc753-476a-4ccc-8f2c-16bba05a2189
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610191604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3610191604
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2768671167
Short name T28
Test name
Test status
Simulation time 82648977094 ps
CPU time 1143.3 seconds
Started Jul 26 05:04:01 PM PDT 24
Finished Jul 26 05:23:05 PM PDT 24
Peak memory 265240 kb
Host smart-467efb18-e829-46e1-9de5-6aed630876a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768671167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2768671167
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.911224097
Short name T125
Test name
Test status
Simulation time 34533981063 ps
CPU time 313.47 seconds
Started Jul 26 05:04:02 PM PDT 24
Finished Jul 26 05:09:16 PM PDT 24
Peak memory 248588 kb
Host smart-412398a3-db07-47b7-a4de-0d8139af0015
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911224097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.911224097
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2092295047
Short name T582
Test name
Test status
Simulation time 1370590263 ps
CPU time 38.08 seconds
Started Jul 26 05:04:05 PM PDT 24
Finished Jul 26 05:04:43 PM PDT 24
Peak memory 256664 kb
Host smart-dad25556-2f12-45ed-b188-a3432810bbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20922
95047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2092295047
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3313241143
Short name T452
Test name
Test status
Simulation time 226987929 ps
CPU time 30.15 seconds
Started Jul 26 05:04:01 PM PDT 24
Finished Jul 26 05:04:32 PM PDT 24
Peak memory 248500 kb
Host smart-08c97ab9-4420-4934-b981-441e628cef81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33132
41143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3313241143
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1376462948
Short name T78
Test name
Test status
Simulation time 7146480588 ps
CPU time 51.92 seconds
Started Jul 26 05:04:05 PM PDT 24
Finished Jul 26 05:04:57 PM PDT 24
Peak memory 256836 kb
Host smart-c6852438-2c13-44a0-92b7-ea7a21ed1c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13764
62948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1376462948
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1172015958
Short name T609
Test name
Test status
Simulation time 885507287 ps
CPU time 23.23 seconds
Started Jul 26 05:04:05 PM PDT 24
Finished Jul 26 05:04:28 PM PDT 24
Peak memory 256200 kb
Host smart-49627d47-b1d4-47e9-851f-c76bdea59cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11720
15958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1172015958
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2287268960
Short name T515
Test name
Test status
Simulation time 28996023019 ps
CPU time 1857.79 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:34:58 PM PDT 24
Peak memory 288788 kb
Host smart-45cd263f-28cf-4ccb-bd7b-91fde405dfb7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287268960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2287268960
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2092717355
Short name T113
Test name
Test status
Simulation time 48846867585 ps
CPU time 1581.88 seconds
Started Jul 26 05:04:10 PM PDT 24
Finished Jul 26 05:30:32 PM PDT 24
Peak memory 289596 kb
Host smart-14d1b8e0-b52c-46ec-9aba-7af9c43b6dc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092717355 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2092717355
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1518010013
Short name T656
Test name
Test status
Simulation time 183660571849 ps
CPU time 1649.05 seconds
Started Jul 26 05:04:03 PM PDT 24
Finished Jul 26 05:31:33 PM PDT 24
Peak memory 272672 kb
Host smart-21d24c50-431f-4dc4-951c-0ec03f57c6d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518010013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1518010013
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2778675386
Short name T48
Test name
Test status
Simulation time 1172073451 ps
CPU time 74.15 seconds
Started Jul 26 05:04:11 PM PDT 24
Finished Jul 26 05:05:26 PM PDT 24
Peak memory 256116 kb
Host smart-b89234e5-72b1-4553-a0b1-3a9eb13020fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
75386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2778675386
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3155343070
Short name T93
Test name
Test status
Simulation time 2110039243 ps
CPU time 73.37 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:05:14 PM PDT 24
Peak memory 248728 kb
Host smart-b94b04a6-9557-43da-920f-8ace1ac065f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31553
43070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3155343070
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2523877771
Short name T346
Test name
Test status
Simulation time 36082420726 ps
CPU time 2555.21 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:46:36 PM PDT 24
Peak memory 289752 kb
Host smart-04f0f0a0-49e4-4c19-bfed-f66720ac06c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523877771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2523877771
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4286109108
Short name T200
Test name
Test status
Simulation time 45557278227 ps
CPU time 2591 seconds
Started Jul 26 05:04:10 PM PDT 24
Finished Jul 26 05:47:22 PM PDT 24
Peak memory 286532 kb
Host smart-e31e1060-051d-43d9-8eb1-3fbbe12926c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286109108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4286109108
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2875751513
Short name T618
Test name
Test status
Simulation time 28757874772 ps
CPU time 581.62 seconds
Started Jul 26 05:04:04 PM PDT 24
Finished Jul 26 05:13:46 PM PDT 24
Peak memory 249108 kb
Host smart-129a2a9c-5637-4d88-9f35-242a696c0c38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875751513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2875751513
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2325427231
Short name T388
Test name
Test status
Simulation time 698494799 ps
CPU time 24.31 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:04:25 PM PDT 24
Peak memory 255692 kb
Host smart-bf222e0a-30b8-4570-baea-433191bbc68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23254
27231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2325427231
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1109839911
Short name T43
Test name
Test status
Simulation time 200705001 ps
CPU time 7.55 seconds
Started Jul 26 05:04:01 PM PDT 24
Finished Jul 26 05:04:08 PM PDT 24
Peak memory 248428 kb
Host smart-f9207b97-4f74-42b9-806c-c926a705208f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11098
39911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1109839911
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3639027274
Short name T599
Test name
Test status
Simulation time 550425174 ps
CPU time 39.34 seconds
Started Jul 26 05:04:09 PM PDT 24
Finished Jul 26 05:04:48 PM PDT 24
Peak memory 256808 kb
Host smart-e08235e9-f28f-4658-9e21-fb9ccdbcd2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36390
27274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3639027274
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2736676239
Short name T115
Test name
Test status
Simulation time 46069407124 ps
CPU time 2610.05 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:47:31 PM PDT 24
Peak memory 286424 kb
Host smart-d0f59e59-a8fd-4f19-a143-65b91522eb20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736676239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2736676239
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3296310362
Short name T669
Test name
Test status
Simulation time 39056339664 ps
CPU time 3459.28 seconds
Started Jul 26 05:04:11 PM PDT 24
Finished Jul 26 06:01:51 PM PDT 24
Peak memory 322164 kb
Host smart-d0d1ca43-d8dc-4134-b7e6-fd6055bf7f8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296310362 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3296310362
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1193039418
Short name T75
Test name
Test status
Simulation time 22822426130 ps
CPU time 1389.57 seconds
Started Jul 26 05:04:12 PM PDT 24
Finished Jul 26 05:27:22 PM PDT 24
Peak memory 289404 kb
Host smart-99870ed4-9bc9-4fc3-bedd-86c680611c0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193039418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1193039418
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.380210097
Short name T512
Test name
Test status
Simulation time 15134681733 ps
CPU time 251.79 seconds
Started Jul 26 05:04:19 PM PDT 24
Finished Jul 26 05:08:31 PM PDT 24
Peak memory 257252 kb
Host smart-102ceb52-c56c-4bd8-8989-728f4827aee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38021
0097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.380210097
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1746952232
Short name T73
Test name
Test status
Simulation time 2789569345 ps
CPU time 42.01 seconds
Started Jul 26 05:04:12 PM PDT 24
Finished Jul 26 05:04:54 PM PDT 24
Peak memory 248896 kb
Host smart-4b1e324a-6ece-46b5-90e6-6fbc0bd04edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17469
52232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1746952232
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2103621485
Short name T625
Test name
Test status
Simulation time 39252614433 ps
CPU time 851.26 seconds
Started Jul 26 05:04:11 PM PDT 24
Finished Jul 26 05:18:23 PM PDT 24
Peak memory 272452 kb
Host smart-b40f8691-6d2b-41ea-aaa6-21a109b911c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103621485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2103621485
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2595265787
Short name T535
Test name
Test status
Simulation time 79107884259 ps
CPU time 1723.51 seconds
Started Jul 26 05:04:12 PM PDT 24
Finished Jul 26 05:32:56 PM PDT 24
Peak memory 285628 kb
Host smart-4cf30009-cf26-4d19-80f6-d9f1314885e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595265787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2595265787
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1140221362
Short name T546
Test name
Test status
Simulation time 2337010693 ps
CPU time 98.88 seconds
Started Jul 26 05:04:15 PM PDT 24
Finished Jul 26 05:05:54 PM PDT 24
Peak memory 248808 kb
Host smart-852dce21-8485-4a98-9856-7083d492bcae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140221362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1140221362
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.111050473
Short name T617
Test name
Test status
Simulation time 653466654 ps
CPU time 7.02 seconds
Started Jul 26 05:04:00 PM PDT 24
Finished Jul 26 05:04:07 PM PDT 24
Peak memory 248800 kb
Host smart-8199a8c6-1ec7-424b-b21b-1776c0f81494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11105
0473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.111050473
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1191206815
Short name T310
Test name
Test status
Simulation time 1044888572 ps
CPU time 21.06 seconds
Started Jul 26 05:04:06 PM PDT 24
Finished Jul 26 05:04:27 PM PDT 24
Peak memory 254948 kb
Host smart-759f4507-1d7a-479f-a774-a9b36b3503f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11912
06815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1191206815
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2242001967
Short name T67
Test name
Test status
Simulation time 1854417868 ps
CPU time 18.19 seconds
Started Jul 26 05:04:05 PM PDT 24
Finished Jul 26 05:04:24 PM PDT 24
Peak memory 256932 kb
Host smart-95ce0e10-3b55-484e-b0b4-a4529dedf9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22420
01967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2242001967
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1826619079
Short name T565
Test name
Test status
Simulation time 101396705806 ps
CPU time 1187.25 seconds
Started Jul 26 05:04:15 PM PDT 24
Finished Jul 26 05:24:02 PM PDT 24
Peak memory 288980 kb
Host smart-eb6cb2eb-0b45-42e0-b0ba-9f9e6fc791fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826619079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1826619079
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2909443074
Short name T626
Test name
Test status
Simulation time 23091910440 ps
CPU time 1644.96 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:31:38 PM PDT 24
Peak memory 273424 kb
Host smart-a20c6881-6754-4659-81cb-446a2ae7b070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909443074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2909443074
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1400131971
Short name T300
Test name
Test status
Simulation time 507197074 ps
CPU time 51.64 seconds
Started Jul 26 05:04:14 PM PDT 24
Finished Jul 26 05:05:06 PM PDT 24
Peak memory 256884 kb
Host smart-b040c5b7-a3b0-47c4-8e0e-0bdbce1a95b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14001
31971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1400131971
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.577327284
Short name T475
Test name
Test status
Simulation time 711302823 ps
CPU time 43.66 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:04:57 PM PDT 24
Peak memory 248372 kb
Host smart-28f0cfef-3c9a-42c8-83d7-79273a9686ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57732
7284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.577327284
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.934905070
Short name T205
Test name
Test status
Simulation time 15842987408 ps
CPU time 1245.75 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:24:59 PM PDT 24
Peak memory 273228 kb
Host smart-d916312e-6229-454f-a514-06f3a29c354c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934905070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.934905070
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2055304987
Short name T576
Test name
Test status
Simulation time 75399129016 ps
CPU time 2172.08 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:40:25 PM PDT 24
Peak memory 273396 kb
Host smart-403fe880-07e4-44ff-82c2-49542646e6fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055304987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2055304987
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3200427148
Short name T605
Test name
Test status
Simulation time 3259575542 ps
CPU time 144.21 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:06:37 PM PDT 24
Peak memory 254308 kb
Host smart-66e0b1b1-ffca-4a25-b4bf-ed7d73de2fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200427148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3200427148
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2066119306
Short name T502
Test name
Test status
Simulation time 164436015 ps
CPU time 13.33 seconds
Started Jul 26 05:04:14 PM PDT 24
Finished Jul 26 05:04:27 PM PDT 24
Peak memory 254828 kb
Host smart-02d4c6c6-feef-4b32-8dca-42b6044faa22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20661
19306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2066119306
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2457798424
Short name T586
Test name
Test status
Simulation time 3682447598 ps
CPU time 61.33 seconds
Started Jul 26 05:04:14 PM PDT 24
Finished Jul 26 05:05:15 PM PDT 24
Peak memory 249800 kb
Host smart-10f728da-fcb1-4b05-bfdb-b88d05485553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24577
98424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2457798424
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2402713353
Short name T394
Test name
Test status
Simulation time 427215373 ps
CPU time 39.78 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:04:53 PM PDT 24
Peak memory 256028 kb
Host smart-22b9f435-7373-46ff-a501-a38543f22308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24027
13353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2402713353
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.738448446
Short name T703
Test name
Test status
Simulation time 21735474853 ps
CPU time 1191.27 seconds
Started Jul 26 05:04:19 PM PDT 24
Finished Jul 26 05:24:10 PM PDT 24
Peak memory 288428 kb
Host smart-679f8504-48fd-4aa0-a5dc-35645d62d6a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738448446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.738448446
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2039600926
Short name T80
Test name
Test status
Simulation time 132308886457 ps
CPU time 1443.43 seconds
Started Jul 26 05:04:11 PM PDT 24
Finished Jul 26 05:28:15 PM PDT 24
Peak memory 290188 kb
Host smart-0e7ed07a-7ef0-483d-9244-498d1fc27a0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039600926 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2039600926
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.440228474
Short name T645
Test name
Test status
Simulation time 16277867958 ps
CPU time 731.39 seconds
Started Jul 26 05:04:14 PM PDT 24
Finished Jul 26 05:16:26 PM PDT 24
Peak memory 273168 kb
Host smart-3707ebd3-6563-4fc2-a6bf-788b7e9d5c3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440228474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.440228474
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1649941239
Short name T611
Test name
Test status
Simulation time 1739502779 ps
CPU time 127.56 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:06:21 PM PDT 24
Peak memory 256944 kb
Host smart-2cabe321-9673-45f9-8665-ab1666f868b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16499
41239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1649941239
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3845286848
Short name T674
Test name
Test status
Simulation time 496316301 ps
CPU time 11.57 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:04:24 PM PDT 24
Peak memory 253268 kb
Host smart-a77b59ad-9f9d-41a2-adbe-dc346b8d0385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38452
86848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3845286848
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3835623026
Short name T562
Test name
Test status
Simulation time 101523434796 ps
CPU time 1401.41 seconds
Started Jul 26 05:04:12 PM PDT 24
Finished Jul 26 05:27:34 PM PDT 24
Peak memory 273156 kb
Host smart-9dcaad30-8571-4da4-8136-2fa6f0b3d91e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835623026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3835623026
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1476107507
Short name T114
Test name
Test status
Simulation time 122004186496 ps
CPU time 1869.75 seconds
Started Jul 26 05:04:14 PM PDT 24
Finished Jul 26 05:35:24 PM PDT 24
Peak memory 273340 kb
Host smart-e58c5699-b023-49b8-b435-36e3f88dd3aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476107507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1476107507
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.157234214
Short name T306
Test name
Test status
Simulation time 11418508821 ps
CPU time 501.69 seconds
Started Jul 26 05:04:13 PM PDT 24
Finished Jul 26 05:12:35 PM PDT 24
Peak memory 248596 kb
Host smart-aaf8ed8b-ceae-4ecd-bc28-45f89c025128
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157234214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.157234214
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1927574863
Short name T463
Test name
Test status
Simulation time 244790586 ps
CPU time 8.41 seconds
Started Jul 26 05:04:09 PM PDT 24
Finished Jul 26 05:04:17 PM PDT 24
Peak memory 254488 kb
Host smart-2c2b1579-0570-4540-8647-7598727790b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275
74863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1927574863
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2679828081
Short name T309
Test name
Test status
Simulation time 722832071 ps
CPU time 24.97 seconds
Started Jul 26 05:04:12 PM PDT 24
Finished Jul 26 05:04:37 PM PDT 24
Peak memory 256164 kb
Host smart-b7b4383e-1a2a-49e9-9fb9-e4f75abf362b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26798
28081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2679828081
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1624552572
Short name T46
Test name
Test status
Simulation time 70570429 ps
CPU time 5.31 seconds
Started Jul 26 05:04:14 PM PDT 24
Finished Jul 26 05:04:19 PM PDT 24
Peak memory 240164 kb
Host smart-49d15392-21b5-4bac-bb4f-abf0bf2e13d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16245
52572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1624552572
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.955123230
Short name T433
Test name
Test status
Simulation time 494601181 ps
CPU time 13.56 seconds
Started Jul 26 05:04:14 PM PDT 24
Finished Jul 26 05:04:27 PM PDT 24
Peak memory 257000 kb
Host smart-8765ed6d-327d-490f-82cd-b5e4263a13c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95512
3230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.955123230
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1111823790
Short name T590
Test name
Test status
Simulation time 85481009071 ps
CPU time 1216.38 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:24:40 PM PDT 24
Peak memory 272668 kb
Host smart-267d3d9b-f3f6-4990-8c01-5b6a594374b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111823790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1111823790
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.913293333
Short name T651
Test name
Test status
Simulation time 1778046442 ps
CPU time 128.85 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:06:31 PM PDT 24
Peak memory 256688 kb
Host smart-b8baa8b8-8c9e-45e5-b1c6-f079fb599eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91329
3333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.913293333
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3027963571
Short name T694
Test name
Test status
Simulation time 3482278156 ps
CPU time 52.77 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:05:16 PM PDT 24
Peak memory 256688 kb
Host smart-d570d094-42ce-4b76-8f54-ef80fd34ac1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30279
63571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3027963571
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1966288027
Short name T545
Test name
Test status
Simulation time 8246187143 ps
CPU time 840.59 seconds
Started Jul 26 05:04:27 PM PDT 24
Finished Jul 26 05:18:28 PM PDT 24
Peak memory 273348 kb
Host smart-a58fe839-60fb-413a-be8f-d5b8605c2577
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966288027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1966288027
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1904180928
Short name T568
Test name
Test status
Simulation time 9875387573 ps
CPU time 378.49 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:10:40 PM PDT 24
Peak memory 248748 kb
Host smart-45b96b6a-009b-406e-a375-2c4541216b96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904180928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1904180928
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3206250925
Short name T378
Test name
Test status
Simulation time 2288258909 ps
CPU time 40.2 seconds
Started Jul 26 05:04:12 PM PDT 24
Finished Jul 26 05:04:53 PM PDT 24
Peak memory 256260 kb
Host smart-2e9c4c80-6a45-4d76-b398-67af469b53e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32062
50925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3206250925
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2344106004
Short name T375
Test name
Test status
Simulation time 539744397 ps
CPU time 11.85 seconds
Started Jul 26 05:04:14 PM PDT 24
Finished Jul 26 05:04:26 PM PDT 24
Peak memory 248516 kb
Host smart-88712c29-9f2e-4ec3-a071-24974bd74e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23441
06004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2344106004
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2360591916
Short name T30
Test name
Test status
Simulation time 264097653 ps
CPU time 38.66 seconds
Started Jul 26 05:04:24 PM PDT 24
Finished Jul 26 05:05:02 PM PDT 24
Peak memory 257032 kb
Host smart-ab53c84e-0cd6-438a-aec7-eec0db7b5bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23605
91916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2360591916
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3666290882
Short name T659
Test name
Test status
Simulation time 468456926 ps
CPU time 8.79 seconds
Started Jul 26 05:04:15 PM PDT 24
Finished Jul 26 05:04:24 PM PDT 24
Peak memory 248756 kb
Host smart-db2599a1-1600-42a4-898f-da85630c3ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36662
90882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3666290882
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1701907033
Short name T447
Test name
Test status
Simulation time 547629466 ps
CPU time 26.59 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:04:49 PM PDT 24
Peak memory 247760 kb
Host smart-a1db90e6-e933-43f3-b998-2d50847fbc78
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701907033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1701907033
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2830413593
Short name T686
Test name
Test status
Simulation time 179136991484 ps
CPU time 6088.87 seconds
Started Jul 26 05:04:26 PM PDT 24
Finished Jul 26 06:45:55 PM PDT 24
Peak memory 338368 kb
Host smart-41e8b095-d360-412c-94f0-75966c253727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830413593 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2830413593
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.460621756
Short name T668
Test name
Test status
Simulation time 4291123717 ps
CPU time 95.38 seconds
Started Jul 26 05:05:02 PM PDT 24
Finished Jul 26 05:06:38 PM PDT 24
Peak memory 256508 kb
Host smart-02ac15dc-4d03-4563-bdbe-e0c98918cbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46062
1756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.460621756
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4145541019
Short name T459
Test name
Test status
Simulation time 276548902 ps
CPU time 23.2 seconds
Started Jul 26 05:31:25 PM PDT 24
Finished Jul 26 05:31:49 PM PDT 24
Peak memory 256468 kb
Host smart-63511927-40ee-4e4e-b3ce-990dd6e8e0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41455
41019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4145541019
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3955580535
Short name T40
Test name
Test status
Simulation time 106530614153 ps
CPU time 754.39 seconds
Started Jul 26 05:04:27 PM PDT 24
Finished Jul 26 05:17:01 PM PDT 24
Peak memory 273288 kb
Host smart-d7ee77e5-eb46-4f36-ab92-84bd30f852e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955580535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3955580535
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.510189518
Short name T701
Test name
Test status
Simulation time 48880789217 ps
CPU time 1221.18 seconds
Started Jul 26 05:04:24 PM PDT 24
Finished Jul 26 05:24:45 PM PDT 24
Peak memory 281608 kb
Host smart-bbd8c88c-add0-443d-a778-0c3e4e0ed272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510189518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.510189518
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.162383052
Short name T295
Test name
Test status
Simulation time 24949289634 ps
CPU time 359.99 seconds
Started Jul 26 05:04:21 PM PDT 24
Finished Jul 26 05:10:22 PM PDT 24
Peak memory 248844 kb
Host smart-e8e9ff64-83ef-4c8b-b599-f4f9e4367fe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162383052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.162383052
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.545347679
Short name T551
Test name
Test status
Simulation time 3408877515 ps
CPU time 51.43 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:05:14 PM PDT 24
Peak memory 256464 kb
Host smart-0f37c728-f0a4-48d0-a7ff-fadf6fb8b2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54534
7679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.545347679
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.970562269
Short name T412
Test name
Test status
Simulation time 3071023883 ps
CPU time 35.47 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:04:58 PM PDT 24
Peak memory 256224 kb
Host smart-587ce3ef-41b2-419e-a090-895131999c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97056
2269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.970562269
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2096033472
Short name T663
Test name
Test status
Simulation time 373198183 ps
CPU time 31.76 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:04:54 PM PDT 24
Peak memory 256124 kb
Host smart-88021e3e-42ff-42fd-be3c-44ea40f77749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20960
33472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2096033472
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3764226889
Short name T616
Test name
Test status
Simulation time 228399794 ps
CPU time 22.1 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:38:04 PM PDT 24
Peak memory 256916 kb
Host smart-b6b1b03c-fae7-4e60-917c-88e1ba706958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37642
26889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3764226889
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.916943416
Short name T63
Test name
Test status
Simulation time 31343249670 ps
CPU time 3517.4 seconds
Started Jul 26 05:28:15 PM PDT 24
Finished Jul 26 06:26:53 PM PDT 24
Peak memory 321824 kb
Host smart-ba7c9a1b-aeab-446c-9a1d-f70aa7d4c6f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916943416 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.916943416
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2881431707
Short name T233
Test name
Test status
Simulation time 343807612 ps
CPU time 2.96 seconds
Started Jul 26 05:03:12 PM PDT 24
Finished Jul 26 05:03:15 PM PDT 24
Peak memory 249016 kb
Host smart-a385fc99-0674-4523-b1bf-6faff41afe1b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2881431707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2881431707
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4174934573
Short name T570
Test name
Test status
Simulation time 917815488 ps
CPU time 38.21 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:04:06 PM PDT 24
Peak memory 248800 kb
Host smart-df4b03bd-5653-45de-a919-60b58464f3be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4174934573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4174934573
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.264054512
Short name T638
Test name
Test status
Simulation time 4761951777 ps
CPU time 133.08 seconds
Started Jul 26 05:02:58 PM PDT 24
Finished Jul 26 05:05:11 PM PDT 24
Peak memory 256664 kb
Host smart-e5d90d97-00b6-420b-a4a4-256418acbc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26405
4512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.264054512
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.986762444
Short name T523
Test name
Test status
Simulation time 1304577209 ps
CPU time 27.33 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:03:33 PM PDT 24
Peak memory 248620 kb
Host smart-c240a486-c77c-4b1c-90f2-e6657b4f60d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98676
2444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.986762444
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2095631257
Short name T633
Test name
Test status
Simulation time 35080742017 ps
CPU time 2071.96 seconds
Started Jul 26 05:03:11 PM PDT 24
Finished Jul 26 05:37:44 PM PDT 24
Peak memory 273284 kb
Host smart-de264f2f-080e-4a17-aafe-bdee1fc52d39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095631257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2095631257
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1064785452
Short name T612
Test name
Test status
Simulation time 40079993237 ps
CPU time 1167.96 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:22:34 PM PDT 24
Peak memory 272908 kb
Host smart-375bc0a3-781e-43ed-8bd8-b797677e34b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064785452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1064785452
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3024402150
Short name T7
Test name
Test status
Simulation time 10604492091 ps
CPU time 451.26 seconds
Started Jul 26 05:03:22 PM PDT 24
Finished Jul 26 05:10:53 PM PDT 24
Peak memory 248852 kb
Host smart-51328c9b-adcb-429b-b75f-5b406397a443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024402150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3024402150
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3429869263
Short name T242
Test name
Test status
Simulation time 1160459282 ps
CPU time 37.46 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:03:44 PM PDT 24
Peak memory 256268 kb
Host smart-d0ab3051-07fd-4ad6-8231-efd9eeb4783e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34298
69263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3429869263
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4083311264
Short name T552
Test name
Test status
Simulation time 169828611 ps
CPU time 5.56 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:03:30 PM PDT 24
Peak memory 254796 kb
Host smart-27acbf8c-041d-47a7-ab94-98113c51ed39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40833
11264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4083311264
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1551625366
Short name T10
Test name
Test status
Simulation time 1717172672 ps
CPU time 22.98 seconds
Started Jul 26 05:03:10 PM PDT 24
Finished Jul 26 05:03:33 PM PDT 24
Peak memory 273792 kb
Host smart-56b834fd-47ac-4c9c-9c9c-23431ff21da0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1551625366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1551625366
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3656303246
Short name T84
Test name
Test status
Simulation time 1719343800 ps
CPU time 54.83 seconds
Started Jul 26 05:03:09 PM PDT 24
Finished Jul 26 05:04:04 PM PDT 24
Peak memory 256544 kb
Host smart-1429fd7a-926d-4f41-b96d-60231cb2c20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36563
03246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3656303246
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3669276219
Short name T390
Test name
Test status
Simulation time 179374081 ps
CPU time 22.11 seconds
Started Jul 26 05:03:12 PM PDT 24
Finished Jul 26 05:03:34 PM PDT 24
Peak memory 256916 kb
Host smart-5b0fbf1c-9227-4159-ac0b-51f6b1a368f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36692
76219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3669276219
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.626699636
Short name T277
Test name
Test status
Simulation time 6897654193 ps
CPU time 345.1 seconds
Started Jul 26 05:03:15 PM PDT 24
Finished Jul 26 05:09:01 PM PDT 24
Peak memory 256960 kb
Host smart-e66a96a3-f742-4e05-b0a6-91ece6afc6bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626699636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.626699636
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.152429367
Short name T62
Test name
Test status
Simulation time 245755020369 ps
CPU time 4178.63 seconds
Started Jul 26 05:03:08 PM PDT 24
Finished Jul 26 06:12:47 PM PDT 24
Peak memory 305300 kb
Host smart-25da01d0-36ff-4183-a3d5-5a7c7a1c3543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152429367 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.152429367
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1393280946
Short name T103
Test name
Test status
Simulation time 109592708313 ps
CPU time 3021.81 seconds
Started Jul 26 05:04:24 PM PDT 24
Finished Jul 26 05:54:46 PM PDT 24
Peak memory 281428 kb
Host smart-e047938c-f171-4ea5-b742-3c594c8d1c2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393280946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1393280946
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1200398255
Short name T314
Test name
Test status
Simulation time 7985667326 ps
CPU time 155.68 seconds
Started Jul 26 05:04:28 PM PDT 24
Finished Jul 26 05:07:04 PM PDT 24
Peak memory 257088 kb
Host smart-fa70189a-488e-4ffb-bafd-f9b369d7eb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12003
98255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1200398255
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1569541052
Short name T2
Test name
Test status
Simulation time 322933220 ps
CPU time 14.56 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:04:38 PM PDT 24
Peak memory 248780 kb
Host smart-68606e78-c8be-43e4-bb2e-a3a73d5fbf12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15695
41052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1569541052
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1911537212
Short name T353
Test name
Test status
Simulation time 141211968269 ps
CPU time 1956.15 seconds
Started Jul 26 05:04:21 PM PDT 24
Finished Jul 26 05:36:57 PM PDT 24
Peak memory 273188 kb
Host smart-3ce4ad1b-0120-4c46-8f35-c8e82dd73205
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911537212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1911537212
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1187098729
Short name T29
Test name
Test status
Simulation time 28448312503 ps
CPU time 1357.82 seconds
Started Jul 26 05:04:21 PM PDT 24
Finished Jul 26 05:26:59 PM PDT 24
Peak memory 288320 kb
Host smart-21d0298a-6c8f-403e-9fdc-97707065e0b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187098729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1187098729
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3379088563
Short name T597
Test name
Test status
Simulation time 25031320495 ps
CPU time 507.11 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:12:50 PM PDT 24
Peak memory 248768 kb
Host smart-71dfd8b8-d27a-4676-a644-d1055f56f964
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379088563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3379088563
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1310032337
Short name T23
Test name
Test status
Simulation time 1556248432 ps
CPU time 53.23 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:05:16 PM PDT 24
Peak memory 256056 kb
Host smart-d9e40225-9dec-4b5e-bb11-a4cbb235647d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13100
32337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1310032337
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.703846466
Short name T529
Test name
Test status
Simulation time 4173467569 ps
CPU time 37.99 seconds
Started Jul 26 05:06:41 PM PDT 24
Finished Jul 26 05:07:19 PM PDT 24
Peak memory 248352 kb
Host smart-a8e9d798-6ea1-4f3c-a7b5-8253c01c2f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70384
6466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.703846466
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3569920987
Short name T553
Test name
Test status
Simulation time 267325574 ps
CPU time 35.14 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:04:57 PM PDT 24
Peak memory 256376 kb
Host smart-b2212733-b2fb-4b94-b4e4-123da3538fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35699
20987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3569920987
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3003374421
Short name T457
Test name
Test status
Simulation time 1566452336 ps
CPU time 49.17 seconds
Started Jul 26 05:21:12 PM PDT 24
Finished Jul 26 05:22:01 PM PDT 24
Peak memory 256372 kb
Host smart-cb89fc30-1711-476b-b27f-a1ff6495de27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30033
74421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3003374421
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1690192797
Short name T639
Test name
Test status
Simulation time 13807618926 ps
CPU time 1215.22 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:24:39 PM PDT 24
Peak memory 285512 kb
Host smart-0af5715e-ec3e-47ef-a225-e5e01093660d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690192797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1690192797
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2874512650
Short name T702
Test name
Test status
Simulation time 37547439036 ps
CPU time 1829.71 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:34:52 PM PDT 24
Peak memory 289196 kb
Host smart-8d29b459-c17d-4d8c-8eed-947fad9eb5e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874512650 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2874512650
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.588626512
Short name T481
Test name
Test status
Simulation time 27857773190 ps
CPU time 1926.91 seconds
Started Jul 26 05:04:24 PM PDT 24
Finished Jul 26 05:36:31 PM PDT 24
Peak memory 283200 kb
Host smart-7348f597-14e1-46b3-ae83-36fe633e6216
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588626512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.588626512
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1012494580
Short name T437
Test name
Test status
Simulation time 3356456840 ps
CPU time 148.68 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:06:51 PM PDT 24
Peak memory 256984 kb
Host smart-e0090851-14cb-4230-8e17-44c37ef227ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10124
94580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1012494580
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.949078016
Short name T469
Test name
Test status
Simulation time 164628400 ps
CPU time 3.91 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:04:27 PM PDT 24
Peak memory 240048 kb
Host smart-c924f507-bfdb-4f75-9c31-a761f9ac85a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94907
8016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.949078016
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2088350158
Short name T579
Test name
Test status
Simulation time 10498350567 ps
CPU time 977.89 seconds
Started Jul 26 05:04:24 PM PDT 24
Finished Jul 26 05:20:42 PM PDT 24
Peak memory 282684 kb
Host smart-f955bfde-b82c-4448-bda6-8908602358a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088350158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2088350158
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2878150283
Short name T267
Test name
Test status
Simulation time 33648239872 ps
CPU time 334 seconds
Started Jul 26 05:04:22 PM PDT 24
Finished Jul 26 05:09:56 PM PDT 24
Peak memory 248744 kb
Host smart-0d537a0d-eb2f-46c9-bf4c-a56d3d58f5c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878150283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2878150283
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.774413342
Short name T440
Test name
Test status
Simulation time 434161274 ps
CPU time 31.63 seconds
Started Jul 26 05:04:46 PM PDT 24
Finished Jul 26 05:05:18 PM PDT 24
Peak memory 248896 kb
Host smart-75cf5668-e966-4ff3-ad7b-0d786054d644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77441
3342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.774413342
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.219573609
Short name T714
Test name
Test status
Simulation time 714749548 ps
CPU time 13.35 seconds
Started Jul 26 05:04:26 PM PDT 24
Finished Jul 26 05:04:39 PM PDT 24
Peak memory 248160 kb
Host smart-6fd8e102-259c-4309-99e5-6473f59ab2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21957
3609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.219573609
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4184216675
Short name T298
Test name
Test status
Simulation time 422553597 ps
CPU time 24.15 seconds
Started Jul 26 05:04:25 PM PDT 24
Finished Jul 26 05:04:49 PM PDT 24
Peak memory 249288 kb
Host smart-7ad33ec3-4e4d-4f08-8569-7e6d41a28924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41842
16675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4184216675
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.513603344
Short name T392
Test name
Test status
Simulation time 690255443 ps
CPU time 45.36 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:05:09 PM PDT 24
Peak memory 248724 kb
Host smart-4d608c0f-179c-4814-a821-05267db1c079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51360
3344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.513603344
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1834366997
Short name T473
Test name
Test status
Simulation time 55785436811 ps
CPU time 2755.21 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:50:19 PM PDT 24
Peak memory 289156 kb
Host smart-b5958588-f38a-4532-8cda-72d01bc51430
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834366997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1834366997
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.458554395
Short name T395
Test name
Test status
Simulation time 36243412874 ps
CPU time 1218.81 seconds
Started Jul 26 05:04:32 PM PDT 24
Finished Jul 26 05:24:51 PM PDT 24
Peak memory 272932 kb
Host smart-b10030b0-6f40-45ee-a9ca-69a94ec96f75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458554395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.458554395
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.735974316
Short name T486
Test name
Test status
Simulation time 813042009 ps
CPU time 46.24 seconds
Started Jul 26 05:04:31 PM PDT 24
Finished Jul 26 05:05:17 PM PDT 24
Peak memory 256840 kb
Host smart-7400481c-9a33-42fd-8665-5e41d7e22cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73597
4316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.735974316
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.480153628
Short name T124
Test name
Test status
Simulation time 4203424467 ps
CPU time 21.89 seconds
Started Jul 26 05:04:35 PM PDT 24
Finished Jul 26 05:04:57 PM PDT 24
Peak memory 255496 kb
Host smart-56cdc77d-a3ab-43d3-a8af-d2ca88c6d7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48015
3628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.480153628
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1342762056
Short name T684
Test name
Test status
Simulation time 171037603126 ps
CPU time 2585.36 seconds
Started Jul 26 05:04:34 PM PDT 24
Finished Jul 26 05:47:39 PM PDT 24
Peak memory 281508 kb
Host smart-542f6ef4-30e7-443e-b312-2fc43141086a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342762056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1342762056
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1997911692
Short name T402
Test name
Test status
Simulation time 20394832898 ps
CPU time 763.01 seconds
Started Jul 26 05:04:35 PM PDT 24
Finished Jul 26 05:17:18 PM PDT 24
Peak memory 269272 kb
Host smart-3e02ee09-adc1-48f5-a00d-a32c4f37a6a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997911692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1997911692
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.526277226
Short name T327
Test name
Test status
Simulation time 7642084848 ps
CPU time 300.04 seconds
Started Jul 26 05:04:32 PM PDT 24
Finished Jul 26 05:09:32 PM PDT 24
Peak memory 248912 kb
Host smart-89a40fd9-db65-4f74-820d-420a44949043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526277226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.526277226
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3971920713
Short name T641
Test name
Test status
Simulation time 79050193 ps
CPU time 4.11 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 05:04:37 PM PDT 24
Peak memory 248752 kb
Host smart-7169179d-3075-4514-8f29-071d4f3de4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39719
20713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3971920713
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1764815815
Short name T675
Test name
Test status
Simulation time 238475587 ps
CPU time 26.55 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 05:05:00 PM PDT 24
Peak memory 248764 kb
Host smart-bcf265e6-ceea-43a7-b5ab-6c63e5971c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17648
15815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1764815815
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2337627369
Short name T290
Test name
Test status
Simulation time 391650240 ps
CPU time 26.88 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 05:05:00 PM PDT 24
Peak memory 256308 kb
Host smart-fd96a01c-daca-45f2-b5d2-121ecc0a2ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23376
27369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2337627369
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3455819907
Short name T438
Test name
Test status
Simulation time 1153952434 ps
CPU time 48.4 seconds
Started Jul 26 05:04:32 PM PDT 24
Finished Jul 26 05:05:21 PM PDT 24
Peak memory 256792 kb
Host smart-3731397b-3dc2-452a-8e5d-af4ed54b397f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34558
19907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3455819907
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3701213389
Short name T311
Test name
Test status
Simulation time 1884438477 ps
CPU time 199.8 seconds
Started Jul 26 05:04:31 PM PDT 24
Finished Jul 26 05:07:51 PM PDT 24
Peak memory 256844 kb
Host smart-0298bbf5-37b4-4353-8f35-912abec492ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701213389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3701213389
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3472702608
Short name T405
Test name
Test status
Simulation time 19657464619 ps
CPU time 1059.16 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 05:22:13 PM PDT 24
Peak memory 283252 kb
Host smart-ac2e36f0-e5bd-4d58-b93c-f15b2b5d1434
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472702608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3472702608
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2021165621
Short name T275
Test name
Test status
Simulation time 247200531 ps
CPU time 20.46 seconds
Started Jul 26 05:04:32 PM PDT 24
Finished Jul 26 05:04:52 PM PDT 24
Peak memory 256956 kb
Host smart-9a9d9bf7-4508-45f3-839b-5c843022122e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20211
65621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2021165621
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1755350715
Short name T644
Test name
Test status
Simulation time 1956173079 ps
CPU time 43.84 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 05:05:17 PM PDT 24
Peak memory 248748 kb
Host smart-14c0b34a-2f41-4091-97fe-dc434412aca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17553
50715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1755350715
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3154967184
Short name T334
Test name
Test status
Simulation time 62221839516 ps
CPU time 1730.97 seconds
Started Jul 26 05:04:35 PM PDT 24
Finished Jul 26 05:33:26 PM PDT 24
Peak memory 273112 kb
Host smart-b7354e56-3e1b-4c87-92a0-0ad60a2b0d90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154967184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3154967184
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.640716439
Short name T203
Test name
Test status
Simulation time 53142708643 ps
CPU time 1577.64 seconds
Started Jul 26 05:04:34 PM PDT 24
Finished Jul 26 05:30:51 PM PDT 24
Peak memory 289500 kb
Host smart-08ffaa57-02c1-4018-9b2b-ace86185e31f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640716439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.640716439
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2766574728
Short name T6
Test name
Test status
Simulation time 8393267613 ps
CPU time 349.34 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 05:10:22 PM PDT 24
Peak memory 255824 kb
Host smart-f8f4256c-b568-46c9-9d7e-055bbd3e4e20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766574728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2766574728
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2494836231
Short name T507
Test name
Test status
Simulation time 79503150 ps
CPU time 9.33 seconds
Started Jul 26 05:04:32 PM PDT 24
Finished Jul 26 05:04:41 PM PDT 24
Peak memory 248684 kb
Host smart-9d5885e3-8351-4dbe-a929-fa43ae26904e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24948
36231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2494836231
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.706698294
Short name T712
Test name
Test status
Simulation time 1584673365 ps
CPU time 43.55 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 05:05:16 PM PDT 24
Peak memory 256056 kb
Host smart-0c71fdd6-3534-493e-bf64-2d5afd72f10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70669
8294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.706698294
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1908483171
Short name T432
Test name
Test status
Simulation time 2104577188 ps
CPU time 32.32 seconds
Started Jul 26 05:04:34 PM PDT 24
Finished Jul 26 05:05:06 PM PDT 24
Peak memory 248356 kb
Host smart-762a548f-f265-4513-b254-7e4af5a8f54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19084
83171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1908483171
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4027649466
Short name T666
Test name
Test status
Simulation time 825490420 ps
CPU time 61.56 seconds
Started Jul 26 05:04:34 PM PDT 24
Finished Jul 26 05:05:36 PM PDT 24
Peak memory 255948 kb
Host smart-e5eee784-058c-4675-9d4a-0337e23e313b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40276
49466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4027649466
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.265956156
Short name T710
Test name
Test status
Simulation time 29246995945 ps
CPU time 923.1 seconds
Started Jul 26 05:04:35 PM PDT 24
Finished Jul 26 05:19:59 PM PDT 24
Peak memory 273328 kb
Host smart-579cb067-538e-4bf2-a2b0-38c29bf415b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265956156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.265956156
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.4013637634
Short name T610
Test name
Test status
Simulation time 22506583173 ps
CPU time 1482.02 seconds
Started Jul 26 05:04:37 PM PDT 24
Finished Jul 26 05:29:19 PM PDT 24
Peak memory 273252 kb
Host smart-6493f226-3e5b-49fa-93a0-5e4152e4c502
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013637634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.4013637634
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.80907592
Short name T673
Test name
Test status
Simulation time 16333169776 ps
CPU time 270.11 seconds
Started Jul 26 05:04:35 PM PDT 24
Finished Jul 26 05:09:06 PM PDT 24
Peak memory 256988 kb
Host smart-42841937-3efd-4a27-a630-3b1788c9ca70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80907
592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.80907592
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3719471556
Short name T69
Test name
Test status
Simulation time 1428601670 ps
CPU time 21.53 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 05:04:55 PM PDT 24
Peak memory 248744 kb
Host smart-8d4be103-33d4-473e-9bda-698870f04bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
71556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3719471556
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.890348509
Short name T471
Test name
Test status
Simulation time 42163445889 ps
CPU time 2493.98 seconds
Started Jul 26 05:04:34 PM PDT 24
Finished Jul 26 05:46:08 PM PDT 24
Peak memory 284120 kb
Host smart-eda46161-ec50-4b87-b054-f7b7d0ea1eb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890348509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.890348509
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3613812989
Short name T670
Test name
Test status
Simulation time 174210563 ps
CPU time 19.56 seconds
Started Jul 26 05:04:33 PM PDT 24
Finished Jul 26 05:04:52 PM PDT 24
Peak memory 256208 kb
Host smart-c5a0cf1f-5b04-4152-b90b-446c7b97f83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36138
12989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3613812989
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.425434046
Short name T527
Test name
Test status
Simulation time 773458528 ps
CPU time 44.69 seconds
Started Jul 26 05:04:31 PM PDT 24
Finished Jul 26 05:05:16 PM PDT 24
Peak memory 248520 kb
Host smart-262e9c3d-d381-4d93-856d-3d7e607fcbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42543
4046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.425434046
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1942646055
Short name T316
Test name
Test status
Simulation time 326702406 ps
CPU time 9.2 seconds
Started Jul 26 05:04:34 PM PDT 24
Finished Jul 26 05:04:43 PM PDT 24
Peak memory 252912 kb
Host smart-1b73932a-fc6a-4c47-aca8-ed41a8c22623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19426
46055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1942646055
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2819314734
Short name T662
Test name
Test status
Simulation time 503839527 ps
CPU time 35.66 seconds
Started Jul 26 05:04:31 PM PDT 24
Finished Jul 26 05:05:07 PM PDT 24
Peak memory 256764 kb
Host smart-d642faf6-c026-4ccc-b1db-5bd5bcb6cee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28193
14734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2819314734
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.240204107
Short name T672
Test name
Test status
Simulation time 44147099704 ps
CPU time 759.8 seconds
Started Jul 26 05:04:32 PM PDT 24
Finished Jul 26 05:17:12 PM PDT 24
Peak memory 265176 kb
Host smart-bebb832e-10a0-47f8-a935-6574d623705f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240204107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.240204107
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2043974781
Short name T55
Test name
Test status
Simulation time 51955655654 ps
CPU time 922.5 seconds
Started Jul 26 05:04:43 PM PDT 24
Finished Jul 26 05:20:06 PM PDT 24
Peak memory 272932 kb
Host smart-f2b5eb88-5026-4e0d-9786-b2c07b245311
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043974781 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2043974781
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3748636452
Short name T261
Test name
Test status
Simulation time 8260260394 ps
CPU time 762.57 seconds
Started Jul 26 05:04:50 PM PDT 24
Finished Jul 26 05:17:32 PM PDT 24
Peak memory 273260 kb
Host smart-be079aa2-e1ae-4542-b467-67bd4db5c014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748636452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3748636452
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2696268611
Short name T400
Test name
Test status
Simulation time 1706604093 ps
CPU time 54.66 seconds
Started Jul 26 05:04:48 PM PDT 24
Finished Jul 26 05:05:43 PM PDT 24
Peak memory 256040 kb
Host smart-74a94b62-fd69-49b4-a1fa-26cfd17eff65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26962
68611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2696268611
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.442948
Short name T525
Test name
Test status
Simulation time 4957697637 ps
CPU time 38.08 seconds
Started Jul 26 05:04:49 PM PDT 24
Finished Jul 26 05:05:27 PM PDT 24
Peak memory 256948 kb
Host smart-9a9f4ea3-9bf6-4985-b6ac-174f5d36aad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44294
8 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.442948
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.385469833
Short name T356
Test name
Test status
Simulation time 15766131833 ps
CPU time 1529.85 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:30:13 PM PDT 24
Peak memory 289064 kb
Host smart-93c6cdb5-64ab-416c-88a2-218998adef3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385469833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.385469833
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.374586076
Short name T381
Test name
Test status
Simulation time 11210899260 ps
CPU time 1313.71 seconds
Started Jul 26 05:04:43 PM PDT 24
Finished Jul 26 05:26:37 PM PDT 24
Peak memory 289672 kb
Host smart-59e6c271-74da-4530-8a1b-944dfae06a10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374586076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.374586076
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3663880153
Short name T326
Test name
Test status
Simulation time 40964369296 ps
CPU time 461.08 seconds
Started Jul 26 05:04:45 PM PDT 24
Finished Jul 26 05:12:26 PM PDT 24
Peak memory 248748 kb
Host smart-94b7b35c-6e68-4277-a906-35cb8673bd6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663880153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3663880153
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.129149369
Short name T575
Test name
Test status
Simulation time 1492709216 ps
CPU time 29.63 seconds
Started Jul 26 05:04:43 PM PDT 24
Finished Jul 26 05:05:13 PM PDT 24
Peak memory 256192 kb
Host smart-94b5eedd-a120-433d-8747-802cbb5f63f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12914
9369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.129149369
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2761467471
Short name T441
Test name
Test status
Simulation time 210010326 ps
CPU time 9.45 seconds
Started Jul 26 05:04:41 PM PDT 24
Finished Jul 26 05:04:51 PM PDT 24
Peak memory 248332 kb
Host smart-2f97568c-ccc1-4179-8bc1-88be26466467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27614
67471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2761467471
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1154276291
Short name T259
Test name
Test status
Simulation time 708192654 ps
CPU time 48.28 seconds
Started Jul 26 05:04:46 PM PDT 24
Finished Jul 26 05:05:35 PM PDT 24
Peak memory 248644 kb
Host smart-3997e5ed-80b2-433e-9442-ef5cec7bb7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11542
76291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1154276291
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1692704559
Short name T658
Test name
Test status
Simulation time 1386684636 ps
CPU time 25.71 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:05:08 PM PDT 24
Peak memory 256656 kb
Host smart-0505975f-6d10-4235-87ac-430b830b8a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16927
04559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1692704559
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1449970155
Short name T315
Test name
Test status
Simulation time 184229557779 ps
CPU time 2541.96 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:47:05 PM PDT 24
Peak memory 289748 kb
Host smart-9e29281d-d406-4404-ac9c-bdc33010646a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449970155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1449970155
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3302518955
Short name T255
Test name
Test status
Simulation time 168157876626 ps
CPU time 2987.95 seconds
Started Jul 26 05:04:43 PM PDT 24
Finished Jul 26 05:54:31 PM PDT 24
Peak memory 288688 kb
Host smart-6314c360-50fc-414d-946f-b77630b8c2b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302518955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3302518955
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.4203488209
Short name T682
Test name
Test status
Simulation time 4570458280 ps
CPU time 23.7 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:05:06 PM PDT 24
Peak memory 256620 kb
Host smart-f5bd1050-9efa-48bc-8757-36264b7a04bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
88209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.4203488209
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3694098202
Short name T243
Test name
Test status
Simulation time 1707391618 ps
CPU time 34.17 seconds
Started Jul 26 05:04:48 PM PDT 24
Finished Jul 26 05:05:23 PM PDT 24
Peak memory 256904 kb
Host smart-4795e9f6-ec8b-4337-8cfe-31c1702eca51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36940
98202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3694098202
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1003713436
Short name T319
Test name
Test status
Simulation time 14282703694 ps
CPU time 1194.11 seconds
Started Jul 26 05:04:44 PM PDT 24
Finished Jul 26 05:24:38 PM PDT 24
Peak memory 281492 kb
Host smart-690e9a26-8d7c-48f7-8dfb-6bbde36c14e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003713436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1003713436
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4084068765
Short name T257
Test name
Test status
Simulation time 130681283020 ps
CPU time 1255.56 seconds
Started Jul 26 05:04:43 PM PDT 24
Finished Jul 26 05:25:39 PM PDT 24
Peak memory 287128 kb
Host smart-1deee4dc-42f2-4d3c-8a3a-54d52cff8c56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084068765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4084068765
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1790746415
Short name T321
Test name
Test status
Simulation time 208946405037 ps
CPU time 427.44 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:11:49 PM PDT 24
Peak memory 248776 kb
Host smart-cd9d0fb3-75eb-4047-b746-69d0cf6474cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790746415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1790746415
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.4079670897
Short name T691
Test name
Test status
Simulation time 248704459 ps
CPU time 21.49 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:05:04 PM PDT 24
Peak memory 248856 kb
Host smart-77040356-9e7e-4986-8f3f-a414fb09690b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40796
70897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.4079670897
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3254799434
Short name T430
Test name
Test status
Simulation time 1013730746 ps
CPU time 17.58 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:05:00 PM PDT 24
Peak memory 248760 kb
Host smart-4c57cec6-1781-4562-acc8-a94bf7102bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32547
99434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3254799434
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1329339068
Short name T280
Test name
Test status
Simulation time 3532091839 ps
CPU time 51.16 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:05:34 PM PDT 24
Peak memory 248884 kb
Host smart-6d02ff1a-9046-4e95-9723-27752d287b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13293
39068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1329339068
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3162683991
Short name T492
Test name
Test status
Simulation time 235843817 ps
CPU time 11.88 seconds
Started Jul 26 05:04:47 PM PDT 24
Finished Jul 26 05:04:59 PM PDT 24
Peak memory 256812 kb
Host smart-81cc54a6-a0dd-49a6-bf30-24db7ee2cdd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31626
83991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3162683991
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.831968091
Short name T104
Test name
Test status
Simulation time 45843672678 ps
CPU time 4916.9 seconds
Started Jul 26 05:04:41 PM PDT 24
Finished Jul 26 06:26:39 PM PDT 24
Peak memory 347108 kb
Host smart-a010105d-42d5-4ce0-9907-e05fdfb9c8df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831968091 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.831968091
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2910337163
Short name T713
Test name
Test status
Simulation time 12797036158 ps
CPU time 862.29 seconds
Started Jul 26 05:04:43 PM PDT 24
Finished Jul 26 05:19:05 PM PDT 24
Peak memory 273032 kb
Host smart-ac574f2c-1d0e-48f2-b88b-3ba0ffb25c81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910337163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2910337163
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3272148973
Short name T621
Test name
Test status
Simulation time 7543398399 ps
CPU time 189.83 seconds
Started Jul 26 05:04:44 PM PDT 24
Finished Jul 26 05:07:54 PM PDT 24
Peak memory 256404 kb
Host smart-bfc89f8b-95d9-4f4f-83a8-9d1a860605c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32721
48973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3272148973
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3900643820
Short name T72
Test name
Test status
Simulation time 760154544 ps
CPU time 35.85 seconds
Started Jul 26 05:04:44 PM PDT 24
Finished Jul 26 05:05:20 PM PDT 24
Peak memory 248720 kb
Host smart-97a4e11d-a011-4056-a684-b7c500b7ee8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39006
43820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3900643820
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1219781017
Short name T355
Test name
Test status
Simulation time 69364871283 ps
CPU time 1398 seconds
Started Jul 26 05:04:43 PM PDT 24
Finished Jul 26 05:28:01 PM PDT 24
Peak memory 289788 kb
Host smart-9b1dc9eb-e7e6-4794-9d12-82f55f2f5b68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219781017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1219781017
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3863640376
Short name T467
Test name
Test status
Simulation time 29711506147 ps
CPU time 1538.35 seconds
Started Jul 26 05:04:44 PM PDT 24
Finished Jul 26 05:30:23 PM PDT 24
Peak memory 273052 kb
Host smart-73be93e6-0259-40dd-a610-ad444e134c1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863640376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3863640376
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1531925419
Short name T338
Test name
Test status
Simulation time 11071490891 ps
CPU time 433.42 seconds
Started Jul 26 05:04:49 PM PDT 24
Finished Jul 26 05:12:03 PM PDT 24
Peak memory 255524 kb
Host smart-89456294-7743-4b68-8b43-d0ef1936f948
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531925419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1531925419
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.398981561
Short name T541
Test name
Test status
Simulation time 618897234 ps
CPU time 33.47 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:05:16 PM PDT 24
Peak memory 256384 kb
Host smart-828b5d7f-4222-4eb2-93dd-98276cae6a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39898
1561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.398981561
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3602566124
Short name T122
Test name
Test status
Simulation time 1567492790 ps
CPU time 54.84 seconds
Started Jul 26 05:04:47 PM PDT 24
Finished Jul 26 05:05:42 PM PDT 24
Peak memory 256424 kb
Host smart-e172bfec-25ed-42f9-996c-9820e84947e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36025
66124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3602566124
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.52879972
Short name T547
Test name
Test status
Simulation time 3634019853 ps
CPU time 62.56 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:05:44 PM PDT 24
Peak memory 256580 kb
Host smart-1c61f6e0-ad31-41cc-88fb-da12358cba70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52879
972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.52879972
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1653114560
Short name T237
Test name
Test status
Simulation time 5707642360 ps
CPU time 50.39 seconds
Started Jul 26 05:04:43 PM PDT 24
Finished Jul 26 05:05:33 PM PDT 24
Peak memory 257044 kb
Host smart-d3433718-df4a-4cf6-98eb-11b805071239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16531
14560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1653114560
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2258819295
Short name T120
Test name
Test status
Simulation time 15755122859 ps
CPU time 886.36 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:19:28 PM PDT 24
Peak memory 270104 kb
Host smart-79d49040-ff63-497c-b5d6-435c2a92575f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258819295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2258819295
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3233650970
Short name T530
Test name
Test status
Simulation time 14824836126 ps
CPU time 1398.97 seconds
Started Jul 26 05:04:55 PM PDT 24
Finished Jul 26 05:28:15 PM PDT 24
Peak memory 289520 kb
Host smart-744a3e56-1f12-4c66-80f7-157baf378a37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233650970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3233650970
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1330595924
Short name T488
Test name
Test status
Simulation time 1554904944 ps
CPU time 84.87 seconds
Started Jul 26 05:04:53 PM PDT 24
Finished Jul 26 05:06:18 PM PDT 24
Peak memory 256976 kb
Host smart-814f2fd9-d7a6-4140-880e-93ebd7f6fdcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13305
95924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1330595924
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2170433120
Short name T460
Test name
Test status
Simulation time 80797555 ps
CPU time 7.67 seconds
Started Jul 26 05:04:52 PM PDT 24
Finished Jul 26 05:05:00 PM PDT 24
Peak memory 248368 kb
Host smart-f4500a7c-4215-464f-8c68-6d85cf9550a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21704
33120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2170433120
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.28453808
Short name T244
Test name
Test status
Simulation time 91510934108 ps
CPU time 1329.77 seconds
Started Jul 26 05:04:55 PM PDT 24
Finished Jul 26 05:27:05 PM PDT 24
Peak memory 272736 kb
Host smart-0e559d0b-ce63-4681-9574-35c0b29c20df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28453808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.28453808
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2590818892
Short name T623
Test name
Test status
Simulation time 194204880230 ps
CPU time 3052.5 seconds
Started Jul 26 05:04:53 PM PDT 24
Finished Jul 26 05:55:46 PM PDT 24
Peak memory 287720 kb
Host smart-5b2121f9-cd79-4956-933c-c862de320d99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590818892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2590818892
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3088400861
Short name T116
Test name
Test status
Simulation time 7508836596 ps
CPU time 337.44 seconds
Started Jul 26 05:04:54 PM PDT 24
Finished Jul 26 05:10:32 PM PDT 24
Peak memory 248892 kb
Host smart-80b2f93f-5993-4d22-969f-b290fd1d198f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088400861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3088400861
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1694376524
Short name T688
Test name
Test status
Simulation time 2177893595 ps
CPU time 36.33 seconds
Started Jul 26 05:04:42 PM PDT 24
Finished Jul 26 05:05:18 PM PDT 24
Peak memory 256912 kb
Host smart-717216c0-ef5c-4654-bee8-de3d38ff67a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16943
76524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1694376524
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3690668706
Short name T556
Test name
Test status
Simulation time 7027835701 ps
CPU time 60.94 seconds
Started Jul 26 05:04:55 PM PDT 24
Finished Jul 26 05:05:56 PM PDT 24
Peak memory 256584 kb
Host smart-d626ec78-861c-4183-849d-468a43126ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36906
68706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3690668706
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1658545447
Short name T246
Test name
Test status
Simulation time 568752688 ps
CPU time 37.54 seconds
Started Jul 26 05:04:55 PM PDT 24
Finished Jul 26 05:05:32 PM PDT 24
Peak memory 255756 kb
Host smart-fa5b97a6-de0b-4455-a42c-cb43962fb603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16585
45447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1658545447
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3452479014
Short name T516
Test name
Test status
Simulation time 16386074 ps
CPU time 2.91 seconds
Started Jul 26 05:04:43 PM PDT 24
Finished Jul 26 05:04:46 PM PDT 24
Peak memory 249044 kb
Host smart-b85bd799-4018-4977-b5d9-5a59434d8a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34524
79014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3452479014
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.919453456
Short name T584
Test name
Test status
Simulation time 47778563975 ps
CPU time 1364.03 seconds
Started Jul 26 05:04:51 PM PDT 24
Finished Jul 26 05:27:36 PM PDT 24
Peak memory 289216 kb
Host smart-a8196b90-a7d9-4a5e-84e2-5cfc80069ccc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919453456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.919453456
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2588688464
Short name T198
Test name
Test status
Simulation time 20654988298 ps
CPU time 702.02 seconds
Started Jul 26 05:04:52 PM PDT 24
Finished Jul 26 05:16:34 PM PDT 24
Peak memory 268604 kb
Host smart-cf2a28d3-0537-44bb-b656-e8249f764cc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588688464 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2588688464
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.949287459
Short name T420
Test name
Test status
Simulation time 74286358504 ps
CPU time 2050.61 seconds
Started Jul 26 05:04:53 PM PDT 24
Finished Jul 26 05:39:04 PM PDT 24
Peak memory 286676 kb
Host smart-8f688529-4c5c-4074-8143-41ad21ab6ec7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949287459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.949287459
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2745771922
Short name T455
Test name
Test status
Simulation time 742870341 ps
CPU time 45.12 seconds
Started Jul 26 05:04:53 PM PDT 24
Finished Jul 26 05:05:38 PM PDT 24
Peak memory 256116 kb
Host smart-b4c88091-ff4b-4e7c-b2bd-0c1b2c11cfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27457
71922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2745771922
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4253176867
Short name T491
Test name
Test status
Simulation time 165895121 ps
CPU time 4.22 seconds
Started Jul 26 05:04:52 PM PDT 24
Finished Jul 26 05:04:56 PM PDT 24
Peak memory 240564 kb
Host smart-e6f10550-527a-4fa8-894c-0f8cca047830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42531
76867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4253176867
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3874883957
Short name T500
Test name
Test status
Simulation time 99391575054 ps
CPU time 2563.16 seconds
Started Jul 26 05:04:54 PM PDT 24
Finished Jul 26 05:47:38 PM PDT 24
Peak memory 289040 kb
Host smart-0e3daf6f-b89d-4352-b19a-d9fbf4356887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874883957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3874883957
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.569485944
Short name T589
Test name
Test status
Simulation time 11272796981 ps
CPU time 429.41 seconds
Started Jul 26 05:04:52 PM PDT 24
Finished Jul 26 05:12:02 PM PDT 24
Peak memory 248864 kb
Host smart-48b657e3-39ed-49e3-bab4-612a205d6413
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569485944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.569485944
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3068774557
Short name T22
Test name
Test status
Simulation time 714112760 ps
CPU time 45.92 seconds
Started Jul 26 05:04:52 PM PDT 24
Finished Jul 26 05:05:38 PM PDT 24
Peak memory 256840 kb
Host smart-dc855d89-52ae-4eac-9bbc-cc19172e3125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30687
74557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3068774557
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.4147262184
Short name T304
Test name
Test status
Simulation time 568405862 ps
CPU time 14.49 seconds
Started Jul 26 05:04:52 PM PDT 24
Finished Jul 26 05:05:07 PM PDT 24
Peak memory 248112 kb
Host smart-12cb1727-38b5-4d87-a888-44ab0af2f909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41472
62184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.4147262184
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2681224540
Short name T709
Test name
Test status
Simulation time 1005948314 ps
CPU time 19.32 seconds
Started Jul 26 05:04:54 PM PDT 24
Finished Jul 26 05:05:13 PM PDT 24
Peak memory 248084 kb
Host smart-402370d6-3d81-4556-8476-554be94934fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26812
24540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2681224540
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3182245942
Short name T416
Test name
Test status
Simulation time 512619985 ps
CPU time 29.06 seconds
Started Jul 26 05:04:50 PM PDT 24
Finished Jul 26 05:05:19 PM PDT 24
Peak memory 256972 kb
Host smart-1ff6e23f-f5d1-4e85-aa83-b89ff407524b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31822
45942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3182245942
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1733860251
Short name T221
Test name
Test status
Simulation time 80240841 ps
CPU time 3.62 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:03:29 PM PDT 24
Peak memory 249112 kb
Host smart-f3e650a8-56dc-4358-9000-e267474c199f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1733860251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1733860251
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.4204701287
Short name T580
Test name
Test status
Simulation time 28873243277 ps
CPU time 1823.76 seconds
Started Jul 26 05:03:07 PM PDT 24
Finished Jul 26 05:33:31 PM PDT 24
Peak memory 281588 kb
Host smart-46c618bd-10e1-441c-87c0-b666d4722969
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204701287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4204701287
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2031935356
Short name T399
Test name
Test status
Simulation time 878447286 ps
CPU time 39.56 seconds
Started Jul 26 05:03:11 PM PDT 24
Finished Jul 26 05:03:51 PM PDT 24
Peak memory 248720 kb
Host smart-e989e64e-865f-423f-bb68-443a5d125083
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2031935356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2031935356
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3945579439
Short name T601
Test name
Test status
Simulation time 6164306559 ps
CPU time 172.64 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:06:17 PM PDT 24
Peak memory 256888 kb
Host smart-8957ac6a-fd55-4ab6-a168-f69dd6ecc834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39455
79439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3945579439
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3576651322
Short name T627
Test name
Test status
Simulation time 314984486 ps
CPU time 8.55 seconds
Started Jul 26 05:03:10 PM PDT 24
Finished Jul 26 05:03:19 PM PDT 24
Peak memory 248164 kb
Host smart-64d48f5a-e206-4d2a-bc1e-0f598824ca12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35766
51322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3576651322
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1288909746
Short name T661
Test name
Test status
Simulation time 7007353738 ps
CPU time 827.9 seconds
Started Jul 26 05:03:14 PM PDT 24
Finished Jul 26 05:17:02 PM PDT 24
Peak memory 272764 kb
Host smart-db9e71d6-4630-4aba-be74-8898a439fa57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288909746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1288909746
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3330852158
Short name T435
Test name
Test status
Simulation time 34458068595 ps
CPU time 1128.99 seconds
Started Jul 26 05:03:15 PM PDT 24
Finished Jul 26 05:22:04 PM PDT 24
Peak memory 273408 kb
Host smart-3e57b9c7-91fc-4f61-a63b-4425b2d253c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330852158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3330852158
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1077196803
Short name T537
Test name
Test status
Simulation time 62805469804 ps
CPU time 359.59 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:09:24 PM PDT 24
Peak memory 248556 kb
Host smart-481706c0-d3ea-4ab5-9efa-43cbe387e318
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077196803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1077196803
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.4216428964
Short name T47
Test name
Test status
Simulation time 2666383101 ps
CPU time 48.37 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:03:54 PM PDT 24
Peak memory 257292 kb
Host smart-421c0c69-cdea-46a0-9562-eda4d2fbba11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42164
28964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.4216428964
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.297327110
Short name T550
Test name
Test status
Simulation time 1864988372 ps
CPU time 40.22 seconds
Started Jul 26 05:03:16 PM PDT 24
Finished Jul 26 05:03:56 PM PDT 24
Peak memory 249720 kb
Host smart-d986098f-2b35-4ed5-9e13-2b1268de4a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29732
7110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.297327110
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.4118158936
Short name T260
Test name
Test status
Simulation time 137918398 ps
CPU time 14.12 seconds
Started Jul 26 05:03:03 PM PDT 24
Finished Jul 26 05:03:17 PM PDT 24
Peak memory 255864 kb
Host smart-174a2e45-bf81-4879-b23a-5e74d923dcd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41181
58936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4118158936
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2159442153
Short name T649
Test name
Test status
Simulation time 505179793 ps
CPU time 10.45 seconds
Started Jul 26 05:03:20 PM PDT 24
Finished Jul 26 05:03:30 PM PDT 24
Peak memory 256900 kb
Host smart-500c8940-a2d2-4bc9-a24c-ec90b5b64a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21594
42153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2159442153
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1277999398
Short name T716
Test name
Test status
Simulation time 136123260965 ps
CPU time 3867.35 seconds
Started Jul 26 05:03:20 PM PDT 24
Finished Jul 26 06:07:48 PM PDT 24
Peak memory 303576 kb
Host smart-645c8d0c-aa74-4433-b840-b6457c9329df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277999398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1277999398
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3162007628
Short name T226
Test name
Test status
Simulation time 23952383 ps
CPU time 2.64 seconds
Started Jul 26 05:03:11 PM PDT 24
Finished Jul 26 05:03:14 PM PDT 24
Peak memory 249064 kb
Host smart-28b5d623-ed9c-4dd2-83cc-708b82cb7f6b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3162007628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3162007628
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2245388805
Short name T245
Test name
Test status
Simulation time 49257058265 ps
CPU time 1670.05 seconds
Started Jul 26 05:03:17 PM PDT 24
Finished Jul 26 05:31:07 PM PDT 24
Peak memory 273120 kb
Host smart-e8e1ffa9-220c-4cec-9e90-5a29c62c9215
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245388805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2245388805
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.248988573
Short name T480
Test name
Test status
Simulation time 120749582 ps
CPU time 6.88 seconds
Started Jul 26 05:03:18 PM PDT 24
Finished Jul 26 05:03:25 PM PDT 24
Peak memory 248820 kb
Host smart-c02dadcc-0def-4253-8712-62c8bdd0322d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=248988573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.248988573
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.709204009
Short name T657
Test name
Test status
Simulation time 763998667 ps
CPU time 65.69 seconds
Started Jul 26 05:03:34 PM PDT 24
Finished Jul 26 05:04:40 PM PDT 24
Peak memory 256468 kb
Host smart-5d5a571b-0daa-47da-8cd0-bfb4618551a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70920
4009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.709204009
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1024859054
Short name T382
Test name
Test status
Simulation time 69226649 ps
CPU time 5.06 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:03:28 PM PDT 24
Peak memory 240080 kb
Host smart-2844c311-6c1f-446d-b159-9c7ed84b4b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10248
59054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1024859054
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1097060083
Short name T317
Test name
Test status
Simulation time 42320799840 ps
CPU time 2514.77 seconds
Started Jul 26 05:03:29 PM PDT 24
Finished Jul 26 05:45:25 PM PDT 24
Peak memory 289688 kb
Host smart-0f450632-e703-44f1-9997-ebd2cbc05241
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097060083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1097060083
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.783987355
Short name T508
Test name
Test status
Simulation time 6190835441 ps
CPU time 815.78 seconds
Started Jul 26 05:03:36 PM PDT 24
Finished Jul 26 05:17:12 PM PDT 24
Peak memory 273400 kb
Host smart-d87e6795-6047-4bf8-94a8-ba54514f05f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783987355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.783987355
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1600016861
Short name T324
Test name
Test status
Simulation time 22565221325 ps
CPU time 490.34 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:11:38 PM PDT 24
Peak memory 248756 kb
Host smart-5e6f9492-a3c2-4ca0-9c87-7679590c9801
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600016861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1600016861
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.726628652
Short name T411
Test name
Test status
Simulation time 618948458 ps
CPU time 27.25 seconds
Started Jul 26 05:03:25 PM PDT 24
Finished Jul 26 05:03:53 PM PDT 24
Peak memory 256228 kb
Host smart-04d252d9-3880-41f4-9ba9-951f0d72e5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72662
8652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.726628652
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2233332181
Short name T624
Test name
Test status
Simulation time 1030422156 ps
CPU time 35.69 seconds
Started Jul 26 05:03:15 PM PDT 24
Finished Jul 26 05:03:53 PM PDT 24
Peak memory 256148 kb
Host smart-deb14266-f845-49ae-9dc3-2b38e979664c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22333
32181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2233332181
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3679445952
Short name T64
Test name
Test status
Simulation time 1693920342 ps
CPU time 25.73 seconds
Started Jul 26 05:03:06 PM PDT 24
Finished Jul 26 05:03:32 PM PDT 24
Peak memory 248508 kb
Host smart-ba8b6106-9255-421f-9751-a8bd251ffe66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36794
45952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3679445952
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.566887361
Short name T660
Test name
Test status
Simulation time 286424699 ps
CPU time 12.82 seconds
Started Jul 26 05:03:17 PM PDT 24
Finished Jul 26 05:03:30 PM PDT 24
Peak memory 255272 kb
Host smart-4a08bb57-ae46-4630-8c64-6807fc595d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56688
7361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.566887361
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4131637850
Short name T230
Test name
Test status
Simulation time 46560613 ps
CPU time 4.27 seconds
Started Jul 26 05:03:10 PM PDT 24
Finished Jul 26 05:03:15 PM PDT 24
Peak memory 249136 kb
Host smart-e823a65d-5c33-4b60-a307-c993f8e31f03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4131637850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4131637850
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2770466644
Short name T425
Test name
Test status
Simulation time 29066973908 ps
CPU time 1577.56 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:29:42 PM PDT 24
Peak memory 288252 kb
Host smart-cdd4a760-2e97-404d-8f6a-1cc7b1ff2bd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770466644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2770466644
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3609176796
Short name T708
Test name
Test status
Simulation time 3565664022 ps
CPU time 35.87 seconds
Started Jul 26 05:03:18 PM PDT 24
Finished Jul 26 05:03:54 PM PDT 24
Peak memory 248760 kb
Host smart-9c38edcf-3623-47e9-8c0e-03cf924e2092
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3609176796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3609176796
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2616719970
Short name T495
Test name
Test status
Simulation time 1187476350 ps
CPU time 110.41 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:05:18 PM PDT 24
Peak memory 256760 kb
Host smart-02982e95-cba5-445b-9462-f2349e1b1a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26167
19970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2616719970
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3074361328
Short name T461
Test name
Test status
Simulation time 374955236 ps
CPU time 23.12 seconds
Started Jul 26 05:03:13 PM PDT 24
Finished Jul 26 05:03:37 PM PDT 24
Peak memory 248356 kb
Host smart-d0b4b8e8-01c2-4c76-ba88-09904d7a51e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30743
61328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3074361328
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3816090294
Short name T484
Test name
Test status
Simulation time 62796248297 ps
CPU time 1533.35 seconds
Started Jul 26 05:03:19 PM PDT 24
Finished Jul 26 05:28:52 PM PDT 24
Peak memory 288132 kb
Host smart-b159434a-b3fe-43c3-9668-7f3dca8b723f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816090294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3816090294
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.604168842
Short name T711
Test name
Test status
Simulation time 14290852921 ps
CPU time 1067.19 seconds
Started Jul 26 05:03:21 PM PDT 24
Finished Jul 26 05:21:09 PM PDT 24
Peak memory 271332 kb
Host smart-4b44eb8b-741c-4b00-b916-5749e6efb79c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604168842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.604168842
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.186530703
Short name T705
Test name
Test status
Simulation time 22816794912 ps
CPU time 492.82 seconds
Started Jul 26 05:03:30 PM PDT 24
Finished Jul 26 05:11:43 PM PDT 24
Peak memory 248900 kb
Host smart-80e72dcb-2bb8-4dce-a43f-5ab1145e9356
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186530703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.186530703
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.588212663
Short name T533
Test name
Test status
Simulation time 233745531 ps
CPU time 17.03 seconds
Started Jul 26 05:03:11 PM PDT 24
Finished Jul 26 05:03:28 PM PDT 24
Peak memory 248876 kb
Host smart-87dbf4c5-d417-4ffa-a02d-d7abd3fc1940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58821
2663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.588212663
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.451151638
Short name T85
Test name
Test status
Simulation time 3259368053 ps
CPU time 44.61 seconds
Started Jul 26 05:03:07 PM PDT 24
Finished Jul 26 05:03:52 PM PDT 24
Peak memory 248792 kb
Host smart-69d4294f-3e2f-4dfa-8c09-ead2b72ceed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45115
1638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.451151638
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1233188628
Short name T204
Test name
Test status
Simulation time 1168720600 ps
CPU time 13.46 seconds
Started Jul 26 05:03:08 PM PDT 24
Finished Jul 26 05:03:22 PM PDT 24
Peak memory 247984 kb
Host smart-7c0e786b-f8b2-46dc-8433-5283951f4ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12331
88628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1233188628
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.4267746945
Short name T678
Test name
Test status
Simulation time 409088646 ps
CPU time 19.06 seconds
Started Jul 26 05:03:09 PM PDT 24
Finished Jul 26 05:03:28 PM PDT 24
Peak memory 256892 kb
Host smart-536addbd-8005-41d1-be89-ab1f1359ca92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42677
46945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4267746945
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2975479462
Short name T640
Test name
Test status
Simulation time 70735181174 ps
CPU time 2192.13 seconds
Started Jul 26 05:03:14 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 288972 kb
Host smart-6c8902c4-743c-4333-acee-8898796acecb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975479462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2975479462
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1366022735
Short name T109
Test name
Test status
Simulation time 23711233 ps
CPU time 2.36 seconds
Started Jul 26 05:03:14 PM PDT 24
Finished Jul 26 05:03:19 PM PDT 24
Peak memory 249156 kb
Host smart-3361c83c-a3f5-4d68-8ced-66d8e126ca76
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1366022735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1366022735
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3499175296
Short name T581
Test name
Test status
Simulation time 21719221242 ps
CPU time 1327.43 seconds
Started Jul 26 05:03:08 PM PDT 24
Finished Jul 26 05:25:16 PM PDT 24
Peak memory 267320 kb
Host smart-16bf3810-43cf-4dfe-b9bd-6154697b465c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499175296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3499175296
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3952933287
Short name T434
Test name
Test status
Simulation time 153085473 ps
CPU time 9.01 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:03:32 PM PDT 24
Peak memory 248676 kb
Host smart-3670373d-406f-4f12-b30c-5d9e2f04c041
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3952933287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3952933287
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4176901801
Short name T693
Test name
Test status
Simulation time 15690241230 ps
CPU time 252.32 seconds
Started Jul 26 05:03:18 PM PDT 24
Finished Jul 26 05:07:30 PM PDT 24
Peak memory 256608 kb
Host smart-b5402803-ef30-4cd1-82cd-f1f07f16ab3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41769
01801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4176901801
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3807424841
Short name T451
Test name
Test status
Simulation time 504763060 ps
CPU time 11.39 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:03:39 PM PDT 24
Peak memory 248564 kb
Host smart-77dfe9d9-c38a-4ea3-9f94-4aa49fcabb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38074
24841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3807424841
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.590016278
Short name T335
Test name
Test status
Simulation time 39208147694 ps
CPU time 1110.63 seconds
Started Jul 26 05:03:31 PM PDT 24
Finished Jul 26 05:22:02 PM PDT 24
Peak memory 272856 kb
Host smart-ec70ad24-daaf-4ef4-8749-7bc760a03871
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590016278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.590016278
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1502976497
Short name T427
Test name
Test status
Simulation time 105847184337 ps
CPU time 1565.8 seconds
Started Jul 26 05:03:18 PM PDT 24
Finished Jul 26 05:29:24 PM PDT 24
Peak memory 273296 kb
Host smart-95eaf78b-a7a3-49df-82e0-74083301e37b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502976497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1502976497
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3582697768
Short name T687
Test name
Test status
Simulation time 10781300939 ps
CPU time 64.64 seconds
Started Jul 26 05:03:37 PM PDT 24
Finished Jul 26 05:04:41 PM PDT 24
Peak memory 254804 kb
Host smart-9c47db6a-29ed-4fe9-84cb-b4ead04519f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582697768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3582697768
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.432460028
Short name T397
Test name
Test status
Simulation time 925892427 ps
CPU time 56.02 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:04:23 PM PDT 24
Peak memory 256312 kb
Host smart-e3caf38c-ae2d-451b-8804-0f780278a3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43246
0028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.432460028
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3519148722
Short name T241
Test name
Test status
Simulation time 1128498387 ps
CPU time 18.24 seconds
Started Jul 26 05:03:08 PM PDT 24
Finished Jul 26 05:03:26 PM PDT 24
Peak memory 256572 kb
Host smart-c00c8c6b-eb54-4266-a181-285bf2bd010c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35191
48722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3519148722
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1425394314
Short name T466
Test name
Test status
Simulation time 1151884476 ps
CPU time 35.94 seconds
Started Jul 26 05:03:10 PM PDT 24
Finished Jul 26 05:03:46 PM PDT 24
Peak memory 249460 kb
Host smart-a4e58ed4-10ac-49f4-8c39-2bb896d064f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14253
94314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1425394314
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1450922964
Short name T483
Test name
Test status
Simulation time 170019101 ps
CPU time 13.16 seconds
Started Jul 26 05:03:14 PM PDT 24
Finished Jul 26 05:03:27 PM PDT 24
Peak memory 254824 kb
Host smart-0c9e2745-9a3a-4679-bd9a-02f942a76708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14509
22964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1450922964
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3047235788
Short name T24
Test name
Test status
Simulation time 10575987921 ps
CPU time 1033.59 seconds
Started Jul 26 05:03:16 PM PDT 24
Finished Jul 26 05:20:30 PM PDT 24
Peak memory 289396 kb
Host smart-e1d60ae5-5111-4904-bf2c-efc56e3a538d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047235788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3047235788
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2639748098
Short name T220
Test name
Test status
Simulation time 97423224 ps
CPU time 2.86 seconds
Started Jul 26 05:03:28 PM PDT 24
Finished Jul 26 05:03:31 PM PDT 24
Peak memory 249004 kb
Host smart-a3ee490f-afe3-4572-b92b-73ed9325b9a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2639748098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2639748098
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3529001794
Short name T380
Test name
Test status
Simulation time 54990620335 ps
CPU time 1341.49 seconds
Started Jul 26 05:03:14 PM PDT 24
Finished Jul 26 05:25:35 PM PDT 24
Peak memory 288632 kb
Host smart-9f32b0e5-b7cb-4965-9155-c01e32a78f3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529001794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3529001794
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2274691288
Short name T111
Test name
Test status
Simulation time 2675371842 ps
CPU time 53.6 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:04:16 PM PDT 24
Peak memory 248720 kb
Host smart-088d5e98-7705-46fe-aebc-f75822c19d64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2274691288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2274691288
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3490313624
Short name T489
Test name
Test status
Simulation time 47489570014 ps
CPU time 280.07 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:08:07 PM PDT 24
Peak memory 257028 kb
Host smart-c559a152-b71d-43c2-bba4-348b242de969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34903
13624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3490313624
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.135768148
Short name T74
Test name
Test status
Simulation time 865743111 ps
CPU time 24.43 seconds
Started Jul 26 05:03:18 PM PDT 24
Finished Jul 26 05:03:42 PM PDT 24
Peak memory 248836 kb
Host smart-0b13d87a-fbfb-4935-87dd-46f8234f94d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13576
8148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.135768148
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.758631538
Short name T320
Test name
Test status
Simulation time 83977530589 ps
CPU time 1350.12 seconds
Started Jul 26 05:03:23 PM PDT 24
Finished Jul 26 05:25:54 PM PDT 24
Peak memory 272624 kb
Host smart-fd1bb3b7-a94c-4fad-8946-1b5cd2911388
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758631538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.758631538
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1748222793
Short name T548
Test name
Test status
Simulation time 10083060652 ps
CPU time 1006.58 seconds
Started Jul 26 05:03:24 PM PDT 24
Finished Jul 26 05:20:11 PM PDT 24
Peak memory 283520 kb
Host smart-30c3d0c0-6ed3-4966-b327-f72909c442f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748222793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1748222793
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3486992300
Short name T689
Test name
Test status
Simulation time 8515400276 ps
CPU time 368.67 seconds
Started Jul 26 05:03:13 PM PDT 24
Finished Jul 26 05:09:22 PM PDT 24
Peak memory 248704 kb
Host smart-5aef3045-5c07-4602-9048-c7ba306c7aa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486992300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3486992300
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.539228973
Short name T603
Test name
Test status
Simulation time 843351401 ps
CPU time 49.32 seconds
Started Jul 26 05:03:18 PM PDT 24
Finished Jul 26 05:04:07 PM PDT 24
Peak memory 256072 kb
Host smart-6c17dc1c-0844-42b3-9262-db8f3b9ba2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53922
8973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.539228973
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1660237527
Short name T133
Test name
Test status
Simulation time 1997034120 ps
CPU time 21.51 seconds
Started Jul 26 05:03:14 PM PDT 24
Finished Jul 26 05:03:36 PM PDT 24
Peak memory 248292 kb
Host smart-281a2c27-9074-4426-acf5-76c409087009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16602
37527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1660237527
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.4249493828
Short name T112
Test name
Test status
Simulation time 248178048 ps
CPU time 17.15 seconds
Started Jul 26 05:03:27 PM PDT 24
Finished Jul 26 05:03:44 PM PDT 24
Peak memory 248764 kb
Host smart-b06f302c-e13d-47cf-b9c5-0c997705cae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42494
93828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.4249493828
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3703839545
Short name T532
Test name
Test status
Simulation time 3293776917 ps
CPU time 50.53 seconds
Started Jul 26 05:03:09 PM PDT 24
Finished Jul 26 05:04:00 PM PDT 24
Peak memory 256748 kb
Host smart-c87fa6bd-f262-4f94-b01b-8f0304d8cf1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37038
39545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3703839545
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3896409167
Short name T301
Test name
Test status
Simulation time 29505771688 ps
CPU time 1005.86 seconds
Started Jul 26 05:03:20 PM PDT 24
Finished Jul 26 05:20:06 PM PDT 24
Peak memory 273480 kb
Host smart-38532af7-df73-48c4-a552-ea6377e58f42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896409167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3896409167
Directory /workspace/9.alert_handler_stress_all/latest
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