Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	92858	1			T11	56		T4	24		T5	92
class_i[0x1]	62256	1			T7	2282		T5	11		T6	2332
class_i[0x2]	63999	1			T11	10		T4	3755		T5	605
class_i[0x3]	40489	1			T11	203		T4	41		T18	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	64489	1			T7	540		T11	167		T4	966
alert[0x1]	62994	1			T7	548		T4	963		T5	138
alert[0x2]	62906	1			T7	587		T11	67		T4	985
alert[0x3]	69213	1			T7	607		T11	35		T4	906

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

259365

1

T7

2282

T11

269

T4

3820

esc_ping_fail

237

1

T13

3

T15

2

T16

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	64423	1			T7	540		T11	167		T4	966
esc_integrity_fail	alert[0x1]	62936	1			T7	548		T4	963		T5	138
esc_integrity_fail	alert[0x2]	62847	1			T7	587		T11	67		T4	985
esc_integrity_fail	alert[0x3]	69159	1			T7	607		T11	35		T4	906
esc_ping_fail	alert[0x0]	66	1			T15	1		T16	2		T306	2
esc_ping_fail	alert[0x1]	58	1			T13	1		T16	1		T306	1
esc_ping_fail	alert[0x2]	59	1			T13	2		T306	2		T312	1
esc_ping_fail	alert[0x3]	54	1			T15	1		T306	4		T312	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	92792	1			T11	56		T4	24		T5	92
esc_integrity_fail	class_i[0x1]	62200	1			T7	2282		T5	11		T6	2332
esc_integrity_fail	class_i[0x2]	63937	1			T11	10		T4	3755		T5	605
esc_integrity_fail	class_i[0x3]	40436	1			T11	203		T4	41		T18	1
esc_ping_fail	class_i[0x0]	66	1			T306	1		T307	4		T61	4
esc_ping_fail	class_i[0x1]	56	1			T313	4		T312	1		T228	1
esc_ping_fail	class_i[0x2]	62	1			T15	2		T312	3		T228	5
esc_ping_fail	class_i[0x3]	53	1			T13	3		T16	3		T306	8