Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T5	2		T20	3		T68	1
class_index[0x1]	59	1			T11	1		T4	1		T5	1
class_index[0x2]	70	1			T4	2		T5	1		T20	1
class_index[0x3]	54	1			T5	1		T20	2		T42	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	92	1			T4	1		T6	1		T20	2
intr_timeout_cnt[1]	69	1			T5	1		T40	1		T20	2
intr_timeout_cnt[2]	25	1			T4	1		T5	1		T68	1
intr_timeout_cnt[3]	11	1			T58	1		T63	1		T260	1
intr_timeout_cnt[4]	13	1			T11	1		T4	1		T5	1
intr_timeout_cnt[5]	9	1			T5	2		T261	1		T117	1
intr_timeout_cnt[6]	6	1			T20	2		T243	1		T262	1
intr_timeout_cnt[7]	12	1			T20	2		T80	1		T36	1
intr_timeout_cnt[8]	6	1			T63	1		T119	1		T95	1
intr_timeout_cnt[9]	2	1			T68	1		T263	1		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1] , class_index[0x2] , class_index[0x3]]	[intr_timeout_cnt[9]]	--	--	3

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	18	1			T20	1		T69	1		T76	1
class_index[0x0]	intr_timeout_cnt[1]	21	1			T79	1		T81	1		T264	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T80	1		T265	1		T266	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T63	1		T260	1		T266	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T69	1		T243	1		T246	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T5	2		T235	1		T55	1
class_index[0x0]	intr_timeout_cnt[7]	3	1			T20	2		T36	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T68	1		T263	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	22	1			T6	1		T73	1		T75	1
class_index[0x1]	intr_timeout_cnt[1]	17	1			T40	1		T79	1		T47	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T4	1		T5	1		T267	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T95	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	5	1			T11	1		T77	1		T268	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T261	1		T117	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T20	2		T263	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T80	1		T95	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T63	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	34	1			T4	1		T20	1		T69	1
class_index[0x2]	intr_timeout_cnt[1]	12	1			T44	1		T79	1		T82	1
class_index[0x2]	intr_timeout_cnt[2]	9	1			T68	1		T36	1		T111	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T58	1		T111	1		T56	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T4	1		T5	1		T92	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T120	1		T269	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T270	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T271	1		T272	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T95	1		T54	1		T272	1
class_index[0x3]	intr_timeout_cnt[0]	18	1			T120	1		T121	3		T234	1
class_index[0x3]	intr_timeout_cnt[1]	19	1			T5	1		T20	2		T42	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T47	2		T118	1		T273	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T274	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	1	1			T42	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T275	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T243	1		T262	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	5	1			T276	1		T277	1		T278	1
class_index[0x3]	intr_timeout_cnt[8]	2	1			T119	1		T101	1		-	-