Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	363516	1			T1	1427		T2	1727		T3	31
all_values[1]	363516	1			T1	1427		T2	1727		T3	31
all_values[2]	363516	1			T1	1427		T2	1727		T3	31
all_values[3]	363516	1			T1	1427		T2	1727		T3	31

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

724355

1

T1

2824

T2

3494

T3

55

auto[1]

729709

1

T1

2884

T2

3414

T3

69

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

864460

1

T1

3866

T2

3535

T3

66

auto[1]

589604

1

T1

1842

T2

3373

T3

58

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104279	1			T1	464		T2	473		T3	7
all_values[0]	auto[0]	auto[1]	77366	1			T1	262		T2	411		T3	7
all_values[0]	auto[1]	auto[0]	104984	1			T1	440		T2	448		T3	9
all_values[0]	auto[1]	auto[1]	76887	1			T1	261		T2	395		T3	8
all_values[1]	auto[0]	auto[0]	108695	1			T1	380		T2	442		T3	9
all_values[1]	auto[0]	auto[1]	71799	1			T1	349		T2	435		T3	9
all_values[1]	auto[1]	auto[0]	110897	1			T1	357		T2	427		T3	7
all_values[1]	auto[1]	auto[1]	72125	1			T1	341		T2	423		T3	6
all_values[2]	auto[0]	auto[0]	108176	1			T1	393		T2	435		T3	8
all_values[2]	auto[0]	auto[1]	72591	1			T1	297		T2	434		T3	4
all_values[2]	auto[1]	auto[0]	109868	1			T1	409		T2	429		T3	10
all_values[2]	auto[1]	auto[1]	72881	1			T1	328		T2	429		T3	9
all_values[3]	auto[0]	auto[0]	108167	1			T1	676		T2	438		T3	6
all_values[3]	auto[0]	auto[1]	73282	1			T1	3		T2	426		T3	5
all_values[3]	auto[1]	auto[0]	109394	1			T1	747		T2	443		T3	10
all_values[3]	auto[1]	auto[1]	72673	1			T1	1		T2	420		T3	10