Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	363516	1			T1	1427		T2	1727		T3	31
all_pins[1]	363516	1			T1	1427		T2	1727		T3	31
all_pins[2]	363516	1			T1	1427		T2	1727		T3	31
all_pins[3]	363516	1			T1	1427		T2	1727		T3	31

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1159498	1			T1	4777		T2	5241		T3	91
values[0x1]	294566	1			T1	931		T2	1667		T3	33
transitions[0x0=>0x1]	196200	1			T1	640		T2	1064		T3	21
transitions[0x1=>0x0]	196424	1			T1	640		T2	1064		T3	22

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	286629	1			T1	1166		T2	1332		T3	23
all_pins[0]	values[0x1]	76887	1			T1	261		T2	395		T3	8
all_pins[0]	transitions[0x0=>0x1]	76248	1			T1	261		T2	395		T3	7
all_pins[0]	transitions[0x1=>0x0]	72258	1			T1	1		T2	420		T3	10
all_pins[1]	values[0x0]	291391	1			T1	1086		T2	1304		T3	25
all_pins[1]	values[0x1]	72125	1			T1	341		T2	423		T3	6
all_pins[1]	transitions[0x0=>0x1]	39420	1			T1	209		T2	234		T3	3
all_pins[1]	transitions[0x1=>0x0]	44182	1			T1	129		T2	206		T3	5
all_pins[2]	values[0x0]	290635	1			T1	1099		T2	1298		T3	22
all_pins[2]	values[0x1]	72881	1			T1	328		T2	429		T3	9
all_pins[2]	transitions[0x0=>0x1]	40347	1			T1	170		T2	220		T3	6
all_pins[2]	transitions[0x1=>0x0]	39591	1			T1	183		T2	214		T3	3
all_pins[3]	values[0x0]	290843	1			T1	1426		T2	1307		T3	21
all_pins[3]	values[0x1]	72673	1			T1	1		T2	420		T3	10
all_pins[3]	transitions[0x0=>0x1]	40185	1			T2	215		T3	5		T7	107
all_pins[3]	transitions[0x1=>0x0]	40393	1			T1	327		T2	224		T3	4