Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 24 0 24 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 4 0 4 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 24 0 24 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 278 1 T161 7 T162 4 T163 4
all_values[1] 278 1 T161 7 T162 4 T163 4
all_values[2] 278 1 T161 7 T162 4 T163 4
all_values[3] 278 1 T161 7 T162 4 T163 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 606 1 T161 17 T162 10 T163 9
auto[1] 506 1 T161 11 T162 6 T163 7



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 443 1 T161 12 T162 7 T163 3
auto[1] 669 1 T161 16 T162 9 T163 13



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 671 1 T161 18 T162 10 T163 9
auto[1] 441 1 T161 10 T162 6 T163 7



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 24 0 24 100.00
Automatically Generated Cross Bins 24 0 24 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 68 1 T162 1 T351 2 T352 1
all_values[0] auto[0] auto[0] auto[1] 27 1 T161 1 T163 1 T353 3
all_values[0] auto[0] auto[1] auto[0] 62 1 T161 1 T162 1 T255 2
all_values[0] auto[0] auto[1] auto[1] 23 1 T161 1 T162 1 T163 1
all_values[0] auto[1] auto[0] auto[1] 50 1 T161 2 T163 2 T353 2
all_values[0] auto[1] auto[1] auto[1] 48 1 T161 2 T162 1 T255 1
all_values[1] auto[0] auto[0] auto[0] 52 1 T161 1 T255 1 T353 3
all_values[1] auto[0] auto[0] auto[1] 33 1 T161 1 T162 1 T163 1
all_values[1] auto[0] auto[1] auto[0] 43 1 T162 2 T163 1 T255 2
all_values[1] auto[0] auto[1] auto[1] 28 1 T161 2 T351 1 T352 1
all_values[1] auto[1] auto[0] auto[1] 69 1 T161 3 T162 1 T163 2
all_values[1] auto[1] auto[1] auto[1] 53 1 T255 1 T354 1 T355 4
all_values[2] auto[0] auto[0] auto[0] 63 1 T161 3 T162 2 T163 1
all_values[2] auto[0] auto[0] auto[1] 21 1 T353 2 T351 1 T356 1
all_values[2] auto[0] auto[1] auto[0] 57 1 T161 3 T163 1 T255 2
all_values[2] auto[0] auto[1] auto[1] 27 1 T163 1 T353 1 T355 1
all_values[2] auto[1] auto[0] auto[1] 65 1 T161 1 T162 1 T353 1
all_values[2] auto[1] auto[1] auto[1] 45 1 T162 1 T163 1 T255 2
all_values[3] auto[0] auto[0] auto[0] 58 1 T161 4 T162 1 T255 4
all_values[3] auto[0] auto[0] auto[1] 36 1 T162 1 T163 1 T351 1
all_values[3] auto[0] auto[1] auto[0] 40 1 T353 1 T354 1 T355 1
all_values[3] auto[0] auto[1] auto[1] 33 1 T161 1 T163 1 T353 1
all_values[3] auto[1] auto[0] auto[1] 64 1 T161 1 T162 2 T163 1
all_values[3] auto[1] auto[1] auto[1] 47 1 T161 1 T163 1 T353 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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