Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	82605	1			T2	976		T7	204		T12	1693
accum_cnt_1000	227017	1			T1	1847		T2	1391		T7	659
accum_cnt_100	25117	1			T1	153		T2	68		T7	36
accum_cnt_50	65189	1			T1	102		T2	72		T3	34
accum_cnt_10	193801	1			T1	1097		T2	2602		T3	72
accum_cnt_0	430453	1			T1	1077		T2	14		T3	14

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267713	1			T1	1069		T2	1295		T3	30
class_index[0x1]	267713	1			T1	1069		T2	1295		T3	30
class_index[0x2]	267713	1			T1	1069		T2	1295		T3	30
class_index[0x3]	267713	1			T1	1069		T2	1295		T3	30

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23182	1			T7	51		T65	648		T42	330
class_index[0x0]	accum_cnt_1000	57462	1			T1	913		T7	556		T4	40
class_index[0x0]	accum_cnt_100	6626	1			T1	87		T7	34		T11	10
class_index[0x0]	accum_cnt_50	19099	1			T1	50		T3	4		T7	25
class_index[0x0]	accum_cnt_10	56371	1			T1	15		T2	1293		T3	18
class_index[0x0]	accum_cnt_0	90159	1			T1	4		T2	2		T3	8
class_index[0x1]	accum_cnt_2000	19449	1			T2	610		T12	471		T17	166
class_index[0x1]	accum_cnt_1000	59295	1			T2	555		T12	403		T5	7
class_index[0x1]	accum_cnt_100	6245	1			T2	30		T11	6		T12	20
class_index[0x1]	accum_cnt_50	15161	1			T2	29		T3	14		T11	3
class_index[0x1]	accum_cnt_10	43525	1			T1	3		T2	11		T3	14
class_index[0x1]	accum_cnt_0	112729	1			T1	1066		T2	3		T3	2
class_index[0x2]	accum_cnt_2000	17303	1			T7	153		T12	693		T17	147
class_index[0x2]	accum_cnt_1000	54438	1			T1	934		T7	103		T4	232
class_index[0x2]	accum_cnt_100	6205	1			T1	66		T7	2		T11	3
class_index[0x2]	accum_cnt_50	13297	1			T1	52		T7	9		T11	8
class_index[0x2]	accum_cnt_10	40396	1			T1	14		T2	1289		T3	26
class_index[0x2]	accum_cnt_0	124941	1			T1	3		T2	6		T3	4
class_index[0x3]	accum_cnt_2000	22671	1			T2	366		T12	529		T5	11
class_index[0x3]	accum_cnt_1000	55822	1			T2	836		T11	9		T4	18
class_index[0x3]	accum_cnt_100	6041	1			T2	38		T4	138		T12	30
class_index[0x3]	accum_cnt_50	17632	1			T2	43		T3	16		T4	109
class_index[0x3]	accum_cnt_10	53509	1			T1	1065		T2	9		T3	14
class_index[0x3]	accum_cnt_0	102624	1			T1	4		T2	3		T7	674