Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3117	1			T5	6		T19	5		T20	276
alert[0x1]	6946	1			T7	21		T4	18		T5	1
alert[0x2]	5026	1			T11	5		T4	5		T19	246
alert[0x3]	15182	1			T5	1		T19	265		T13	1
alert[0x4]	6665	1			T7	558		T4	4		T5	2
alert[0x5]	7458	1			T4	1		T18	5		T19	142
alert[0x6]	12249	1			T1	1		T7	204		T18	1
alert[0x7]	6102	1			T13	1		T20	24		T66	21
alert[0x8]	2879	1			T1	3		T4	6		T19	33
alert[0x9]	10396	1			T4	14		T66	33		T258	1
alert[0xa]	5787	1			T7	4		T19	390		T20	25
alert[0xb]	5053	1			T4	2		T19	29		T6	2
alert[0xc]	5500	1			T4	140		T19	11		T6	5
alert[0xd]	2485	1			T11	1		T5	3		T19	81
alert[0xe]	6143	1			T7	12		T19	99		T20	159
alert[0xf]	8819	1			T4	3		T19	588		T40	1
alert[0x10]	11862	1			T65	107		T69	29		T66	563
alert[0x11]	6348	1			T7	402		T40	10		T69	2080
alert[0x12]	5208	1			T4	20		T5	3		T19	15
alert[0x13]	3849	1			T7	4		T19	1134		T40	1
alert[0x14]	6507	1			T7	34		T11	105		T5	10
alert[0x15]	2489	1			T6	1		T40	1		T20	57
alert[0x16]	9615	1			T7	54		T5	33		T20	19
alert[0x17]	6963	1			T7	17		T65	223		T66	54
alert[0x18]	5111	1			T7	10		T5	6		T18	3
alert[0x19]	9315	1			T7	221		T6	37		T20	620
alert[0x1a]	11257	1			T7	56		T6	821		T65	1
alert[0x1b]	7900	1			T7	9		T4	37		T19	39
alert[0x1c]	6250	1			T4	18		T19	9		T6	16
alert[0x1d]	13197	1			T7	16		T19	87		T16	1
alert[0x1e]	8271	1			T4	4		T18	17		T19	112
alert[0x1f]	7593	1			T18	9		T66	281		T258	39
alert[0x20]	2225	1			T5	3		T40	1		T20	37
alert[0x21]	10497	1			T7	106		T4	7		T19	3
alert[0x22]	11816	1			T4	2		T17	2		T19	6
alert[0x23]	9589	1			T7	8		T4	25		T19	99
alert[0x24]	9360	1			T4	133		T19	196		T65	307
alert[0x25]	6302	1			T7	93		T4	80		T5	7
alert[0x26]	4814	1			T19	729		T20	2		T66	47
alert[0x27]	2494	1			T19	670		T40	1		T13	1
alert[0x28]	7784	1			T11	6		T18	9		T66	147
alert[0x29]	3094	1			T11	1		T5	1		T40	74
alert[0x2a]	11007	1			T40	23		T20	31		T65	3404
alert[0x2b]	14256	1			T7	1845		T5	61		T19	14
alert[0x2c]	13646	1			T7	11		T11	4		T4	73
alert[0x2d]	2712	1			T1	1		T19	13		T6	1
alert[0x2e]	14049	1			T4	120		T17	9		T19	11
alert[0x2f]	12183	1			T1	3		T7	1534		T11	4
alert[0x30]	5894	1			T7	7		T13	1		T16	1
alert[0x31]	5362	1			T4	14		T5	5		T19	13
alert[0x32]	6481	1			T7	21		T19	15		T6	12
alert[0x33]	12210	1			T65	87		T70	4		T258	144
alert[0x34]	14854	1			T7	66		T6	63		T13	1
alert[0x35]	5533	1			T4	19		T18	13		T19	697
alert[0x36]	3964	1			T7	369		T4	4		T15	1
alert[0x37]	10592	1			T7	13		T5	1		T19	1898
alert[0x38]	4444	1			T4	49		T20	124		T44	86
alert[0x39]	9921	1			T7	23		T4	35		T17	62
alert[0x3a]	2405	1			T7	11		T4	6		T40	4
alert[0x3b]	16008	1			T4	2		T40	3		T306	1
alert[0x3c]	6278	1			T7	4		T40	23		T65	3
alert[0x3d]	7187	1			T17	1		T18	2		T19	132
alert[0x3e]	5483	1			T5	4		T19	41		T20	914
alert[0x3f]	11817	1			T7	52		T4	63		T5	1
alert[0x40]	11277	1			T7	288		T18	1		T6	119

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	125172	1			T7	45		T11	1		T4	823
class_i[0x1]	144519	1			T11	50		T17	3		T18	18
class_i[0x2]	141826	1			T1	8		T7	6028		T11	75
class_i[0x3]	95563	1			T4	9		T5	75		T17	71

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

506387

1

T7

6073

T11

126

T4

1006

alert_ping_fail

693

1

T1

8

T13

12

T14

3

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3109	1			T5	6		T19	5		T20	276
alert_integrity_fail	alert[0x1]	6939	1			T7	21		T4	18		T5	1
alert_integrity_fail	alert[0x2]	5020	1			T11	5		T4	5		T19	246
alert_integrity_fail	alert[0x3]	15169	1			T5	1		T19	265		T65	143
alert_integrity_fail	alert[0x4]	6656	1			T7	558		T4	4		T5	2
alert_integrity_fail	alert[0x5]	7444	1			T4	1		T18	5		T19	142
alert_integrity_fail	alert[0x6]	12234	1			T7	204		T18	1		T6	1
alert_integrity_fail	alert[0x7]	6095	1			T20	24		T66	21		T44	221
alert_integrity_fail	alert[0x8]	2864	1			T4	6		T19	33		T40	1
alert_integrity_fail	alert[0x9]	10392	1			T4	14		T66	33		T258	1
alert_integrity_fail	alert[0xa]	5770	1			T7	4		T19	390		T20	25
alert_integrity_fail	alert[0xb]	5048	1			T4	2		T19	29		T6	2
alert_integrity_fail	alert[0xc]	5497	1			T4	140		T19	11		T6	5
alert_integrity_fail	alert[0xd]	2467	1			T11	1		T5	3		T19	81
alert_integrity_fail	alert[0xe]	6135	1			T7	12		T19	99		T20	159
alert_integrity_fail	alert[0xf]	8809	1			T4	3		T19	588		T40	1
alert_integrity_fail	alert[0x10]	11851	1			T65	107		T69	29		T66	563
alert_integrity_fail	alert[0x11]	6340	1			T7	402		T40	10		T69	2080
alert_integrity_fail	alert[0x12]	5200	1			T4	20		T5	3		T19	15
alert_integrity_fail	alert[0x13]	3837	1			T7	4		T19	1134		T40	1
alert_integrity_fail	alert[0x14]	6497	1			T7	34		T11	105		T5	10
alert_integrity_fail	alert[0x15]	2471	1			T6	1		T40	1		T20	57
alert_integrity_fail	alert[0x16]	9596	1			T7	54		T5	33		T20	19
alert_integrity_fail	alert[0x17]	6956	1			T7	17		T65	223		T66	54
alert_integrity_fail	alert[0x18]	5104	1			T7	10		T5	6		T18	3
alert_integrity_fail	alert[0x19]	9309	1			T7	221		T6	37		T20	620
alert_integrity_fail	alert[0x1a]	11250	1			T7	56		T6	821		T65	1
alert_integrity_fail	alert[0x1b]	7887	1			T7	9		T4	37		T19	39
alert_integrity_fail	alert[0x1c]	6228	1			T4	18		T19	9		T6	16
alert_integrity_fail	alert[0x1d]	13179	1			T7	16		T19	87		T258	33
alert_integrity_fail	alert[0x1e]	8263	1			T4	4		T18	17		T19	112
alert_integrity_fail	alert[0x1f]	7579	1			T18	9		T66	281		T258	39
alert_integrity_fail	alert[0x20]	2217	1			T5	3		T40	1		T20	37
alert_integrity_fail	alert[0x21]	10482	1			T7	106		T4	7		T19	3
alert_integrity_fail	alert[0x22]	11802	1			T4	2		T17	2		T19	6
alert_integrity_fail	alert[0x23]	9581	1			T7	8		T4	25		T19	99
alert_integrity_fail	alert[0x24]	9345	1			T4	133		T19	196		T65	307
alert_integrity_fail	alert[0x25]	6286	1			T7	93		T4	80		T5	7
alert_integrity_fail	alert[0x26]	4808	1			T19	729		T20	2		T66	47
alert_integrity_fail	alert[0x27]	2487	1			T19	670		T40	1		T20	36
alert_integrity_fail	alert[0x28]	7771	1			T11	6		T18	9		T66	147
alert_integrity_fail	alert[0x29]	3084	1			T11	1		T5	1		T40	74
alert_integrity_fail	alert[0x2a]	10992	1			T40	23		T20	31		T65	3404
alert_integrity_fail	alert[0x2b]	14243	1			T7	1845		T5	61		T19	14
alert_integrity_fail	alert[0x2c]	13629	1			T7	11		T11	4		T4	73
alert_integrity_fail	alert[0x2d]	2702	1			T19	13		T6	1		T20	16
alert_integrity_fail	alert[0x2e]	14040	1			T4	120		T17	9		T19	11
alert_integrity_fail	alert[0x2f]	12166	1			T7	1534		T11	4		T4	102
alert_integrity_fail	alert[0x30]	5880	1			T7	7		T258	41		T84	641
alert_integrity_fail	alert[0x31]	5358	1			T4	14		T5	5		T19	13
alert_integrity_fail	alert[0x32]	6473	1			T7	21		T19	15		T6	12
alert_integrity_fail	alert[0x33]	12202	1			T65	87		T70	4		T258	144
alert_integrity_fail	alert[0x34]	14846	1			T7	66		T6	63		T66	10
alert_integrity_fail	alert[0x35]	5524	1			T4	19		T18	13		T19	697
alert_integrity_fail	alert[0x36]	3956	1			T7	369		T4	4		T258	4
alert_integrity_fail	alert[0x37]	10576	1			T7	13		T5	1		T19	1898
alert_integrity_fail	alert[0x38]	4437	1			T4	49		T20	124		T44	86
alert_integrity_fail	alert[0x39]	9911	1			T7	23		T4	35		T17	62
alert_integrity_fail	alert[0x3a]	2396	1			T7	11		T4	6		T40	4
alert_integrity_fail	alert[0x3b]	15997	1			T4	2		T40	3		T280	118
alert_integrity_fail	alert[0x3c]	6266	1			T7	4		T40	23		T65	3
alert_integrity_fail	alert[0x3d]	7176	1			T17	1		T18	2		T19	132
alert_integrity_fail	alert[0x3e]	5474	1			T5	4		T19	41		T20	914
alert_integrity_fail	alert[0x3f]	11812	1			T7	52		T4	63		T5	1
alert_integrity_fail	alert[0x40]	11273	1			T7	288		T18	1		T6	119
alert_ping_fail	alert[0x0]	8	1			T307	1		T61	1		T308	1
alert_ping_fail	alert[0x1]	7	1			T309	1		T310	1		T311	1
alert_ping_fail	alert[0x2]	6	1			T306	1		T307	1		T309	1
alert_ping_fail	alert[0x3]	13	1			T13	1		T312	1		T307	1
alert_ping_fail	alert[0x4]	9	1			T312	1		T309	1		T199	1
alert_ping_fail	alert[0x5]	14	1			T304	1		T106	1		T306	1
alert_ping_fail	alert[0x6]	15	1			T1	1		T288	1		T307	1
alert_ping_fail	alert[0x7]	7	1			T13	1		T306	1		T223	1
alert_ping_fail	alert[0x8]	15	1			T1	3		T228	1		T291	1
alert_ping_fail	alert[0x9]	4	1			T313	1		T292	1		T314	1
alert_ping_fail	alert[0xa]	17	1			T16	1		T313	1		T312	1
alert_ping_fail	alert[0xb]	5	1			T228	1		T109	1		T315	1
alert_ping_fail	alert[0xc]	3	1			T109	1		T316	1		T317	1
alert_ping_fail	alert[0xd]	18	1			T13	1		T306	1		T312	1
alert_ping_fail	alert[0xe]	8	1			T313	1		T318	1		T319	1
alert_ping_fail	alert[0xf]	10	1			T306	1		T223	1		T228	1
alert_ping_fail	alert[0x10]	11	1			T312	1		T309	3		T315	1
alert_ping_fail	alert[0x11]	8	1			T228	1		T61	1		T37	3
alert_ping_fail	alert[0x12]	8	1			T13	1		T109	1		T320	2
alert_ping_fail	alert[0x13]	12	1			T13	1		T228	1		T109	1
alert_ping_fail	alert[0x14]	10	1			T13	1		T306	1		T321	1
alert_ping_fail	alert[0x15]	18	1			T223	1		T228	1		T294	2
alert_ping_fail	alert[0x16]	19	1			T304	1		T318	1		T322	1
alert_ping_fail	alert[0x17]	7	1			T306	1		T312	1		T319	1
alert_ping_fail	alert[0x18]	7	1			T306	1		T312	1		T318	1
alert_ping_fail	alert[0x19]	6	1			T318	1		T320	1		T323	1
alert_ping_fail	alert[0x1a]	7	1			T324	1		T311	1		T325	1
alert_ping_fail	alert[0x1b]	13	1			T222	1		T15	1		T313	1
alert_ping_fail	alert[0x1c]	22	1			T228	1		T61	1		T318	1
alert_ping_fail	alert[0x1d]	18	1			T16	1		T106	1		T288	1
alert_ping_fail	alert[0x1e]	8	1			T228	1		T318	1		T310	2
alert_ping_fail	alert[0x1f]	14	1			T106	1		T326	1		T309	1
alert_ping_fail	alert[0x20]	8	1			T222	1		T306	1		T228	1
alert_ping_fail	alert[0x21]	15	1			T222	1		T16	1		T223	1
alert_ping_fail	alert[0x22]	14	1			T306	1		T303	1		T309	1
alert_ping_fail	alert[0x23]	8	1			T309	2		T327	1		T308	1
alert_ping_fail	alert[0x24]	15	1			T312	1		T228	1		T61	3
alert_ping_fail	alert[0x25]	16	1			T306	1		T312	1		T318	2
alert_ping_fail	alert[0x26]	6	1			T313	1		T228	1		T37	1
alert_ping_fail	alert[0x27]	7	1			T13	1		T15	1		T109	2
alert_ping_fail	alert[0x28]	13	1			T309	1		T321	2		T320	1
alert_ping_fail	alert[0x29]	10	1			T306	1		T318	2		T309	2
alert_ping_fail	alert[0x2a]	15	1			T306	1		T307	1		T223	1
alert_ping_fail	alert[0x2b]	13	1			T16	1		T228	1		T303	2
alert_ping_fail	alert[0x2c]	17	1			T14	3		T222	1		T15	1
alert_ping_fail	alert[0x2d]	10	1			T1	1		T228	1		T319	1
alert_ping_fail	alert[0x2e]	9	1			T15	1		T303	1		T37	1
alert_ping_fail	alert[0x2f]	17	1			T1	3		T15	1		T313	1
alert_ping_fail	alert[0x30]	14	1			T13	1		T16	1		T313	1
alert_ping_fail	alert[0x31]	4	1			T306	1		T312	1		T328	1
alert_ping_fail	alert[0x32]	8	1			T307	1		T309	1		T199	1
alert_ping_fail	alert[0x33]	8	1			T318	1		T199	1		T310	1
alert_ping_fail	alert[0x34]	8	1			T13	1		T312	1		T329	1
alert_ping_fail	alert[0x35]	9	1			T13	1		T306	1		T318	1
alert_ping_fail	alert[0x36]	8	1			T15	1		T313	1		T61	1
alert_ping_fail	alert[0x37]	16	1			T13	1		T309	1		T37	1
alert_ping_fail	alert[0x38]	7	1			T109	1		T320	1		T330	1
alert_ping_fail	alert[0x39]	10	1			T306	1		T313	1		T292	1
alert_ping_fail	alert[0x3a]	9	1			T61	1		T37	2		T109	1
alert_ping_fail	alert[0x3b]	11	1			T306	1		T313	2		T307	1
alert_ping_fail	alert[0x3c]	12	1			T312	1		T37	1		T199	1
alert_ping_fail	alert[0x3d]	11	1			T13	1		T306	1		T312	1
alert_ping_fail	alert[0x3e]	9	1			T109	1		T331	1		T329	1
alert_ping_fail	alert[0x3f]	5	1			T306	1		T307	1		T315	1
alert_ping_fail	alert[0x40]	4	1			T309	1		T37	1		T321	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	124991	1			T7	45		T11	1		T4	823
alert_integrity_fail	class_i[0x1]	144367	1			T11	50		T17	3		T18	18
alert_integrity_fail	class_i[0x2]	141618	1			T7	6028		T11	75		T4	174
alert_integrity_fail	class_i[0x3]	95411	1			T4	9		T5	75		T17	71
alert_ping_fail	class_i[0x0]	181	1			T14	3		T16	1		T306	15
alert_ping_fail	class_i[0x1]	152	1			T16	2		T106	3		T306	2
alert_ping_fail	class_i[0x2]	208	1			T1	8		T13	1		T222	4
alert_ping_fail	class_i[0x3]	152	1			T13	11		T16	1		T306	2