Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.23 99.99 98.71 97.09 100.00 100.00 99.38 99.44


Total test records in report: 830
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T774 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.151660841 Jul 28 05:18:38 PM PDT 24 Jul 28 05:18:43 PM PDT 24 103974932 ps
T144 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1148272191 Jul 28 05:18:19 PM PDT 24 Jul 28 05:36:06 PM PDT 24 12991661100 ps
T775 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3010820330 Jul 28 05:18:12 PM PDT 24 Jul 28 05:18:20 PM PDT 24 220597384 ps
T776 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.907838694 Jul 28 05:18:33 PM PDT 24 Jul 28 05:18:38 PM PDT 24 183015236 ps
T138 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1981160277 Jul 28 05:18:27 PM PDT 24 Jul 28 05:20:23 PM PDT 24 891809494 ps
T145 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.148949097 Jul 28 05:18:25 PM PDT 24 Jul 28 05:22:33 PM PDT 24 1798820436 ps
T777 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2568762472 Jul 28 05:18:41 PM PDT 24 Jul 28 05:18:47 PM PDT 24 242439370 ps
T778 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3375479501 Jul 28 05:18:31 PM PDT 24 Jul 28 05:18:37 PM PDT 24 125939427 ps
T779 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1573940509 Jul 28 05:18:21 PM PDT 24 Jul 28 05:18:24 PM PDT 24 21358893 ps
T169 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3571688011 Jul 28 05:18:29 PM PDT 24 Jul 28 05:18:32 PM PDT 24 99996135 ps
T780 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.638012212 Jul 28 05:18:35 PM PDT 24 Jul 28 05:18:46 PM PDT 24 155423556 ps
T152 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.666829342 Jul 28 05:18:41 PM PDT 24 Jul 28 05:24:03 PM PDT 24 3905371689 ps
T141 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2538868220 Jul 28 05:18:33 PM PDT 24 Jul 28 05:25:17 PM PDT 24 52464057284 ps
T781 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.498876071 Jul 28 05:18:22 PM PDT 24 Jul 28 05:18:24 PM PDT 24 7193795 ps
T782 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1175373577 Jul 28 05:18:46 PM PDT 24 Jul 28 05:18:48 PM PDT 24 8403730 ps
T783 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3396218847 Jul 28 05:18:17 PM PDT 24 Jul 28 05:18:26 PM PDT 24 431276868 ps
T148 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.965315346 Jul 28 05:18:17 PM PDT 24 Jul 28 05:20:56 PM PDT 24 4448383758 ps
T784 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1429666610 Jul 28 05:18:48 PM PDT 24 Jul 28 05:18:50 PM PDT 24 8833474 ps
T785 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1635932267 Jul 28 05:18:02 PM PDT 24 Jul 28 05:22:19 PM PDT 24 30226712475 ps
T786 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.988628553 Jul 28 05:18:46 PM PDT 24 Jul 28 05:18:47 PM PDT 24 8011212 ps
T787 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.537098483 Jul 28 05:18:30 PM PDT 24 Jul 28 05:18:39 PM PDT 24 468784791 ps
T183 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3728583819 Jul 28 05:18:15 PM PDT 24 Jul 28 05:18:18 PM PDT 24 102072607 ps
T788 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2638329485 Jul 28 05:18:24 PM PDT 24 Jul 28 05:18:28 PM PDT 24 44114345 ps
T149 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.140235725 Jul 28 05:18:43 PM PDT 24 Jul 28 05:36:12 PM PDT 24 55504802165 ps
T168 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3668544570 Jul 28 05:18:22 PM PDT 24 Jul 28 05:19:42 PM PDT 24 1761475232 ps
T143 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3361783875 Jul 28 05:18:42 PM PDT 24 Jul 28 05:22:49 PM PDT 24 12963934105 ps
T146 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4018721499 Jul 28 05:18:22 PM PDT 24 Jul 28 05:23:23 PM PDT 24 6060530920 ps
T789 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2486145392 Jul 28 05:18:22 PM PDT 24 Jul 28 05:18:57 PM PDT 24 576792987 ps
T155 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3649802879 Jul 28 05:18:29 PM PDT 24 Jul 28 05:24:10 PM PDT 24 5115660098 ps
T790 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.729564199 Jul 28 05:18:41 PM PDT 24 Jul 28 05:18:47 PM PDT 24 118254249 ps
T166 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2268266215 Jul 28 05:18:19 PM PDT 24 Jul 28 05:18:22 PM PDT 24 94359608 ps
T791 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3035596959 Jul 28 05:18:46 PM PDT 24 Jul 28 05:18:47 PM PDT 24 21064919 ps
T147 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1557369718 Jul 28 05:18:29 PM PDT 24 Jul 28 05:24:52 PM PDT 24 30323798642 ps
T792 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1505218344 Jul 28 05:18:34 PM PDT 24 Jul 28 05:18:47 PM PDT 24 151440241 ps
T180 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1774795569 Jul 28 05:18:17 PM PDT 24 Jul 28 05:18:20 PM PDT 24 31008181 ps
T793 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1368358762 Jul 28 05:18:17 PM PDT 24 Jul 28 05:18:23 PM PDT 24 249325770 ps
T794 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.559779976 Jul 28 05:18:26 PM PDT 24 Jul 28 05:18:46 PM PDT 24 524301169 ps
T795 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1716239241 Jul 28 05:18:33 PM PDT 24 Jul 28 05:18:34 PM PDT 24 11999556 ps
T796 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.368593125 Jul 28 05:18:17 PM PDT 24 Jul 28 05:21:44 PM PDT 24 1687158409 ps
T797 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2415488605 Jul 28 05:18:34 PM PDT 24 Jul 28 05:18:40 PM PDT 24 35724291 ps
T798 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.475044454 Jul 28 05:18:39 PM PDT 24 Jul 28 05:18:40 PM PDT 24 17599237 ps
T799 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1795922026 Jul 28 05:18:38 PM PDT 24 Jul 28 05:18:48 PM PDT 24 213498534 ps
T800 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1675599040 Jul 28 05:18:46 PM PDT 24 Jul 28 05:18:52 PM PDT 24 34064724 ps
T801 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.356623344 Jul 28 05:18:05 PM PDT 24 Jul 28 05:18:14 PM PDT 24 197148883 ps
T167 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1058965208 Jul 28 05:18:29 PM PDT 24 Jul 28 05:19:09 PM PDT 24 307041003 ps
T802 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1603232348 Jul 28 05:18:33 PM PDT 24 Jul 28 05:18:42 PM PDT 24 53545153 ps
T174 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1315503102 Jul 28 05:18:20 PM PDT 24 Jul 28 05:19:01 PM PDT 24 2707379779 ps
T803 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1607449067 Jul 28 05:18:39 PM PDT 24 Jul 28 05:18:49 PM PDT 24 84889986 ps
T804 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3203277140 Jul 28 05:19:14 PM PDT 24 Jul 28 05:19:16 PM PDT 24 16669920 ps
T805 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3677261133 Jul 28 05:18:14 PM PDT 24 Jul 28 05:18:23 PM PDT 24 484838715 ps
T806 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2661656429 Jul 28 05:18:17 PM PDT 24 Jul 28 05:18:22 PM PDT 24 502249837 ps
T156 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.520898364 Jul 28 05:18:20 PM PDT 24 Jul 28 05:29:30 PM PDT 24 8398380747 ps
T807 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.690140584 Jul 28 05:18:36 PM PDT 24 Jul 28 05:18:37 PM PDT 24 16235427 ps
T808 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3729837569 Jul 28 05:18:50 PM PDT 24 Jul 28 05:18:52 PM PDT 24 7415605 ps
T809 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1972293804 Jul 28 05:18:21 PM PDT 24 Jul 28 05:18:30 PM PDT 24 99128857 ps
T810 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3425725945 Jul 28 05:18:33 PM PDT 24 Jul 28 05:18:38 PM PDT 24 43165921 ps
T811 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4021556632 Jul 28 05:18:31 PM PDT 24 Jul 28 05:18:37 PM PDT 24 318677381 ps
T812 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2586276137 Jul 28 05:18:32 PM PDT 24 Jul 28 05:18:48 PM PDT 24 1351561035 ps
T813 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1706342798 Jul 28 05:18:28 PM PDT 24 Jul 28 05:18:34 PM PDT 24 114914240 ps
T157 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3513097873 Jul 28 05:18:34 PM PDT 24 Jul 28 05:25:16 PM PDT 24 6385300706 ps
T814 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1345114940 Jul 28 05:18:27 PM PDT 24 Jul 28 05:18:36 PM PDT 24 467664826 ps
T815 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.832809642 Jul 28 05:18:36 PM PDT 24 Jul 28 05:18:37 PM PDT 24 37387967 ps
T816 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.292629376 Jul 28 05:18:32 PM PDT 24 Jul 28 05:18:41 PM PDT 24 230527467 ps
T817 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.406877985 Jul 28 05:18:36 PM PDT 24 Jul 28 05:18:38 PM PDT 24 9918434 ps
T818 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2575375956 Jul 28 05:18:03 PM PDT 24 Jul 28 05:18:05 PM PDT 24 9728434 ps
T819 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2246351119 Jul 28 05:18:28 PM PDT 24 Jul 28 05:27:26 PM PDT 24 32302791777 ps
T820 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4004563368 Jul 28 05:18:19 PM PDT 24 Jul 28 05:20:56 PM PDT 24 1916200875 ps
T171 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.434418864 Jul 28 05:18:24 PM PDT 24 Jul 28 05:19:01 PM PDT 24 4404184035 ps
T821 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1148795775 Jul 28 05:18:15 PM PDT 24 Jul 28 05:19:47 PM PDT 24 3405985060 ps
T822 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2548485560 Jul 28 05:18:31 PM PDT 24 Jul 28 05:18:36 PM PDT 24 63723789 ps
T823 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1024682748 Jul 28 05:18:29 PM PDT 24 Jul 28 05:18:30 PM PDT 24 10271108 ps
T824 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2546252028 Jul 28 05:18:42 PM PDT 24 Jul 28 05:18:43 PM PDT 24 11954469 ps
T153 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3575754154 Jul 28 05:18:49 PM PDT 24 Jul 28 05:24:57 PM PDT 24 4504224585 ps
T154 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3832108132 Jul 28 05:18:07 PM PDT 24 Jul 28 05:19:51 PM PDT 24 1135296640 ps
T825 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.789017048 Jul 28 05:18:18 PM PDT 24 Jul 28 05:38:10 PM PDT 24 16870618896 ps
T826 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2039514988 Jul 28 05:18:27 PM PDT 24 Jul 28 05:18:35 PM PDT 24 180048350 ps
T827 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.11937720 Jul 28 05:18:40 PM PDT 24 Jul 28 05:27:43 PM PDT 24 8614258543 ps
T828 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1400281143 Jul 28 05:18:48 PM PDT 24 Jul 28 05:18:49 PM PDT 24 8455209 ps
T829 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2698754201 Jul 28 05:18:49 PM PDT 24 Jul 28 05:18:50 PM PDT 24 6501597 ps
T830 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4252998456 Jul 28 05:18:36 PM PDT 24 Jul 28 05:18:49 PM PDT 24 118767248 ps

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2190015594
Short name T5
Test name
Test status
Simulation time 34818465008 ps
CPU time 2998.19 seconds
Started Jul 28 05:19:57 PM PDT 24
Finished Jul 28 06:09:56 PM PDT 24
Peak memory 305448 kb
Host smart-ea14c456-e10f-42a5-a799-9939d0363f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190015594 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2190015594
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.891119406
Short name T20
Test name
Test status
Simulation time 72971357797 ps
CPU time 4505.92 seconds
Started Jul 28 05:19:06 PM PDT 24
Finished Jul 28 06:34:18 PM PDT 24
Peak memory 303452 kb
Host smart-1b5a8433-c0ae-47ff-ad6b-b4755a8cc12d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891119406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.891119406
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1990505181
Short name T8
Test name
Test status
Simulation time 224019956 ps
CPU time 12.95 seconds
Started Jul 28 05:18:59 PM PDT 24
Finished Jul 28 05:19:17 PM PDT 24
Peak memory 270900 kb
Host smart-db01fd47-0d8a-4890-9698-ec595ed9cfec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1990505181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1990505181
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.68143385
Short name T124
Test name
Test status
Simulation time 15416266556 ps
CPU time 1181.84 seconds
Started Jul 28 05:18:25 PM PDT 24
Finished Jul 28 05:38:07 PM PDT 24
Peak memory 265368 kb
Host smart-7862c5b7-ebdf-4710-94b9-bc8b5f1a30d5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68143385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.68143385
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.875327140
Short name T89
Test name
Test status
Simulation time 685337728 ps
CPU time 40.09 seconds
Started Jul 28 05:19:27 PM PDT 24
Finished Jul 28 05:20:07 PM PDT 24
Peak memory 248808 kb
Host smart-07d5789c-b4e5-4860-ad2e-cbd3ca4efae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87532
7140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.875327140
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3097128860
Short name T66
Test name
Test status
Simulation time 112896430445 ps
CPU time 3357.09 seconds
Started Jul 28 05:20:19 PM PDT 24
Finished Jul 28 06:16:17 PM PDT 24
Peak memory 289832 kb
Host smart-adebd906-8cf2-4fd0-be0c-2af4ad066272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097128860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3097128860
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2012586711
Short name T136
Test name
Test status
Simulation time 4740815633 ps
CPU time 610.92 seconds
Started Jul 28 05:18:24 PM PDT 24
Finished Jul 28 05:28:35 PM PDT 24
Peak memory 264912 kb
Host smart-7e8bf898-a99b-4d67-af16-a991c88cb64a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012586711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2012586711
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.4036691635
Short name T222
Test name
Test status
Simulation time 279385479708 ps
CPU time 2437.65 seconds
Started Jul 28 05:18:47 PM PDT 24
Finished Jul 28 05:59:26 PM PDT 24
Peak memory 281696 kb
Host smart-52dfded3-f9e0-44e6-99a7-927cde515e8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036691635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4036691635
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2217625045
Short name T85
Test name
Test status
Simulation time 33812415416 ps
CPU time 2115.44 seconds
Started Jul 28 05:19:40 PM PDT 24
Finished Jul 28 05:54:55 PM PDT 24
Peak memory 298072 kb
Host smart-d891ab21-9605-4684-980c-3ec4490e52cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217625045 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2217625045
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.371791002
Short name T101
Test name
Test status
Simulation time 1038685821535 ps
CPU time 10173.3 seconds
Started Jul 28 05:19:38 PM PDT 24
Finished Jul 28 08:09:13 PM PDT 24
Peak memory 354856 kb
Host smart-f2329ff9-0608-4092-985c-b14ecb412f92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371791002 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.371791002
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2109154611
Short name T130
Test name
Test status
Simulation time 4619652954 ps
CPU time 667.74 seconds
Started Jul 28 05:18:34 PM PDT 24
Finished Jul 28 05:29:42 PM PDT 24
Peak memory 265432 kb
Host smart-e66786a0-335a-4e93-a320-8fe521c49138
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109154611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2109154611
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.22670091
Short name T23
Test name
Test status
Simulation time 990195069 ps
CPU time 63.46 seconds
Started Jul 28 05:19:31 PM PDT 24
Finished Jul 28 05:20:34 PM PDT 24
Peak memory 249768 kb
Host smart-a1803401-7ade-4535-bc46-d7d719929a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22670
091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.22670091
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3220724103
Short name T125
Test name
Test status
Simulation time 8283795381 ps
CPU time 170.63 seconds
Started Jul 28 05:18:03 PM PDT 24
Finished Jul 28 05:20:54 PM PDT 24
Peak memory 271368 kb
Host smart-95123151-0b42-4bb7-af64-18ddde7d53a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3220724103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3220724103
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2697146555
Short name T123
Test name
Test status
Simulation time 97353268292 ps
CPU time 530.38 seconds
Started Jul 28 05:18:39 PM PDT 24
Finished Jul 28 05:27:30 PM PDT 24
Peak memory 265624 kb
Host smart-200e184a-54fe-4b10-ad2d-daff868bc168
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697146555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2697146555
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1142232148
Short name T19
Test name
Test status
Simulation time 36322904017 ps
CPU time 1021.33 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:36:10 PM PDT 24
Peak memory 281016 kb
Host smart-4531583a-c6f8-4fb7-97b0-dc3252e5f54c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142232148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1142232148
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3178366694
Short name T1
Test name
Test status
Simulation time 251812537327 ps
CPU time 2580.58 seconds
Started Jul 28 05:20:07 PM PDT 24
Finished Jul 28 06:03:08 PM PDT 24
Peak memory 283992 kb
Host smart-36fe88ce-6b06-4241-84a0-01345cd5d940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178366694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3178366694
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.635449154
Short name T306
Test name
Test status
Simulation time 14614053711 ps
CPU time 597.25 seconds
Started Jul 28 05:20:20 PM PDT 24
Finished Jul 28 05:30:18 PM PDT 24
Peak memory 248868 kb
Host smart-a81480b9-5947-4685-a6a5-d127a6ded78d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635449154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.635449154
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3511338479
Short name T178
Test name
Test status
Simulation time 129059595 ps
CPU time 10.29 seconds
Started Jul 28 05:18:30 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 243540 kb
Host smart-cac2dcd5-00ab-4417-9055-d1ea257f2347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511338479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3511338479
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4095148865
Short name T355
Test name
Test status
Simulation time 10713394 ps
CPU time 1.75 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 237480 kb
Host smart-58df5c2b-9c03-4540-a6f5-7bbeb9ef4ea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4095148865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.4095148865
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4018721499
Short name T146
Test name
Test status
Simulation time 6060530920 ps
CPU time 301.36 seconds
Started Jul 28 05:18:22 PM PDT 24
Finished Jul 28 05:23:23 PM PDT 24
Peak memory 266480 kb
Host smart-0b2e448b-40f6-4be1-b99f-872c94003646
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4018721499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.4018721499
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3007337749
Short name T47
Test name
Test status
Simulation time 141433577194 ps
CPU time 4177.46 seconds
Started Jul 28 05:19:26 PM PDT 24
Finished Jul 28 06:29:04 PM PDT 24
Peak memory 297912 kb
Host smart-1fb03f56-f086-49f2-80a7-019fb7ec26ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007337749 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3007337749
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.148949097
Short name T145
Test name
Test status
Simulation time 1798820436 ps
CPU time 247.52 seconds
Started Jul 28 05:18:25 PM PDT 24
Finished Jul 28 05:22:33 PM PDT 24
Peak memory 265288 kb
Host smart-ed60bdff-89d1-45bc-9750-18c6a5025b13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=148949097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.148949097
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.492664011
Short name T338
Test name
Test status
Simulation time 91352449681 ps
CPU time 2709.03 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 06:04:04 PM PDT 24
Peak memory 289668 kb
Host smart-471a0d16-c534-4288-891d-3ac04d0780a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492664011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.492664011
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3145753501
Short name T65
Test name
Test status
Simulation time 59652846883 ps
CPU time 5506.78 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 06:50:56 PM PDT 24
Peak memory 371372 kb
Host smart-37a9cb26-8950-460b-a0d8-d19c8a86b4cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145753501 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3145753501
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.172840515
Short name T335
Test name
Test status
Simulation time 192488763010 ps
CPU time 2839.92 seconds
Started Jul 28 05:19:30 PM PDT 24
Finished Jul 28 06:06:50 PM PDT 24
Peak memory 289196 kb
Host smart-2c0207d9-e0fa-4a51-bea3-9b9fee44ae75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172840515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.172840515
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4256267065
Short name T228
Test name
Test status
Simulation time 51097044567 ps
CPU time 530.93 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:28:28 PM PDT 24
Peak memory 248712 kb
Host smart-1d1611ed-5481-4b02-8bf5-789d25c88424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256267065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4256267065
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3587339302
Short name T135
Test name
Test status
Simulation time 8792920922 ps
CPU time 311.36 seconds
Started Jul 28 05:18:10 PM PDT 24
Finished Jul 28 05:23:22 PM PDT 24
Peak memory 265420 kb
Host smart-3c9f1566-43c6-435e-8af8-e2c559b26e6e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587339302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3587339302
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2904642539
Short name T176
Test name
Test status
Simulation time 243701271 ps
CPU time 20.24 seconds
Started Jul 28 05:18:42 PM PDT 24
Finished Jul 28 05:19:03 PM PDT 24
Peak memory 237472 kb
Host smart-b53dd056-2bc1-4bab-97fd-a09534ac7b92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2904642539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2904642539
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3246032621
Short name T221
Test name
Test status
Simulation time 56571480015 ps
CPU time 1545.97 seconds
Started Jul 28 05:19:29 PM PDT 24
Finished Jul 28 05:45:15 PM PDT 24
Peak memory 271816 kb
Host smart-5f099588-3014-49fa-95b2-6f2139a8bef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246032621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3246032621
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2449552325
Short name T95
Test name
Test status
Simulation time 55174633261 ps
CPU time 3097.56 seconds
Started Jul 28 05:19:28 PM PDT 24
Finished Jul 28 06:11:06 PM PDT 24
Peak memory 289856 kb
Host smart-95a274a5-0274-4919-b7a0-d3b096cd6198
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449552325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2449552325
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.4156483712
Short name T642
Test name
Test status
Simulation time 12213698268 ps
CPU time 478.58 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:27:06 PM PDT 24
Peak memory 248708 kb
Host smart-053c3c29-40c2-4a3e-95e1-d61676a0b076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156483712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.4156483712
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1240222654
Short name T134
Test name
Test status
Simulation time 5298018270 ps
CPU time 583.94 seconds
Started Jul 28 05:18:28 PM PDT 24
Finished Jul 28 05:28:13 PM PDT 24
Peak memory 272272 kb
Host smart-c5f6166b-9fc3-4e08-8242-ccc868d843ff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240222654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1240222654
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2366326839
Short name T239
Test name
Test status
Simulation time 364354265 ps
CPU time 10.52 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:19:05 PM PDT 24
Peak memory 248716 kb
Host smart-6275a1af-ca11-45ab-8b1d-f754232d2951
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2366326839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2366326839
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3074215466
Short name T324
Test name
Test status
Simulation time 13391541748 ps
CPU time 512.8 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 05:27:58 PM PDT 24
Peak memory 248840 kb
Host smart-42ef53c1-d7a8-43d5-b922-5ffc4b174ae1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074215466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3074215466
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.205233468
Short name T164
Test name
Test status
Simulation time 227529173 ps
CPU time 2.78 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:12 PM PDT 24
Peak memory 237456 kb
Host smart-9c9791d1-e5df-41b7-bcb6-fb352ebf2da7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=205233468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.205233468
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1284620772
Short name T727
Test name
Test status
Simulation time 11860390 ps
CPU time 1.49 seconds
Started Jul 28 05:18:25 PM PDT 24
Finished Jul 28 05:18:27 PM PDT 24
Peak memory 236612 kb
Host smart-79266a4e-61bb-4849-8ed4-9472911daca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284620772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1284620772
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.650568483
Short name T676
Test name
Test status
Simulation time 57548649668 ps
CPU time 3337.64 seconds
Started Jul 28 05:19:13 PM PDT 24
Finished Jul 28 06:14:51 PM PDT 24
Peak memory 288880 kb
Host smart-ed99b868-1f1e-4211-a12c-3e3f35a455d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650568483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.650568483
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1485640415
Short name T110
Test name
Test status
Simulation time 22208581107 ps
CPU time 1656.45 seconds
Started Jul 28 05:19:05 PM PDT 24
Finished Jul 28 05:46:42 PM PDT 24
Peak memory 289708 kb
Host smart-d668f8a0-47da-4442-a00e-12cb4381ea86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485640415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1485640415
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4044267881
Short name T131
Test name
Test status
Simulation time 3822619259 ps
CPU time 301.37 seconds
Started Jul 28 05:18:22 PM PDT 24
Finished Jul 28 05:23:23 PM PDT 24
Peak memory 265412 kb
Host smart-4bfd4e9f-dddb-4fac-b4a3-d35a2be6a973
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4044267881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.4044267881
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3980627016
Short name T142
Test name
Test status
Simulation time 2633058463 ps
CPU time 376.14 seconds
Started Jul 28 05:18:32 PM PDT 24
Finished Jul 28 05:24:49 PM PDT 24
Peak memory 268348 kb
Host smart-4d465640-b151-4518-81cf-9278019c80c6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980627016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3980627016
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2485347850
Short name T45
Test name
Test status
Simulation time 51820155682 ps
CPU time 3614.75 seconds
Started Jul 28 05:19:36 PM PDT 24
Finished Jul 28 06:19:51 PM PDT 24
Peak memory 305920 kb
Host smart-54167e98-1a68-406b-8ddc-f4085b16131c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485347850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2485347850
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3814222427
Short name T291
Test name
Test status
Simulation time 37802452421 ps
CPU time 943.84 seconds
Started Jul 28 05:19:29 PM PDT 24
Finished Jul 28 05:35:14 PM PDT 24
Peak memory 273328 kb
Host smart-dc4993df-5ee6-4b74-a07c-e19f2e8e0836
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814222427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3814222427
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2613276370
Short name T109
Test name
Test status
Simulation time 52096938608 ps
CPU time 577.91 seconds
Started Jul 28 05:19:31 PM PDT 24
Finished Jul 28 05:29:09 PM PDT 24
Peak memory 255540 kb
Host smart-7509e101-b4f3-4d24-ba5b-d473ff0a0c69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613276370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2613276370
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1103975386
Short name T195
Test name
Test status
Simulation time 5505564163 ps
CPU time 298.61 seconds
Started Jul 28 05:18:14 PM PDT 24
Finished Jul 28 05:23:13 PM PDT 24
Peak memory 240584 kb
Host smart-8c6ab8cf-5290-4b11-b7b7-eb70a892cdc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1103975386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1103975386
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1251804790
Short name T275
Test name
Test status
Simulation time 62890578772 ps
CPU time 1896.44 seconds
Started Jul 28 05:19:16 PM PDT 24
Finished Jul 28 05:50:53 PM PDT 24
Peak memory 287332 kb
Host smart-ff6d0e9a-a9c5-45d3-a3f4-8e64f0aa5118
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251804790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1251804790
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2958754213
Short name T263
Test name
Test status
Simulation time 89381177119 ps
CPU time 7286.62 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 07:20:52 PM PDT 24
Peak memory 370528 kb
Host smart-731e60a9-0d27-470e-9951-8b54ce3d2cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958754213 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2958754213
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1173718461
Short name T314
Test name
Test status
Simulation time 10138887322 ps
CPU time 200.97 seconds
Started Jul 28 05:19:29 PM PDT 24
Finished Jul 28 05:22:50 PM PDT 24
Peak memory 255384 kb
Host smart-d228aecf-44cb-428b-8be3-b112e9707a0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173718461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1173718461
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.655259370
Short name T243
Test name
Test status
Simulation time 83856164166 ps
CPU time 1230.47 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:40:04 PM PDT 24
Peak memory 281920 kb
Host smart-a4dad5ea-53e5-4720-8502-93b152880677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655259370 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.655259370
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.494659414
Short name T42
Test name
Test status
Simulation time 33629359035 ps
CPU time 1363 seconds
Started Jul 28 05:19:47 PM PDT 24
Finished Jul 28 05:42:31 PM PDT 24
Peak memory 289348 kb
Host smart-a2feea16-9f83-406e-bc99-03e2d9419080
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494659414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.494659414
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.594471476
Short name T211
Test name
Test status
Simulation time 83268752 ps
CPU time 3.94 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:18:52 PM PDT 24
Peak memory 249072 kb
Host smart-80923513-1d23-49fe-aa5d-f2f4c9eb7e26
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=594471476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.594471476
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1901156948
Short name T217
Test name
Test status
Simulation time 23155135 ps
CPU time 3.06 seconds
Started Jul 28 05:18:34 PM PDT 24
Finished Jul 28 05:18:37 PM PDT 24
Peak memory 249056 kb
Host smart-73d1ed9a-3d1e-4a13-9921-b6cfb8a5b4dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1901156948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1901156948
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1830585172
Short name T203
Test name
Test status
Simulation time 63054989 ps
CPU time 3.44 seconds
Started Jul 28 05:19:06 PM PDT 24
Finished Jul 28 05:19:09 PM PDT 24
Peak memory 249112 kb
Host smart-de4f300c-2d39-4650-b578-de3bdc420dda
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1830585172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1830585172
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2964148776
Short name T204
Test name
Test status
Simulation time 33686064 ps
CPU time 2.55 seconds
Started Jul 28 05:19:10 PM PDT 24
Finished Jul 28 05:19:13 PM PDT 24
Peak memory 249060 kb
Host smart-64c494c7-d71c-4f75-8979-b11b9840f1c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2964148776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2964148776
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3085794282
Short name T752
Test name
Test status
Simulation time 25285819 ps
CPU time 1.51 seconds
Started Jul 28 05:18:12 PM PDT 24
Finished Jul 28 05:18:14 PM PDT 24
Peak memory 237404 kb
Host smart-d3567a8d-bff3-4293-b001-fcc8db8c2d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3085794282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3085794282
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1175633722
Short name T340
Test name
Test status
Simulation time 299447357795 ps
CPU time 2181.29 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:55:05 PM PDT 24
Peak memory 272748 kb
Host smart-b42ca17a-a0b7-4716-ae6b-65b91e68e7f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175633722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1175633722
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2236541907
Short name T345
Test name
Test status
Simulation time 74732709998 ps
CPU time 2880.15 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 06:07:11 PM PDT 24
Peak memory 286232 kb
Host smart-eaaa46e5-b6cb-47f2-9217-31882718b955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236541907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2236541907
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3612427042
Short name T108
Test name
Test status
Simulation time 18567009121 ps
CPU time 272.41 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:23:47 PM PDT 24
Peak memory 257036 kb
Host smart-b16ed783-9c8e-4f32-9b2a-7fd3b04a5bcb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612427042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3612427042
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1378590168
Short name T295
Test name
Test status
Simulation time 179365350415 ps
CPU time 5001.21 seconds
Started Jul 28 05:19:27 PM PDT 24
Finished Jul 28 06:42:48 PM PDT 24
Peak memory 349924 kb
Host smart-9d10c06d-33c7-4e0c-bb2e-b66861c39768
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378590168 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1378590168
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2254872362
Short name T309
Test name
Test status
Simulation time 14210619037 ps
CPU time 536.13 seconds
Started Jul 28 05:19:57 PM PDT 24
Finished Jul 28 05:28:54 PM PDT 24
Peak memory 247816 kb
Host smart-1491696e-0962-4bae-b1dd-b45a272f0389
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254872362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2254872362
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3120610542
Short name T128
Test name
Test status
Simulation time 1652131901 ps
CPU time 203.34 seconds
Started Jul 28 05:18:26 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 271656 kb
Host smart-a20edd95-d7c5-4979-8cd5-09971c6023cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3120610542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3120610542
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3649802879
Short name T155
Test name
Test status
Simulation time 5115660098 ps
CPU time 340.97 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:24:10 PM PDT 24
Peak memory 265368 kb
Host smart-07269a5b-9b0f-4469-9d6b-5d3774475ffa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3649802879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3649802879
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.4151465547
Short name T327
Test name
Test status
Simulation time 54607085267 ps
CPU time 287.57 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:23:17 PM PDT 24
Peak memory 247672 kb
Host smart-bf168245-f0cb-4168-a9af-364fada5ad87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151465547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.4151465547
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2360829725
Short name T462
Test name
Test status
Simulation time 34200886363 ps
CPU time 2246.51 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:56:15 PM PDT 24
Peak memory 281568 kb
Host smart-fe6b7afd-ea12-4257-ab10-5c6f1465016c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360829725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2360829725
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.4288294375
Short name T274
Test name
Test status
Simulation time 322584487201 ps
CPU time 7034.7 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 07:16:01 PM PDT 24
Peak memory 350048 kb
Host smart-d2271739-83ee-4d5e-bb29-45aa00ed1c22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288294375 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.4288294375
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3105155153
Short name T284
Test name
Test status
Simulation time 35922587838 ps
CPU time 761.54 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:31:36 PM PDT 24
Peak memory 266440 kb
Host smart-03feab85-d7b3-438a-b3ba-74c9fccd1034
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105155153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3105155153
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.335708524
Short name T261
Test name
Test status
Simulation time 949581187 ps
CPU time 31.46 seconds
Started Jul 28 05:19:01 PM PDT 24
Finished Jul 28 05:19:32 PM PDT 24
Peak memory 256100 kb
Host smart-fd1fd940-e9d1-4f02-9454-f1bcea195e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33570
8524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.335708524
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.554858084
Short name T348
Test name
Test status
Simulation time 43308671627 ps
CPU time 849.97 seconds
Started Jul 28 05:19:20 PM PDT 24
Finished Jul 28 05:33:30 PM PDT 24
Peak memory 273060 kb
Host smart-3b3f9aaa-3dc6-4e76-88f1-f4d68c020bed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554858084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.554858084
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3328046137
Short name T58
Test name
Test status
Simulation time 92351979 ps
CPU time 10.11 seconds
Started Jul 28 05:18:59 PM PDT 24
Finished Jul 28 05:19:09 PM PDT 24
Peak memory 249592 kb
Host smart-e67fa8b1-bd33-488a-95b3-0e8f36cb4e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33280
46137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3328046137
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.499003063
Short name T297
Test name
Test status
Simulation time 502298993 ps
CPU time 23.81 seconds
Started Jul 28 05:19:01 PM PDT 24
Finished Jul 28 05:19:25 PM PDT 24
Peak memory 256740 kb
Host smart-b2ac0b62-de50-49bb-bcf3-839da682a04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49900
3063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.499003063
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2430001690
Short name T63
Test name
Test status
Simulation time 4545042129 ps
CPU time 65.23 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:19:52 PM PDT 24
Peak memory 248720 kb
Host smart-ad126348-920e-4d9a-8ce5-3642fd515470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24300
01690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2430001690
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2818439409
Short name T302
Test name
Test status
Simulation time 4892415386 ps
CPU time 76.88 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:20:38 PM PDT 24
Peak memory 257060 kb
Host smart-61267f65-2664-4c73-9dd0-62f83ae9f79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
39409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2818439409
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4207604679
Short name T272
Test name
Test status
Simulation time 14676086552 ps
CPU time 800.52 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:32:16 PM PDT 24
Peak memory 266844 kb
Host smart-81bd89f0-8077-4989-a8eb-3cb79bf80e75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207604679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4207604679
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1266321854
Short name T294
Test name
Test status
Simulation time 173928208826 ps
CPU time 2694.25 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 06:04:31 PM PDT 24
Peak memory 283168 kb
Host smart-ffd5986d-16c5-4f95-b7a4-2d9129ac576b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266321854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1266321854
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.892075681
Short name T292
Test name
Test status
Simulation time 21511313690 ps
CPU time 542.8 seconds
Started Jul 28 05:19:43 PM PDT 24
Finished Jul 28 05:28:46 PM PDT 24
Peak memory 247904 kb
Host smart-88ac17a1-5666-4832-905f-8835ab20436d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892075681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.892075681
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.691303694
Short name T269
Test name
Test status
Simulation time 117681431619 ps
CPU time 1763.1 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:48:07 PM PDT 24
Peak memory 285672 kb
Host smart-f10d02a7-48df-486e-a3ed-d2466685542a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691303694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.691303694
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1155363934
Short name T270
Test name
Test status
Simulation time 379601047 ps
CPU time 22 seconds
Started Jul 28 05:19:00 PM PDT 24
Finished Jul 28 05:19:22 PM PDT 24
Peak memory 248844 kb
Host smart-9804b364-a65a-487b-b891-45914968f642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11553
63934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1155363934
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3157897217
Short name T7
Test name
Test status
Simulation time 5220143290 ps
CPU time 648.31 seconds
Started Jul 28 05:19:02 PM PDT 24
Finished Jul 28 05:29:51 PM PDT 24
Peak memory 273084 kb
Host smart-3ef3c279-19fc-4a35-92d0-82d26da6dba5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157897217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3157897217
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.254922155
Short name T86
Test name
Test status
Simulation time 119374571483 ps
CPU time 1710.3 seconds
Started Jul 28 05:19:00 PM PDT 24
Finished Jul 28 05:47:30 PM PDT 24
Peak memory 283412 kb
Host smart-6112f642-84d1-46b7-9328-37e1a90b89fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254922155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.254922155
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1309927340
Short name T122
Test name
Test status
Simulation time 1689876297 ps
CPU time 108.9 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:20:37 PM PDT 24
Peak memory 267916 kb
Host smart-0661bd77-6596-468d-8ff3-5ead262b76e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1309927340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1309927340
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1148272191
Short name T144
Test name
Test status
Simulation time 12991661100 ps
CPU time 1066.09 seconds
Started Jul 28 05:18:19 PM PDT 24
Finished Jul 28 05:36:06 PM PDT 24
Peak memory 272596 kb
Host smart-c460d9ca-c3ab-45ba-8036-a2a1f64fddc3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148272191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1148272191
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2238226681
Short name T170
Test name
Test status
Simulation time 132797036 ps
CPU time 6.4 seconds
Started Jul 28 05:18:35 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 237456 kb
Host smart-317ddc0e-8651-4be5-8359-e40db33b44fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2238226681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2238226681
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3668544570
Short name T168
Test name
Test status
Simulation time 1761475232 ps
CPU time 79.51 seconds
Started Jul 28 05:18:22 PM PDT 24
Finished Jul 28 05:19:42 PM PDT 24
Peak memory 240364 kb
Host smart-563ed6c8-b508-4981-be36-a0718daf3995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3668544570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3668544570
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3571688011
Short name T169
Test name
Test status
Simulation time 99996135 ps
CPU time 3.03 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:18:32 PM PDT 24
Peak memory 237428 kb
Host smart-ac5aa6c7-efee-424e-9936-e2301904f1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3571688011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3571688011
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3799972074
Short name T172
Test name
Test status
Simulation time 200274134 ps
CPU time 3.82 seconds
Started Jul 28 05:18:26 PM PDT 24
Finished Jul 28 05:18:30 PM PDT 24
Peak memory 236524 kb
Host smart-a2ba3679-88d7-4c00-abbb-b89c7f1cee07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3799972074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3799972074
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1058965208
Short name T167
Test name
Test status
Simulation time 307041003 ps
CPU time 40.33 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:19:09 PM PDT 24
Peak memory 240580 kb
Host smart-09243af3-8bd9-414f-bc15-b981f71069de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1058965208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1058965208
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1774795569
Short name T180
Test name
Test status
Simulation time 31008181 ps
CPU time 2.7 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:18:20 PM PDT 24
Peak memory 237856 kb
Host smart-c485cca5-149d-4b31-b607-380c4425cc65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1774795569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1774795569
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1315503102
Short name T174
Test name
Test status
Simulation time 2707379779 ps
CPU time 40.39 seconds
Started Jul 28 05:18:20 PM PDT 24
Finished Jul 28 05:19:01 PM PDT 24
Peak memory 237756 kb
Host smart-bd120eaf-4b24-4cbf-b2eb-08fb9fa1bfa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1315503102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1315503102
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.434418864
Short name T171
Test name
Test status
Simulation time 4404184035 ps
CPU time 36.75 seconds
Started Jul 28 05:18:24 PM PDT 24
Finished Jul 28 05:19:01 PM PDT 24
Peak memory 240088 kb
Host smart-275f69a3-b1c1-448b-abc7-790b90a5a42d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=434418864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.434418864
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1971127417
Short name T175
Test name
Test status
Simulation time 71904704 ps
CPU time 2.15 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:23 PM PDT 24
Peak memory 237468 kb
Host smart-8b10af8c-b769-4b7c-94ec-2d5089c2952e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1971127417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1971127417
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3545210675
Short name T165
Test name
Test status
Simulation time 122005163 ps
CPU time 3.64 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 237760 kb
Host smart-0bca977d-363d-492d-a24f-a2fdabcd0f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3545210675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3545210675
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1076349898
Short name T160
Test name
Test status
Simulation time 55959059 ps
CPU time 3.63 seconds
Started Jul 28 05:18:33 PM PDT 24
Finished Jul 28 05:18:37 PM PDT 24
Peak memory 236596 kb
Host smart-9554dc8d-f9b7-4560-a7c9-d822861b102d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1076349898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1076349898
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3237322457
Short name T173
Test name
Test status
Simulation time 99629449 ps
CPU time 2.95 seconds
Started Jul 28 05:18:20 PM PDT 24
Finished Jul 28 05:18:23 PM PDT 24
Peak memory 237892 kb
Host smart-f083e179-d586-46da-9e84-c3dbf3d93e02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3237322457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3237322457
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1845318544
Short name T182
Test name
Test status
Simulation time 59488793 ps
CPU time 2.06 seconds
Started Jul 28 05:18:51 PM PDT 24
Finished Jul 28 05:18:53 PM PDT 24
Peak memory 236596 kb
Host smart-ce6057b8-5b60-46f8-88ca-b8a4e4b97120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1845318544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1845318544
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1591839794
Short name T159
Test name
Test status
Simulation time 126628846 ps
CPU time 2.49 seconds
Started Jul 28 05:18:28 PM PDT 24
Finished Jul 28 05:18:31 PM PDT 24
Peak memory 237512 kb
Host smart-b19d51f6-16d4-49c3-bac2-60d71e6bec29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1591839794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1591839794
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2268266215
Short name T166
Test name
Test status
Simulation time 94359608 ps
CPU time 3.34 seconds
Started Jul 28 05:18:19 PM PDT 24
Finished Jul 28 05:18:22 PM PDT 24
Peak memory 236628 kb
Host smart-29176cef-e8ca-4c51-9be6-1d9436593e62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2268266215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2268266215
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3728583819
Short name T183
Test name
Test status
Simulation time 102072607 ps
CPU time 2.92 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:18:18 PM PDT 24
Peak memory 236596 kb
Host smart-aec2dd5c-ccb4-402b-8520-2d8164994c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3728583819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3728583819
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.312166357
Short name T177
Test name
Test status
Simulation time 116893393 ps
CPU time 4.26 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:25 PM PDT 24
Peak memory 237832 kb
Host smart-9ed1a604-64a5-4eef-bb90-332e9f74aad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=312166357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.312166357
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.533594358
Short name T24
Test name
Test status
Simulation time 43872055444 ps
CPU time 2800.46 seconds
Started Jul 28 05:19:51 PM PDT 24
Finished Jul 28 06:06:31 PM PDT 24
Peak memory 287320 kb
Host smart-80a15ded-fe59-4a29-a679-0819320eedf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533594358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.533594358
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.368593125
Short name T796
Test name
Test status
Simulation time 1687158409 ps
CPU time 206.43 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:21:44 PM PDT 24
Peak memory 240456 kb
Host smart-0fa6f748-d3b5-43cc-a4e2-fc6c0a2bfd34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=368593125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.368593125
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3396218847
Short name T783
Test name
Test status
Simulation time 431276868 ps
CPU time 8.88 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:18:26 PM PDT 24
Peak memory 249104 kb
Host smart-6117c1fc-c387-437b-ae3e-0d3a39583227
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3396218847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3396218847
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4249632970
Short name T767
Test name
Test status
Simulation time 197601348 ps
CPU time 8.93 seconds
Started Jul 28 05:17:56 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 251504 kb
Host smart-3f18d7d4-5057-40a2-8471-500d832716b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249632970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.4249632970
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2616065280
Short name T746
Test name
Test status
Simulation time 1078350817 ps
CPU time 8.82 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 237520 kb
Host smart-6f376340-bfed-4ea2-b830-eaec1170f649
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2616065280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2616065280
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2575375956
Short name T818
Test name
Test status
Simulation time 9728434 ps
CPU time 1.27 seconds
Started Jul 28 05:18:03 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 235480 kb
Host smart-e11c13ab-aa34-4b79-8c0f-c59b3ee2c068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2575375956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2575375956
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1441178689
Short name T768
Test name
Test status
Simulation time 94502494 ps
CPU time 12.59 seconds
Started Jul 28 05:18:14 PM PDT 24
Finished Jul 28 05:18:27 PM PDT 24
Peak memory 245608 kb
Host smart-2ea00ce2-e8e7-452e-8b9b-dc844d7b3667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1441178689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1441178689
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3230507046
Short name T132
Test name
Test status
Simulation time 9081510371 ps
CPU time 587.7 seconds
Started Jul 28 05:18:20 PM PDT 24
Finished Jul 28 05:28:08 PM PDT 24
Peak memory 265432 kb
Host smart-002eef5d-d096-482f-b99f-ab7e7c63df7b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230507046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3230507046
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.311106252
Short name T718
Test name
Test status
Simulation time 1232457090 ps
CPU time 21.84 seconds
Started Jul 28 05:18:16 PM PDT 24
Finished Jul 28 05:18:38 PM PDT 24
Peak memory 248704 kb
Host smart-0b00c900-623e-4e80-8e2e-9f96e5164ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=311106252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.311106252
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3856052587
Short name T158
Test name
Test status
Simulation time 173558254 ps
CPU time 3.8 seconds
Started Jul 28 05:18:23 PM PDT 24
Finished Jul 28 05:18:27 PM PDT 24
Peak memory 237500 kb
Host smart-60f91c90-0312-4288-be06-c4a627b3f68e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3856052587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3856052587
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.290100261
Short name T192
Test name
Test status
Simulation time 14925270343 ps
CPU time 159.89 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:21:09 PM PDT 24
Peak memory 237624 kb
Host smart-198f60f9-15f5-42f3-a17b-7a72c81ff5c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=290100261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.290100261
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1148795775
Short name T821
Test name
Test status
Simulation time 3405985060 ps
CPU time 91.78 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:19:47 PM PDT 24
Peak memory 240580 kb
Host smart-1f13eefc-a014-4525-9476-d2ca7762c768
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1148795775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1148795775
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2661656429
Short name T806
Test name
Test status
Simulation time 502249837 ps
CPU time 5.58 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:18:22 PM PDT 24
Peak memory 240456 kb
Host smart-1c3184c9-c562-4adf-b322-b33a51ea9eeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2661656429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2661656429
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1795922026
Short name T799
Test name
Test status
Simulation time 213498534 ps
CPU time 9.65 seconds
Started Jul 28 05:18:38 PM PDT 24
Finished Jul 28 05:18:48 PM PDT 24
Peak memory 250720 kb
Host smart-0a519bd8-af86-4794-9fcf-9431933af5d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795922026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1795922026
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1345114940
Short name T814
Test name
Test status
Simulation time 467664826 ps
CPU time 9.05 seconds
Started Jul 28 05:18:27 PM PDT 24
Finished Jul 28 05:18:36 PM PDT 24
Peak memory 237524 kb
Host smart-f53348d1-ebb6-4d1a-803f-372cfeb703c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1345114940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1345114940
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2486145392
Short name T789
Test name
Test status
Simulation time 576792987 ps
CPU time 35.41 seconds
Started Jul 28 05:18:22 PM PDT 24
Finished Jul 28 05:18:57 PM PDT 24
Peak memory 248584 kb
Host smart-3c19d29b-c467-4e6e-adf2-5be50917f2c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2486145392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2486145392
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2346417027
Short name T769
Test name
Test status
Simulation time 115276800 ps
CPU time 15.02 seconds
Started Jul 28 05:18:19 PM PDT 24
Finished Jul 28 05:18:34 PM PDT 24
Peak memory 254056 kb
Host smart-f70b2f56-937d-42a0-bc9d-05a3eaba9c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2346417027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2346417027
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1841993481
Short name T748
Test name
Test status
Simulation time 62204403 ps
CPU time 8.9 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:30 PM PDT 24
Peak memory 251552 kb
Host smart-2f95529c-2b4e-4eb0-aca7-f82965eb86c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841993481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1841993481
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1222488471
Short name T743
Test name
Test status
Simulation time 122329465 ps
CPU time 4.51 seconds
Started Jul 28 05:18:09 PM PDT 24
Finished Jul 28 05:18:14 PM PDT 24
Peak memory 237492 kb
Host smart-d1028daf-b284-4b4b-a0ef-15580e8aca04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1222488471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1222488471
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3622520880
Short name T352
Test name
Test status
Simulation time 11555520 ps
CPU time 1.62 seconds
Started Jul 28 05:18:40 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 237428 kb
Host smart-ea156f40-a9a9-4954-80d2-af960ef37515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3622520880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3622520880
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2047926
Short name T186
Test name
Test status
Simulation time 2806340144 ps
CPU time 46.6 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:19:15 PM PDT 24
Peak memory 248692 kb
Host smart-68bbd35d-3f0d-4a31-a62f-e8466e395dfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2047926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outst
anding.2047926
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2376532236
Short name T150
Test name
Test status
Simulation time 4435759281 ps
CPU time 351.18 seconds
Started Jul 28 05:18:25 PM PDT 24
Finished Jul 28 05:24:16 PM PDT 24
Peak memory 269084 kb
Host smart-7699211d-471a-4010-afb0-cda8c7c0db37
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376532236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2376532236
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.182742049
Short name T759
Test name
Test status
Simulation time 814442774 ps
CPU time 16.2 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:18:33 PM PDT 24
Peak memory 253400 kb
Host smart-959811f9-52a6-401d-93cf-8868b046b98b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=182742049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.182742049
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3822630529
Short name T362
Test name
Test status
Simulation time 132979609 ps
CPU time 5.47 seconds
Started Jul 28 05:18:35 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 240484 kb
Host smart-7ebd701d-6dfc-484f-a882-68c6da0f0647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822630529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3822630529
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2548485560
Short name T822
Test name
Test status
Simulation time 63723789 ps
CPU time 5.57 seconds
Started Jul 28 05:18:31 PM PDT 24
Finished Jul 28 05:18:36 PM PDT 24
Peak memory 237400 kb
Host smart-87aeacbc-991a-44ee-afe3-10cc4b68e90a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2548485560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2548485560
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.498876071
Short name T781
Test name
Test status
Simulation time 7193795 ps
CPU time 1.53 seconds
Started Jul 28 05:18:22 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 237452 kb
Host smart-98369e6c-d513-4dbf-9a18-31d4cda1b059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=498876071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.498876071
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4252998456
Short name T830
Test name
Test status
Simulation time 118767248 ps
CPU time 13.07 seconds
Started Jul 28 05:18:36 PM PDT 24
Finished Jul 28 05:18:49 PM PDT 24
Peak memory 245856 kb
Host smart-987bfcfd-8443-47f4-8df1-2e54531acbb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4252998456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4252998456
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.838353468
Short name T139
Test name
Test status
Simulation time 6583856233 ps
CPU time 226.75 seconds
Started Jul 28 05:18:47 PM PDT 24
Finished Jul 28 05:22:34 PM PDT 24
Peak memory 272624 kb
Host smart-9e90cdc0-9f06-41f3-9180-33d961175af9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=838353468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.838353468
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3667591305
Short name T717
Test name
Test status
Simulation time 42457212 ps
CPU time 5.65 seconds
Started Jul 28 05:18:44 PM PDT 24
Finished Jul 28 05:18:50 PM PDT 24
Peak memory 254656 kb
Host smart-a3c0e94c-bed9-43c6-8696-07f563aca68e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3667591305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3667591305
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1505218344
Short name T792
Test name
Test status
Simulation time 151440241 ps
CPU time 12.36 seconds
Started Jul 28 05:18:34 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 251744 kb
Host smart-0160f3a0-7bb2-4e38-a0b1-767206d74d28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505218344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1505218344
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3227957857
Short name T185
Test name
Test status
Simulation time 64479499 ps
CPU time 3.33 seconds
Started Jul 28 05:18:28 PM PDT 24
Finished Jul 28 05:18:31 PM PDT 24
Peak memory 240360 kb
Host smart-b1c2fd0a-6cc9-42b5-8f96-1957cf49bb9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3227957857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3227957857
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.983598309
Short name T732
Test name
Test status
Simulation time 12529137 ps
CPU time 1.6 seconds
Started Jul 28 05:18:35 PM PDT 24
Finished Jul 28 05:18:37 PM PDT 24
Peak memory 235460 kb
Host smart-a804e337-e592-436e-9966-f404fa27b26d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=983598309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.983598309
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2036799586
Short name T193
Test name
Test status
Simulation time 650977197 ps
CPU time 22.37 seconds
Started Jul 28 05:18:30 PM PDT 24
Finished Jul 28 05:18:53 PM PDT 24
Peak memory 248612 kb
Host smart-1cae82ab-8a85-4702-a803-37341c632b9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2036799586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2036799586
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3575754154
Short name T153
Test name
Test status
Simulation time 4504224585 ps
CPU time 367.6 seconds
Started Jul 28 05:18:49 PM PDT 24
Finished Jul 28 05:24:57 PM PDT 24
Peak memory 265392 kb
Host smart-685237e2-c8d2-49a1-b1c9-31e19559c0b8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575754154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3575754154
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.729564199
Short name T790
Test name
Test status
Simulation time 118254249 ps
CPU time 6.64 seconds
Started Jul 28 05:18:41 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 254560 kb
Host smart-bd94540f-e269-4fd6-a05c-05a6b2c08e36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=729564199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.729564199
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2251766770
Short name T202
Test name
Test status
Simulation time 221025790 ps
CPU time 8.82 seconds
Started Jul 28 05:18:27 PM PDT 24
Finished Jul 28 05:18:36 PM PDT 24
Peak memory 248856 kb
Host smart-298ba6a2-3542-43fe-8baf-6858ca0e224c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251766770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2251766770
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3375479501
Short name T778
Test name
Test status
Simulation time 125939427 ps
CPU time 5.56 seconds
Started Jul 28 05:18:31 PM PDT 24
Finished Jul 28 05:18:37 PM PDT 24
Peak memory 240432 kb
Host smart-ac2fff8f-8580-440c-8495-14b2e3b30262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3375479501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3375479501
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1756370415
Short name T356
Test name
Test status
Simulation time 13951918 ps
CPU time 1.52 seconds
Started Jul 28 05:18:41 PM PDT 24
Finished Jul 28 05:18:42 PM PDT 24
Peak memory 237436 kb
Host smart-8ab9343e-6fb3-4f31-b69f-06305f79ceca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1756370415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1756370415
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1230558652
Short name T771
Test name
Test status
Simulation time 740880938 ps
CPU time 46.39 seconds
Started Jul 28 05:18:33 PM PDT 24
Finished Jul 28 05:19:19 PM PDT 24
Peak memory 248616 kb
Host smart-5201546d-5726-47d9-b8d1-31903b708351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1230558652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1230558652
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4004563368
Short name T820
Test name
Test status
Simulation time 1916200875 ps
CPU time 156.84 seconds
Started Jul 28 05:18:19 PM PDT 24
Finished Jul 28 05:20:56 PM PDT 24
Peak memory 257104 kb
Host smart-15e38c8e-267b-4947-b262-7ff5ca40ace8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4004563368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.4004563368
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3034158104
Short name T140
Test name
Test status
Simulation time 25337810854 ps
CPU time 983.38 seconds
Started Jul 28 05:18:42 PM PDT 24
Finished Jul 28 05:35:05 PM PDT 24
Peak memory 265480 kb
Host smart-5922f1f4-b12d-4427-8308-72ae5c037ca3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034158104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3034158104
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2638329485
Short name T788
Test name
Test status
Simulation time 44114345 ps
CPU time 3.48 seconds
Started Jul 28 05:18:24 PM PDT 24
Finished Jul 28 05:18:28 PM PDT 24
Peak memory 248068 kb
Host smart-aab43ca1-c963-4e33-826b-21cd9fe88798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2638329485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2638329485
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2698274069
Short name T754
Test name
Test status
Simulation time 459718545 ps
CPU time 9.52 seconds
Started Jul 28 05:18:39 PM PDT 24
Finished Jul 28 05:18:48 PM PDT 24
Peak memory 237448 kb
Host smart-6d9c0205-9a51-46d3-961a-125c720a6982
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2698274069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2698274069
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1995204589
Short name T163
Test name
Test status
Simulation time 9960783 ps
CPU time 1.38 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:18:45 PM PDT 24
Peak memory 237480 kb
Host smart-6f0f135e-d826-465f-953e-e67769bb86f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1995204589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1995204589
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3938314803
Short name T741
Test name
Test status
Simulation time 266855164 ps
CPU time 19.77 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:18:35 PM PDT 24
Peak memory 245632 kb
Host smart-7f1dde08-c810-4d5a-bb99-03446cb2ff8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3938314803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3938314803
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2538868220
Short name T141
Test name
Test status
Simulation time 52464057284 ps
CPU time 403.81 seconds
Started Jul 28 05:18:33 PM PDT 24
Finished Jul 28 05:25:17 PM PDT 24
Peak memory 265360 kb
Host smart-7557ea6b-8590-4be2-8de6-9025f924907d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2538868220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2538868220
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.11937720
Short name T827
Test name
Test status
Simulation time 8614258543 ps
CPU time 542.67 seconds
Started Jul 28 05:18:40 PM PDT 24
Finished Jul 28 05:27:43 PM PDT 24
Peak memory 269792 kb
Host smart-d89fa529-4137-48fe-9297-c4b4f7ec4977
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11937720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.11937720
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2740791789
Short name T720
Test name
Test status
Simulation time 193902867 ps
CPU time 4.59 seconds
Started Jul 28 05:18:35 PM PDT 24
Finished Jul 28 05:18:40 PM PDT 24
Peak memory 250668 kb
Host smart-0e1f9d08-802c-4178-bfe2-ff1e48f68e02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2740791789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2740791789
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3077151907
Short name T360
Test name
Test status
Simulation time 64200343 ps
CPU time 4.76 seconds
Started Jul 28 05:18:28 PM PDT 24
Finished Jul 28 05:18:33 PM PDT 24
Peak memory 256484 kb
Host smart-e2c4d8f2-beca-44c0-8f35-f5a68a400254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077151907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3077151907
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3425725945
Short name T810
Test name
Test status
Simulation time 43165921 ps
CPU time 5.06 seconds
Started Jul 28 05:18:33 PM PDT 24
Finished Jul 28 05:18:38 PM PDT 24
Peak memory 240392 kb
Host smart-54e89f47-601a-469d-a920-9d2d6b06663d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3425725945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3425725945
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.363684431
Short name T744
Test name
Test status
Simulation time 9436016 ps
CPU time 1.56 seconds
Started Jul 28 05:18:31 PM PDT 24
Finished Jul 28 05:18:32 PM PDT 24
Peak memory 237484 kb
Host smart-42089c07-79db-4600-aec6-3d1b22648e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=363684431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.363684431
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2254592664
Short name T194
Test name
Test status
Simulation time 340039752 ps
CPU time 22.66 seconds
Started Jul 28 05:18:24 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 245684 kb
Host smart-8d6b9a0b-d989-4136-bc8b-5c9d5b8fa7d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2254592664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2254592664
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.292629376
Short name T816
Test name
Test status
Simulation time 230527467 ps
CPU time 8.59 seconds
Started Jul 28 05:18:32 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 248064 kb
Host smart-88e31d24-447a-4186-b4d8-5fb539eebf25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=292629376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.292629376
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1972293804
Short name T809
Test name
Test status
Simulation time 99128857 ps
CPU time 8.37 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:30 PM PDT 24
Peak memory 240408 kb
Host smart-80feb3b6-5d6e-4f32-ae25-e7d1d7650a07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972293804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1972293804
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1675599040
Short name T800
Test name
Test status
Simulation time 34064724 ps
CPU time 5.1 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:18:52 PM PDT 24
Peak memory 237496 kb
Host smart-72751ebc-6fa8-495b-8811-090274a509f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1675599040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1675599040
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.523100395
Short name T749
Test name
Test status
Simulation time 19333389 ps
CPU time 1.31 seconds
Started Jul 28 05:18:52 PM PDT 24
Finished Jul 28 05:18:54 PM PDT 24
Peak memory 237488 kb
Host smart-82239c3f-7a51-44cf-ac78-10e541e40c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=523100395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.523100395
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2411825648
Short name T745
Test name
Test status
Simulation time 1066461718 ps
CPU time 35.31 seconds
Started Jul 28 05:18:34 PM PDT 24
Finished Jul 28 05:19:09 PM PDT 24
Peak memory 244764 kb
Host smart-4f3d29a6-c5be-4ca9-8127-d6595d797c54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2411825648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2411825648
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.340475634
Short name T127
Test name
Test status
Simulation time 1607368466 ps
CPU time 101.04 seconds
Started Jul 28 05:18:28 PM PDT 24
Finished Jul 28 05:20:09 PM PDT 24
Peak memory 265288 kb
Host smart-6d30ff9a-3113-4e08-b96f-b83dd6758dd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=340475634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.340475634
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.510052337
Short name T137
Test name
Test status
Simulation time 8515485766 ps
CPU time 670.27 seconds
Started Jul 28 05:18:42 PM PDT 24
Finished Jul 28 05:29:53 PM PDT 24
Peak memory 265420 kb
Host smart-b488217d-9b87-4b13-8d8b-e309ad1461ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510052337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.510052337
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2586276137
Short name T812
Test name
Test status
Simulation time 1351561035 ps
CPU time 15.71 seconds
Started Jul 28 05:18:32 PM PDT 24
Finished Jul 28 05:18:48 PM PDT 24
Peak memory 255272 kb
Host smart-a3f69405-4441-464b-aab9-7481eac12732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2586276137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2586276137
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.221167224
Short name T773
Test name
Test status
Simulation time 934189202 ps
CPU time 7.42 seconds
Started Jul 28 05:18:44 PM PDT 24
Finished Jul 28 05:18:51 PM PDT 24
Peak memory 240816 kb
Host smart-fbb7ceea-c23b-4b8b-a7af-3df24ac9ccc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221167224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.221167224
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3122193540
Short name T753
Test name
Test status
Simulation time 22086957 ps
CPU time 3.58 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:18:52 PM PDT 24
Peak memory 237468 kb
Host smart-88758c28-a34f-4d7a-a588-544746a1c849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3122193540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3122193540
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3475649288
Short name T766
Test name
Test status
Simulation time 9525343 ps
CPU time 1.53 seconds
Started Jul 28 05:18:39 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 235540 kb
Host smart-b5465442-86db-4fb6-874b-150804eb949b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3475649288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3475649288
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1607449067
Short name T803
Test name
Test status
Simulation time 84889986 ps
CPU time 9.45 seconds
Started Jul 28 05:18:39 PM PDT 24
Finished Jul 28 05:18:49 PM PDT 24
Peak memory 244844 kb
Host smart-fd1764b4-7943-4476-aded-46a9f3cfc5d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1607449067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1607449067
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3361783875
Short name T143
Test name
Test status
Simulation time 12963934105 ps
CPU time 247.36 seconds
Started Jul 28 05:18:42 PM PDT 24
Finished Jul 28 05:22:49 PM PDT 24
Peak memory 265416 kb
Host smart-5eba093c-8073-4b3f-8814-2820a33a3f52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3361783875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3361783875
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1385544976
Short name T725
Test name
Test status
Simulation time 83064061 ps
CPU time 11.56 seconds
Started Jul 28 05:18:35 PM PDT 24
Finished Jul 28 05:18:46 PM PDT 24
Peak memory 248636 kb
Host smart-c3243fb3-8405-4c85-9d9a-07ebe38a1f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1385544976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1385544976
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3570169839
Short name T359
Test name
Test status
Simulation time 137262164 ps
CPU time 5.28 seconds
Started Jul 28 05:18:50 PM PDT 24
Finished Jul 28 05:18:55 PM PDT 24
Peak memory 252136 kb
Host smart-48457661-611c-4407-802c-5df12e94e912
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570169839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3570169839
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2575691198
Short name T757
Test name
Test status
Simulation time 103994286 ps
CPU time 3.46 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:18:57 PM PDT 24
Peak memory 240432 kb
Host smart-7ea7e0f4-f5b9-4bf2-935e-2c83a78a929c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2575691198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2575691198
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4026140708
Short name T750
Test name
Test status
Simulation time 18796391 ps
CPU time 1.46 seconds
Started Jul 28 05:18:39 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 236488 kb
Host smart-d3e5f1f2-685a-44c7-a9e6-04dfe1496f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4026140708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.4026140708
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1326366198
Short name T765
Test name
Test status
Simulation time 490919423 ps
CPU time 18.99 seconds
Started Jul 28 05:18:32 PM PDT 24
Finished Jul 28 05:18:51 PM PDT 24
Peak memory 248532 kb
Host smart-344f626b-e0c4-41ec-9849-952ed8584200
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1326366198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1326366198
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3513097873
Short name T157
Test name
Test status
Simulation time 6385300706 ps
CPU time 401.83 seconds
Started Jul 28 05:18:34 PM PDT 24
Finished Jul 28 05:25:16 PM PDT 24
Peak memory 265416 kb
Host smart-e1a2a3fd-090d-457a-a847-4c51aa60173b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3513097873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3513097873
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.140235725
Short name T149
Test name
Test status
Simulation time 55504802165 ps
CPU time 1048.86 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:36:12 PM PDT 24
Peak memory 265308 kb
Host smart-08362a89-0546-41c3-9417-313361264b53
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140235725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.140235725
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2568762472
Short name T777
Test name
Test status
Simulation time 242439370 ps
CPU time 5.38 seconds
Started Jul 28 05:18:41 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 252024 kb
Host smart-df3ed70f-6dac-4062-983a-0aaa50c64176
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2568762472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2568762472
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2934350840
Short name T179
Test name
Test status
Simulation time 70116423 ps
CPU time 5.82 seconds
Started Jul 28 05:18:26 PM PDT 24
Finished Jul 28 05:18:32 PM PDT 24
Peak memory 256956 kb
Host smart-38c182b2-866e-4e42-bb12-63da13f38a29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934350840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2934350840
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1476846
Short name T740
Test name
Test status
Simulation time 22576630 ps
CPU time 3.39 seconds
Started Jul 28 05:18:33 PM PDT 24
Finished Jul 28 05:18:37 PM PDT 24
Peak memory 236552 kb
Host smart-c58298e0-65ee-41a3-be69-09c53ac9f42a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1476846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1476846
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2546252028
Short name T824
Test name
Test status
Simulation time 11954469 ps
CPU time 1.35 seconds
Started Jul 28 05:18:42 PM PDT 24
Finished Jul 28 05:18:43 PM PDT 24
Peak memory 237408 kb
Host smart-dd9effff-d50b-4b9a-a766-805d2654f498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2546252028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2546252028
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1383354127
Short name T733
Test name
Test status
Simulation time 514109433 ps
CPU time 17.79 seconds
Started Jul 28 05:18:32 PM PDT 24
Finished Jul 28 05:18:49 PM PDT 24
Peak memory 244800 kb
Host smart-fe4b7baa-3107-4f62-b2be-97d3125b32ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1383354127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1383354127
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.666829342
Short name T152
Test name
Test status
Simulation time 3905371689 ps
CPU time 322.18 seconds
Started Jul 28 05:18:41 PM PDT 24
Finished Jul 28 05:24:03 PM PDT 24
Peak memory 265440 kb
Host smart-cb7da2ad-8dc5-4d70-9789-6af414e4555a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666829342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.666829342
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4021556632
Short name T811
Test name
Test status
Simulation time 318677381 ps
CPU time 6.59 seconds
Started Jul 28 05:18:31 PM PDT 24
Finished Jul 28 05:18:37 PM PDT 24
Peak memory 252428 kb
Host smart-fcf0ef23-e7cc-47b5-a73a-756c125b1517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4021556632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4021556632
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2099538222
Short name T184
Test name
Test status
Simulation time 2053760112 ps
CPU time 76.66 seconds
Started Jul 28 05:18:23 PM PDT 24
Finished Jul 28 05:19:40 PM PDT 24
Peak memory 237488 kb
Host smart-6dc3b953-4f1b-4f89-9891-8df03321e7aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2099538222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2099538222
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.9894948
Short name T770
Test name
Test status
Simulation time 848228679 ps
CPU time 115.76 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:20:44 PM PDT 24
Peak memory 237492 kb
Host smart-e6f801f8-d86d-4f65-afe1-9337973ed254
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=9894948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.9894948
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4182345010
Short name T187
Test name
Test status
Simulation time 195937245 ps
CPU time 4.9 seconds
Started Jul 28 05:18:19 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 248652 kb
Host smart-8a8a84ba-e5f4-4189-afb0-82026b2dfc96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4182345010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.4182345010
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1706342798
Short name T813
Test name
Test status
Simulation time 114914240 ps
CPU time 5.11 seconds
Started Jul 28 05:18:28 PM PDT 24
Finished Jul 28 05:18:34 PM PDT 24
Peak memory 248640 kb
Host smart-0f10bf23-245b-4004-a37d-3fa7a54d6f7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706342798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1706342798
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4190202049
Short name T357
Test name
Test status
Simulation time 826806063 ps
CPU time 9.25 seconds
Started Jul 28 05:18:31 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 237488 kb
Host smart-eab360d0-d8d5-4a86-af0c-c7c023e75691
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4190202049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4190202049
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1536178214
Short name T762
Test name
Test status
Simulation time 4481054993 ps
CPU time 22.47 seconds
Started Jul 28 05:18:14 PM PDT 24
Finished Jul 28 05:18:37 PM PDT 24
Peak memory 245792 kb
Host smart-b6f15829-169a-46ef-b814-e7d3b26befc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1536178214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1536178214
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.965315346
Short name T148
Test name
Test status
Simulation time 4448383758 ps
CPU time 159.37 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:20:56 PM PDT 24
Peak memory 268652 kb
Host smart-bf7dc105-fc0a-4e88-9c65-62a5474ee35f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=965315346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.965315346
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.789017048
Short name T825
Test name
Test status
Simulation time 16870618896 ps
CPU time 1191.4 seconds
Started Jul 28 05:18:18 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 265436 kb
Host smart-28a19472-2bcd-4d8e-a852-5a7dfa51ade3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789017048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.789017048
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.356623344
Short name T801
Test name
Test status
Simulation time 197148883 ps
CPU time 9.01 seconds
Started Jul 28 05:18:05 PM PDT 24
Finished Jul 28 05:18:14 PM PDT 24
Peak memory 253076 kb
Host smart-43cb1a5e-5505-4d68-83b4-fa54f21e239b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=356623344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.356623344
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2130040845
Short name T737
Test name
Test status
Simulation time 8904144 ps
CPU time 1.61 seconds
Started Jul 28 05:18:42 PM PDT 24
Finished Jul 28 05:18:44 PM PDT 24
Peak memory 236584 kb
Host smart-8fb6bba6-26a5-4980-945c-48b95238a625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2130040845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2130040845
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.822156050
Short name T764
Test name
Test status
Simulation time 6304514 ps
CPU time 1.35 seconds
Started Jul 28 05:18:38 PM PDT 24
Finished Jul 28 05:18:39 PM PDT 24
Peak memory 237544 kb
Host smart-6a4dc48a-4409-469b-b42f-add0e8127654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=822156050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.822156050
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.183439428
Short name T724
Test name
Test status
Simulation time 10600648 ps
CPU time 1.31 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:18:31 PM PDT 24
Peak memory 237496 kb
Host smart-3550d9f7-8250-47a5-a368-b898e9c8e872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=183439428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.183439428
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1716239241
Short name T795
Test name
Test status
Simulation time 11999556 ps
CPU time 1.66 seconds
Started Jul 28 05:18:33 PM PDT 24
Finished Jul 28 05:18:34 PM PDT 24
Peak memory 236564 kb
Host smart-852a4478-c1b8-42d0-a706-b2f4d0f97700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1716239241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1716239241
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2000492211
Short name T730
Test name
Test status
Simulation time 10472199 ps
CPU time 1.35 seconds
Started Jul 28 05:18:35 PM PDT 24
Finished Jul 28 05:18:36 PM PDT 24
Peak memory 237500 kb
Host smart-086d204e-4f66-4cb0-8e4b-425a2d105fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2000492211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2000492211
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3203277140
Short name T804
Test name
Test status
Simulation time 16669920 ps
CPU time 1.42 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:16 PM PDT 24
Peak memory 235552 kb
Host smart-5b18ead3-42a1-4fe7-a132-85b7c96247d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3203277140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3203277140
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1057141739
Short name T726
Test name
Test status
Simulation time 6826653 ps
CPU time 1.48 seconds
Started Jul 28 05:18:37 PM PDT 24
Finished Jul 28 05:18:39 PM PDT 24
Peak memory 237492 kb
Host smart-0b2b2a25-4474-49a1-9e83-ed0090b3a564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1057141739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1057141739
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.832809642
Short name T815
Test name
Test status
Simulation time 37387967 ps
CPU time 1.35 seconds
Started Jul 28 05:18:36 PM PDT 24
Finished Jul 28 05:18:37 PM PDT 24
Peak memory 237424 kb
Host smart-308080e3-4c82-4647-a10f-b6be4e1f5163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=832809642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.832809642
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3304021640
Short name T161
Test name
Test status
Simulation time 9061924 ps
CPU time 1.52 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:18:46 PM PDT 24
Peak memory 236584 kb
Host smart-a2404748-8a6e-4223-9216-a824d24f015a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3304021640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3304021640
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1175373577
Short name T782
Test name
Test status
Simulation time 8403730 ps
CPU time 1.42 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:18:48 PM PDT 24
Peak memory 235540 kb
Host smart-ccb2c573-ebdb-40d1-8ba5-546de0c8876e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1175373577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1175373577
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1635932267
Short name T785
Test name
Test status
Simulation time 30226712475 ps
CPU time 256.94 seconds
Started Jul 28 05:18:02 PM PDT 24
Finished Jul 28 05:22:19 PM PDT 24
Peak memory 240536 kb
Host smart-94554e98-9679-401b-8e35-68e9c02b1fb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1635932267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1635932267
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1013702231
Short name T358
Test name
Test status
Simulation time 16873237467 ps
CPU time 226.77 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:21:53 PM PDT 24
Peak memory 240548 kb
Host smart-d750b991-1b20-4115-b699-376a22a6e6c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1013702231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1013702231
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1368358762
Short name T793
Test name
Test status
Simulation time 249325770 ps
CPU time 5.77 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:18:23 PM PDT 24
Peak memory 240424 kb
Host smart-e5f77b0a-a4f9-4d24-a0f9-2378f8e4a01f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1368358762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1368358762
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1157437903
Short name T363
Test name
Test status
Simulation time 637305646 ps
CPU time 9.91 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:31 PM PDT 24
Peak memory 240468 kb
Host smart-2a36e1d8-92f5-4812-8d29-440b58dead55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157437903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1157437903
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3677261133
Short name T805
Test name
Test status
Simulation time 484838715 ps
CPU time 8.92 seconds
Started Jul 28 05:18:14 PM PDT 24
Finished Jul 28 05:18:23 PM PDT 24
Peak memory 237396 kb
Host smart-34f623fc-1cb9-4211-ac71-92420232ab46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3677261133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3677261133
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3782925594
Short name T751
Test name
Test status
Simulation time 8434155 ps
CPU time 1.5 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 237536 kb
Host smart-96f1d63c-c4bc-4528-9a39-05d4ac86e2c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3782925594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3782925594
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.559779976
Short name T794
Test name
Test status
Simulation time 524301169 ps
CPU time 19.73 seconds
Started Jul 28 05:18:26 PM PDT 24
Finished Jul 28 05:18:46 PM PDT 24
Peak memory 248556 kb
Host smart-c60ec42a-f64f-4831-ae1a-601fed2948f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=559779976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.559779976
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1440130283
Short name T126
Test name
Test status
Simulation time 3937713704 ps
CPU time 158.01 seconds
Started Jul 28 05:18:09 PM PDT 24
Finished Jul 28 05:20:47 PM PDT 24
Peak memory 265444 kb
Host smart-4304488f-30b7-46e7-853e-0c56c9a0d991
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1440130283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1440130283
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2542750537
Short name T738
Test name
Test status
Simulation time 261959914 ps
CPU time 8.43 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:30 PM PDT 24
Peak memory 253064 kb
Host smart-45ffe06e-8e63-4064-bae6-d76a30f1da94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2542750537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2542750537
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3904404088
Short name T735
Test name
Test status
Simulation time 6531110 ps
CPU time 1.47 seconds
Started Jul 28 05:18:41 PM PDT 24
Finished Jul 28 05:18:43 PM PDT 24
Peak memory 235512 kb
Host smart-48186602-5a58-436b-80d6-950560ccbdb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3904404088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3904404088
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2003061230
Short name T255
Test name
Test status
Simulation time 10818570 ps
CPU time 1.61 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:18:45 PM PDT 24
Peak memory 237460 kb
Host smart-a91cd227-5639-4481-b58b-1c7db95606c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2003061230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2003061230
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.690140584
Short name T807
Test name
Test status
Simulation time 16235427 ps
CPU time 1.33 seconds
Started Jul 28 05:18:36 PM PDT 24
Finished Jul 28 05:18:37 PM PDT 24
Peak memory 236608 kb
Host smart-4430bdf5-45cd-4109-af77-d8d5d6e4361b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=690140584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.690140584
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.475044454
Short name T798
Test name
Test status
Simulation time 17599237 ps
CPU time 1.31 seconds
Started Jul 28 05:18:39 PM PDT 24
Finished Jul 28 05:18:40 PM PDT 24
Peak memory 237512 kb
Host smart-77594484-8844-4718-b7de-4e516c7a5380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=475044454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.475044454
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1721069603
Short name T354
Test name
Test status
Simulation time 15125243 ps
CPU time 1.31 seconds
Started Jul 28 05:18:50 PM PDT 24
Finished Jul 28 05:18:52 PM PDT 24
Peak memory 236576 kb
Host smart-6d494141-2103-4428-aec8-44cc74d874e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1721069603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1721069603
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2698754201
Short name T829
Test name
Test status
Simulation time 6501597 ps
CPU time 1.4 seconds
Started Jul 28 05:18:49 PM PDT 24
Finished Jul 28 05:18:50 PM PDT 24
Peak memory 235520 kb
Host smart-ce6f0546-06da-4130-a85e-74435f94289f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2698754201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2698754201
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.609055836
Short name T729
Test name
Test status
Simulation time 9675478 ps
CPU time 1.6 seconds
Started Jul 28 05:18:52 PM PDT 24
Finished Jul 28 05:18:53 PM PDT 24
Peak memory 236576 kb
Host smart-43fa66ba-0248-4799-becf-d9cc70b4cb23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=609055836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.609055836
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4023763560
Short name T162
Test name
Test status
Simulation time 8761409 ps
CPU time 1.46 seconds
Started Jul 28 05:18:41 PM PDT 24
Finished Jul 28 05:18:43 PM PDT 24
Peak memory 236604 kb
Host smart-e5070e2c-c194-4850-835c-58783691fa42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4023763560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4023763560
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1429666610
Short name T784
Test name
Test status
Simulation time 8833474 ps
CPU time 1.73 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:18:50 PM PDT 24
Peak memory 236588 kb
Host smart-0546ed99-04dd-454b-9520-dec4c3bea25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1429666610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1429666610
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3510389439
Short name T364
Test name
Test status
Simulation time 1119345147 ps
CPU time 157.01 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:20:46 PM PDT 24
Peak memory 240440 kb
Host smart-67ea6e91-45a7-4c2a-be8d-16138a24b157
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3510389439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3510389439
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.385542311
Short name T760
Test name
Test status
Simulation time 5719784549 ps
CPU time 405.46 seconds
Started Jul 28 05:18:26 PM PDT 24
Finished Jul 28 05:25:12 PM PDT 24
Peak memory 237568 kb
Host smart-9c550b46-750b-4554-8586-de973d60d4d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=385542311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.385542311
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2915360978
Short name T188
Test name
Test status
Simulation time 76456019 ps
CPU time 3.34 seconds
Started Jul 28 05:18:24 PM PDT 24
Finished Jul 28 05:18:28 PM PDT 24
Peak memory 248544 kb
Host smart-ea1c4c50-2019-41c2-b431-d64c40cce362
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2915360978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2915360978
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1623775076
Short name T181
Test name
Test status
Simulation time 139952252 ps
CPU time 10.23 seconds
Started Jul 28 05:18:16 PM PDT 24
Finished Jul 28 05:18:26 PM PDT 24
Peak memory 251900 kb
Host smart-6fff43c9-aae6-4a8d-a743-0d77a1d0f402
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623775076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1623775076
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1737741154
Short name T191
Test name
Test status
Simulation time 193287649 ps
CPU time 4.86 seconds
Started Jul 28 05:18:19 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 237484 kb
Host smart-92d54a89-fa57-4a05-9e46-06947bbd3f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1737741154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1737741154
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3856996854
Short name T739
Test name
Test status
Simulation time 17031266 ps
CPU time 1.67 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:18:17 PM PDT 24
Peak memory 237456 kb
Host smart-75c4af3e-1d87-4d90-9a92-12f51d1a3bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3856996854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3856996854
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1613354990
Short name T189
Test name
Test status
Simulation time 845932965 ps
CPU time 11.95 seconds
Started Jul 28 05:18:26 PM PDT 24
Finished Jul 28 05:18:38 PM PDT 24
Peak memory 248636 kb
Host smart-8cf5c36c-1ad6-4f60-8734-a7dd77510fb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1613354990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1613354990
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3832108132
Short name T154
Test name
Test status
Simulation time 1135296640 ps
CPU time 104.11 seconds
Started Jul 28 05:18:07 PM PDT 24
Finished Jul 28 05:19:51 PM PDT 24
Peak memory 265304 kb
Host smart-9fa3ddc4-84b6-45ef-b5ca-19742c6129f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3832108132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3832108132
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3774273125
Short name T254
Test name
Test status
Simulation time 259995714 ps
CPU time 8.96 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:30 PM PDT 24
Peak memory 248704 kb
Host smart-04ecf2f6-8c45-4ff6-8e5f-919054151e94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3774273125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3774273125
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2412375211
Short name T734
Test name
Test status
Simulation time 17038332 ps
CPU time 1.41 seconds
Started Jul 28 05:18:34 PM PDT 24
Finished Jul 28 05:18:36 PM PDT 24
Peak memory 235580 kb
Host smart-26f3b685-0d6e-4d4b-99e5-d1a5ffe4c61f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2412375211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2412375211
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2663557140
Short name T758
Test name
Test status
Simulation time 10854738 ps
CPU time 1.32 seconds
Started Jul 28 05:18:37 PM PDT 24
Finished Jul 28 05:18:39 PM PDT 24
Peak memory 236500 kb
Host smart-3671461a-666a-46b9-986e-930593119533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2663557140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2663557140
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1231116218
Short name T351
Test name
Test status
Simulation time 10043859 ps
CPU time 1.64 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:18:44 PM PDT 24
Peak memory 237496 kb
Host smart-514bbef0-8e56-4911-9105-27cbcbf0c9e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1231116218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1231116218
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.406877985
Short name T817
Test name
Test status
Simulation time 9918434 ps
CPU time 1.41 seconds
Started Jul 28 05:18:36 PM PDT 24
Finished Jul 28 05:18:38 PM PDT 24
Peak memory 235488 kb
Host smart-d8360110-f684-4085-b0e8-b5dd14ca4fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=406877985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.406877985
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3035596959
Short name T791
Test name
Test status
Simulation time 21064919 ps
CPU time 1.49 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 237524 kb
Host smart-4ae7c0b5-274d-436f-8e0a-1bffdb3853a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3035596959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3035596959
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1197367811
Short name T723
Test name
Test status
Simulation time 6667148 ps
CPU time 1.52 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:18:45 PM PDT 24
Peak memory 237460 kb
Host smart-db3dc808-55ba-475b-9939-1fc3151c28f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1197367811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1197367811
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2149148312
Short name T755
Test name
Test status
Simulation time 9976483 ps
CPU time 1.62 seconds
Started Jul 28 05:18:56 PM PDT 24
Finished Jul 28 05:18:57 PM PDT 24
Peak memory 237456 kb
Host smart-3713dab1-75ff-4ce5-a9ad-8ab2f311d986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2149148312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2149148312
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.267171758
Short name T722
Test name
Test status
Simulation time 6307074 ps
CPU time 1.43 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:18:44 PM PDT 24
Peak memory 237476 kb
Host smart-7edfc47e-08c9-4848-8106-7d0a987372f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=267171758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.267171758
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1400281143
Short name T828
Test name
Test status
Simulation time 8455209 ps
CPU time 1.49 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:18:49 PM PDT 24
Peak memory 236544 kb
Host smart-b3626a56-2e3c-4f96-9270-82d3eccbce52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1400281143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1400281143
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3729837569
Short name T808
Test name
Test status
Simulation time 7415605 ps
CPU time 1.41 seconds
Started Jul 28 05:18:50 PM PDT 24
Finished Jul 28 05:18:52 PM PDT 24
Peak memory 236640 kb
Host smart-bb0f4352-da8f-41ad-8ba7-d971fa05cea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3729837569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3729837569
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.116689089
Short name T763
Test name
Test status
Simulation time 65917459 ps
CPU time 9.9 seconds
Started Jul 28 05:18:11 PM PDT 24
Finished Jul 28 05:18:21 PM PDT 24
Peak memory 256868 kb
Host smart-5fc34d54-3972-4d90-a83e-398e6acef5af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116689089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.116689089
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1573940509
Short name T779
Test name
Test status
Simulation time 21358893 ps
CPU time 3.32 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 239368 kb
Host smart-a24b3622-64b2-47cb-a58f-4413256a5998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1573940509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1573940509
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1386276394
Short name T353
Test name
Test status
Simulation time 6538808 ps
CPU time 1.45 seconds
Started Jul 28 05:18:26 PM PDT 24
Finished Jul 28 05:18:28 PM PDT 24
Peak memory 237488 kb
Host smart-326b4d3c-0427-4a81-9335-af73f8cf837e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1386276394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1386276394
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.40664793
Short name T731
Test name
Test status
Simulation time 261404791 ps
CPU time 18.81 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:27 PM PDT 24
Peak memory 245704 kb
Host smart-70c84c34-ba4f-4fbf-81c8-36b1a2bd2e40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=40664793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outst
anding.40664793
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2246351119
Short name T819
Test name
Test status
Simulation time 32302791777 ps
CPU time 537.33 seconds
Started Jul 28 05:18:28 PM PDT 24
Finished Jul 28 05:27:26 PM PDT 24
Peak memory 265416 kb
Host smart-1c7b55af-07b4-4d7b-9307-4bbf086ec38d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246351119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2246351119
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.638012212
Short name T780
Test name
Test status
Simulation time 155423556 ps
CPU time 10.73 seconds
Started Jul 28 05:18:35 PM PDT 24
Finished Jul 28 05:18:46 PM PDT 24
Peak memory 248600 kb
Host smart-22056215-60a9-4108-9fc0-b49c32a3a6af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=638012212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.638012212
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2369764623
Short name T361
Test name
Test status
Simulation time 70815104 ps
CPU time 6.21 seconds
Started Jul 28 05:18:19 PM PDT 24
Finished Jul 28 05:18:25 PM PDT 24
Peak memory 239608 kb
Host smart-0bf4665d-40f9-45c5-9ffc-e223c01c4a44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369764623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2369764623
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2415488605
Short name T797
Test name
Test status
Simulation time 35724291 ps
CPU time 5.79 seconds
Started Jul 28 05:18:34 PM PDT 24
Finished Jul 28 05:18:40 PM PDT 24
Peak memory 237464 kb
Host smart-e2c5b4fc-9dce-4ba5-bfa4-370ed4413ac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2415488605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2415488605
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.988628553
Short name T786
Test name
Test status
Simulation time 8011212 ps
CPU time 1.33 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 236608 kb
Host smart-b098fbb2-8cb7-4603-9158-cbc8422db1eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=988628553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.988628553
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2901329547
Short name T736
Test name
Test status
Simulation time 294055123 ps
CPU time 19.16 seconds
Started Jul 28 05:18:27 PM PDT 24
Finished Jul 28 05:18:46 PM PDT 24
Peak memory 244720 kb
Host smart-3548bb04-92c9-462c-912f-248071b34994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2901329547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2901329547
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1981160277
Short name T138
Test name
Test status
Simulation time 891809494 ps
CPU time 115.32 seconds
Started Jul 28 05:18:27 PM PDT 24
Finished Jul 28 05:20:23 PM PDT 24
Peak memory 265500 kb
Host smart-61face8c-faaf-4fd7-8056-20519778ef94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1981160277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1981160277
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4180853854
Short name T721
Test name
Test status
Simulation time 104643728 ps
CPU time 7.3 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:28 PM PDT 24
Peak memory 248388 kb
Host smart-69085dc8-6ccf-4626-930f-2b67c69c4fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4180853854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.4180853854
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1603232348
Short name T802
Test name
Test status
Simulation time 53545153 ps
CPU time 8.2 seconds
Started Jul 28 05:18:33 PM PDT 24
Finished Jul 28 05:18:42 PM PDT 24
Peak memory 251240 kb
Host smart-b48c2040-3e88-4f7e-8867-83f41a9e3bbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603232348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1603232348
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2039514988
Short name T826
Test name
Test status
Simulation time 180048350 ps
CPU time 7.77 seconds
Started Jul 28 05:18:27 PM PDT 24
Finished Jul 28 05:18:35 PM PDT 24
Peak memory 240380 kb
Host smart-aa58edc6-53cf-4fb1-83fd-4b48c6f0ab52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2039514988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2039514988
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1418334819
Short name T761
Test name
Test status
Simulation time 7330321 ps
CPU time 1.46 seconds
Started Jul 28 05:18:33 PM PDT 24
Finished Jul 28 05:18:35 PM PDT 24
Peak memory 237476 kb
Host smart-6643a015-7307-446e-8903-9fdb912bfab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1418334819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1418334819
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.472243014
Short name T190
Test name
Test status
Simulation time 1073735098 ps
CPU time 37.27 seconds
Started Jul 28 05:18:09 PM PDT 24
Finished Jul 28 05:18:46 PM PDT 24
Peak memory 248564 kb
Host smart-5e8a2891-e971-4b4e-8be5-68c8fe5d3171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=472243014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.472243014
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1557369718
Short name T147
Test name
Test status
Simulation time 30323798642 ps
CPU time 382.8 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:24:52 PM PDT 24
Peak memory 265368 kb
Host smart-c9f6bff0-ac1b-412c-8dd1-c81b2fd6870a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1557369718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1557369718
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.537098483
Short name T787
Test name
Test status
Simulation time 468784791 ps
CPU time 8.8 seconds
Started Jul 28 05:18:30 PM PDT 24
Finished Jul 28 05:18:39 PM PDT 24
Peak memory 251680 kb
Host smart-199971a3-46e4-4d05-9029-3a43934f0b05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=537098483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.537098483
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3010820330
Short name T775
Test name
Test status
Simulation time 220597384 ps
CPU time 7.81 seconds
Started Jul 28 05:18:12 PM PDT 24
Finished Jul 28 05:18:20 PM PDT 24
Peak memory 239468 kb
Host smart-de80c9f5-5bfa-4868-be46-cee0a538b868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010820330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3010820330
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.907838694
Short name T776
Test name
Test status
Simulation time 183015236 ps
CPU time 4.35 seconds
Started Jul 28 05:18:33 PM PDT 24
Finished Jul 28 05:18:38 PM PDT 24
Peak memory 236600 kb
Host smart-24930e1a-c360-4dc8-b06d-8194fab44a46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=907838694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.907838694
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3214700859
Short name T756
Test name
Test status
Simulation time 31058454 ps
CPU time 1.4 seconds
Started Jul 28 05:18:24 PM PDT 24
Finished Jul 28 05:18:25 PM PDT 24
Peak memory 237468 kb
Host smart-555d9ea6-bdf3-470a-bf8e-f9146bc2b368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3214700859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3214700859
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.487893742
Short name T728
Test name
Test status
Simulation time 93603581 ps
CPU time 12.01 seconds
Started Jul 28 05:18:35 PM PDT 24
Finished Jul 28 05:18:47 PM PDT 24
Peak memory 248572 kb
Host smart-5c343cc6-e2c4-46db-b10c-347b2a6e339d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=487893742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.487893742
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.145946551
Short name T129
Test name
Test status
Simulation time 5280242486 ps
CPU time 181.94 seconds
Started Jul 28 05:18:36 PM PDT 24
Finished Jul 28 05:21:38 PM PDT 24
Peak memory 265424 kb
Host smart-d7672782-7a58-4cf7-a312-c7c7965f0651
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=145946551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.145946551
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.799234239
Short name T151
Test name
Test status
Simulation time 4746582841 ps
CPU time 318.57 seconds
Started Jul 28 05:18:20 PM PDT 24
Finished Jul 28 05:23:39 PM PDT 24
Peak memory 269552 kb
Host smart-8f6e8373-4fc3-4c22-be24-f3ba12a5b4b6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799234239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.799234239
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3440287057
Short name T742
Test name
Test status
Simulation time 192642421 ps
CPU time 11.91 seconds
Started Jul 28 05:18:36 PM PDT 24
Finished Jul 28 05:18:48 PM PDT 24
Peak memory 248560 kb
Host smart-242fe1fb-66c6-4cb2-bdd3-58b504bba466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3440287057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3440287057
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1258528644
Short name T747
Test name
Test status
Simulation time 315591495 ps
CPU time 6.89 seconds
Started Jul 28 05:18:34 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 240688 kb
Host smart-d2165e0e-e1c5-47f5-8c96-781cfbabada4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258528644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1258528644
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.151660841
Short name T774
Test name
Test status
Simulation time 103974932 ps
CPU time 5.16 seconds
Started Jul 28 05:18:38 PM PDT 24
Finished Jul 28 05:18:43 PM PDT 24
Peak memory 240332 kb
Host smart-5ffa5f02-12e3-44f1-85f9-8fabe896730b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=151660841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.151660841
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1024682748
Short name T823
Test name
Test status
Simulation time 10271108 ps
CPU time 1.56 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:18:30 PM PDT 24
Peak memory 237444 kb
Host smart-37416316-4c9a-4e8f-be3f-5df01d7619c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1024682748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1024682748
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.836807349
Short name T772
Test name
Test status
Simulation time 1013534094 ps
CPU time 20.23 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 245672 kb
Host smart-367ee2ee-7a5c-474f-9d29-37f7ed9acbc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=836807349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.836807349
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2076711325
Short name T133
Test name
Test status
Simulation time 11403101103 ps
CPU time 369.83 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:24:27 PM PDT 24
Peak memory 271772 kb
Host smart-de51a43b-de35-4d4e-818d-e628592dcf14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2076711325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2076711325
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.520898364
Short name T156
Test name
Test status
Simulation time 8398380747 ps
CPU time 669.52 seconds
Started Jul 28 05:18:20 PM PDT 24
Finished Jul 28 05:29:30 PM PDT 24
Peak memory 265588 kb
Host smart-29e21df3-5b18-4d61-88fe-03214d0980b7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520898364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.520898364
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3572648431
Short name T719
Test name
Test status
Simulation time 650677707 ps
CPU time 11.83 seconds
Started Jul 28 05:18:28 PM PDT 24
Finished Jul 28 05:18:40 PM PDT 24
Peak memory 248404 kb
Host smart-e479e873-45d6-4062-8e4e-076efc6f5714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3572648431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3572648431
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.159953420
Short name T94
Test name
Test status
Simulation time 12904070650 ps
CPU time 1184.26 seconds
Started Jul 28 05:18:36 PM PDT 24
Finished Jul 28 05:38:20 PM PDT 24
Peak memory 281288 kb
Host smart-7d536a2d-5a6d-4638-a4c4-d60b6f1263cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159953420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.159953420
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.173688287
Short name T381
Test name
Test status
Simulation time 3277012335 ps
CPU time 30.68 seconds
Started Jul 28 05:18:47 PM PDT 24
Finished Jul 28 05:19:18 PM PDT 24
Peak memory 248896 kb
Host smart-b82be182-d336-4d5c-9bef-02afcd757b29
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=173688287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.173688287
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.4271432951
Short name T532
Test name
Test status
Simulation time 2509905143 ps
CPU time 160.39 seconds
Started Jul 28 05:18:50 PM PDT 24
Finished Jul 28 05:21:31 PM PDT 24
Peak memory 257060 kb
Host smart-5cdbda60-3a50-42f3-a288-4683627c6fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42714
32951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4271432951
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2939148786
Short name T516
Test name
Test status
Simulation time 1361789394 ps
CPU time 45.68 seconds
Started Jul 28 05:18:49 PM PDT 24
Finished Jul 28 05:19:40 PM PDT 24
Peak memory 248380 kb
Host smart-772915ec-543b-41f2-9713-5d5c36513daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29391
48786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2939148786
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1305785922
Short name T409
Test name
Test status
Simulation time 58508845415 ps
CPU time 1425.76 seconds
Started Jul 28 05:18:42 PM PDT 24
Finished Jul 28 05:42:28 PM PDT 24
Peak memory 288508 kb
Host smart-9efa4fb7-d438-4a5a-93d8-f2080b1d851e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305785922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1305785922
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1477736236
Short name T534
Test name
Test status
Simulation time 428789461 ps
CPU time 14.31 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:18:59 PM PDT 24
Peak memory 248808 kb
Host smart-24b8145e-7e7d-45f1-99bf-2f8254428b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14777
36236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1477736236
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4292681595
Short name T616
Test name
Test status
Simulation time 3479109571 ps
CPU time 19.98 seconds
Started Jul 28 05:19:09 PM PDT 24
Finished Jul 28 05:19:29 PM PDT 24
Peak memory 248556 kb
Host smart-b11c5e55-8fbc-4079-819e-6662725667e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42926
81595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4292681595
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2724381474
Short name T432
Test name
Test status
Simulation time 349111224 ps
CPU time 7.44 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:18:52 PM PDT 24
Peak memory 252636 kb
Host smart-020f8dde-8dd9-4dd7-a707-b3966fc7cc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
81474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2724381474
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2871122795
Short name T404
Test name
Test status
Simulation time 335390785 ps
CPU time 20.97 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:19:14 PM PDT 24
Peak memory 256840 kb
Host smart-79605da3-bcf1-4786-b249-6dfca2e8c7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28711
22795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2871122795
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2531679510
Short name T704
Test name
Test status
Simulation time 11535749205 ps
CPU time 1307.03 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:40:58 PM PDT 24
Peak memory 281600 kb
Host smart-30e1dcea-ee76-4735-b6fa-a916847e945c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531679510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2531679510
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1831415852
Short name T246
Test name
Test status
Simulation time 117935376904 ps
CPU time 1099.69 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:37:16 PM PDT 24
Peak memory 281840 kb
Host smart-4529ee11-3d49-470b-84d7-d11e95778ba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831415852 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1831415852
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.4282163118
Short name T411
Test name
Test status
Simulation time 146176467 ps
CPU time 8.44 seconds
Started Jul 28 05:18:49 PM PDT 24
Finished Jul 28 05:18:58 PM PDT 24
Peak memory 248764 kb
Host smart-e53b31d7-bee7-4fa5-b30e-092f8d48fc3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4282163118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.4282163118
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3124675919
Short name T530
Test name
Test status
Simulation time 29349697258 ps
CPU time 144.18 seconds
Started Jul 28 05:18:41 PM PDT 24
Finished Jul 28 05:21:05 PM PDT 24
Peak memory 256336 kb
Host smart-a6bfa1f9-114a-4067-8bc8-f724bb94e481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31246
75919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3124675919
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3272521819
Short name T493
Test name
Test status
Simulation time 302168458 ps
CPU time 18.24 seconds
Started Jul 28 05:18:39 PM PDT 24
Finished Jul 28 05:18:58 PM PDT 24
Peak memory 248764 kb
Host smart-7e063f85-ba9d-46da-8ad0-3daf2d51c572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32725
21819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3272521819
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1821582613
Short name T543
Test name
Test status
Simulation time 68236906549 ps
CPU time 2092.87 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:53:37 PM PDT 24
Peak memory 282980 kb
Host smart-28672f4a-864e-4874-823d-876fa8b73327
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821582613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1821582613
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.214552436
Short name T61
Test name
Test status
Simulation time 28551665936 ps
CPU time 309.3 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:23:54 PM PDT 24
Peak memory 248040 kb
Host smart-de7fb7ff-6c0a-40f6-b218-a57726370a12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214552436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.214552436
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1067880700
Short name T614
Test name
Test status
Simulation time 1617133442 ps
CPU time 24.16 seconds
Started Jul 28 05:18:51 PM PDT 24
Finished Jul 28 05:19:15 PM PDT 24
Peak memory 256248 kb
Host smart-2fd82513-747c-4f18-833f-fdd3a49ad83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10678
80700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1067880700
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.514937370
Short name T520
Test name
Test status
Simulation time 175482267 ps
CPU time 3.75 seconds
Started Jul 28 05:18:40 PM PDT 24
Finished Jul 28 05:18:44 PM PDT 24
Peak memory 240124 kb
Host smart-fa68244c-5f79-4b8b-888a-60e16acda96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51493
7370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.514937370
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4171607211
Short name T29
Test name
Test status
Simulation time 1317318582 ps
CPU time 16.22 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:19:10 PM PDT 24
Peak memory 271180 kb
Host smart-da78334f-bf08-4600-9f9c-66155c4e1a36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4171607211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4171607211
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.180582007
Short name T497
Test name
Test status
Simulation time 128343497 ps
CPU time 16.19 seconds
Started Jul 28 05:18:44 PM PDT 24
Finished Jul 28 05:19:00 PM PDT 24
Peak memory 248332 kb
Host smart-7e209aa4-e921-437d-9fd1-9a5d52f6efaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18058
2007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.180582007
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.4042213818
Short name T450
Test name
Test status
Simulation time 2709718956 ps
CPU time 29.87 seconds
Started Jul 28 05:18:52 PM PDT 24
Finished Jul 28 05:19:22 PM PDT 24
Peak memory 256964 kb
Host smart-b043f070-ceeb-458a-9a3f-bff52b5d2f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40422
13818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4042213818
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2225220763
Short name T474
Test name
Test status
Simulation time 9294836662 ps
CPU time 202.96 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:22:21 PM PDT 24
Peak memory 257104 kb
Host smart-9b1a2c42-fd40-45ae-a6eb-3ce98dfa10b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225220763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2225220763
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.750588503
Short name T216
Test name
Test status
Simulation time 145249219 ps
CPU time 2.22 seconds
Started Jul 28 05:19:16 PM PDT 24
Finished Jul 28 05:19:19 PM PDT 24
Peak memory 249140 kb
Host smart-bf04ff98-2de1-4161-a3f7-e7c0b0d4cc5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=750588503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.750588503
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1056241827
Short name T579
Test name
Test status
Simulation time 51651667536 ps
CPU time 1748.82 seconds
Started Jul 28 05:18:58 PM PDT 24
Finished Jul 28 05:48:08 PM PDT 24
Peak memory 281580 kb
Host smart-dbdae8cc-4289-46ee-ba00-6a1d4384eeda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056241827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1056241827
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.674013774
Short name T611
Test name
Test status
Simulation time 799871070 ps
CPU time 19.15 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:19:13 PM PDT 24
Peak memory 248804 kb
Host smart-8ee706e2-0f49-4ece-acfd-adf3f0cd51db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=674013774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.674013774
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4048166910
Short name T684
Test name
Test status
Simulation time 21244443219 ps
CPU time 326.42 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:24:41 PM PDT 24
Peak memory 256300 kb
Host smart-f2d240b9-c248-4965-adcb-eea155645e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40481
66910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4048166910
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2702558258
Short name T624
Test name
Test status
Simulation time 870568129 ps
CPU time 53.59 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:20:15 PM PDT 24
Peak memory 248380 kb
Host smart-1279b087-a5ac-4cb0-957a-7287fbe343cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27025
58258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2702558258
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1351389133
Short name T305
Test name
Test status
Simulation time 9848858395 ps
CPU time 827.57 seconds
Started Jul 28 05:18:56 PM PDT 24
Finished Jul 28 05:32:44 PM PDT 24
Peak memory 273340 kb
Host smart-5e30d321-627e-4460-bd7a-5eef76a1abb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351389133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1351389133
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1564292032
Short name T511
Test name
Test status
Simulation time 128156389753 ps
CPU time 1889.81 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:50:23 PM PDT 24
Peak memory 272908 kb
Host smart-1ed84294-eb9c-497f-970d-ab672c3f4bb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564292032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1564292032
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.601920450
Short name T310
Test name
Test status
Simulation time 4459054239 ps
CPU time 193.47 seconds
Started Jul 28 05:19:10 PM PDT 24
Finished Jul 28 05:22:24 PM PDT 24
Peak memory 248836 kb
Host smart-2c66696e-ae16-4b63-98db-c88614d2d665
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601920450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.601920450
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1858750496
Short name T545
Test name
Test status
Simulation time 1056266405 ps
CPU time 19.92 seconds
Started Jul 28 05:19:03 PM PDT 24
Finished Jul 28 05:19:23 PM PDT 24
Peak memory 248748 kb
Host smart-792ef1fb-ee1d-42d2-be0a-e24ea0b30057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18587
50496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1858750496
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3639710712
Short name T112
Test name
Test status
Simulation time 1218495599 ps
CPU time 39.23 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:19:43 PM PDT 24
Peak memory 248512 kb
Host smart-063a58bb-a91b-42ca-828a-42f6696ba4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36397
10712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3639710712
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1456406212
Short name T260
Test name
Test status
Simulation time 64050290 ps
CPU time 11.05 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:19:22 PM PDT 24
Peak memory 248136 kb
Host smart-4b3444e6-752e-4239-a7ab-3601384d0c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14564
06212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1456406212
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2170702176
Short name T64
Test name
Test status
Simulation time 729710444 ps
CPU time 22.18 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:19:33 PM PDT 24
Peak memory 248756 kb
Host smart-52965f49-f56e-406b-bcfa-b0b225850f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21707
02176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2170702176
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2468433330
Short name T645
Test name
Test status
Simulation time 5709233880 ps
CPU time 318.91 seconds
Started Jul 28 05:18:51 PM PDT 24
Finished Jul 28 05:24:10 PM PDT 24
Peak memory 252580 kb
Host smart-70b94608-1383-4e0a-bfe0-f95772d33f99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468433330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2468433330
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1895313701
Short name T220
Test name
Test status
Simulation time 57898848 ps
CPU time 2.66 seconds
Started Jul 28 05:19:00 PM PDT 24
Finished Jul 28 05:19:03 PM PDT 24
Peak memory 249036 kb
Host smart-d8f99104-0558-49a4-90a6-9a9cd108ca92
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1895313701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1895313701
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.4057293763
Short name T418
Test name
Test status
Simulation time 48895143244 ps
CPU time 3143.48 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 06:11:28 PM PDT 24
Peak memory 288996 kb
Host smart-a12c88a5-6f9a-4eea-b8a4-7dcb63f12bcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057293763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.4057293763
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1790749936
Short name T32
Test name
Test status
Simulation time 248561517 ps
CPU time 8.13 seconds
Started Jul 28 05:19:01 PM PDT 24
Finished Jul 28 05:19:10 PM PDT 24
Peak memory 248712 kb
Host smart-98b796da-a6f7-493c-a2c9-3fb66bdebf30
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1790749936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1790749936
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2030190071
Short name T615
Test name
Test status
Simulation time 6499258090 ps
CPU time 169.09 seconds
Started Jul 28 05:18:58 PM PDT 24
Finished Jul 28 05:21:47 PM PDT 24
Peak memory 256504 kb
Host smart-0760bfce-c998-4a0f-a7a4-d2ffab6fe780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20301
90071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2030190071
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.4283393966
Short name T436
Test name
Test status
Simulation time 1274150006 ps
CPU time 14.51 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:19:09 PM PDT 24
Peak memory 248352 kb
Host smart-169adcaa-46de-44e9-a217-ccf2f99e9275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42833
93966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4283393966
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1803460621
Short name T343
Test name
Test status
Simulation time 167776944388 ps
CPU time 2549.01 seconds
Started Jul 28 05:19:07 PM PDT 24
Finished Jul 28 06:01:37 PM PDT 24
Peak memory 283752 kb
Host smart-81a9cf3e-34df-415c-becf-8a2af11b2e12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803460621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1803460621
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.902576610
Short name T507
Test name
Test status
Simulation time 209469258512 ps
CPU time 3298.44 seconds
Started Jul 28 05:19:06 PM PDT 24
Finished Jul 28 06:14:05 PM PDT 24
Peak memory 289744 kb
Host smart-093a65f5-1394-411a-b99e-084d0d25311f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902576610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.902576610
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3417922481
Short name T315
Test name
Test status
Simulation time 39838363513 ps
CPU time 500.71 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:27:38 PM PDT 24
Peak memory 248928 kb
Host smart-43e0fdb4-8c4e-499a-957f-6d5074fde4f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417922481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3417922481
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2799681138
Short name T383
Test name
Test status
Simulation time 241496180 ps
CPU time 21.2 seconds
Started Jul 28 05:18:52 PM PDT 24
Finished Jul 28 05:19:13 PM PDT 24
Peak memory 256076 kb
Host smart-5a61d427-194f-4219-bb51-2bdd7b8bbd29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27996
81138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2799681138
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2951560942
Short name T107
Test name
Test status
Simulation time 295961456 ps
CPU time 34.39 seconds
Started Jul 28 05:19:10 PM PDT 24
Finished Jul 28 05:19:44 PM PDT 24
Peak memory 256952 kb
Host smart-40f0f31c-96ab-4e7f-bb9b-914456c6da5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29515
60942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2951560942
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3990477075
Short name T626
Test name
Test status
Simulation time 1048872331 ps
CPU time 19.96 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:19:14 PM PDT 24
Peak memory 249140 kb
Host smart-94becae6-f809-480f-ae9d-4617b81eabbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39904
77075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3990477075
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.883197497
Short name T39
Test name
Test status
Simulation time 1008582116 ps
CPU time 19.02 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:19:23 PM PDT 24
Peak memory 256912 kb
Host smart-2757e14f-c680-4b6e-b66c-89b07831f751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88319
7497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.883197497
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2141950954
Short name T31
Test name
Test status
Simulation time 19431163691 ps
CPU time 1297.02 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:40:33 PM PDT 24
Peak memory 283884 kb
Host smart-a733136d-a00e-4c66-a37d-1525685ac396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141950954 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2141950954
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.652618896
Short name T587
Test name
Test status
Simulation time 442107746292 ps
CPU time 1618.22 seconds
Started Jul 28 05:19:20 PM PDT 24
Finished Jul 28 05:46:19 PM PDT 24
Peak memory 272988 kb
Host smart-5d8ca251-fde7-4c8e-b891-b5dc68a4f9b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652618896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.652618896
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3473587680
Short name T454
Test name
Test status
Simulation time 140252821 ps
CPU time 9.26 seconds
Started Jul 28 05:18:56 PM PDT 24
Finished Jul 28 05:19:05 PM PDT 24
Peak memory 248712 kb
Host smart-65cc59d7-6d0f-47af-99b5-8c82519d291d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3473587680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3473587680
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2038614932
Short name T618
Test name
Test status
Simulation time 3787962287 ps
CPU time 138.15 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:21:32 PM PDT 24
Peak memory 256980 kb
Host smart-de0fe5e6-d94a-40b4-aec2-05504c13beb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20386
14932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2038614932
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2122117015
Short name T72
Test name
Test status
Simulation time 1728311493 ps
CPU time 30.69 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:19:35 PM PDT 24
Peak memory 256552 kb
Host smart-5cbda7f2-fffc-45fe-8c7d-d226ca46294d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21221
17015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2122117015
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1791418309
Short name T408
Test name
Test status
Simulation time 22588402051 ps
CPU time 1155.96 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:38:11 PM PDT 24
Peak memory 288520 kb
Host smart-335e6158-1ea8-45ac-94f7-ff1871aedfb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791418309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1791418309
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2997961828
Short name T321
Test name
Test status
Simulation time 49926066078 ps
CPU time 611.98 seconds
Started Jul 28 05:19:05 PM PDT 24
Finished Jul 28 05:29:17 PM PDT 24
Peak memory 248796 kb
Host smart-d9fa394d-2a97-4444-87ca-7aab7f4f2d8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997961828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2997961828
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2235963092
Short name T99
Test name
Test status
Simulation time 734267168 ps
CPU time 24.61 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:39 PM PDT 24
Peak memory 257040 kb
Host smart-99ed82c3-3128-47e5-b397-bf2e0a47b27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22359
63092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2235963092
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3439270634
Short name T458
Test name
Test status
Simulation time 2768415870 ps
CPU time 52.03 seconds
Started Jul 28 05:19:07 PM PDT 24
Finished Jul 28 05:20:00 PM PDT 24
Peak memory 248820 kb
Host smart-f1b08161-b34b-4f42-a702-3cac8763d71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392
70634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3439270634
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.231447402
Short name T11
Test name
Test status
Simulation time 2711724640 ps
CPU time 38.84 seconds
Started Jul 28 05:19:01 PM PDT 24
Finished Jul 28 05:19:40 PM PDT 24
Peak memory 249208 kb
Host smart-ef6e03ed-8f25-4516-b19a-f2dbb271323c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23144
7402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.231447402
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1716921617
Short name T98
Test name
Test status
Simulation time 350530888 ps
CPU time 21.9 seconds
Started Jul 28 05:19:00 PM PDT 24
Finished Jul 28 05:19:22 PM PDT 24
Peak memory 256908 kb
Host smart-049bfbd4-3b52-497a-8506-de725c9f26b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169
21617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1716921617
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.809061786
Short name T524
Test name
Test status
Simulation time 1455265458 ps
CPU time 44.35 seconds
Started Jul 28 05:19:07 PM PDT 24
Finished Jul 28 05:19:51 PM PDT 24
Peak memory 256988 kb
Host smart-156155b8-5033-4db3-a909-1fd54e6e3c94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809061786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.809061786
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1764604282
Short name T652
Test name
Test status
Simulation time 33296690203 ps
CPU time 3426.69 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 06:16:16 PM PDT 24
Peak memory 304784 kb
Host smart-6da01bcf-13dd-4da5-8071-e7b9073d24cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764604282 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1764604282
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.212994311
Short name T206
Test name
Test status
Simulation time 200463098 ps
CPU time 3.89 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:19:13 PM PDT 24
Peak memory 248984 kb
Host smart-d572be83-666a-44ee-b1f9-bed872832591
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=212994311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.212994311
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1872641393
Short name T636
Test name
Test status
Simulation time 6872128589 ps
CPU time 30.85 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:19:25 PM PDT 24
Peak memory 248796 kb
Host smart-c0de6e7c-8b42-4f9f-9933-79ec54afa041
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1872641393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1872641393
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.349095876
Short name T531
Test name
Test status
Simulation time 3303479764 ps
CPU time 67.98 seconds
Started Jul 28 05:18:59 PM PDT 24
Finished Jul 28 05:20:07 PM PDT 24
Peak memory 256052 kb
Host smart-d8979a93-3278-46cb-9d32-0c7926e50b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34909
5876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.349095876
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.541880383
Short name T554
Test name
Test status
Simulation time 179010626 ps
CPU time 12.28 seconds
Started Jul 28 05:19:02 PM PDT 24
Finished Jul 28 05:19:14 PM PDT 24
Peak memory 248956 kb
Host smart-fa83c548-22d2-4cca-9868-7aaa2271d329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54188
0383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.541880383
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.90382675
Short name T14
Test name
Test status
Simulation time 25381688261 ps
CPU time 1475.68 seconds
Started Jul 28 05:19:05 PM PDT 24
Finished Jul 28 05:43:41 PM PDT 24
Peak memory 273132 kb
Host smart-baf7d8e6-33ad-4c1b-8fec-54b5fb928f23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90382675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.90382675
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.165484379
Short name T544
Test name
Test status
Simulation time 9482326650 ps
CPU time 930.19 seconds
Started Jul 28 05:19:00 PM PDT 24
Finished Jul 28 05:34:31 PM PDT 24
Peak memory 269300 kb
Host smart-0eff479a-5ac4-4fe4-b31c-a76800e8d3e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165484379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.165484379
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.560792107
Short name T655
Test name
Test status
Simulation time 3823310696 ps
CPU time 152.05 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:21:26 PM PDT 24
Peak memory 248572 kb
Host smart-e6ce3010-94ea-4a44-9641-1fd3ac388b37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560792107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.560792107
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1604585025
Short name T480
Test name
Test status
Simulation time 807807761 ps
CPU time 22.61 seconds
Started Jul 28 05:19:05 PM PDT 24
Finished Jul 28 05:19:27 PM PDT 24
Peak memory 256180 kb
Host smart-f6d8dcc3-ad10-4fc5-a9a1-6cde3b78b3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16045
85025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1604585025
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1369312381
Short name T298
Test name
Test status
Simulation time 994707828 ps
CPU time 54.71 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:19:59 PM PDT 24
Peak memory 248132 kb
Host smart-8c050cb2-0138-4afa-91fe-f4d3a6575522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13693
12381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1369312381
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.62209367
Short name T278
Test name
Test status
Simulation time 203342855 ps
CPU time 20.96 seconds
Started Jul 28 05:19:10 PM PDT 24
Finished Jul 28 05:19:31 PM PDT 24
Peak memory 249288 kb
Host smart-f9fbd236-7a89-4334-a1da-e8d7adfcdfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62209
367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.62209367
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1572696043
Short name T701
Test name
Test status
Simulation time 366010984 ps
CPU time 10.3 seconds
Started Jul 28 05:19:02 PM PDT 24
Finished Jul 28 05:19:13 PM PDT 24
Peak memory 248744 kb
Host smart-cb9b6477-1eca-4277-9a55-a3e3b88ed6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15726
96043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1572696043
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2252534978
Short name T467
Test name
Test status
Simulation time 82820104328 ps
CPU time 1958.22 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:51:32 PM PDT 24
Peak memory 289148 kb
Host smart-c567b7e9-2b58-499c-ae76-a5c219eff1e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252534978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2252534978
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3634770841
Short name T245
Test name
Test status
Simulation time 15017364579 ps
CPU time 968.89 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:35:26 PM PDT 24
Peak memory 268188 kb
Host smart-c0e8bab6-3be9-4eaa-b190-4eda773ea3af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634770841 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3634770841
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3972653006
Short name T218
Test name
Test status
Simulation time 190058888 ps
CPU time 4.64 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:19:00 PM PDT 24
Peak memory 249000 kb
Host smart-d857b337-3586-41a0-88cc-545fc26535f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3972653006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3972653006
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1214743090
Short name T548
Test name
Test status
Simulation time 99568827 ps
CPU time 6.79 seconds
Started Jul 28 05:19:18 PM PDT 24
Finished Jul 28 05:19:24 PM PDT 24
Peak memory 248752 kb
Host smart-a84e0743-c3bd-44fc-b204-b5e6cba8667c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1214743090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1214743090
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2361818436
Short name T390
Test name
Test status
Simulation time 5420451837 ps
CPU time 164.62 seconds
Started Jul 28 05:19:10 PM PDT 24
Finished Jul 28 05:21:55 PM PDT 24
Peak memory 256924 kb
Host smart-e56e947a-f175-43a7-b6bd-54e0f0339c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23618
18436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2361818436
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2098088007
Short name T668
Test name
Test status
Simulation time 3236135720 ps
CPU time 48.77 seconds
Started Jul 28 05:19:07 PM PDT 24
Finished Jul 28 05:19:56 PM PDT 24
Peak memory 256552 kb
Host smart-1692b151-2612-4570-8935-3720a629fed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20980
88007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2098088007
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.304421956
Short name T697
Test name
Test status
Simulation time 57187373192 ps
CPU time 1609.68 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:45:59 PM PDT 24
Peak memory 288772 kb
Host smart-124820cc-a52a-4ad4-81ec-a920280adf2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304421956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.304421956
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1936980688
Short name T665
Test name
Test status
Simulation time 48014665139 ps
CPU time 2556.98 seconds
Started Jul 28 05:19:13 PM PDT 24
Finished Jul 28 06:01:50 PM PDT 24
Peak memory 288972 kb
Host smart-1cd87a92-ff31-4be5-9f6c-7e7e23911a98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936980688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1936980688
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.4091027338
Short name T13
Test name
Test status
Simulation time 17902482010 ps
CPU time 371.07 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:25:05 PM PDT 24
Peak memory 248940 kb
Host smart-a4aeda5d-9bac-417d-85dd-d0aa9c116e76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091027338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.4091027338
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3606727533
Short name T279
Test name
Test status
Simulation time 1107354994 ps
CPU time 48.04 seconds
Started Jul 28 05:19:03 PM PDT 24
Finished Jul 28 05:19:51 PM PDT 24
Peak memory 256180 kb
Host smart-1f1f7b99-7945-42b8-8123-1b37b97d5a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36067
27533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3606727533
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3871236245
Short name T104
Test name
Test status
Simulation time 4596517586 ps
CPU time 78.32 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:20:22 PM PDT 24
Peak memory 256804 kb
Host smart-efbf4857-c5b6-4035-8944-8105661abd61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
36245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3871236245
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2735243681
Short name T410
Test name
Test status
Simulation time 642467736 ps
CPU time 41.22 seconds
Started Jul 28 05:19:07 PM PDT 24
Finished Jul 28 05:19:49 PM PDT 24
Peak memory 248224 kb
Host smart-1fe6cb98-d894-41da-b6a0-116d26dd20f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27352
43681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2735243681
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.397281499
Short name T447
Test name
Test status
Simulation time 288917873 ps
CPU time 25.31 seconds
Started Jul 28 05:19:10 PM PDT 24
Finished Jul 28 05:19:35 PM PDT 24
Peak memory 256072 kb
Host smart-d20a58e2-3cb7-466c-ae4a-7176326a22d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39728
1499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.397281499
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.255144535
Short name T96
Test name
Test status
Simulation time 19254968893 ps
CPU time 1771.56 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:48:46 PM PDT 24
Peak memory 301860 kb
Host smart-bfd49c9f-b212-4018-ab6b-e141f6aff7e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255144535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.255144535
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2355971741
Short name T205
Test name
Test status
Simulation time 39599252 ps
CPU time 2.27 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:17 PM PDT 24
Peak memory 249152 kb
Host smart-63856432-e441-4580-b9fe-02fdba51133b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2355971741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2355971741
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2044779770
Short name T91
Test name
Test status
Simulation time 97341256182 ps
CPU time 1579.15 seconds
Started Jul 28 05:19:20 PM PDT 24
Finished Jul 28 05:45:39 PM PDT 24
Peak memory 273388 kb
Host smart-d0931a0a-5721-4e83-b2f1-096c0e52360b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044779770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2044779770
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3544540833
Short name T392
Test name
Test status
Simulation time 702678209 ps
CPU time 17.83 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:19:11 PM PDT 24
Peak memory 248732 kb
Host smart-75733dec-d1e2-4db2-8d56-0404334d5270
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3544540833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3544540833
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.238556661
Short name T537
Test name
Test status
Simulation time 4079152883 ps
CPU time 246.02 seconds
Started Jul 28 05:19:09 PM PDT 24
Finished Jul 28 05:23:15 PM PDT 24
Peak memory 257072 kb
Host smart-44c96229-b1d2-473a-a28d-ac9b1e2124d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23855
6661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.238556661
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.549589973
Short name T227
Test name
Test status
Simulation time 994371462 ps
CPU time 22.66 seconds
Started Jul 28 05:19:16 PM PDT 24
Finished Jul 28 05:19:39 PM PDT 24
Peak memory 256888 kb
Host smart-ff474d55-8b00-4fa4-9802-08a3786883f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54958
9973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.549589973
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2726100052
Short name T538
Test name
Test status
Simulation time 92611515893 ps
CPU time 1405.17 seconds
Started Jul 28 05:19:01 PM PDT 24
Finished Jul 28 05:42:26 PM PDT 24
Peak memory 273304 kb
Host smart-9dcdab5b-8ab1-44e0-84da-c5f116b02650
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726100052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2726100052
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3871989163
Short name T331
Test name
Test status
Simulation time 2409358879 ps
CPU time 101.71 seconds
Started Jul 28 05:19:03 PM PDT 24
Finished Jul 28 05:20:45 PM PDT 24
Peak memory 253936 kb
Host smart-ce495828-7bad-4768-bbd8-1065db4022db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871989163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3871989163
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1234037962
Short name T556
Test name
Test status
Simulation time 1236947495 ps
CPU time 18.92 seconds
Started Jul 28 05:19:07 PM PDT 24
Finished Jul 28 05:19:26 PM PDT 24
Peak memory 256112 kb
Host smart-f1ae34d9-d6e0-407f-b898-7222a37f9496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12340
37962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1234037962
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1260629542
Short name T639
Test name
Test status
Simulation time 406276863 ps
CPU time 34.77 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:19:52 PM PDT 24
Peak memory 256328 kb
Host smart-0c88f6fe-8e45-44d4-b3bb-c17bb632afb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12606
29542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1260629542
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1733456845
Short name T664
Test name
Test status
Simulation time 137939351 ps
CPU time 9.43 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:19:03 PM PDT 24
Peak memory 248796 kb
Host smart-0def7eea-becf-40c2-87ae-c8bc63c10156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17334
56845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1733456845
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2232741587
Short name T368
Test name
Test status
Simulation time 6650758830 ps
CPU time 366.64 seconds
Started Jul 28 05:19:09 PM PDT 24
Finished Jul 28 05:25:16 PM PDT 24
Peak memory 256832 kb
Host smart-cd2b6414-1901-41f8-8425-ab431f52eddf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232741587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2232741587
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3345773569
Short name T219
Test name
Test status
Simulation time 153534547 ps
CPU time 4.16 seconds
Started Jul 28 05:19:18 PM PDT 24
Finished Jul 28 05:19:22 PM PDT 24
Peak memory 249060 kb
Host smart-0dad457f-12ed-4707-8c12-1271646565f2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3345773569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3345773569
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.71930973
Short name T422
Test name
Test status
Simulation time 16620750042 ps
CPU time 933.19 seconds
Started Jul 28 05:19:12 PM PDT 24
Finished Jul 28 05:34:46 PM PDT 24
Peak memory 289608 kb
Host smart-f3c9e119-e026-4d1b-8fd4-d19c090877e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71930973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.71930973
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2820325498
Short name T225
Test name
Test status
Simulation time 591877556 ps
CPU time 10.16 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:19:27 PM PDT 24
Peak memory 247884 kb
Host smart-0f730203-23cd-40d5-973f-886bac64a295
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2820325498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2820325498
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2256644358
Short name T589
Test name
Test status
Simulation time 1119389196 ps
CPU time 96.32 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:20:58 PM PDT 24
Peak memory 257004 kb
Host smart-5ee626c9-e3f5-4513-82e8-2452774f0d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22566
44358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2256644358
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2656851048
Short name T547
Test name
Test status
Simulation time 787028633 ps
CPU time 25.49 seconds
Started Jul 28 05:19:26 PM PDT 24
Finished Jul 28 05:19:51 PM PDT 24
Peak memory 248396 kb
Host smart-1767c09b-f41d-442a-bdbd-93238b1909ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26568
51048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2656851048
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.877715522
Short name T15
Test name
Test status
Simulation time 17700228598 ps
CPU time 188.77 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:22:20 PM PDT 24
Peak memory 247804 kb
Host smart-e678542b-42ab-4771-84c5-801c3dd798e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877715522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.877715522
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.101858268
Short name T387
Test name
Test status
Simulation time 524547239 ps
CPU time 10.12 seconds
Started Jul 28 05:19:27 PM PDT 24
Finished Jul 28 05:19:37 PM PDT 24
Peak memory 248696 kb
Host smart-a476190d-fbe7-4886-a098-14e9ade393a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10185
8268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.101858268
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1486380364
Short name T197
Test name
Test status
Simulation time 1327577280 ps
CPU time 19.35 seconds
Started Jul 28 05:19:07 PM PDT 24
Finished Jul 28 05:19:27 PM PDT 24
Peak memory 256088 kb
Host smart-a5b68aed-309f-4a7e-a694-f5619b0e880e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14863
80364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1486380364
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.586072655
Short name T371
Test name
Test status
Simulation time 130385857 ps
CPU time 13.54 seconds
Started Jul 28 05:19:10 PM PDT 24
Finished Jul 28 05:19:23 PM PDT 24
Peak memory 248844 kb
Host smart-98432104-98e8-4216-b279-ab9cae72adc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58607
2655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.586072655
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2552291229
Short name T590
Test name
Test status
Simulation time 454796091 ps
CPU time 11.61 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:19:20 PM PDT 24
Peak memory 248804 kb
Host smart-cee73234-5c06-4e03-af65-566ed6d16698
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2552291229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2552291229
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.44745760
Short name T460
Test name
Test status
Simulation time 15127798787 ps
CPU time 207.53 seconds
Started Jul 28 05:19:09 PM PDT 24
Finished Jul 28 05:22:37 PM PDT 24
Peak memory 256460 kb
Host smart-fa9b2608-f261-4cb7-89ce-bdf752f94946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44745
760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.44745760
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2184419974
Short name T121
Test name
Test status
Simulation time 786283103 ps
CPU time 18.61 seconds
Started Jul 28 05:19:05 PM PDT 24
Finished Jul 28 05:19:24 PM PDT 24
Peak memory 248384 kb
Host smart-61a4c821-254a-4b01-97ce-7a3b7b656f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21844
19974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2184419974
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.822130347
Short name T337
Test name
Test status
Simulation time 117707623115 ps
CPU time 3231.85 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 06:13:14 PM PDT 24
Peak memory 287616 kb
Host smart-ac6f0782-9cb1-46d0-bdc4-5d9127b6de94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822130347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.822130347
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1943436488
Short name T660
Test name
Test status
Simulation time 67581922243 ps
CPU time 1319.45 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:41:16 PM PDT 24
Peak memory 289736 kb
Host smart-3749fa0e-767b-4103-b5d2-992bed193450
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943436488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1943436488
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3871288253
Short name T622
Test name
Test status
Simulation time 25625290644 ps
CPU time 523.11 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:27:51 PM PDT 24
Peak memory 248940 kb
Host smart-cb032010-c4ec-4212-ab88-942f337d1e05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871288253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3871288253
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1150535093
Short name T59
Test name
Test status
Simulation time 2672549711 ps
CPU time 45.08 seconds
Started Jul 28 05:19:16 PM PDT 24
Finished Jul 28 05:20:01 PM PDT 24
Peak memory 256448 kb
Host smart-423445c1-2687-476e-b597-10918757d4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
35093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1150535093
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3873588801
Short name T114
Test name
Test status
Simulation time 1593506852 ps
CPU time 33.77 seconds
Started Jul 28 05:18:56 PM PDT 24
Finished Jul 28 05:19:30 PM PDT 24
Peak memory 248696 kb
Host smart-4398dff2-bd20-44dd-b9e1-22e618105bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38735
88801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3873588801
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4081759196
Short name T702
Test name
Test status
Simulation time 43581070 ps
CPU time 3.94 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:19:27 PM PDT 24
Peak memory 239932 kb
Host smart-2e370d85-6aa4-43ff-ad44-9e56a33de6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40817
59196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4081759196
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1133714794
Short name T54
Test name
Test status
Simulation time 128336872224 ps
CPU time 5255.59 seconds
Started Jul 28 05:19:15 PM PDT 24
Finished Jul 28 06:46:51 PM PDT 24
Peak memory 305136 kb
Host smart-d331d4ba-2bb6-4951-9358-21e6d272dedd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133714794 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1133714794
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2442923238
Short name T41
Test name
Test status
Simulation time 212337782 ps
CPU time 4.1 seconds
Started Jul 28 05:19:16 PM PDT 24
Finished Jul 28 05:19:20 PM PDT 24
Peak memory 249076 kb
Host smart-fca373a2-24c1-43e0-824a-9bd4b4f9d07f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2442923238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2442923238
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3375802985
Short name T515
Test name
Test status
Simulation time 414394607 ps
CPU time 20.33 seconds
Started Jul 28 05:18:58 PM PDT 24
Finished Jul 28 05:19:19 PM PDT 24
Peak memory 248736 kb
Host smart-c7292555-7f43-421f-ba15-a080d634e712
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3375802985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3375802985
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.285751751
Short name T470
Test name
Test status
Simulation time 5536571332 ps
CPU time 56.9 seconds
Started Jul 28 05:19:13 PM PDT 24
Finished Jul 28 05:20:10 PM PDT 24
Peak memory 257048 kb
Host smart-f945d03a-c44a-43bc-8327-8a4c4aaf9ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28575
1751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.285751751
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.618312383
Short name T73
Test name
Test status
Simulation time 205038533 ps
CPU time 13.07 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:28 PM PDT 24
Peak memory 248588 kb
Host smart-5f804b2f-7e20-4a9a-8ec1-c4810e20660b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61831
2383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.618312383
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3753207383
Short name T565
Test name
Test status
Simulation time 137016713732 ps
CPU time 1996.69 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:52:21 PM PDT 24
Peak memory 270424 kb
Host smart-5a15c603-fc51-4121-9c41-28aa6356dae7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753207383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3753207383
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.97541273
Short name T699
Test name
Test status
Simulation time 34959523623 ps
CPU time 374.09 seconds
Started Jul 28 05:19:29 PM PDT 24
Finished Jul 28 05:25:43 PM PDT 24
Peak memory 248812 kb
Host smart-3d334352-2293-4c7f-8441-401639c8c0b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97541273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.97541273
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1344715643
Short name T372
Test name
Test status
Simulation time 67938825 ps
CPU time 2.63 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:17 PM PDT 24
Peak memory 248796 kb
Host smart-cc7df2ed-18f3-47d3-b1ce-112431a31864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13447
15643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1344715643
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2333186097
Short name T643
Test name
Test status
Simulation time 9438890152 ps
CPU time 38.8 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:20:02 PM PDT 24
Peak memory 248112 kb
Host smart-67a8e36c-6310-435f-a3b3-c83c9db6c571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23331
86097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2333186097
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3139676509
Short name T399
Test name
Test status
Simulation time 3730193372 ps
CPU time 73.49 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:20:09 PM PDT 24
Peak memory 257020 kb
Host smart-1bc84fa8-e8bf-4b72-9c56-afba51a12a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31396
76509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3139676509
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3348891436
Short name T416
Test name
Test status
Simulation time 836358053 ps
CPU time 21.29 seconds
Started Jul 28 05:19:15 PM PDT 24
Finished Jul 28 05:19:37 PM PDT 24
Peak memory 255536 kb
Host smart-316fd4cb-0268-46c0-bdb5-1866db404c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33488
91436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3348891436
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2077266129
Short name T115
Test name
Test status
Simulation time 51079249515 ps
CPU time 1324.92 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:41:09 PM PDT 24
Peak memory 286544 kb
Host smart-6e4072c0-ee20-4806-96d1-e5974e95b82f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077266129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2077266129
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.381507562
Short name T209
Test name
Test status
Simulation time 138322998 ps
CPU time 3.86 seconds
Started Jul 28 05:19:05 PM PDT 24
Finished Jul 28 05:19:09 PM PDT 24
Peak memory 249132 kb
Host smart-bfd43040-85da-4972-8e08-b2cd7b0440d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=381507562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.381507562
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3850111620
Short name T708
Test name
Test status
Simulation time 317623304449 ps
CPU time 2404.9 seconds
Started Jul 28 05:19:20 PM PDT 24
Finished Jul 28 05:59:25 PM PDT 24
Peak memory 285428 kb
Host smart-57785207-21e1-4ec5-8317-72ce04ae0e54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850111620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3850111620
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.356324374
Short name T437
Test name
Test status
Simulation time 154072416 ps
CPU time 8.83 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:19:20 PM PDT 24
Peak memory 248672 kb
Host smart-2dccf441-78c2-45ec-bf71-47d41c18f25c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=356324374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.356324374
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1859156676
Short name T518
Test name
Test status
Simulation time 9417740139 ps
CPU time 95.02 seconds
Started Jul 28 05:19:20 PM PDT 24
Finished Jul 28 05:20:55 PM PDT 24
Peak memory 256928 kb
Host smart-a2759163-f484-44a5-90a6-eb873f688888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18591
56676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1859156676
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1862022410
Short name T596
Test name
Test status
Simulation time 86353237 ps
CPU time 9.81 seconds
Started Jul 28 05:19:06 PM PDT 24
Finished Jul 28 05:19:16 PM PDT 24
Peak memory 254864 kb
Host smart-90e0db6a-f6f7-4c05-a82b-98b83a17d542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18620
22410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1862022410
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.251117509
Short name T628
Test name
Test status
Simulation time 72850767916 ps
CPU time 1982.04 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:52:17 PM PDT 24
Peak memory 273380 kb
Host smart-8cede60e-c383-4a85-b2c6-8edc64b92662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251117509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.251117509
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4159368785
Short name T237
Test name
Test status
Simulation time 28012243530 ps
CPU time 1489.86 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:44:07 PM PDT 24
Peak memory 272908 kb
Host smart-f29b8acd-737a-4f93-9ce4-1b4cadd4251f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159368785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4159368785
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.943488180
Short name T330
Test name
Test status
Simulation time 6558389212 ps
CPU time 273.99 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:23:51 PM PDT 24
Peak memory 248860 kb
Host smart-50a94d4c-67dd-43a9-bc07-d5847a1b49b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943488180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.943488180
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.641154593
Short name T700
Test name
Test status
Simulation time 313836877 ps
CPU time 11 seconds
Started Jul 28 05:19:20 PM PDT 24
Finished Jul 28 05:19:31 PM PDT 24
Peak memory 256896 kb
Host smart-f8566cfa-4f26-4766-afd3-4397eaf5913f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64115
4593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.641154593
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2969963840
Short name T448
Test name
Test status
Simulation time 726940415 ps
CPU time 45.3 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:19:56 PM PDT 24
Peak memory 248832 kb
Host smart-da2abcd7-a37f-4084-aa96-e7128e09b010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29699
63840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2969963840
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1090502828
Short name T118
Test name
Test status
Simulation time 3090310879 ps
CPU time 29.95 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:44 PM PDT 24
Peak memory 248792 kb
Host smart-5acba602-07db-4f96-bd1d-2eb9d7a6e17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10905
02828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1090502828
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3644764191
Short name T573
Test name
Test status
Simulation time 258046329 ps
CPU time 16.14 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:19:38 PM PDT 24
Peak memory 255816 kb
Host smart-128f7f88-edee-4dea-82d5-54296a76fae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36447
64191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3644764191
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3287512626
Short name T208
Test name
Test status
Simulation time 15276692 ps
CPU time 2.31 seconds
Started Jul 28 05:18:49 PM PDT 24
Finished Jul 28 05:18:51 PM PDT 24
Peak memory 249128 kb
Host smart-eddf2618-535d-4813-8836-c2eec29ea975
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3287512626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3287512626
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.457101556
Short name T621
Test name
Test status
Simulation time 286427664328 ps
CPU time 3354.65 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 06:14:49 PM PDT 24
Peak memory 289268 kb
Host smart-d000b179-69df-4138-9e30-f42033196456
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457101556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.457101556
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.329547677
Short name T473
Test name
Test status
Simulation time 426589402 ps
CPU time 13.25 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:19:00 PM PDT 24
Peak memory 248740 kb
Host smart-87a93d55-ca33-437e-8fdc-d8cc01466890
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=329547677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.329547677
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.945349906
Short name T472
Test name
Test status
Simulation time 7985834434 ps
CPU time 251.94 seconds
Started Jul 28 05:18:50 PM PDT 24
Finished Jul 28 05:23:02 PM PDT 24
Peak memory 257184 kb
Host smart-a59b5826-c596-481f-8ab9-2252c22a2b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94534
9906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.945349906
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.359685175
Short name T457
Test name
Test status
Simulation time 744467946 ps
CPU time 42.54 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:19:27 PM PDT 24
Peak memory 249288 kb
Host smart-d5f3d67d-83f7-44e0-8915-6e0c3ddff0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35968
5175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.359685175
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2447000344
Short name T551
Test name
Test status
Simulation time 93063237446 ps
CPU time 2803.74 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 06:05:32 PM PDT 24
Peak memory 287192 kb
Host smart-8e0a4204-fbaf-4e54-a171-761f0695f43b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447000344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2447000344
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3872749799
Short name T449
Test name
Test status
Simulation time 54324031421 ps
CPU time 2878.15 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 06:06:44 PM PDT 24
Peak memory 289636 kb
Host smart-e2597a3b-3362-4675-84e3-cbb42479827f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872749799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3872749799
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3338484645
Short name T452
Test name
Test status
Simulation time 63943110346 ps
CPU time 285.24 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:23:32 PM PDT 24
Peak memory 248768 kb
Host smart-5b8176b8-0edd-46e4-9681-665662446ef2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338484645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3338484645
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2288628377
Short name T681
Test name
Test status
Simulation time 151203246 ps
CPU time 11.46 seconds
Started Jul 28 05:18:37 PM PDT 24
Finished Jul 28 05:18:48 PM PDT 24
Peak memory 248832 kb
Host smart-ba36d963-c59b-4f45-a3cd-2eeeada71458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22886
28377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2288628377
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1492100004
Short name T698
Test name
Test status
Simulation time 158810488 ps
CPU time 10.75 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:18:54 PM PDT 24
Peak memory 248352 kb
Host smart-d191014a-79b6-43f9-a3ae-38a8e3d3b041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14921
00004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1492100004
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.170696428
Short name T10
Test name
Test status
Simulation time 747517031 ps
CPU time 21.98 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:19:15 PM PDT 24
Peak memory 266968 kb
Host smart-421d30a4-d8b7-4aa5-9bb0-6a23e6765b01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=170696428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.170696428
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1947143982
Short name T715
Test name
Test status
Simulation time 3764127131 ps
CPU time 36.62 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:19:19 PM PDT 24
Peak memory 248892 kb
Host smart-26882a48-c437-46cf-b27f-305850128ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19471
43982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1947143982
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1687931547
Short name T576
Test name
Test status
Simulation time 5956681114 ps
CPU time 114.12 seconds
Started Jul 28 05:18:47 PM PDT 24
Finished Jul 28 05:20:41 PM PDT 24
Peak memory 256984 kb
Host smart-56e3e542-a2d6-4f4f-8cbd-f7e067b41ba6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687931547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1687931547
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.128798759
Short name T386
Test name
Test status
Simulation time 15985452247 ps
CPU time 763.79 seconds
Started Jul 28 05:19:24 PM PDT 24
Finished Jul 28 05:32:08 PM PDT 24
Peak memory 272364 kb
Host smart-abaecbe9-2bfe-458f-83d9-93d5f4519bf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128798759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.128798759
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2489622276
Short name T481
Test name
Test status
Simulation time 3801908290 ps
CPU time 203.85 seconds
Started Jul 28 05:19:12 PM PDT 24
Finished Jul 28 05:22:36 PM PDT 24
Peak memory 256368 kb
Host smart-e3980cd8-ce52-4933-84f7-7d082038552c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24896
22276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2489622276
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3238232258
Short name T414
Test name
Test status
Simulation time 795425835 ps
CPU time 55.22 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:20:16 PM PDT 24
Peak memory 256536 kb
Host smart-dfd47775-bce5-46b1-b04b-8c46e945c202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32382
32258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3238232258
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2746643160
Short name T365
Test name
Test status
Simulation time 132359332027 ps
CPU time 1004.85 seconds
Started Jul 28 05:19:12 PM PDT 24
Finished Jul 28 05:35:57 PM PDT 24
Peak memory 273416 kb
Host smart-254d5629-44bc-4d5f-a1b9-6c185b645f96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746643160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2746643160
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3020682134
Short name T673
Test name
Test status
Simulation time 8818444202 ps
CPU time 750.81 seconds
Started Jul 28 05:19:13 PM PDT 24
Finished Jul 28 05:31:44 PM PDT 24
Peak memory 273460 kb
Host smart-b8efae07-e394-4fc1-bfc9-66be6db62eff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020682134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3020682134
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2646151529
Short name T663
Test name
Test status
Simulation time 9169194784 ps
CPU time 343.45 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:25:05 PM PDT 24
Peak memory 248688 kb
Host smart-29e480e1-8e37-4919-ba55-26ac7bbdce47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646151529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2646151529
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2975249683
Short name T401
Test name
Test status
Simulation time 123085639 ps
CPU time 11.1 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:19:22 PM PDT 24
Peak memory 256376 kb
Host smart-b6a96f44-4981-4827-bb5a-9c3863b9bb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29752
49683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2975249683
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1036360036
Short name T620
Test name
Test status
Simulation time 70976662 ps
CPU time 7.02 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:19:29 PM PDT 24
Peak memory 254956 kb
Host smart-f6b4c322-b4d5-4bb6-ac7e-f4c7917c3bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10363
60036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1036360036
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.412870409
Short name T80
Test name
Test status
Simulation time 466661354 ps
CPU time 14.83 seconds
Started Jul 28 05:19:13 PM PDT 24
Finished Jul 28 05:19:28 PM PDT 24
Peak memory 248792 kb
Host smart-c1f49afd-7ff1-4d60-b41f-4effab71a2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41287
0409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.412870409
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2199207619
Short name T464
Test name
Test status
Simulation time 1036497567 ps
CPU time 31.54 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:19:43 PM PDT 24
Peak memory 256988 kb
Host smart-345f39d1-4171-48fe-a01b-8de343a6111f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21992
07619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2199207619
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3302940279
Short name T580
Test name
Test status
Simulation time 2206452534 ps
CPU time 60.49 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:20:09 PM PDT 24
Peak memory 257084 kb
Host smart-132f58f3-7fef-4125-9467-99aec766af2e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302940279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3302940279
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.752257378
Short name T247
Test name
Test status
Simulation time 19518433921 ps
CPU time 1223.15 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:39:40 PM PDT 24
Peak memory 273588 kb
Host smart-f1cd26a4-0982-475b-b831-55f3cd9dc673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752257378 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.752257378
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1051947474
Short name T523
Test name
Test status
Simulation time 30529984235 ps
CPU time 1943.38 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:51:37 PM PDT 24
Peak memory 283872 kb
Host smart-9d2090dc-19ec-48e5-bf8c-1b6974efaca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051947474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1051947474
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1518983023
Short name T570
Test name
Test status
Simulation time 5338067954 ps
CPU time 124.23 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:21:15 PM PDT 24
Peak memory 256364 kb
Host smart-020ab35e-4adf-4f24-a645-e9bfe5f6c76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15189
83023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1518983023
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.391309876
Short name T632
Test name
Test status
Simulation time 622651356 ps
CPU time 43.24 seconds
Started Jul 28 05:19:12 PM PDT 24
Finished Jul 28 05:19:56 PM PDT 24
Peak memory 248544 kb
Host smart-deaff471-e07d-4b05-b3e8-fffd374b026d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39130
9876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.391309876
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3473141344
Short name T304
Test name
Test status
Simulation time 315635721963 ps
CPU time 1747.88 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:48:25 PM PDT 24
Peak memory 272236 kb
Host smart-d6ad082c-1d3b-485e-965f-cac142a0b825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473141344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3473141344
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.675481923
Short name T586
Test name
Test status
Simulation time 57856428252 ps
CPU time 1356.47 seconds
Started Jul 28 05:19:10 PM PDT 24
Finished Jul 28 05:41:47 PM PDT 24
Peak memory 289828 kb
Host smart-87104714-e726-425e-a3e0-dd5d080507c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675481923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.675481923
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3034782485
Short name T369
Test name
Test status
Simulation time 1001895210 ps
CPU time 27.44 seconds
Started Jul 28 05:19:10 PM PDT 24
Finished Jul 28 05:19:37 PM PDT 24
Peak memory 248756 kb
Host smart-30edf5e8-9d73-46e6-bc1a-99b47b3f5b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30347
82485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3034782485
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2624160551
Short name T671
Test name
Test status
Simulation time 792227386 ps
CPU time 46.67 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 05:20:12 PM PDT 24
Peak memory 248696 kb
Host smart-70f0cbe4-e4ff-4ac1-bd25-5865b2ce98ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26241
60551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2624160551
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3862091736
Short name T267
Test name
Test status
Simulation time 2381071903 ps
CPU time 16.77 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:19:38 PM PDT 24
Peak memory 249452 kb
Host smart-e458db60-f7ce-455b-aa4a-af333e189b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38620
91736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3862091736
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2848692982
Short name T435
Test name
Test status
Simulation time 1846636159 ps
CPU time 70.55 seconds
Started Jul 28 05:19:19 PM PDT 24
Finished Jul 28 05:20:30 PM PDT 24
Peak memory 256872 kb
Host smart-6b3dad9d-5894-4556-903c-d2ab7a036bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28486
92982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2848692982
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3888295022
Short name T683
Test name
Test status
Simulation time 98765121222 ps
CPU time 2393.52 seconds
Started Jul 28 05:19:15 PM PDT 24
Finished Jul 28 05:59:09 PM PDT 24
Peak memory 305340 kb
Host smart-8078eeb8-5ca0-4448-b45a-e3b6e59d4775
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888295022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3888295022
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.333244878
Short name T637
Test name
Test status
Simulation time 50391529949 ps
CPU time 811.93 seconds
Started Jul 28 05:19:15 PM PDT 24
Finished Jul 28 05:32:47 PM PDT 24
Peak memory 273072 kb
Host smart-895fd5b0-18f7-4096-818b-3f20e8712541
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333244878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.333244878
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.945799134
Short name T595
Test name
Test status
Simulation time 124884558 ps
CPU time 8.48 seconds
Started Jul 28 05:19:09 PM PDT 24
Finished Jul 28 05:19:18 PM PDT 24
Peak memory 251888 kb
Host smart-7e87163c-5d62-4f77-b16f-edd04b775d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94579
9134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.945799134
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2289197378
Short name T712
Test name
Test status
Simulation time 801914414 ps
CPU time 36.52 seconds
Started Jul 28 05:19:24 PM PDT 24
Finished Jul 28 05:20:01 PM PDT 24
Peak memory 257000 kb
Host smart-28267075-35d7-4f5f-aa0b-2f714bca2714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22891
97378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2289197378
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2964791190
Short name T688
Test name
Test status
Simulation time 83139396913 ps
CPU time 1508.51 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:44:23 PM PDT 24
Peak memory 273268 kb
Host smart-71d82c0b-1bd2-44e7-b397-ab61e93dffcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964791190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2964791190
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1936903331
Short name T311
Test name
Test status
Simulation time 7324373729 ps
CPU time 324.01 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:24:45 PM PDT 24
Peak memory 248904 kb
Host smart-ab196518-1221-480c-8ed1-39ed37007d30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936903331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1936903331
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2769779118
Short name T567
Test name
Test status
Simulation time 449846511 ps
CPU time 9.54 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:23 PM PDT 24
Peak memory 253588 kb
Host smart-9eac6448-1ae9-42aa-b124-88b68972fc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27697
79118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2769779118
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2648507174
Short name T301
Test name
Test status
Simulation time 534903524 ps
CPU time 26.16 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:19:48 PM PDT 24
Peak memory 248280 kb
Host smart-817c8904-486d-4eb3-89f9-125c1fc473cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26485
07174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2648507174
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1872180214
Short name T375
Test name
Test status
Simulation time 169898147 ps
CPU time 10.07 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:19:21 PM PDT 24
Peak memory 248844 kb
Host smart-143a14c7-a7de-4ec2-b04d-655f0e70d3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18721
80214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1872180214
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3113926309
Short name T535
Test name
Test status
Simulation time 416819609 ps
CPU time 4.63 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:19 PM PDT 24
Peak memory 248836 kb
Host smart-682078a0-c721-4770-84ce-1b05a64ecf38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31139
26309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3113926309
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1851632276
Short name T659
Test name
Test status
Simulation time 44450863391 ps
CPU time 2995.73 seconds
Started Jul 28 05:19:27 PM PDT 24
Finished Jul 28 06:09:23 PM PDT 24
Peak memory 289844 kb
Host smart-afa8ecc9-2e18-4510-96f5-f58644478651
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851632276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1851632276
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2455918749
Short name T691
Test name
Test status
Simulation time 36564830372 ps
CPU time 2201.26 seconds
Started Jul 28 05:19:30 PM PDT 24
Finished Jul 28 05:56:12 PM PDT 24
Peak memory 288972 kb
Host smart-4fc5842b-a0fd-48bc-8e21-2aa628bcd01c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455918749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2455918749
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1624146301
Short name T444
Test name
Test status
Simulation time 6742197568 ps
CPU time 198.27 seconds
Started Jul 28 05:19:38 PM PDT 24
Finished Jul 28 05:22:56 PM PDT 24
Peak memory 257088 kb
Host smart-f649b88b-663a-42af-8188-b58d8e4c60b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16241
46301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1624146301
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2848878034
Short name T440
Test name
Test status
Simulation time 115543529 ps
CPU time 12.81 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:19:36 PM PDT 24
Peak memory 248348 kb
Host smart-e1a0ebdc-f8ad-4a52-954a-cc66b27619c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28488
78034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2848878034
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1192605721
Short name T288
Test name
Test status
Simulation time 28482651227 ps
CPU time 1589.22 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 05:45:54 PM PDT 24
Peak memory 270588 kb
Host smart-43c92b43-29ab-45b4-a99e-48b129ea8025
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192605721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1192605721
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1621512641
Short name T281
Test name
Test status
Simulation time 21837298531 ps
CPU time 1383.59 seconds
Started Jul 28 05:19:27 PM PDT 24
Finished Jul 28 05:42:31 PM PDT 24
Peak memory 273412 kb
Host smart-584f2062-04b2-4090-bdf7-d36246dfd948
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621512641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1621512641
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3518089768
Short name T318
Test name
Test status
Simulation time 12630824611 ps
CPU time 370.08 seconds
Started Jul 28 05:19:29 PM PDT 24
Finished Jul 28 05:25:39 PM PDT 24
Peak memory 248904 kb
Host smart-57ed1766-e686-4b5f-a3ff-919ccf01e34e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518089768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3518089768
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3776351541
Short name T561
Test name
Test status
Simulation time 739987069 ps
CPU time 29.79 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:19:51 PM PDT 24
Peak memory 248884 kb
Host smart-a61c3dae-1285-484c-84f6-442af235595c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37763
51541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3776351541
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.197959302
Short name T82
Test name
Test status
Simulation time 3736867748 ps
CPU time 31.47 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:46 PM PDT 24
Peak memory 256300 kb
Host smart-0a3e792e-c2f8-4bb9-b5e2-6ab51c047ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19795
9302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.197959302
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.804070216
Short name T55
Test name
Test status
Simulation time 1230772223 ps
CPU time 55.26 seconds
Started Jul 28 05:19:16 PM PDT 24
Finished Jul 28 05:20:11 PM PDT 24
Peak memory 248788 kb
Host smart-1c05f1f4-6aee-4b8f-a44f-769229a57e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80407
0216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.804070216
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3131067305
Short name T374
Test name
Test status
Simulation time 376036674 ps
CPU time 14.25 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:19:35 PM PDT 24
Peak memory 256488 kb
Host smart-e4c8a4e3-ebe1-48e3-b128-5abcb2c3ac18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
67305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3131067305
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.218342249
Short name T287
Test name
Test status
Simulation time 35067568608 ps
CPU time 1544.01 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 05:45:09 PM PDT 24
Peak memory 289024 kb
Host smart-b5b21823-6fff-4906-aeba-df873b3d004a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218342249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.218342249
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1474253599
Short name T273
Test name
Test status
Simulation time 397148820326 ps
CPU time 5652.48 seconds
Started Jul 28 05:19:16 PM PDT 24
Finished Jul 28 06:53:29 PM PDT 24
Peak memory 355436 kb
Host smart-acd31bdb-12b3-464d-ab19-9139c78cb752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474253599 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1474253599
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2498872685
Short name T434
Test name
Test status
Simulation time 136607962726 ps
CPU time 759.16 seconds
Started Jul 28 05:19:24 PM PDT 24
Finished Jul 28 05:32:03 PM PDT 24
Peak memory 272404 kb
Host smart-9fbe27f7-f162-4f51-9e4c-e49fffb5a3fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498872685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2498872685
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2553000685
Short name T34
Test name
Test status
Simulation time 943656038 ps
CPU time 79.24 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:20:41 PM PDT 24
Peak memory 249872 kb
Host smart-2d81d0b6-71b2-4bff-9f97-15b5251838d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25530
00685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2553000685
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3639058174
Short name T475
Test name
Test status
Simulation time 2641855578 ps
CPU time 62.91 seconds
Started Jul 28 05:19:26 PM PDT 24
Finished Jul 28 05:20:29 PM PDT 24
Peak memory 248488 kb
Host smart-44202e79-1f6e-4ca4-9af2-3045cb82cf0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36390
58174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3639058174
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.910115843
Short name T349
Test name
Test status
Simulation time 95827077591 ps
CPU time 1433.02 seconds
Started Jul 28 05:19:31 PM PDT 24
Finished Jul 28 05:43:25 PM PDT 24
Peak memory 271888 kb
Host smart-5afbbe01-eea3-4716-9014-11d8db1ee7ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910115843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.910115843
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2529285684
Short name T226
Test name
Test status
Simulation time 50324004399 ps
CPU time 864.05 seconds
Started Jul 28 05:19:27 PM PDT 24
Finished Jul 28 05:33:51 PM PDT 24
Peak memory 271360 kb
Host smart-a2ac8d01-3cc6-4189-97e5-97939e65ec3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529285684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2529285684
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.4154158977
Short name T308
Test name
Test status
Simulation time 10697186354 ps
CPU time 430.95 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:26:33 PM PDT 24
Peak memory 248788 kb
Host smart-68c513ec-0368-462a-922e-58da542c653f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154158977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.4154158977
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.499124139
Short name T690
Test name
Test status
Simulation time 1600520374 ps
CPU time 26.44 seconds
Started Jul 28 05:19:11 PM PDT 24
Finished Jul 28 05:19:37 PM PDT 24
Peak memory 256244 kb
Host smart-60081b52-d526-4151-8cff-20c309695f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49912
4139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.499124139
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.638564361
Short name T486
Test name
Test status
Simulation time 205141943 ps
CPU time 19.41 seconds
Started Jul 28 05:19:28 PM PDT 24
Finished Jul 28 05:19:47 PM PDT 24
Peak memory 256896 kb
Host smart-48d5690a-50f2-48b0-bf97-59fcaff84499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63856
4361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.638564361
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.4018029752
Short name T420
Test name
Test status
Simulation time 828751722 ps
CPU time 25.17 seconds
Started Jul 28 05:19:24 PM PDT 24
Finished Jul 28 05:19:49 PM PDT 24
Peak memory 256944 kb
Host smart-3451deb2-2279-4108-a7e6-1cdc95991780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40180
29752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.4018029752
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.319907979
Short name T117
Test name
Test status
Simulation time 3254886504 ps
CPU time 284.92 seconds
Started Jul 28 05:19:26 PM PDT 24
Finished Jul 28 05:24:11 PM PDT 24
Peak memory 265228 kb
Host smart-13c21824-e6bf-4052-9fe8-65e6bfe0d4fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319907979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.319907979
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3285248743
Short name T504
Test name
Test status
Simulation time 194401298010 ps
CPU time 3275.07 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 06:13:57 PM PDT 24
Peak memory 289484 kb
Host smart-f41669fb-a06a-4452-8c86-0e178b52b4a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285248743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3285248743
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1084505589
Short name T256
Test name
Test status
Simulation time 3666221983 ps
CPU time 148.8 seconds
Started Jul 28 05:19:24 PM PDT 24
Finished Jul 28 05:21:53 PM PDT 24
Peak memory 252028 kb
Host smart-1de2c42b-987a-4ea0-a6fe-c9da787ebe2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10845
05589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1084505589
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3623787720
Short name T710
Test name
Test status
Simulation time 1559967192 ps
CPU time 37.1 seconds
Started Jul 28 05:19:16 PM PDT 24
Finished Jul 28 05:19:53 PM PDT 24
Peak memory 248684 kb
Host smart-847cb6f9-77ce-421a-926b-7f9582b73b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237
87720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3623787720
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3971621578
Short name T249
Test name
Test status
Simulation time 53651906000 ps
CPU time 1275.32 seconds
Started Jul 28 05:19:30 PM PDT 24
Finished Jul 28 05:40:45 PM PDT 24
Peak memory 285048 kb
Host smart-168aefc3-3069-4242-a002-fc9b085d6a36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971621578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3971621578
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1371214891
Short name T608
Test name
Test status
Simulation time 47297693424 ps
CPU time 706.18 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:31:07 PM PDT 24
Peak memory 265096 kb
Host smart-f0506c3c-4b45-45b1-af34-83551087a575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371214891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1371214891
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1222120158
Short name T199
Test name
Test status
Simulation time 30446717189 ps
CPU time 333.76 seconds
Started Jul 28 05:19:29 PM PDT 24
Finished Jul 28 05:25:03 PM PDT 24
Peak memory 248668 kb
Host smart-22e97157-9862-4ca9-8237-9ffbd0ba4f4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222120158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1222120158
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1472517712
Short name T443
Test name
Test status
Simulation time 883818328 ps
CPU time 41.04 seconds
Started Jul 28 05:19:14 PM PDT 24
Finished Jul 28 05:19:56 PM PDT 24
Peak memory 256352 kb
Host smart-df0ae20d-ea43-4ebf-800e-87b8058002fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14725
17712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1472517712
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.761167719
Short name T709
Test name
Test status
Simulation time 918454444 ps
CPU time 29.25 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:19:51 PM PDT 24
Peak memory 248836 kb
Host smart-6d434a0f-1b4d-4d24-9b11-dc7ec7a830ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76116
7719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.761167719
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.996284695
Short name T630
Test name
Test status
Simulation time 1327620226 ps
CPU time 24.22 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:19:48 PM PDT 24
Peak memory 255968 kb
Host smart-d77645eb-a263-48b0-8066-6a893ba4ed5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99628
4695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.996284695
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2243678066
Short name T79
Test name
Test status
Simulation time 80234217203 ps
CPU time 1166.71 seconds
Started Jul 28 05:19:24 PM PDT 24
Finished Jul 28 05:38:51 PM PDT 24
Peak memory 285976 kb
Host smart-335989ce-dd5c-4f55-a815-cfa76453e03a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243678066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2243678066
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3599458703
Short name T97
Test name
Test status
Simulation time 54303664785 ps
CPU time 903.84 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:34:27 PM PDT 24
Peak memory 281752 kb
Host smart-d23eca1d-43ac-4d4b-8e93-73867eef02a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599458703 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3599458703
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1026035977
Short name T609
Test name
Test status
Simulation time 165554537085 ps
CPU time 2069.75 seconds
Started Jul 28 05:19:34 PM PDT 24
Finished Jul 28 05:54:04 PM PDT 24
Peak memory 273120 kb
Host smart-c8829ef7-7e1a-4b7f-b2fd-ae8f9eb97c90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026035977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1026035977
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3063852808
Short name T259
Test name
Test status
Simulation time 1413240186 ps
CPU time 74.47 seconds
Started Jul 28 05:19:34 PM PDT 24
Finished Jul 28 05:20:48 PM PDT 24
Peak memory 256500 kb
Host smart-8573773a-55a6-4bbf-b66b-e0f2a005eca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30638
52808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3063852808
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1951437285
Short name T666
Test name
Test status
Simulation time 458266188 ps
CPU time 29.91 seconds
Started Jul 28 05:19:20 PM PDT 24
Finished Jul 28 05:19:50 PM PDT 24
Peak memory 248420 kb
Host smart-874c5bb8-325a-4f11-b302-a169e554ace0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19514
37285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1951437285
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3006225479
Short name T334
Test name
Test status
Simulation time 153144926277 ps
CPU time 2382.62 seconds
Started Jul 28 05:19:28 PM PDT 24
Finished Jul 28 05:59:11 PM PDT 24
Peak memory 289780 kb
Host smart-963bd834-732d-4dbd-97c5-03f365a36333
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006225479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3006225479
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.934715396
Short name T299
Test name
Test status
Simulation time 123188716204 ps
CPU time 1768.95 seconds
Started Jul 28 05:19:31 PM PDT 24
Finished Jul 28 05:49:00 PM PDT 24
Peak memory 273400 kb
Host smart-6b0b7ce8-8754-40b4-a04a-154cc1b7e656
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934715396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.934715396
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1588798619
Short name T539
Test name
Test status
Simulation time 4893384735 ps
CPU time 83.47 seconds
Started Jul 28 05:19:24 PM PDT 24
Finished Jul 28 05:20:47 PM PDT 24
Peak memory 257072 kb
Host smart-45f0d4d8-c83d-467c-951d-fa0cfcc2ab81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15887
98619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1588798619
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1728566868
Short name T421
Test name
Test status
Simulation time 1001498637 ps
CPU time 59.65 seconds
Started Jul 28 05:19:32 PM PDT 24
Finished Jul 28 05:20:32 PM PDT 24
Peak memory 256540 kb
Host smart-b43954ed-94b4-441e-8edf-11fd1a22bc96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17285
66868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1728566868
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3604316429
Short name T235
Test name
Test status
Simulation time 11598681111 ps
CPU time 58.02 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:20:32 PM PDT 24
Peak memory 256060 kb
Host smart-1d5ddb06-e90f-4fa5-a109-dace83fcfff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36043
16429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3604316429
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2765241348
Short name T238
Test name
Test status
Simulation time 3213017630 ps
CPU time 51.01 seconds
Started Jul 28 05:19:31 PM PDT 24
Finished Jul 28 05:20:22 PM PDT 24
Peak memory 256948 kb
Host smart-eaf6d2b9-1c7e-4850-b5ab-49ed944f724e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27652
41348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2765241348
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2294715316
Short name T286
Test name
Test status
Simulation time 203038554118 ps
CPU time 2903.38 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 06:07:47 PM PDT 24
Peak memory 286392 kb
Host smart-8d2cbb71-33b9-4806-b0f0-2c6cfe693c54
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294715316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2294715316
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2414998696
Short name T17
Test name
Test status
Simulation time 127105408421 ps
CPU time 636.9 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:30:00 PM PDT 24
Peak memory 273444 kb
Host smart-7b90ca44-b789-4490-9906-76b5abc3fd9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414998696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2414998696
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.262770391
Short name T599
Test name
Test status
Simulation time 3101163438 ps
CPU time 180.54 seconds
Started Jul 28 05:19:32 PM PDT 24
Finished Jul 28 05:22:33 PM PDT 24
Peak memory 256352 kb
Host smart-7c9e6fd2-f587-4cfc-b2c8-4824fcb91359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
0391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.262770391
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.137429834
Short name T687
Test name
Test status
Simulation time 1083118248 ps
CPU time 64.61 seconds
Started Jul 28 05:19:30 PM PDT 24
Finished Jul 28 05:20:35 PM PDT 24
Peak memory 248684 kb
Host smart-d8b6e78a-4431-4f3a-86e0-908d611608e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13742
9834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.137429834
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2326690100
Short name T344
Test name
Test status
Simulation time 81856633294 ps
CPU time 2536.67 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 06:01:40 PM PDT 24
Peak memory 289180 kb
Host smart-e8f973c8-c688-48e7-9ec8-113643502312
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326690100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2326690100
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1260779593
Short name T707
Test name
Test status
Simulation time 72021377348 ps
CPU time 1484.72 seconds
Started Jul 28 05:19:27 PM PDT 24
Finished Jul 28 05:44:12 PM PDT 24
Peak memory 289164 kb
Host smart-1465d2bd-5646-42d7-8197-04468525f898
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260779593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1260779593
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3547726919
Short name T617
Test name
Test status
Simulation time 2888343962 ps
CPU time 119.75 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:21:22 PM PDT 24
Peak memory 248732 kb
Host smart-dc9a9eae-f9e3-40ca-88dd-d8f37805c959
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547726919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3547726919
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3185632733
Short name T716
Test name
Test status
Simulation time 1273118311 ps
CPU time 33.28 seconds
Started Jul 28 05:19:26 PM PDT 24
Finished Jul 28 05:20:00 PM PDT 24
Peak memory 256304 kb
Host smart-4a6614d0-a51d-4b34-8637-bb31c529cad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31856
32733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3185632733
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1766354805
Short name T428
Test name
Test status
Simulation time 16258461805 ps
CPU time 49.14 seconds
Started Jul 28 05:19:35 PM PDT 24
Finished Jul 28 05:20:24 PM PDT 24
Peak memory 248884 kb
Host smart-98bd4a8c-f696-45c9-875b-386bcb25cbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17663
54805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1766354805
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3560499588
Short name T252
Test name
Test status
Simulation time 985723231 ps
CPU time 26.55 seconds
Started Jul 28 05:19:30 PM PDT 24
Finished Jul 28 05:19:57 PM PDT 24
Peak memory 248736 kb
Host smart-3b6b78a2-7a79-439f-9c4b-a50bd073ebb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35604
99588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3560499588
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1224358594
Short name T70
Test name
Test status
Simulation time 19980805471 ps
CPU time 1759.44 seconds
Started Jul 28 05:19:27 PM PDT 24
Finished Jul 28 05:48:47 PM PDT 24
Peak memory 305784 kb
Host smart-95b38718-7cac-48a4-977e-95b215ab5262
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224358594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1224358594
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3988682092
Short name T6
Test name
Test status
Simulation time 192815878866 ps
CPU time 7603.99 seconds
Started Jul 28 05:19:26 PM PDT 24
Finished Jul 28 07:26:11 PM PDT 24
Peak memory 355304 kb
Host smart-b807d650-83d7-4117-a658-55eb7ded08b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988682092 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3988682092
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.478704419
Short name T81
Test name
Test status
Simulation time 32565976882 ps
CPU time 1902.36 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:51:15 PM PDT 24
Peak memory 283512 kb
Host smart-e5a1d899-66fb-408e-bd2c-3c6d12e65474
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478704419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.478704419
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1452497339
Short name T657
Test name
Test status
Simulation time 617766832 ps
CPU time 43.83 seconds
Started Jul 28 05:19:36 PM PDT 24
Finished Jul 28 05:20:20 PM PDT 24
Peak memory 256732 kb
Host smart-c2eea929-a7e5-4d6b-a444-ce4469baf3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
97339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1452497339
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1705673070
Short name T484
Test name
Test status
Simulation time 3635191640 ps
CPU time 18.55 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:19:41 PM PDT 24
Peak memory 248220 kb
Host smart-4914a68e-4625-4d05-905f-24f80247a930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17056
73070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1705673070
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1652173251
Short name T711
Test name
Test status
Simulation time 216260722149 ps
CPU time 2990.29 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 06:09:16 PM PDT 24
Peak memory 289048 kb
Host smart-98c0db11-6ae6-4a02-8150-e5a5bfb28646
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652173251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1652173251
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3367007119
Short name T674
Test name
Test status
Simulation time 267394910373 ps
CPU time 2553.05 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 06:02:07 PM PDT 24
Peak memory 289572 kb
Host smart-2a36d9cd-ad3d-4a43-b872-9af142893085
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367007119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3367007119
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2030794007
Short name T558
Test name
Test status
Simulation time 7371067527 ps
CPU time 149.47 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 05:21:55 PM PDT 24
Peak memory 247680 kb
Host smart-81ad1697-ca12-423e-a579-47959e8f1044
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030794007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2030794007
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1628230400
Short name T21
Test name
Test status
Simulation time 626362415 ps
CPU time 9.66 seconds
Started Jul 28 05:19:24 PM PDT 24
Finished Jul 28 05:19:33 PM PDT 24
Peak memory 252876 kb
Host smart-e757c471-b11f-4c29-9b00-223dd837244a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16282
30400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1628230400
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3054283891
Short name T653
Test name
Test status
Simulation time 923041420 ps
CPU time 13.8 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:19:37 PM PDT 24
Peak memory 248240 kb
Host smart-85f4de85-b71c-40d3-b100-f1cc2d823575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30542
83891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3054283891
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.331383241
Short name T584
Test name
Test status
Simulation time 5762143461 ps
CPU time 22.17 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:19:56 PM PDT 24
Peak memory 248168 kb
Host smart-e2581f85-5130-4440-8f22-aa2312b414ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33138
3241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.331383241
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3434851922
Short name T613
Test name
Test status
Simulation time 544328586 ps
CPU time 24.25 seconds
Started Jul 28 05:19:35 PM PDT 24
Finished Jul 28 05:20:00 PM PDT 24
Peak memory 256952 kb
Host smart-49d9cf2e-a3ed-44d2-ab48-7bb6f8171e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34348
51922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3434851922
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.174665125
Short name T517
Test name
Test status
Simulation time 51576007159 ps
CPU time 3082.89 seconds
Started Jul 28 05:19:30 PM PDT 24
Finished Jul 28 06:10:54 PM PDT 24
Peak memory 289632 kb
Host smart-eab024f5-c3a3-4176-bce8-22d70d7cdff9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174665125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.174665125
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3700081168
Short name T429
Test name
Test status
Simulation time 1798392068 ps
CPU time 138.78 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:21:41 PM PDT 24
Peak memory 256556 kb
Host smart-c7a03979-2bda-46fe-a732-534068b5b89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37000
81168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3700081168
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3725755649
Short name T694
Test name
Test status
Simulation time 4016566571 ps
CPU time 63 seconds
Started Jul 28 05:19:30 PM PDT 24
Finished Jul 28 05:20:33 PM PDT 24
Peak memory 256500 kb
Host smart-907b53cd-52fa-4b7e-991d-83411ff74239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37257
55649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3725755649
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2164272696
Short name T12
Test name
Test status
Simulation time 59153635556 ps
CPU time 3494.43 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 06:17:48 PM PDT 24
Peak memory 289064 kb
Host smart-ac6ea11b-59e3-47c5-9fec-df71ee03ea8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164272696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2164272696
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.726436207
Short name T527
Test name
Test status
Simulation time 529980002 ps
CPU time 23.92 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 05:19:49 PM PDT 24
Peak memory 248816 kb
Host smart-35cf2f07-d94c-4aef-af6f-98d6ecef7535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72643
6207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.726436207
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2130691538
Short name T675
Test name
Test status
Simulation time 399419590 ps
CPU time 8.12 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:19:32 PM PDT 24
Peak memory 248324 kb
Host smart-55e07152-d1d2-4da1-b1bf-1741508dca10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21306
91538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2130691538
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1620990734
Short name T200
Test name
Test status
Simulation time 206348262 ps
CPU time 11.99 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:19:35 PM PDT 24
Peak memory 253772 kb
Host smart-7219e423-87fa-40b3-a9af-ad88db3afbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16209
90734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1620990734
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3737714483
Short name T490
Test name
Test status
Simulation time 12587802365 ps
CPU time 1380.62 seconds
Started Jul 28 05:19:22 PM PDT 24
Finished Jul 28 05:42:23 PM PDT 24
Peak memory 288440 kb
Host smart-4d7a2be7-6c70-48ca-90ce-8e51dee3693e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737714483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3737714483
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2367174391
Short name T212
Test name
Test status
Simulation time 48014882 ps
CPU time 4.01 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:18:59 PM PDT 24
Peak memory 249060 kb
Host smart-e6f22704-1bbe-4804-9030-93c1106d59de
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2367174391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2367174391
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.834625974
Short name T51
Test name
Test status
Simulation time 169846018305 ps
CPU time 2472.98 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 06:00:08 PM PDT 24
Peak memory 281832 kb
Host smart-13b4e3b8-bc6c-430a-84c2-ed787f0b98d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834625974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.834625974
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3302242281
Short name T376
Test name
Test status
Simulation time 1516184016 ps
CPU time 38.91 seconds
Started Jul 28 05:18:40 PM PDT 24
Finished Jul 28 05:19:19 PM PDT 24
Peak memory 249776 kb
Host smart-b0a218f4-87c1-420c-8c74-bbed77d38fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33022
42281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3302242281
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1649462910
Short name T560
Test name
Test status
Simulation time 470523898 ps
CPU time 31.69 seconds
Started Jul 28 05:18:52 PM PDT 24
Finished Jul 28 05:19:24 PM PDT 24
Peak memory 256244 kb
Host smart-da220753-c654-41d3-aaf3-0331c298780f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16494
62910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1649462910
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2366932943
Short name T303
Test name
Test status
Simulation time 73100024204 ps
CPU time 2543.62 seconds
Started Jul 28 05:18:49 PM PDT 24
Finished Jul 28 06:01:13 PM PDT 24
Peak memory 289128 kb
Host smart-6a7d6c93-5c34-4a6b-b51e-675998258fad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366932943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2366932943
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.946445500
Short name T35
Test name
Test status
Simulation time 8592467587 ps
CPU time 801.48 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:32:10 PM PDT 24
Peak memory 273296 kb
Host smart-99593ecf-1dea-4292-8c3d-ea48662fe5a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946445500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.946445500
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3289492677
Short name T37
Test name
Test status
Simulation time 13373670464 ps
CPU time 562.41 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:28:17 PM PDT 24
Peak memory 248728 kb
Host smart-c1ffc2f1-7888-4779-8715-c1de16a80dd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289492677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3289492677
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2998123126
Short name T380
Test name
Test status
Simulation time 1453297043 ps
CPU time 33.87 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:19:29 PM PDT 24
Peak memory 248752 kb
Host smart-647bfe2c-4f99-4f1f-bd4f-c2a60c9d856e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29981
23126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2998123126
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2813653933
Short name T696
Test name
Test status
Simulation time 763374285 ps
CPU time 47.12 seconds
Started Jul 28 05:18:50 PM PDT 24
Finished Jul 28 05:19:37 PM PDT 24
Peak memory 256344 kb
Host smart-303978fc-c2f4-4fac-b52f-0beb8e8cde42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28136
53933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2813653933
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.4092939700
Short name T28
Test name
Test status
Simulation time 882604296 ps
CPU time 38.7 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:19:33 PM PDT 24
Peak memory 271040 kb
Host smart-42c7108e-ddb4-45d6-a5b3-d968bd79b88d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4092939700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.4092939700
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.337686383
Short name T68
Test name
Test status
Simulation time 589528904 ps
CPU time 20.54 seconds
Started Jul 28 05:18:59 PM PDT 24
Finished Jul 28 05:19:20 PM PDT 24
Peak memory 248412 kb
Host smart-2b21dc4e-10dc-49eb-bb8a-bdc07444d9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33768
6383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.337686383
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.938334553
Short name T610
Test name
Test status
Simulation time 852747295 ps
CPU time 18.89 seconds
Started Jul 28 05:18:41 PM PDT 24
Finished Jul 28 05:19:00 PM PDT 24
Peak memory 256952 kb
Host smart-94d20847-6435-4999-ae99-680527418aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93833
4553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.938334553
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.305757835
Short name T234
Test name
Test status
Simulation time 209630949435 ps
CPU time 5559.01 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 06:51:33 PM PDT 24
Peak memory 306100 kb
Host smart-9a04cdf8-1dbd-4011-98c0-e8e49490d2a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305757835 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.305757835
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3567842692
Short name T605
Test name
Test status
Simulation time 18231951988 ps
CPU time 1068.74 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:37:28 PM PDT 24
Peak memory 271728 kb
Host smart-987dc1a5-6a4b-4d94-89e7-30810d5c4876
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567842692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3567842692
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1910425899
Short name T424
Test name
Test status
Simulation time 13218729006 ps
CPU time 297.13 seconds
Started Jul 28 05:19:34 PM PDT 24
Finished Jul 28 05:24:32 PM PDT 24
Peak memory 257072 kb
Host smart-6a7d28e3-06da-49bf-a879-39aceeca0aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19104
25899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1910425899
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3819453288
Short name T74
Test name
Test status
Simulation time 35793557 ps
CPU time 3.78 seconds
Started Jul 28 05:19:34 PM PDT 24
Finished Jul 28 05:19:38 PM PDT 24
Peak memory 240276 kb
Host smart-bb06da8e-6b71-4c80-b59b-4b9a756679c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38194
53288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3819453288
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1622705223
Short name T350
Test name
Test status
Simulation time 11023598225 ps
CPU time 1207.85 seconds
Started Jul 28 05:19:43 PM PDT 24
Finished Jul 28 05:39:52 PM PDT 24
Peak memory 273408 kb
Host smart-80b02114-d11a-4777-be86-82824c3be254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622705223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1622705223
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3038423168
Short name T463
Test name
Test status
Simulation time 157676307588 ps
CPU time 1621.31 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:46:39 PM PDT 24
Peak memory 270300 kb
Host smart-fe31efd3-f4dd-44a1-bc28-26b596c9ab5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038423168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3038423168
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3913910116
Short name T328
Test name
Test status
Simulation time 9904791040 ps
CPU time 387.89 seconds
Started Jul 28 05:19:32 PM PDT 24
Finished Jul 28 05:26:00 PM PDT 24
Peak memory 248880 kb
Host smart-05835a97-f155-4712-b78b-cdd5c1dc301b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913910116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3913910116
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.797582987
Short name T395
Test name
Test status
Simulation time 1472013991 ps
CPU time 33.02 seconds
Started Jul 28 05:19:21 PM PDT 24
Finished Jul 28 05:19:54 PM PDT 24
Peak memory 248796 kb
Host smart-9ea4fbe8-4e83-4033-aeb5-f206be021c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79758
2987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.797582987
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3145778015
Short name T500
Test name
Test status
Simulation time 464381885 ps
CPU time 11.26 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 05:19:36 PM PDT 24
Peak memory 256064 kb
Host smart-003997c1-4fad-4782-b3d3-d59e2a69854b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457
78015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3145778015
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.4031599602
Short name T92
Test name
Test status
Simulation time 345838926 ps
CPU time 26.64 seconds
Started Jul 28 05:19:41 PM PDT 24
Finished Jul 28 05:20:08 PM PDT 24
Peak memory 248432 kb
Host smart-c1f2ef0f-9b8a-4b9c-82da-71ad7777f952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40315
99602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.4031599602
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.912341346
Short name T627
Test name
Test status
Simulation time 222468397 ps
CPU time 25.06 seconds
Started Jul 28 05:19:25 PM PDT 24
Finished Jul 28 05:19:50 PM PDT 24
Peak memory 256848 kb
Host smart-e6272627-ce89-4176-9e1e-3608878a0ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91234
1346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.912341346
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1269561719
Short name T53
Test name
Test status
Simulation time 161504841343 ps
CPU time 2687.91 seconds
Started Jul 28 05:19:31 PM PDT 24
Finished Jul 28 06:04:19 PM PDT 24
Peak memory 289132 kb
Host smart-f5273a2d-42cd-4c72-82ca-1c8cd408ea4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269561719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1269561719
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1064361221
Short name T634
Test name
Test status
Simulation time 106731510587 ps
CPU time 5877.44 seconds
Started Jul 28 05:19:36 PM PDT 24
Finished Jul 28 06:57:34 PM PDT 24
Peak memory 339072 kb
Host smart-0ffb9463-6d07-4808-a715-38c5e1ed05e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064361221 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1064361221
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3917361345
Short name T18
Test name
Test status
Simulation time 29157420574 ps
CPU time 1374.03 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:42:32 PM PDT 24
Peak memory 273448 kb
Host smart-0f82ec22-840d-4f7d-b981-70b36f245b96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917361345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3917361345
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2531217268
Short name T526
Test name
Test status
Simulation time 99312371 ps
CPU time 11.36 seconds
Started Jul 28 05:19:41 PM PDT 24
Finished Jul 28 05:19:53 PM PDT 24
Peak memory 256240 kb
Host smart-1978e633-9e09-4731-b66e-67e0196962a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25312
17268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2531217268
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3062836282
Short name T603
Test name
Test status
Simulation time 309523042 ps
CPU time 18.83 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:19:58 PM PDT 24
Peak memory 248960 kb
Host smart-59a8603e-dec5-47a1-87fa-3f17b959f7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30628
36282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3062836282
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1446946587
Short name T513
Test name
Test status
Simulation time 89598034222 ps
CPU time 2768.42 seconds
Started Jul 28 05:19:26 PM PDT 24
Finished Jul 28 06:05:35 PM PDT 24
Peak memory 286568 kb
Host smart-4e2e4a72-a31c-4b36-ba9a-f69e4d15a526
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446946587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1446946587
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.4154842777
Short name T651
Test name
Test status
Simulation time 11213771654 ps
CPU time 222.64 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:23:20 PM PDT 24
Peak memory 255808 kb
Host smart-52e1ed91-816c-4f42-99bf-fa4a40e098bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154842777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4154842777
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3722122315
Short name T509
Test name
Test status
Simulation time 248310440 ps
CPU time 8.09 seconds
Started Jul 28 05:19:41 PM PDT 24
Finished Jul 28 05:19:50 PM PDT 24
Peak memory 251620 kb
Host smart-edbe38aa-f7e1-4e01-9911-b15fa6590098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37221
22315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3722122315
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3787332552
Short name T607
Test name
Test status
Simulation time 1731328726 ps
CPU time 41.67 seconds
Started Jul 28 05:19:34 PM PDT 24
Finished Jul 28 05:20:16 PM PDT 24
Peak memory 255848 kb
Host smart-22b347c9-c405-4ae2-a378-811abbe288f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37873
32552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3787332552
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1840524197
Short name T276
Test name
Test status
Simulation time 344666408 ps
CPU time 24.92 seconds
Started Jul 28 05:19:35 PM PDT 24
Finished Jul 28 05:20:00 PM PDT 24
Peak memory 256028 kb
Host smart-7470b8aa-5221-482b-9af0-f945f2a11b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18405
24197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1840524197
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1642645288
Short name T685
Test name
Test status
Simulation time 356653755 ps
CPU time 6.74 seconds
Started Jul 28 05:19:35 PM PDT 24
Finished Jul 28 05:19:42 PM PDT 24
Peak memory 248708 kb
Host smart-3508e31c-d9dd-45e5-9ffb-897cf3762855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426
45288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1642645288
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2867137481
Short name T641
Test name
Test status
Simulation time 45337442861 ps
CPU time 2570.68 seconds
Started Jul 28 05:19:31 PM PDT 24
Finished Jul 28 06:02:23 PM PDT 24
Peak memory 287016 kb
Host smart-e4b99bd1-c63d-4617-9d88-ed1c662b1beb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867137481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2867137481
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3377126870
Short name T400
Test name
Test status
Simulation time 322241218 ps
CPU time 33.96 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:20:11 PM PDT 24
Peak memory 256484 kb
Host smart-e08e17b2-a60f-498b-9cdf-0292abb44047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33771
26870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3377126870
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3097950282
Short name T508
Test name
Test status
Simulation time 801683906 ps
CPU time 52.48 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:20:25 PM PDT 24
Peak memory 256568 kb
Host smart-bcf23ae1-83e2-415d-bde4-b07eeee0a63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30979
50282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3097950282
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.274645773
Short name T347
Test name
Test status
Simulation time 109005246824 ps
CPU time 1853.65 seconds
Started Jul 28 05:19:32 PM PDT 24
Finished Jul 28 05:50:26 PM PDT 24
Peak memory 273256 kb
Host smart-c35e99d8-8847-44ee-87af-2964996b49cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274645773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.274645773
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.243269378
Short name T469
Test name
Test status
Simulation time 15382689981 ps
CPU time 1508.05 seconds
Started Jul 28 05:19:31 PM PDT 24
Finished Jul 28 05:44:40 PM PDT 24
Peak memory 289864 kb
Host smart-efa07b9c-dc8f-4fa0-97fb-cb5ca322c2e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243269378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.243269378
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3287879240
Short name T398
Test name
Test status
Simulation time 3529222279 ps
CPU time 35.73 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:20:09 PM PDT 24
Peak memory 256380 kb
Host smart-772aada5-4d26-4ba5-96b0-3258a77f500c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878
79240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3287879240
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3766121208
Short name T52
Test name
Test status
Simulation time 564253647 ps
CPU time 27.39 seconds
Started Jul 28 05:19:32 PM PDT 24
Finished Jul 28 05:19:59 PM PDT 24
Peak memory 256508 kb
Host smart-d1c79dc8-0ad4-432e-bb0c-a30b50775c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37661
21208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3766121208
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3723542797
Short name T572
Test name
Test status
Simulation time 326016092 ps
CPU time 35.88 seconds
Started Jul 28 05:19:35 PM PDT 24
Finished Jul 28 05:20:11 PM PDT 24
Peak memory 249760 kb
Host smart-459af8c0-c068-4791-8e47-1f5632b5955f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37235
42797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3723542797
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.4029539659
Short name T669
Test name
Test status
Simulation time 1572442584 ps
CPU time 52.52 seconds
Started Jul 28 05:19:35 PM PDT 24
Finished Jul 28 05:20:28 PM PDT 24
Peak memory 256968 kb
Host smart-5d8c2b08-4c47-4792-938c-296a924ad673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40295
39659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4029539659
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3208831463
Short name T488
Test name
Test status
Simulation time 870261525 ps
CPU time 48.73 seconds
Started Jul 28 05:19:36 PM PDT 24
Finished Jul 28 05:20:25 PM PDT 24
Peak memory 248760 kb
Host smart-dc800c96-6983-4397-aa67-8eea244788de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208831463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3208831463
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2340509169
Short name T391
Test name
Test status
Simulation time 12114057487 ps
CPU time 1469.88 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:44:10 PM PDT 24
Peak memory 289432 kb
Host smart-c531684d-c14d-4c5b-b3cf-57d4775897e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340509169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2340509169
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.816889567
Short name T196
Test name
Test status
Simulation time 3724682648 ps
CPU time 68.02 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:20:41 PM PDT 24
Peak memory 256364 kb
Host smart-dae6774d-e34d-4869-9a1f-bd2c455448ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81688
9567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.816889567
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.664615259
Short name T377
Test name
Test status
Simulation time 1470377773 ps
CPU time 27.97 seconds
Started Jul 28 05:19:38 PM PDT 24
Finished Jul 28 05:20:06 PM PDT 24
Peak memory 256832 kb
Host smart-9b536733-61bd-48bb-8285-a953269581ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66461
5259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.664615259
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1108568572
Short name T633
Test name
Test status
Simulation time 433363925165 ps
CPU time 2512.58 seconds
Started Jul 28 05:19:42 PM PDT 24
Finished Jul 28 06:01:35 PM PDT 24
Peak memory 289680 kb
Host smart-74581f18-ee83-46bd-ba51-b03ab56f9430
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108568572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1108568572
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2744736645
Short name T654
Test name
Test status
Simulation time 2979067845 ps
CPU time 30.21 seconds
Started Jul 28 05:19:30 PM PDT 24
Finished Jul 28 05:20:00 PM PDT 24
Peak memory 256280 kb
Host smart-1edc65d2-fefb-488d-a5f6-a0ac9682e21f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27447
36645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2744736645
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1059029633
Short name T22
Test name
Test status
Simulation time 641149306 ps
CPU time 39.29 seconds
Started Jul 28 05:19:44 PM PDT 24
Finished Jul 28 05:20:24 PM PDT 24
Peak memory 255912 kb
Host smart-eb8a0ec7-bd6a-4d89-a9d1-0121b75b8c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10590
29633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1059029633
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.4042609281
Short name T266
Test name
Test status
Simulation time 264536652 ps
CPU time 19.09 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:19:56 PM PDT 24
Peak memory 248296 kb
Host smart-5489bb8f-3e4f-47fc-b570-0eb671562af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40426
09281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.4042609281
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.507055134
Short name T482
Test name
Test status
Simulation time 392661787 ps
CPU time 37.74 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:20:11 PM PDT 24
Peak memory 256992 kb
Host smart-8214866a-7aa2-437a-8262-675e9b6d903b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50705
5134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.507055134
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2748930934
Short name T69
Test name
Test status
Simulation time 39272591281 ps
CPU time 1556.42 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:45:36 PM PDT 24
Peak memory 289572 kb
Host smart-60b50fc6-6f1d-4314-bf67-47533abb85a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748930934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2748930934
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1367402096
Short name T417
Test name
Test status
Simulation time 75432788754 ps
CPU time 2645.61 seconds
Started Jul 28 05:19:32 PM PDT 24
Finished Jul 28 06:03:38 PM PDT 24
Peak memory 289524 kb
Host smart-a006df94-6ff1-4503-be22-9b32326f63a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367402096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1367402096
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1916999608
Short name T233
Test name
Test status
Simulation time 3838680379 ps
CPU time 205.01 seconds
Started Jul 28 05:19:43 PM PDT 24
Finished Jul 28 05:23:08 PM PDT 24
Peak memory 257056 kb
Host smart-74b68637-43f7-4b0d-b7c5-50da55aac609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19169
99608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1916999608
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.303105067
Short name T76
Test name
Test status
Simulation time 4363728912 ps
CPU time 67.38 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:20:45 PM PDT 24
Peak memory 256688 kb
Host smart-8c0b5204-c0e9-4665-9100-7ca9e3fcfabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30310
5067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.303105067
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1157027272
Short name T339
Test name
Test status
Simulation time 10305147799 ps
CPU time 944.28 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:35:18 PM PDT 24
Peak memory 273304 kb
Host smart-9f806a8e-9fd5-4212-abd9-1c9316aa3165
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157027272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1157027272
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1000947925
Short name T419
Test name
Test status
Simulation time 25008147450 ps
CPU time 1768.13 seconds
Started Jul 28 05:19:41 PM PDT 24
Finished Jul 28 05:49:10 PM PDT 24
Peak memory 273340 kb
Host smart-d3f1deeb-2511-4e28-9817-5b1b3fe3728b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000947925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1000947925
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3074637731
Short name T661
Test name
Test status
Simulation time 21509424567 ps
CPU time 451.03 seconds
Started Jul 28 05:19:33 PM PDT 24
Finished Jul 28 05:27:04 PM PDT 24
Peak memory 247788 kb
Host smart-d5c68fe7-bb7e-49c5-9aed-5b2073d1c32f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074637731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3074637731
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3451420756
Short name T453
Test name
Test status
Simulation time 630922318 ps
CPU time 21.96 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:19:59 PM PDT 24
Peak memory 248816 kb
Host smart-ab02e50f-9426-4d09-9743-6cd2e94f2960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34514
20756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3451420756
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.152998867
Short name T451
Test name
Test status
Simulation time 1000821474 ps
CPU time 9.84 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:19:48 PM PDT 24
Peak memory 248128 kb
Host smart-9bb8d8ff-da1c-47df-819c-0f58cc92752c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15299
8867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.152998867
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1744489772
Short name T283
Test name
Test status
Simulation time 8633733199 ps
CPU time 62.58 seconds
Started Jul 28 05:19:40 PM PDT 24
Finished Jul 28 05:20:43 PM PDT 24
Peak memory 248884 kb
Host smart-dcd898e8-6551-4b06-978d-c32b52ec160c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17444
89772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1744489772
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3536533506
Short name T231
Test name
Test status
Simulation time 3271841852 ps
CPU time 47.42 seconds
Started Jul 28 05:19:32 PM PDT 24
Finished Jul 28 05:20:20 PM PDT 24
Peak memory 257016 kb
Host smart-5f0c7f61-b316-42f5-aebd-0a5dcdd30ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35365
33506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3536533506
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3742585128
Short name T264
Test name
Test status
Simulation time 24957609300 ps
CPU time 1289.61 seconds
Started Jul 28 05:19:35 PM PDT 24
Finished Jul 28 05:41:05 PM PDT 24
Peak memory 288048 kb
Host smart-efdb4570-dad0-4ef7-95b4-152228938ed8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742585128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3742585128
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1422528717
Short name T598
Test name
Test status
Simulation time 57391328499 ps
CPU time 1852.11 seconds
Started Jul 28 05:19:35 PM PDT 24
Finished Jul 28 05:50:28 PM PDT 24
Peak memory 273452 kb
Host smart-05cd2ac5-84ba-47d5-a280-b3ab487cc8a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422528717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1422528717
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.665823792
Short name T370
Test name
Test status
Simulation time 142170278 ps
CPU time 9 seconds
Started Jul 28 05:19:40 PM PDT 24
Finished Jul 28 05:19:49 PM PDT 24
Peak memory 254596 kb
Host smart-9fdfd98c-540e-4df9-9e3b-fdb750c64a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66582
3792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.665823792
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.59417421
Short name T670
Test name
Test status
Simulation time 217701390 ps
CPU time 4.56 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:19:41 PM PDT 24
Peak memory 240220 kb
Host smart-bc0d9364-f551-4702-a9e2-7e57c1660db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59417
421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.59417421
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.525089696
Short name T341
Test name
Test status
Simulation time 78160396101 ps
CPU time 1306.24 seconds
Started Jul 28 05:19:50 PM PDT 24
Finished Jul 28 05:41:37 PM PDT 24
Peak memory 272472 kb
Host smart-3fd45c91-8dda-4a0a-811d-037b4023f759
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525089696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.525089696
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1085070115
Short name T433
Test name
Test status
Simulation time 30173587027 ps
CPU time 1938.63 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:51:58 PM PDT 24
Peak memory 285932 kb
Host smart-afc6f8f2-9593-41e5-9231-8099e596b8d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085070115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1085070115
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2980084097
Short name T494
Test name
Test status
Simulation time 1150289233 ps
CPU time 22.18 seconds
Started Jul 28 05:19:43 PM PDT 24
Finished Jul 28 05:20:06 PM PDT 24
Peak memory 248808 kb
Host smart-ba4bda14-0c55-4ee7-aac2-6a9926732781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29800
84097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2980084097
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.4233867659
Short name T514
Test name
Test status
Simulation time 1275228212 ps
CPU time 21.8 seconds
Started Jul 28 05:19:42 PM PDT 24
Finished Jul 28 05:20:04 PM PDT 24
Peak memory 255572 kb
Host smart-66953abf-7b92-4ff5-96b8-e120acd4c9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42338
67659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4233867659
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3221606615
Short name T425
Test name
Test status
Simulation time 1348392860 ps
CPU time 22.27 seconds
Started Jul 28 05:19:36 PM PDT 24
Finished Jul 28 05:19:58 PM PDT 24
Peak memory 248336 kb
Host smart-6fe41476-0a60-4d9d-b2f3-48811e24d1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32216
06615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3221606615
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3493982838
Short name T466
Test name
Test status
Simulation time 403139708 ps
CPU time 7.03 seconds
Started Jul 28 05:19:38 PM PDT 24
Finished Jul 28 05:19:45 PM PDT 24
Peak memory 253388 kb
Host smart-eb6c2f48-f650-4a55-9169-ce34f6d5fb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34939
82838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3493982838
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1361461143
Short name T604
Test name
Test status
Simulation time 1755756983 ps
CPU time 167.9 seconds
Started Jul 28 05:19:43 PM PDT 24
Finished Jul 28 05:22:31 PM PDT 24
Peak memory 252304 kb
Host smart-3d8cfcd4-917f-4f68-a9c1-bc2ff9f89679
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361461143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1361461143
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.271489456
Short name T27
Test name
Test status
Simulation time 13122437332 ps
CPU time 1263.29 seconds
Started Jul 28 05:19:49 PM PDT 24
Finished Jul 28 05:40:53 PM PDT 24
Peak memory 288880 kb
Host smart-d2fdf72d-875a-4f86-8733-6979bbcce17b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271489456 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.271489456
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.33330954
Short name T506
Test name
Test status
Simulation time 9121352739 ps
CPU time 1288.42 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:41:07 PM PDT 24
Peak memory 288092 kb
Host smart-14a8e205-8fec-4e3b-a1af-b3e99575908c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33330954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.33330954
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3961845283
Short name T476
Test name
Test status
Simulation time 1048023204 ps
CPU time 8.18 seconds
Started Jul 28 05:19:42 PM PDT 24
Finished Jul 28 05:19:51 PM PDT 24
Peak memory 254808 kb
Host smart-97880c35-4b0d-4c5b-9c5f-d59fe4bc226e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39618
45283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3961845283
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1954785698
Short name T75
Test name
Test status
Simulation time 1284418483 ps
CPU time 40.3 seconds
Started Jul 28 05:19:47 PM PDT 24
Finished Jul 28 05:20:27 PM PDT 24
Peak memory 256944 kb
Host smart-f74501fd-46e0-4caa-b3f1-9cca21f915fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19547
85698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1954785698
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3452222816
Short name T342
Test name
Test status
Simulation time 74254797837 ps
CPU time 1882.75 seconds
Started Jul 28 05:19:41 PM PDT 24
Finished Jul 28 05:51:04 PM PDT 24
Peak memory 272744 kb
Host smart-eed9757f-f576-42e6-b07b-8d4ccb6e58bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452222816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3452222816
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.819791245
Short name T585
Test name
Test status
Simulation time 15334831497 ps
CPU time 1035.8 seconds
Started Jul 28 05:19:41 PM PDT 24
Finished Jul 28 05:36:57 PM PDT 24
Peak memory 272424 kb
Host smart-33e4334e-b138-43d2-93ae-66b200d431b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819791245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.819791245
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1861737563
Short name T593
Test name
Test status
Simulation time 20653483057 ps
CPU time 252.22 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:23:51 PM PDT 24
Peak memory 247840 kb
Host smart-11ae3e90-6dde-469c-847c-a0bf78405651
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861737563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1861737563
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1341502023
Short name T43
Test name
Test status
Simulation time 1653922290 ps
CPU time 26.97 seconds
Started Jul 28 05:19:40 PM PDT 24
Finished Jul 28 05:20:07 PM PDT 24
Peak memory 256276 kb
Host smart-2b04f773-415f-482f-b711-5e8849595688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13415
02023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1341502023
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3028375587
Short name T60
Test name
Test status
Simulation time 559846472 ps
CPU time 26.7 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:20:06 PM PDT 24
Peak memory 248348 kb
Host smart-8a33dc26-bdfa-4d29-ba0f-a795c06dfcde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30283
75587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3028375587
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2976765368
Short name T277
Test name
Test status
Simulation time 709014618 ps
CPU time 46.59 seconds
Started Jul 28 05:19:37 PM PDT 24
Finished Jul 28 05:20:24 PM PDT 24
Peak memory 256156 kb
Host smart-83e445ae-8718-4bd1-9e7b-6912977bf97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767
65368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2976765368
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.610032009
Short name T438
Test name
Test status
Simulation time 887011336 ps
CPU time 58.65 seconds
Started Jul 28 05:19:44 PM PDT 24
Finished Jul 28 05:20:43 PM PDT 24
Peak memory 256912 kb
Host smart-daaaa742-1fcd-4abc-afbb-7a24f94ee71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61003
2009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.610032009
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1472356786
Short name T282
Test name
Test status
Simulation time 72653246547 ps
CPU time 2339.08 seconds
Started Jul 28 05:19:39 PM PDT 24
Finished Jul 28 05:58:39 PM PDT 24
Peak memory 289768 kb
Host smart-5fbb3677-2f31-4f80-a090-7b89af8828ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472356786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1472356786
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3570952954
Short name T289
Test name
Test status
Simulation time 55806904002 ps
CPU time 1425.27 seconds
Started Jul 28 05:19:50 PM PDT 24
Finished Jul 28 05:43:35 PM PDT 24
Peak memory 289328 kb
Host smart-b50be094-42fc-4d97-a85e-7339724cc043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570952954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3570952954
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1223210131
Short name T393
Test name
Test status
Simulation time 555607472 ps
CPU time 31.38 seconds
Started Jul 28 05:19:44 PM PDT 24
Finished Jul 28 05:20:16 PM PDT 24
Peak memory 256628 kb
Host smart-1f5a249a-a3aa-44a8-bd6c-3aa241a1414b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12232
10131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1223210131
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3989753286
Short name T559
Test name
Test status
Simulation time 98242953 ps
CPU time 4.03 seconds
Started Jul 28 05:19:44 PM PDT 24
Finished Jul 28 05:19:48 PM PDT 24
Peak memory 248308 kb
Host smart-e0e8ed5c-95f2-48a2-bb9e-04d0cc7c6df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39897
53286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3989753286
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2904054391
Short name T583
Test name
Test status
Simulation time 15328180998 ps
CPU time 1314.26 seconds
Started Jul 28 05:19:46 PM PDT 24
Finished Jul 28 05:41:40 PM PDT 24
Peak memory 289188 kb
Host smart-994c352b-d3f2-45b5-8ff3-2b92325bb522
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904054391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2904054391
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1427723284
Short name T236
Test name
Test status
Simulation time 16306998624 ps
CPU time 1468.87 seconds
Started Jul 28 05:19:44 PM PDT 24
Finished Jul 28 05:44:14 PM PDT 24
Peak memory 289816 kb
Host smart-30fc85d8-1c58-4ec8-a1c7-f3900e508e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427723284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1427723284
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2759232045
Short name T316
Test name
Test status
Simulation time 9577275220 ps
CPU time 183.46 seconds
Started Jul 28 05:19:42 PM PDT 24
Finished Jul 28 05:22:46 PM PDT 24
Peak memory 248592 kb
Host smart-0797e076-b4e6-44db-b7c0-3bc06274a60f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759232045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2759232045
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.527676706
Short name T477
Test name
Test status
Simulation time 1010411841 ps
CPU time 16.63 seconds
Started Jul 28 05:19:42 PM PDT 24
Finished Jul 28 05:19:58 PM PDT 24
Peak memory 255236 kb
Host smart-a56e07e5-ebca-4279-af79-4028e837d2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52767
6706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.527676706
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2084309433
Short name T251
Test name
Test status
Simulation time 1234229239 ps
CPU time 73.22 seconds
Started Jul 28 05:19:43 PM PDT 24
Finished Jul 28 05:20:56 PM PDT 24
Peak memory 256204 kb
Host smart-9f297014-9734-4555-aeb7-cb600705b895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20843
09433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2084309433
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1437562998
Short name T285
Test name
Test status
Simulation time 985937742 ps
CPU time 75.36 seconds
Started Jul 28 05:19:41 PM PDT 24
Finished Jul 28 05:20:56 PM PDT 24
Peak memory 248672 kb
Host smart-4c8defd4-4858-4d9e-90eb-76ad5e759746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14375
62998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1437562998
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.138380679
Short name T230
Test name
Test status
Simulation time 220517071 ps
CPU time 9.34 seconds
Started Jul 28 05:19:38 PM PDT 24
Finished Jul 28 05:19:47 PM PDT 24
Peak memory 249280 kb
Host smart-73158150-2701-4239-ae64-fa55a4053d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13838
0679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.138380679
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3598563622
Short name T678
Test name
Test status
Simulation time 16467141684 ps
CPU time 1099.99 seconds
Started Jul 28 05:19:49 PM PDT 24
Finished Jul 28 05:38:09 PM PDT 24
Peak memory 273392 kb
Host smart-8e4b358e-cbdf-4646-829f-6c7107860c3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598563622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3598563622
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.318425433
Short name T426
Test name
Test status
Simulation time 9741680450 ps
CPU time 70.37 seconds
Started Jul 28 05:19:44 PM PDT 24
Finished Jul 28 05:20:55 PM PDT 24
Peak memory 256552 kb
Host smart-bb9f003d-e01e-45b8-ac80-764b7e72bafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31842
5433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.318425433
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3827807668
Short name T373
Test name
Test status
Simulation time 19520360 ps
CPU time 3.07 seconds
Started Jul 28 05:19:46 PM PDT 24
Finished Jul 28 05:19:49 PM PDT 24
Peak memory 239888 kb
Host smart-c66a250c-eec7-4c88-9dae-2cc1e3744bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38278
07668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3827807668
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1506229974
Short name T695
Test name
Test status
Simulation time 32952262300 ps
CPU time 856.13 seconds
Started Jul 28 05:19:45 PM PDT 24
Finished Jul 28 05:34:01 PM PDT 24
Peak memory 273364 kb
Host smart-ed0c242b-fb11-4592-a373-e6ba52ac7d04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506229974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1506229974
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3897379233
Short name T2
Test name
Test status
Simulation time 45435972517 ps
CPU time 1407.81 seconds
Started Jul 28 05:19:54 PM PDT 24
Finished Jul 28 05:43:22 PM PDT 24
Peak memory 288884 kb
Host smart-4290d336-5669-4ab4-aea0-2206e28eb17b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897379233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3897379233
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2448929858
Short name T313
Test name
Test status
Simulation time 8799791326 ps
CPU time 346.12 seconds
Started Jul 28 05:19:47 PM PDT 24
Finished Jul 28 05:25:33 PM PDT 24
Peak memory 247744 kb
Host smart-a77aa32b-401b-406b-b597-4ae3e73ba34e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448929858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2448929858
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3244998325
Short name T495
Test name
Test status
Simulation time 1762838980 ps
CPU time 19.75 seconds
Started Jul 28 05:19:46 PM PDT 24
Finished Jul 28 05:20:06 PM PDT 24
Peak memory 256248 kb
Host smart-4cf1494c-9833-4ce4-b5ef-260db0344d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32449
98325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3244998325
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3616624485
Short name T105
Test name
Test status
Simulation time 740406325 ps
CPU time 51.56 seconds
Started Jul 28 05:19:47 PM PDT 24
Finished Jul 28 05:20:39 PM PDT 24
Peak memory 248844 kb
Host smart-03e647fd-01e4-4754-8051-d80d51226b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36166
24485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3616624485
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1760964501
Short name T116
Test name
Test status
Simulation time 474645546 ps
CPU time 30.96 seconds
Started Jul 28 05:19:43 PM PDT 24
Finished Jul 28 05:20:14 PM PDT 24
Peak memory 256356 kb
Host smart-2f1493ac-2193-4703-8679-f2cad177b4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17609
64501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1760964501
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2400888241
Short name T423
Test name
Test status
Simulation time 281269856 ps
CPU time 5.18 seconds
Started Jul 28 05:19:46 PM PDT 24
Finished Jul 28 05:19:52 PM PDT 24
Peak memory 251204 kb
Host smart-06825d2e-d141-4dea-8ef8-914800fe7e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24008
88241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2400888241
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.406749470
Short name T483
Test name
Test status
Simulation time 15934273196 ps
CPU time 196.26 seconds
Started Jul 28 05:19:45 PM PDT 24
Finished Jul 28 05:23:01 PM PDT 24
Peak memory 253356 kb
Host smart-7826be94-75a0-4d9a-a0e3-8c7da048c07a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406749470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.406749470
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2751072798
Short name T271
Test name
Test status
Simulation time 690701485646 ps
CPU time 4268.39 seconds
Started Jul 28 05:19:47 PM PDT 24
Finished Jul 28 06:30:56 PM PDT 24
Peak memory 334496 kb
Host smart-4486ff8e-313a-49cc-bb61-448cb5f78cb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751072798 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2751072798
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2809301232
Short name T588
Test name
Test status
Simulation time 10275891641 ps
CPU time 140.48 seconds
Started Jul 28 05:19:54 PM PDT 24
Finished Jul 28 05:22:15 PM PDT 24
Peak memory 257100 kb
Host smart-a01bb752-c7e6-4649-bc83-c927bb2a38fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28093
01232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2809301232
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3286415104
Short name T680
Test name
Test status
Simulation time 1422412220 ps
CPU time 41.81 seconds
Started Jul 28 05:19:50 PM PDT 24
Finished Jul 28 05:20:31 PM PDT 24
Peak memory 256632 kb
Host smart-9eb392ba-fd84-40b3-b566-9c547e663f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32864
15104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3286415104
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3493457945
Short name T577
Test name
Test status
Simulation time 74490197768 ps
CPU time 1115.61 seconds
Started Jul 28 05:19:54 PM PDT 24
Finished Jul 28 05:38:30 PM PDT 24
Peak memory 289528 kb
Host smart-a401740a-4876-4e6b-9ead-010f09dff326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493457945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3493457945
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.981604948
Short name T549
Test name
Test status
Simulation time 42565641368 ps
CPU time 1254.13 seconds
Started Jul 28 05:19:51 PM PDT 24
Finished Jul 28 05:40:46 PM PDT 24
Peak memory 270368 kb
Host smart-44a93413-3c54-4c1b-b83d-d768735064a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981604948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.981604948
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1016504296
Short name T479
Test name
Test status
Simulation time 7386113435 ps
CPU time 160.98 seconds
Started Jul 28 05:19:51 PM PDT 24
Finished Jul 28 05:22:32 PM PDT 24
Peak memory 247740 kb
Host smart-8f35c998-fdac-4bd8-aed6-4535ae97a247
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016504296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1016504296
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2691467406
Short name T658
Test name
Test status
Simulation time 547487568 ps
CPU time 9.65 seconds
Started Jul 28 05:19:45 PM PDT 24
Finished Jul 28 05:19:55 PM PDT 24
Peak memory 254612 kb
Host smart-02fba1f0-e19a-4a97-b4a2-6c6376533939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26914
67406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2691467406
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3909332205
Short name T629
Test name
Test status
Simulation time 1668985127 ps
CPU time 55.11 seconds
Started Jul 28 05:19:51 PM PDT 24
Finished Jul 28 05:20:46 PM PDT 24
Peak memory 248184 kb
Host smart-148ffe13-6b16-49da-94a9-e5084cab14f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39093
32205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3909332205
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1168545893
Short name T40
Test name
Test status
Simulation time 410366524 ps
CPU time 31.17 seconds
Started Jul 28 05:19:53 PM PDT 24
Finished Jul 28 05:20:24 PM PDT 24
Peak memory 249140 kb
Host smart-477fb848-ed71-43b5-9cce-a26ef90a2d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11685
45893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1168545893
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2958589431
Short name T542
Test name
Test status
Simulation time 26749893 ps
CPU time 3.24 seconds
Started Jul 28 05:19:49 PM PDT 24
Finished Jul 28 05:19:52 PM PDT 24
Peak memory 251016 kb
Host smart-3a3e174c-a6c2-443e-b689-91f62591b0bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29585
89431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2958589431
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1399648717
Short name T262
Test name
Test status
Simulation time 87323636368 ps
CPU time 502.13 seconds
Started Jul 28 05:19:53 PM PDT 24
Finished Jul 28 05:28:15 PM PDT 24
Peak memory 265792 kb
Host smart-e792a34a-3011-4da0-a356-297e94a6efad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399648717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1399648717
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2738267485
Short name T103
Test name
Test status
Simulation time 100382988761 ps
CPU time 5819.95 seconds
Started Jul 28 05:19:55 PM PDT 24
Finished Jul 28 06:56:56 PM PDT 24
Peak memory 349280 kb
Host smart-fe2dc820-3663-4952-880a-0359724395c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738267485 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2738267485
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3386075914
Short name T210
Test name
Test status
Simulation time 43169299 ps
CPU time 4.01 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:19:13 PM PDT 24
Peak memory 249092 kb
Host smart-e1d2fb81-f4f6-4a00-96e6-0f74dc59ad85
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3386075914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3386075914
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.862522558
Short name T402
Test name
Test status
Simulation time 40363525406 ps
CPU time 1235.48 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:39:24 PM PDT 24
Peak memory 287320 kb
Host smart-7a4e83ea-5fda-467f-b0e9-1ba15d759dc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862522558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.862522558
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.116481814
Short name T240
Test name
Test status
Simulation time 590486149 ps
CPU time 14.79 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:19:01 PM PDT 24
Peak memory 248784 kb
Host smart-d2282e21-1b8a-4ef9-a432-9d02577accb8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=116481814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.116481814
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1170088401
Short name T415
Test name
Test status
Simulation time 5611734771 ps
CPU time 46.36 seconds
Started Jul 28 05:18:47 PM PDT 24
Finished Jul 28 05:19:34 PM PDT 24
Peak memory 257028 kb
Host smart-7889f1bc-8850-438f-bd4b-4ee97c7cf9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11700
88401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1170088401
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2300984961
Short name T682
Test name
Test status
Simulation time 1342038901 ps
CPU time 78.66 seconds
Started Jul 28 05:18:57 PM PDT 24
Finished Jul 28 05:20:16 PM PDT 24
Peak memory 248840 kb
Host smart-4641635c-a20a-4726-acc5-3f33557f7fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23009
84961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2300984961
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2972632609
Short name T336
Test name
Test status
Simulation time 54176806514 ps
CPU time 3043.9 seconds
Started Jul 28 05:18:58 PM PDT 24
Finished Jul 28 06:09:42 PM PDT 24
Peak memory 289244 kb
Host smart-79c55a89-4048-4135-b670-8beb4f72b210
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972632609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2972632609
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.901340336
Short name T498
Test name
Test status
Simulation time 71499143348 ps
CPU time 1387.69 seconds
Started Jul 28 05:18:44 PM PDT 24
Finished Jul 28 05:41:52 PM PDT 24
Peak memory 289604 kb
Host smart-d5449694-00ff-42b7-89b2-0a37a41498d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901340336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.901340336
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1296489852
Short name T319
Test name
Test status
Simulation time 30921627841 ps
CPU time 312.48 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:24:08 PM PDT 24
Peak memory 248904 kb
Host smart-5a519339-4c56-4fa6-a3ef-678868a27944
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296489852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1296489852
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3650257224
Short name T50
Test name
Test status
Simulation time 239208789 ps
CPU time 9.48 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:18:58 PM PDT 24
Peak memory 248836 kb
Host smart-2eb57f3f-4d31-4d51-bf6c-359cee39718f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36502
57224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3650257224
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4137693661
Short name T253
Test name
Test status
Simulation time 593282143 ps
CPU time 45.07 seconds
Started Jul 28 05:18:52 PM PDT 24
Finished Jul 28 05:19:37 PM PDT 24
Peak memory 256528 kb
Host smart-45117c07-101b-4e01-b8d2-7088e353f430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41376
93661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4137693661
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.500149402
Short name T9
Test name
Test status
Simulation time 1563841805 ps
CPU time 18.62 seconds
Started Jul 28 05:18:49 PM PDT 24
Finished Jul 28 05:19:07 PM PDT 24
Peak memory 269748 kb
Host smart-c5a6c804-c583-4f22-8f58-72fcebd97815
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=500149402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.500149402
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.761919676
Short name T394
Test name
Test status
Simulation time 714555629 ps
CPU time 46.22 seconds
Started Jul 28 05:18:50 PM PDT 24
Finished Jul 28 05:19:36 PM PDT 24
Peak memory 256048 kb
Host smart-285e7408-2a9c-480b-99ce-7ebc7335fcba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76191
9676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.761919676
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1907236581
Short name T100
Test name
Test status
Simulation time 239110364 ps
CPU time 7.28 seconds
Started Jul 28 05:19:05 PM PDT 24
Finished Jul 28 05:19:13 PM PDT 24
Peak memory 255132 kb
Host smart-992b7ce2-3dc6-40b9-9d41-2604f00921b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19072
36581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1907236581
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4107887311
Short name T102
Test name
Test status
Simulation time 54579364003 ps
CPU time 2699.75 seconds
Started Jul 28 05:18:37 PM PDT 24
Finished Jul 28 06:03:37 PM PDT 24
Peak memory 317980 kb
Host smart-1de40ea5-c208-485c-8fbe-aaaa98d7d76c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107887311 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4107887311
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.78416668
Short name T575
Test name
Test status
Simulation time 43041174984 ps
CPU time 955.89 seconds
Started Jul 28 05:19:52 PM PDT 24
Finished Jul 28 05:35:48 PM PDT 24
Peak memory 273492 kb
Host smart-ec492f0e-5624-4ffd-8ab8-a5d87aa60c47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78416668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.78416668
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3007083445
Short name T619
Test name
Test status
Simulation time 2572818719 ps
CPU time 170.5 seconds
Started Jul 28 05:19:53 PM PDT 24
Finished Jul 28 05:22:44 PM PDT 24
Peak memory 256992 kb
Host smart-a889c3d3-e0b1-4ad4-b7c2-14c60eabcc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30070
83445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3007083445
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2522570497
Short name T62
Test name
Test status
Simulation time 306218402 ps
CPU time 25.45 seconds
Started Jul 28 05:19:48 PM PDT 24
Finished Jul 28 05:20:14 PM PDT 24
Peak memory 248840 kb
Host smart-2b0695af-a878-4837-8d85-88f361cb0f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25225
70497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2522570497
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3479153870
Short name T597
Test name
Test status
Simulation time 40727548534 ps
CPU time 2270.79 seconds
Started Jul 28 05:19:50 PM PDT 24
Finished Jul 28 05:57:41 PM PDT 24
Peak memory 283748 kb
Host smart-d2605f5a-722d-4437-a3ba-8ce50290feed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479153870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3479153870
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3030963463
Short name T412
Test name
Test status
Simulation time 35153024011 ps
CPU time 1160.02 seconds
Started Jul 28 05:19:52 PM PDT 24
Finished Jul 28 05:39:13 PM PDT 24
Peak memory 272316 kb
Host smart-fe0f8efc-13cb-42eb-b732-ed475a3493b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030963463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3030963463
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3341639847
Short name T329
Test name
Test status
Simulation time 19816135214 ps
CPU time 213.73 seconds
Started Jul 28 05:19:52 PM PDT 24
Finished Jul 28 05:23:26 PM PDT 24
Peak memory 248932 kb
Host smart-7f544ff4-7c18-4d28-bd27-edb05f6fd367
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341639847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3341639847
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3391639073
Short name T555
Test name
Test status
Simulation time 828411806 ps
CPU time 46.49 seconds
Started Jul 28 05:19:52 PM PDT 24
Finished Jul 28 05:20:38 PM PDT 24
Peak memory 256184 kb
Host smart-8be87ca4-f03e-46c0-a71d-11458b5ede95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33916
39073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3391639073
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3175388477
Short name T640
Test name
Test status
Simulation time 232956929 ps
CPU time 8.9 seconds
Started Jul 28 05:19:52 PM PDT 24
Finished Jul 28 05:20:01 PM PDT 24
Peak memory 248808 kb
Host smart-603d8e9d-d02e-4b3c-a0e9-26d0d8016e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31753
88477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3175388477
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.431262612
Short name T459
Test name
Test status
Simulation time 140321034 ps
CPU time 12.2 seconds
Started Jul 28 05:19:50 PM PDT 24
Finished Jul 28 05:20:02 PM PDT 24
Peak memory 248272 kb
Host smart-88879713-2f53-4d81-84b2-edec1a698563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43126
2612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.431262612
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1920754312
Short name T385
Test name
Test status
Simulation time 1146961224 ps
CPU time 17.47 seconds
Started Jul 28 05:19:53 PM PDT 24
Finished Jul 28 05:20:10 PM PDT 24
Peak memory 255036 kb
Host smart-660a0fc2-f44f-4c1f-8ea6-2cbff771e6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19207
54312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1920754312
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4145672203
Short name T44
Test name
Test status
Simulation time 64254727128 ps
CPU time 1744.55 seconds
Started Jul 28 05:19:55 PM PDT 24
Finished Jul 28 05:49:00 PM PDT 24
Peak memory 299772 kb
Host smart-e7e8784f-f1f7-4337-ac97-97f94ee4df87
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145672203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4145672203
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3863416894
Short name T57
Test name
Test status
Simulation time 58329469734 ps
CPU time 1918.09 seconds
Started Jul 28 05:19:56 PM PDT 24
Finished Jul 28 05:51:55 PM PDT 24
Peak memory 285124 kb
Host smart-26d3be4c-3e49-4e26-a8f2-1758ca2f7727
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863416894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3863416894
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2849294449
Short name T648
Test name
Test status
Simulation time 13898884834 ps
CPU time 195.72 seconds
Started Jul 28 05:19:55 PM PDT 24
Finished Jul 28 05:23:11 PM PDT 24
Peak memory 257044 kb
Host smart-7a09f572-b2d0-49af-89a6-e0d935b13667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28492
94449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2849294449
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2591951331
Short name T397
Test name
Test status
Simulation time 808007930 ps
CPU time 44.72 seconds
Started Jul 28 05:19:52 PM PDT 24
Finished Jul 28 05:20:36 PM PDT 24
Peak memory 256356 kb
Host smart-93b0d53b-86c3-4628-a763-c267f864731b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25919
51331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2591951331
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2420124250
Short name T201
Test name
Test status
Simulation time 260959132464 ps
CPU time 1713.05 seconds
Started Jul 28 05:19:55 PM PDT 24
Finished Jul 28 05:48:29 PM PDT 24
Peak memory 266168 kb
Host smart-4ad7df60-cad4-4841-ae5d-3baea808b572
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420124250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2420124250
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3035923704
Short name T592
Test name
Test status
Simulation time 184520874753 ps
CPU time 2061.71 seconds
Started Jul 28 05:20:00 PM PDT 24
Finished Jul 28 05:54:22 PM PDT 24
Peak memory 272756 kb
Host smart-84e87741-84bb-47b0-959c-34f66e42cda3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035923704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3035923704
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2160148011
Short name T427
Test name
Test status
Simulation time 698913388 ps
CPU time 18.04 seconds
Started Jul 28 05:19:49 PM PDT 24
Finished Jul 28 05:20:07 PM PDT 24
Peak memory 256168 kb
Host smart-e5dddb09-a7ab-4bef-9bd6-26c5e8d0b610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21601
48011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2160148011
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1023626551
Short name T30
Test name
Test status
Simulation time 278866347 ps
CPU time 21.65 seconds
Started Jul 28 05:19:54 PM PDT 24
Finished Jul 28 05:20:16 PM PDT 24
Peak memory 248348 kb
Host smart-4714b094-d253-49c2-a2c1-52451ddd0af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10236
26551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1023626551
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1100106595
Short name T503
Test name
Test status
Simulation time 48182415 ps
CPU time 7.01 seconds
Started Jul 28 05:20:01 PM PDT 24
Finished Jul 28 05:20:08 PM PDT 24
Peak memory 254792 kb
Host smart-640ec5de-f3c3-46ce-afa0-2725befc945a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11001
06595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1100106595
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3210225366
Short name T625
Test name
Test status
Simulation time 3617494028 ps
CPU time 55.6 seconds
Started Jul 28 05:19:50 PM PDT 24
Finished Jul 28 05:20:45 PM PDT 24
Peak memory 256956 kb
Host smart-d1542389-0f0e-4cdc-8307-2d31201a608f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32102
25366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3210225366
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2485502343
Short name T290
Test name
Test status
Simulation time 43442038548 ps
CPU time 2406.85 seconds
Started Jul 28 05:19:58 PM PDT 24
Finished Jul 28 06:00:05 PM PDT 24
Peak memory 285388 kb
Host smart-b231c078-d933-4de7-bb12-cbba171e4e94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485502343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2485502343
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2504146948
Short name T280
Test name
Test status
Simulation time 43889733614 ps
CPU time 2316.61 seconds
Started Jul 28 05:19:59 PM PDT 24
Finished Jul 28 05:58:36 PM PDT 24
Peak memory 288624 kb
Host smart-310ef3a0-eb7d-49d9-980d-8f6455d1f1d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504146948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2504146948
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3856472999
Short name T229
Test name
Test status
Simulation time 442325427 ps
CPU time 20.93 seconds
Started Jul 28 05:19:58 PM PDT 24
Finished Jul 28 05:20:19 PM PDT 24
Peak memory 255828 kb
Host smart-ae7df371-b7d3-451f-aa4e-2fa1d1f97b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38564
72999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3856472999
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2545224263
Short name T3
Test name
Test status
Simulation time 4853386655 ps
CPU time 46.63 seconds
Started Jul 28 05:19:58 PM PDT 24
Finished Jul 28 05:20:44 PM PDT 24
Peak memory 248748 kb
Host smart-b6cd8d6a-6a10-403c-b64b-e0e6712053c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25452
24263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2545224263
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1629820565
Short name T106
Test name
Test status
Simulation time 16430407244 ps
CPU time 1185.59 seconds
Started Jul 28 05:19:57 PM PDT 24
Finished Jul 28 05:39:43 PM PDT 24
Peak memory 285280 kb
Host smart-5225d811-7d98-4418-92e9-787ef9240b6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629820565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1629820565
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1984986305
Short name T496
Test name
Test status
Simulation time 12924253274 ps
CPU time 1234.99 seconds
Started Jul 28 05:19:58 PM PDT 24
Finished Jul 28 05:40:33 PM PDT 24
Peak memory 286052 kb
Host smart-5cfa11b0-36e2-4fb1-8955-a9212bf21379
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984986305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1984986305
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3600794778
Short name T317
Test name
Test status
Simulation time 29305641575 ps
CPU time 320.37 seconds
Started Jul 28 05:19:59 PM PDT 24
Finished Jul 28 05:25:19 PM PDT 24
Peak memory 248860 kb
Host smart-c4917a1f-0ca0-47fb-970b-7690a41a2e73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600794778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3600794778
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.401831280
Short name T431
Test name
Test status
Simulation time 649579439 ps
CPU time 25.15 seconds
Started Jul 28 05:19:58 PM PDT 24
Finished Jul 28 05:20:24 PM PDT 24
Peak memory 256036 kb
Host smart-87558486-12d3-4f42-b6b3-65e209d21fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40183
1280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.401831280
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1211887564
Short name T471
Test name
Test status
Simulation time 507939104 ps
CPU time 31.83 seconds
Started Jul 28 05:19:57 PM PDT 24
Finished Jul 28 05:20:29 PM PDT 24
Peak memory 256560 kb
Host smart-78c772c2-d425-42dc-82b0-09430af4b927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12118
87564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1211887564
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1011951679
Short name T265
Test name
Test status
Simulation time 4939941848 ps
CPU time 39.37 seconds
Started Jul 28 05:19:56 PM PDT 24
Finished Jul 28 05:20:35 PM PDT 24
Peak memory 248396 kb
Host smart-bf5be51d-aa73-46f7-84f7-cbdb42e12492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10119
51679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1011951679
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1341269831
Short name T366
Test name
Test status
Simulation time 1086150376 ps
CPU time 72.16 seconds
Started Jul 28 05:19:56 PM PDT 24
Finished Jul 28 05:21:09 PM PDT 24
Peak memory 248772 kb
Host smart-aee73e05-bc5d-4844-85d7-3046c4492ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13412
69831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1341269831
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.901067076
Short name T87
Test name
Test status
Simulation time 25294271443 ps
CPU time 1452.32 seconds
Started Jul 28 05:19:58 PM PDT 24
Finished Jul 28 05:44:11 PM PDT 24
Peak memory 273452 kb
Host smart-12babc89-aeb2-400f-aeb8-0e0060bfda9b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901067076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.901067076
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.4052022483
Short name T36
Test name
Test status
Simulation time 226712813418 ps
CPU time 4270.82 seconds
Started Jul 28 05:19:56 PM PDT 24
Finished Jul 28 06:31:07 PM PDT 24
Peak memory 338880 kb
Host smart-05706c35-b71f-4b2c-8a7c-311d721824eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052022483 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.4052022483
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3824294985
Short name T582
Test name
Test status
Simulation time 51099893397 ps
CPU time 1519.43 seconds
Started Jul 28 05:20:00 PM PDT 24
Finished Jul 28 05:45:20 PM PDT 24
Peak memory 273444 kb
Host smart-28f2e857-77a1-452b-81f5-48b626618360
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824294985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3824294985
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.971118161
Short name T571
Test name
Test status
Simulation time 7124497125 ps
CPU time 161.07 seconds
Started Jul 28 05:19:59 PM PDT 24
Finished Jul 28 05:22:40 PM PDT 24
Peak memory 257072 kb
Host smart-d6aabad1-d255-4a4b-bfd5-a0c6651a139e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97111
8161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.971118161
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3565322212
Short name T439
Test name
Test status
Simulation time 314366265 ps
CPU time 32.23 seconds
Started Jul 28 05:19:59 PM PDT 24
Finished Jul 28 05:20:31 PM PDT 24
Peak memory 248480 kb
Host smart-a7d450c4-da54-42da-be06-0a313a81fb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35653
22212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3565322212
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1906910258
Short name T594
Test name
Test status
Simulation time 499430563292 ps
CPU time 2755.21 seconds
Started Jul 28 05:20:03 PM PDT 24
Finished Jul 28 06:05:58 PM PDT 24
Peak memory 286056 kb
Host smart-c4ed74a3-7f29-4479-bd17-53285314703d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906910258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1906910258
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2669072988
Short name T461
Test name
Test status
Simulation time 225598466208 ps
CPU time 3299.44 seconds
Started Jul 28 05:20:03 PM PDT 24
Finished Jul 28 06:15:03 PM PDT 24
Peak memory 289496 kb
Host smart-cf6c48cc-4c62-4f58-98ee-b056ad2752ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669072988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2669072988
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1460178480
Short name T325
Test name
Test status
Simulation time 54073758445 ps
CPU time 547.08 seconds
Started Jul 28 05:20:05 PM PDT 24
Finished Jul 28 05:29:12 PM PDT 24
Peak memory 248840 kb
Host smart-5204fc4c-3946-4ce2-a885-106057c79014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460178480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1460178480
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.524163160
Short name T581
Test name
Test status
Simulation time 766184504 ps
CPU time 50.92 seconds
Started Jul 28 05:19:58 PM PDT 24
Finished Jul 28 05:20:49 PM PDT 24
Peak memory 256352 kb
Host smart-655e4a3f-65ea-4533-a01f-0dac135a6097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52416
3160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.524163160
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1246103680
Short name T522
Test name
Test status
Simulation time 701497445 ps
CPU time 10.4 seconds
Started Jul 28 05:20:01 PM PDT 24
Finished Jul 28 05:20:11 PM PDT 24
Peak memory 254996 kb
Host smart-e33c2ec3-6cee-4213-8766-d9834da05fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12461
03680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1246103680
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.279758140
Short name T93
Test name
Test status
Simulation time 797883407 ps
CPU time 31.93 seconds
Started Jul 28 05:20:08 PM PDT 24
Finished Jul 28 05:20:40 PM PDT 24
Peak memory 256508 kb
Host smart-973ccae5-1027-4c5b-9eb1-985e826ce6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27975
8140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.279758140
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3190904069
Short name T566
Test name
Test status
Simulation time 557380775 ps
CPU time 37.15 seconds
Started Jul 28 05:19:59 PM PDT 24
Finished Jul 28 05:20:36 PM PDT 24
Peak memory 256332 kb
Host smart-a35a796e-ef32-423c-a8f4-bbbb116e1d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31909
04069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3190904069
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.792980865
Short name T606
Test name
Test status
Simulation time 406840309612 ps
CPU time 2323.6 seconds
Started Jul 28 05:20:05 PM PDT 24
Finished Jul 28 05:58:49 PM PDT 24
Peak memory 288792 kb
Host smart-d0bf9492-2728-47e4-aeac-6fd03e5ef79d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792980865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.792980865
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3280848962
Short name T557
Test name
Test status
Simulation time 26595393440 ps
CPU time 480.24 seconds
Started Jul 28 05:20:09 PM PDT 24
Finished Jul 28 05:28:09 PM PDT 24
Peak memory 272896 kb
Host smart-bac4eee3-2bb0-4cc3-9424-cca6b72700fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280848962 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3280848962
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.708878938
Short name T46
Test name
Test status
Simulation time 8400205235 ps
CPU time 1068.03 seconds
Started Jul 28 05:20:02 PM PDT 24
Finished Jul 28 05:37:50 PM PDT 24
Peak memory 281496 kb
Host smart-58638c50-f6e2-4833-b151-eff337dcb08c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708878938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.708878938
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2765714614
Short name T550
Test name
Test status
Simulation time 2530162843 ps
CPU time 77.88 seconds
Started Jul 28 05:20:06 PM PDT 24
Finished Jul 28 05:21:24 PM PDT 24
Peak memory 256592 kb
Host smart-b3629c87-4071-4b16-b107-d82bee2cad6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27657
14614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2765714614
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2192445924
Short name T692
Test name
Test status
Simulation time 698844958 ps
CPU time 13.89 seconds
Started Jul 28 05:20:05 PM PDT 24
Finished Jul 28 05:20:19 PM PDT 24
Peak memory 255492 kb
Host smart-33bd9e07-d369-407c-9e0d-6664199e7b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21924
45924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2192445924
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3092796983
Short name T714
Test name
Test status
Simulation time 58474989778 ps
CPU time 1352.43 seconds
Started Jul 28 05:20:03 PM PDT 24
Finished Jul 28 05:42:36 PM PDT 24
Peak memory 289432 kb
Host smart-198df2ee-2281-4ec8-8808-dea525547523
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092796983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3092796983
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1242993674
Short name T455
Test name
Test status
Simulation time 13581713104 ps
CPU time 1125.63 seconds
Started Jul 28 05:20:03 PM PDT 24
Finished Jul 28 05:38:49 PM PDT 24
Peak memory 288432 kb
Host smart-9c76c30b-fd2b-4429-87d5-cca7d9654dd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242993674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1242993674
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4235537705
Short name T564
Test name
Test status
Simulation time 17116882950 ps
CPU time 184.59 seconds
Started Jul 28 05:20:08 PM PDT 24
Finished Jul 28 05:23:13 PM PDT 24
Peak memory 248884 kb
Host smart-23338d9b-e82b-45b9-9039-7341432f9645
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235537705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4235537705
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.39818743
Short name T677
Test name
Test status
Simulation time 3260402801 ps
CPU time 47.62 seconds
Started Jul 28 05:20:04 PM PDT 24
Finished Jul 28 05:20:52 PM PDT 24
Peak memory 256536 kb
Host smart-ddb0df02-e0c5-4b9d-a134-7da7cc18fbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.39818743
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1849159935
Short name T26
Test name
Test status
Simulation time 763898882 ps
CPU time 30.96 seconds
Started Jul 28 05:20:06 PM PDT 24
Finished Jul 28 05:20:37 PM PDT 24
Peak memory 247880 kb
Host smart-d0a48365-690b-415b-9e8a-ff7c3996c75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18491
59935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1849159935
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3006799559
Short name T430
Test name
Test status
Simulation time 838856548 ps
CPU time 27.14 seconds
Started Jul 28 05:20:02 PM PDT 24
Finished Jul 28 05:20:29 PM PDT 24
Peak memory 256284 kb
Host smart-d2d8611c-738e-4ddf-a9cb-90477620ad87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30067
99559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3006799559
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.933953143
Short name T540
Test name
Test status
Simulation time 120495120 ps
CPU time 8.78 seconds
Started Jul 28 05:20:04 PM PDT 24
Finished Jul 28 05:20:12 PM PDT 24
Peak memory 254816 kb
Host smart-25a95f95-ab86-40dd-9cd3-7123a5602795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93395
3143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.933953143
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1236379914
Short name T553
Test name
Test status
Simulation time 2265357212 ps
CPU time 228.65 seconds
Started Jul 28 05:20:05 PM PDT 24
Finished Jul 28 05:23:54 PM PDT 24
Peak memory 257108 kb
Host smart-cd2f9cdc-8de4-4c36-9a2c-fd2aa702e36b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236379914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1236379914
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3051811328
Short name T4
Test name
Test status
Simulation time 127365879927 ps
CPU time 8512.3 seconds
Started Jul 28 05:20:02 PM PDT 24
Finished Jul 28 07:41:56 PM PDT 24
Peak memory 347336 kb
Host smart-639309c6-81f8-43b0-80e2-06cfdbfe4f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051811328 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3051811328
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.21820062
Short name T413
Test name
Test status
Simulation time 84382960780 ps
CPU time 2620.32 seconds
Started Jul 28 05:20:10 PM PDT 24
Finished Jul 28 06:03:51 PM PDT 24
Peak memory 289824 kb
Host smart-852050fc-29fc-47e1-bea8-99fe326b42f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21820062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.21820062
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.629623364
Short name T257
Test name
Test status
Simulation time 3224031497 ps
CPU time 74.78 seconds
Started Jul 28 05:20:04 PM PDT 24
Finished Jul 28 05:21:18 PM PDT 24
Peak memory 256168 kb
Host smart-2008cb63-6a1c-43f2-b36c-d548bb1c2e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62962
3364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.629623364
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2479541058
Short name T67
Test name
Test status
Simulation time 723549948 ps
CPU time 14.3 seconds
Started Jul 28 05:20:06 PM PDT 24
Finished Jul 28 05:20:20 PM PDT 24
Peak memory 248760 kb
Host smart-69251a58-3614-4f3e-a415-b533c5537d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
41058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2479541058
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3269830010
Short name T638
Test name
Test status
Simulation time 167125913398 ps
CPU time 2536.31 seconds
Started Jul 28 05:20:08 PM PDT 24
Finished Jul 28 06:02:25 PM PDT 24
Peak memory 289428 kb
Host smart-697367d7-4283-42c8-9262-7b285a5a7d64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269830010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3269830010
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1586415029
Short name T502
Test name
Test status
Simulation time 8660594320 ps
CPU time 175.94 seconds
Started Jul 28 05:20:07 PM PDT 24
Finished Jul 28 05:23:04 PM PDT 24
Peak memory 247780 kb
Host smart-c228d920-af3c-451c-a8fc-3fcdb5a1253f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586415029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1586415029
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.703069221
Short name T647
Test name
Test status
Simulation time 442573249 ps
CPU time 26.96 seconds
Started Jul 28 05:20:08 PM PDT 24
Finished Jul 28 05:20:35 PM PDT 24
Peak memory 256360 kb
Host smart-e3a454a8-df61-4ab9-850c-6cf821c66a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70306
9221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.703069221
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.167563658
Short name T662
Test name
Test status
Simulation time 533909094 ps
CPU time 23.31 seconds
Started Jul 28 05:20:06 PM PDT 24
Finished Jul 28 05:20:30 PM PDT 24
Peak memory 256312 kb
Host smart-c2aaab27-6452-44c6-872e-f0677f333fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16756
3658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.167563658
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3440769644
Short name T491
Test name
Test status
Simulation time 474859849 ps
CPU time 31.34 seconds
Started Jul 28 05:20:07 PM PDT 24
Finished Jul 28 05:20:38 PM PDT 24
Peak memory 256416 kb
Host smart-759be3a5-37b2-413c-a681-be07a32ea28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34407
69644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3440769644
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3588493220
Short name T442
Test name
Test status
Simulation time 1180113258 ps
CPU time 19.74 seconds
Started Jul 28 05:20:06 PM PDT 24
Finished Jul 28 05:20:26 PM PDT 24
Peak memory 256508 kb
Host smart-c4ab6183-3fbf-4260-8296-b9f8ef847e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35884
93220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3588493220
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3785756473
Short name T623
Test name
Test status
Simulation time 20708035418 ps
CPU time 1017.19 seconds
Started Jul 28 05:20:09 PM PDT 24
Finished Jul 28 05:37:06 PM PDT 24
Peak memory 272964 kb
Host smart-152825f1-5067-414c-9171-83cbbfd2e5d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785756473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3785756473
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.45083864
Short name T88
Test name
Test status
Simulation time 103153875370 ps
CPU time 1459.63 seconds
Started Jul 28 05:20:09 PM PDT 24
Finished Jul 28 05:44:29 PM PDT 24
Peak memory 273072 kb
Host smart-1cd09648-bff8-424d-b85c-f90ba247a4cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45083864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.45083864
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.383942179
Short name T528
Test name
Test status
Simulation time 4040850511 ps
CPU time 250.56 seconds
Started Jul 28 05:20:09 PM PDT 24
Finished Jul 28 05:24:20 PM PDT 24
Peak memory 257100 kb
Host smart-50665fb8-f394-493a-aea4-f642cf56b838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38394
2179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.383942179
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.443943122
Short name T578
Test name
Test status
Simulation time 211243122 ps
CPU time 17.45 seconds
Started Jul 28 05:20:09 PM PDT 24
Finished Jul 28 05:20:27 PM PDT 24
Peak memory 248764 kb
Host smart-1c3a3186-246d-4dc5-8cbc-5fcd918bc57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44394
3122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.443943122
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.42672587
Short name T346
Test name
Test status
Simulation time 34187865564 ps
CPU time 2005.91 seconds
Started Jul 28 05:20:08 PM PDT 24
Finished Jul 28 05:53:34 PM PDT 24
Peak memory 283048 kb
Host smart-98a74771-6d46-4c64-80da-0ea10d988283
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42672587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.42672587
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1385017012
Short name T492
Test name
Test status
Simulation time 89610402255 ps
CPU time 2925.84 seconds
Started Jul 28 05:20:08 PM PDT 24
Finished Jul 28 06:08:55 PM PDT 24
Peak memory 289592 kb
Host smart-485700ec-362c-4493-814c-ac1e70757c09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385017012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1385017012
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3872096168
Short name T563
Test name
Test status
Simulation time 15992735901 ps
CPU time 502.37 seconds
Started Jul 28 05:20:09 PM PDT 24
Finished Jul 28 05:28:32 PM PDT 24
Peak memory 255700 kb
Host smart-bcdd695f-2b6c-40fb-8154-bbe1989000fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872096168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3872096168
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.4057964664
Short name T83
Test name
Test status
Simulation time 428958283 ps
CPU time 24.06 seconds
Started Jul 28 05:20:09 PM PDT 24
Finished Jul 28 05:20:33 PM PDT 24
Peak memory 256676 kb
Host smart-33411798-5457-4bd5-b96f-9c19afd963e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40579
64664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.4057964664
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.5963399
Short name T384
Test name
Test status
Simulation time 244638786 ps
CPU time 28.2 seconds
Started Jul 28 05:20:08 PM PDT 24
Finished Jul 28 05:20:37 PM PDT 24
Peak memory 248812 kb
Host smart-bb9e9550-6291-408c-b8a5-b3477d8a0f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59633
99 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.5963399
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1505510488
Short name T268
Test name
Test status
Simulation time 1537492612 ps
CPU time 32.28 seconds
Started Jul 28 05:20:09 PM PDT 24
Finished Jul 28 05:20:42 PM PDT 24
Peak memory 248868 kb
Host smart-b175688b-6fee-4b66-8656-bab3bc09f5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15055
10488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1505510488
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2846348712
Short name T541
Test name
Test status
Simulation time 71711726 ps
CPU time 3.52 seconds
Started Jul 28 05:20:07 PM PDT 24
Finished Jul 28 05:20:11 PM PDT 24
Peak memory 250492 kb
Host smart-c3c2c341-b587-42a0-bd97-f4e9388b30f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28463
48712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2846348712
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.663618156
Short name T672
Test name
Test status
Simulation time 23705728674 ps
CPU time 1165.24 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:39:40 PM PDT 24
Peak memory 285440 kb
Host smart-1134ea22-cf32-4bf8-9637-280c789129a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663618156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.663618156
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2304655032
Short name T84
Test name
Test status
Simulation time 17474302636 ps
CPU time 1589.64 seconds
Started Jul 28 05:20:18 PM PDT 24
Finished Jul 28 05:46:48 PM PDT 24
Peak memory 289828 kb
Host smart-b4df49ee-d74d-49f7-b0e6-6d441b8318f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304655032 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2304655032
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1288861061
Short name T574
Test name
Test status
Simulation time 111902446327 ps
CPU time 806.58 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:33:41 PM PDT 24
Peak memory 273432 kb
Host smart-51f33cc1-5255-49e0-aef3-10481e963f0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288861061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1288861061
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.412048212
Short name T441
Test name
Test status
Simulation time 4769993871 ps
CPU time 274.27 seconds
Started Jul 28 05:20:15 PM PDT 24
Finished Jul 28 05:24:49 PM PDT 24
Peak memory 257080 kb
Host smart-932de831-28c3-43cd-9fae-bf9d8cb519a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41204
8212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.412048212
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1014425263
Short name T78
Test name
Test status
Simulation time 7272799479 ps
CPU time 37.58 seconds
Started Jul 28 05:20:15 PM PDT 24
Finished Jul 28 05:20:53 PM PDT 24
Peak memory 248800 kb
Host smart-8ce3a702-4354-4074-8dd6-b27e005e616f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
25263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1014425263
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2100917293
Short name T679
Test name
Test status
Simulation time 234237679481 ps
CPU time 3294.41 seconds
Started Jul 28 05:20:17 PM PDT 24
Finished Jul 28 06:15:12 PM PDT 24
Peak memory 289076 kb
Host smart-606f6538-a008-4d67-8e2c-60944165a470
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100917293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2100917293
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3621448768
Short name T248
Test name
Test status
Simulation time 12622293421 ps
CPU time 1341.52 seconds
Started Jul 28 05:20:17 PM PDT 24
Finished Jul 28 05:42:39 PM PDT 24
Peak memory 289756 kb
Host smart-5b6eb6ea-05d6-4077-85a1-a855eda791e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621448768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3621448768
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2218346491
Short name T307
Test name
Test status
Simulation time 21614959685 ps
CPU time 287.72 seconds
Started Jul 28 05:20:15 PM PDT 24
Finished Jul 28 05:25:03 PM PDT 24
Peak memory 247776 kb
Host smart-00bcb7ad-1c46-4f6b-8800-20e10cbd0c1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218346491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2218346491
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.199733230
Short name T379
Test name
Test status
Simulation time 616482807 ps
CPU time 47.63 seconds
Started Jul 28 05:20:17 PM PDT 24
Finished Jul 28 05:21:05 PM PDT 24
Peak memory 256380 kb
Host smart-4b05247a-8177-4d56-8a49-cc4676732600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19973
3230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.199733230
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.514543447
Short name T713
Test name
Test status
Simulation time 361764156 ps
CPU time 23.22 seconds
Started Jul 28 05:20:16 PM PDT 24
Finished Jul 28 05:20:39 PM PDT 24
Peak memory 256444 kb
Host smart-b1f52fc7-548d-47b3-8ee6-8a9bf47a084c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51454
3447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.514543447
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3520034200
Short name T224
Test name
Test status
Simulation time 1774019657 ps
CPU time 52.1 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:21:06 PM PDT 24
Peak memory 256520 kb
Host smart-c6c2cf0f-ab2e-47a4-ab9f-60e8a54665a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35200
34200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3520034200
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3405663538
Short name T389
Test name
Test status
Simulation time 433345562 ps
CPU time 28.19 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:20:42 PM PDT 24
Peak memory 256968 kb
Host smart-b6d2842f-de3b-477a-b704-61984fb0dddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34056
63538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3405663538
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1994126285
Short name T445
Test name
Test status
Simulation time 45875142810 ps
CPU time 3116.63 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 06:12:11 PM PDT 24
Peak memory 289808 kb
Host smart-9023e0b5-8b20-45f8-a556-fe4158fbe59a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994126285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1994126285
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3794958368
Short name T568
Test name
Test status
Simulation time 21447938734 ps
CPU time 1163.4 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 288880 kb
Host smart-81bca20b-c7a1-46f8-a7ca-5d76f31bd007
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794958368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3794958368
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3117767700
Short name T529
Test name
Test status
Simulation time 5141850280 ps
CPU time 95.44 seconds
Started Jul 28 05:20:15 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 256312 kb
Host smart-00457be3-845e-4072-bd7a-172650f33394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31177
67700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3117767700
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2700181863
Short name T562
Test name
Test status
Simulation time 509457660 ps
CPU time 18.66 seconds
Started Jul 28 05:20:15 PM PDT 24
Finished Jul 28 05:20:33 PM PDT 24
Peak memory 255404 kb
Host smart-01ca7e5e-7be0-44da-a33f-8e46ea5e4bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27001
81863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2700181863
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.377475682
Short name T656
Test name
Test status
Simulation time 70516708727 ps
CPU time 2027.61 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:54:02 PM PDT 24
Peak memory 286300 kb
Host smart-13133d55-dc6a-4619-8dd2-3ab1d438e3ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377475682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.377475682
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1268741366
Short name T591
Test name
Test status
Simulation time 19314856146 ps
CPU time 1192.8 seconds
Started Jul 28 05:20:13 PM PDT 24
Finished Jul 28 05:40:06 PM PDT 24
Peak memory 273464 kb
Host smart-70b53729-db1a-4aea-a3be-2846c21f26e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268741366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1268741366
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2639786924
Short name T223
Test name
Test status
Simulation time 3674906825 ps
CPU time 153.47 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:22:48 PM PDT 24
Peak memory 248824 kb
Host smart-a667405b-c00d-4e27-850e-f3df05779ae6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639786924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2639786924
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.108692931
Short name T300
Test name
Test status
Simulation time 555702041 ps
CPU time 22.26 seconds
Started Jul 28 05:20:15 PM PDT 24
Finished Jul 28 05:20:38 PM PDT 24
Peak memory 248812 kb
Host smart-17bfc07c-4a31-40c5-b43c-ef1d23df957e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10869
2931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.108692931
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2767527092
Short name T487
Test name
Test status
Simulation time 1386997025 ps
CPU time 41.65 seconds
Started Jul 28 05:20:16 PM PDT 24
Finished Jul 28 05:20:58 PM PDT 24
Peak memory 248788 kb
Host smart-6d1a9b0d-a49f-4a4a-ae7a-1d53b0715de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
27092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2767527092
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.46360615
Short name T120
Test name
Test status
Simulation time 363281967 ps
CPU time 13.44 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:20:28 PM PDT 24
Peak memory 248776 kb
Host smart-4a3e19f0-f16f-481a-b479-da6dd004322d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46360
615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.46360615
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3837495173
Short name T293
Test name
Test status
Simulation time 1284197492 ps
CPU time 79.88 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:21:34 PM PDT 24
Peak memory 256564 kb
Host smart-f5ee09d4-e65b-43eb-bdd7-67a53dba6471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38374
95173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3837495173
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.171804249
Short name T71
Test name
Test status
Simulation time 266401517 ps
CPU time 14.31 seconds
Started Jul 28 05:20:19 PM PDT 24
Finished Jul 28 05:20:33 PM PDT 24
Peak memory 248616 kb
Host smart-edeb24d1-3232-417d-bd09-b0654731840d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171804249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.171804249
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3987096917
Short name T111
Test name
Test status
Simulation time 143064447116 ps
CPU time 7425.57 seconds
Started Jul 28 05:20:16 PM PDT 24
Finished Jul 28 07:24:03 PM PDT 24
Peak memory 354768 kb
Host smart-a45786c3-341b-410e-94e0-05bb7e960a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987096917 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3987096917
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.710506330
Short name T521
Test name
Test status
Simulation time 5576907949 ps
CPU time 305.66 seconds
Started Jul 28 05:20:19 PM PDT 24
Finished Jul 28 05:25:25 PM PDT 24
Peak memory 256632 kb
Host smart-fe618099-967a-4b87-b9dc-f7b4994aad86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71050
6330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.710506330
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2281724447
Short name T569
Test name
Test status
Simulation time 145244448 ps
CPU time 14.02 seconds
Started Jul 28 05:20:17 PM PDT 24
Finished Jul 28 05:20:31 PM PDT 24
Peak memory 255988 kb
Host smart-eca339b3-c64f-4b56-8869-72ca13c226a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22817
24447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2281724447
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3808615785
Short name T333
Test name
Test status
Simulation time 155181673879 ps
CPU time 2238.29 seconds
Started Jul 28 05:20:21 PM PDT 24
Finished Jul 28 05:57:40 PM PDT 24
Peak memory 287512 kb
Host smart-55827345-ea74-45bf-a677-1796edea8265
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808615785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3808615785
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.984042063
Short name T396
Test name
Test status
Simulation time 7843910618 ps
CPU time 891.6 seconds
Started Jul 28 05:20:21 PM PDT 24
Finished Jul 28 05:35:13 PM PDT 24
Peak memory 273404 kb
Host smart-1f66819e-cd66-44e0-bf45-583b63aa0eea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984042063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.984042063
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3538813963
Short name T505
Test name
Test status
Simulation time 113895449 ps
CPU time 15.05 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:20:29 PM PDT 24
Peak memory 255948 kb
Host smart-c0f5084b-6b43-4111-a974-40fee11dc1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35388
13963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3538813963
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1929943603
Short name T519
Test name
Test status
Simulation time 239437853 ps
CPU time 8.68 seconds
Started Jul 28 05:20:17 PM PDT 24
Finished Jul 28 05:20:26 PM PDT 24
Peak memory 248228 kb
Host smart-c5e154a1-4c77-4f5e-9ec1-7ec53f9a3aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19299
43603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1929943603
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4116408824
Short name T644
Test name
Test status
Simulation time 431351179 ps
CPU time 27.38 seconds
Started Jul 28 05:20:18 PM PDT 24
Finished Jul 28 05:20:45 PM PDT 24
Peak memory 248820 kb
Host smart-8a6dae10-d46a-4df4-bad2-4011cdeaebfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41164
08824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4116408824
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.516398734
Short name T465
Test name
Test status
Simulation time 287060083 ps
CPU time 5.36 seconds
Started Jul 28 05:20:14 PM PDT 24
Finished Jul 28 05:20:19 PM PDT 24
Peak memory 251008 kb
Host smart-700ebce5-70fd-4a7a-a0c9-93ee1d549d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51639
8734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.516398734
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3356205241
Short name T646
Test name
Test status
Simulation time 49075644709 ps
CPU time 1519.03 seconds
Started Jul 28 05:20:19 PM PDT 24
Finished Jul 28 05:45:39 PM PDT 24
Peak memory 289852 kb
Host smart-4689f94d-c25c-46b6-9eef-a08f41a1deb7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356205241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3356205241
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.88888606
Short name T489
Test name
Test status
Simulation time 19548365464 ps
CPU time 2387.66 seconds
Started Jul 28 05:20:20 PM PDT 24
Finished Jul 28 06:00:08 PM PDT 24
Peak memory 305564 kb
Host smart-6a308d15-2886-4349-bfbd-75f244e56053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88888606 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.88888606
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3671084512
Short name T213
Test name
Test status
Simulation time 15473349 ps
CPU time 2.4 seconds
Started Jul 28 05:19:02 PM PDT 24
Finished Jul 28 05:19:04 PM PDT 24
Peak memory 249112 kb
Host smart-8f43ddcd-7d43-4bfb-ada1-1819e212a1d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3671084512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3671084512
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2862159310
Short name T232
Test name
Test status
Simulation time 100948276283 ps
CPU time 1662.74 seconds
Started Jul 28 05:18:52 PM PDT 24
Finished Jul 28 05:46:35 PM PDT 24
Peak memory 272928 kb
Host smart-8480f6ac-6e1b-47eb-bddf-05f2e6b17ee0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862159310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2862159310
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3024161011
Short name T631
Test name
Test status
Simulation time 813923589 ps
CPU time 19.59 seconds
Started Jul 28 05:18:43 PM PDT 24
Finished Jul 28 05:19:03 PM PDT 24
Peak memory 248812 kb
Host smart-85ce985d-2725-434d-a427-fdb4528c62f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3024161011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3024161011
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3199149359
Short name T382
Test name
Test status
Simulation time 3766870749 ps
CPU time 114.54 seconds
Started Jul 28 05:18:51 PM PDT 24
Finished Jul 28 05:20:46 PM PDT 24
Peak memory 257280 kb
Host smart-529e595d-c4b8-4f3a-bf01-eaf5d49d2cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31991
49359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3199149359
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3850200741
Short name T378
Test name
Test status
Simulation time 898150363 ps
CPU time 30.51 seconds
Started Jul 28 05:18:47 PM PDT 24
Finished Jul 28 05:19:18 PM PDT 24
Peak memory 248744 kb
Host smart-95286387-336d-49d5-a70a-67f203393361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38502
00741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3850200741
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2522182376
Short name T326
Test name
Test status
Simulation time 274682927250 ps
CPU time 1198.14 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:39:02 PM PDT 24
Peak memory 282576 kb
Host smart-7891efcf-2c7b-4890-acd5-968bb3e11b5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522182376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2522182376
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2905938554
Short name T546
Test name
Test status
Simulation time 142570862420 ps
CPU time 1624.88 seconds
Started Jul 28 05:18:44 PM PDT 24
Finished Jul 28 05:45:49 PM PDT 24
Peak memory 273412 kb
Host smart-cabd4a8d-b966-4955-b7bd-a9fc19340315
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905938554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2905938554
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1799036973
Short name T485
Test name
Test status
Simulation time 3223144809 ps
CPU time 133.34 seconds
Started Jul 28 05:18:52 PM PDT 24
Finished Jul 28 05:21:05 PM PDT 24
Peak memory 248836 kb
Host smart-bbafa6f0-0c7d-4c06-8cfa-34ea6e3be9d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799036973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1799036973
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.477708888
Short name T405
Test name
Test status
Simulation time 312382864 ps
CPU time 19.84 seconds
Started Jul 28 05:19:05 PM PDT 24
Finished Jul 28 05:19:25 PM PDT 24
Peak memory 248792 kb
Host smart-97a8be9e-24fb-4760-abba-7a31f49372d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47770
8888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.477708888
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3257878110
Short name T90
Test name
Test status
Simulation time 967045714 ps
CPU time 56.6 seconds
Started Jul 28 05:18:47 PM PDT 24
Finished Jul 28 05:19:44 PM PDT 24
Peak memory 256492 kb
Host smart-a4a40edb-dfe4-4302-9b14-4b9888a40cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32578
78110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3257878110
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2346317096
Short name T407
Test name
Test status
Simulation time 571516136 ps
CPU time 5 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:18:52 PM PDT 24
Peak memory 248844 kb
Host smart-d6524a2d-e030-4be0-afdf-21d1b5f280a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23463
17096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2346317096
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3312666813
Short name T501
Test name
Test status
Simulation time 2161703385 ps
CPU time 24.31 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:19:17 PM PDT 24
Peak memory 257288 kb
Host smart-1af92672-7cb7-4745-b807-c416bb227726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33126
66813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3312666813
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1950123002
Short name T56
Test name
Test status
Simulation time 57805141015 ps
CPU time 450.98 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 05:26:24 PM PDT 24
Peak memory 256928 kb
Host smart-eef3e74b-9da3-4929-beac-4e1d0a5e4730
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950123002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1950123002
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2150983261
Short name T215
Test name
Test status
Simulation time 126856944 ps
CPU time 3.45 seconds
Started Jul 28 05:18:51 PM PDT 24
Finished Jul 28 05:18:55 PM PDT 24
Peak memory 249140 kb
Host smart-b9ab062c-3be5-4c35-9a72-11ed7afd47e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2150983261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2150983261
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.68978500
Short name T25
Test name
Test status
Simulation time 116026640923 ps
CPU time 998.07 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:35:34 PM PDT 24
Peak memory 289660 kb
Host smart-40f7a5d2-5a77-4d4e-9dd3-60c2bdd1ef5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68978500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.68978500
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1216114319
Short name T456
Test name
Test status
Simulation time 1660656513 ps
CPU time 26.99 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:19:13 PM PDT 24
Peak memory 248804 kb
Host smart-150afa1c-34f0-4892-b8f8-d8d697e43040
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1216114319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1216114319
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.685948014
Short name T388
Test name
Test status
Simulation time 8553259102 ps
CPU time 305.61 seconds
Started Jul 28 05:18:52 PM PDT 24
Finished Jul 28 05:23:58 PM PDT 24
Peak memory 251824 kb
Host smart-9723b58d-44e1-444f-af40-dcfc250c082d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68594
8014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.685948014
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2761998261
Short name T468
Test name
Test status
Simulation time 49890729 ps
CPU time 4.81 seconds
Started Jul 28 05:18:44 PM PDT 24
Finished Jul 28 05:18:49 PM PDT 24
Peak memory 240164 kb
Host smart-c30978ee-a1e5-4ecf-a325-01c485fcf77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27619
98261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2761998261
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2437746029
Short name T703
Test name
Test status
Simulation time 70555546762 ps
CPU time 2512.31 seconds
Started Jul 28 05:18:59 PM PDT 24
Finished Jul 28 06:00:51 PM PDT 24
Peak memory 289076 kb
Host smart-33b80cf0-e072-429f-b9b0-b18c28862642
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437746029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2437746029
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3564383751
Short name T600
Test name
Test status
Simulation time 17790791021 ps
CPU time 1537.01 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:44:25 PM PDT 24
Peak memory 289656 kb
Host smart-82c78d75-aec5-4b10-89c3-d13f43e8a420
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564383751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3564383751
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2956611676
Short name T16
Test name
Test status
Simulation time 4463895500 ps
CPU time 99.04 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:20:33 PM PDT 24
Peak memory 248836 kb
Host smart-9e70f39f-fd04-4755-87d8-8db12c5861c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956611676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2956611676
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3404665284
Short name T686
Test name
Test status
Simulation time 184910152 ps
CPU time 12.55 seconds
Started Jul 28 05:18:49 PM PDT 24
Finished Jul 28 05:19:02 PM PDT 24
Peak memory 248844 kb
Host smart-d12e00a5-8256-4b80-90b0-88c2058cefda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34046
65284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3404665284
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2447796819
Short name T525
Test name
Test status
Simulation time 719214761 ps
CPU time 24.93 seconds
Started Jul 28 05:18:41 PM PDT 24
Finished Jul 28 05:19:06 PM PDT 24
Peak memory 248388 kb
Host smart-aaaa28e1-c862-4e87-877b-344f35cc00ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24477
96819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2447796819
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1950658044
Short name T77
Test name
Test status
Simulation time 2649488757 ps
CPU time 40.75 seconds
Started Jul 28 05:18:51 PM PDT 24
Finished Jul 28 05:19:32 PM PDT 24
Peak memory 248576 kb
Host smart-bef4eacb-f969-4d1a-9178-34064a92a34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19506
58044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1950658044
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2819648625
Short name T693
Test name
Test status
Simulation time 607626246 ps
CPU time 24.42 seconds
Started Jul 28 05:18:58 PM PDT 24
Finished Jul 28 05:19:23 PM PDT 24
Peak memory 256976 kb
Host smart-ed420c78-6bb9-4ef1-b0b8-536c0e05fcfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28196
48625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2819648625
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1407216413
Short name T706
Test name
Test status
Simulation time 638786661 ps
CPU time 53.44 seconds
Started Jul 28 05:18:48 PM PDT 24
Finished Jul 28 05:19:42 PM PDT 24
Peak memory 257048 kb
Host smart-095202e0-b990-4180-9711-bb200e186d61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407216413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1407216413
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1803847359
Short name T649
Test name
Test status
Simulation time 84712167404 ps
CPU time 8113.84 seconds
Started Jul 28 05:18:59 PM PDT 24
Finished Jul 28 07:34:14 PM PDT 24
Peak memory 394976 kb
Host smart-962ecee5-f89f-4a74-b186-c72a22fa23c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803847359 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1803847359
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3577434956
Short name T207
Test name
Test status
Simulation time 44980831 ps
CPU time 3.71 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:18:59 PM PDT 24
Peak memory 249160 kb
Host smart-4cae62ed-7589-4f3c-bd04-60c1d97440e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3577434956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3577434956
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.499947263
Short name T113
Test name
Test status
Simulation time 45332670764 ps
CPU time 2690.77 seconds
Started Jul 28 05:18:53 PM PDT 24
Finished Jul 28 06:03:44 PM PDT 24
Peak memory 286924 kb
Host smart-f006d5cd-d4fe-4b27-98bb-925f61f2cd7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499947263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.499947263
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2588143034
Short name T250
Test name
Test status
Simulation time 261473355 ps
CPU time 13.01 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:18:58 PM PDT 24
Peak memory 248756 kb
Host smart-8675d21d-48ab-4130-a47d-5f1caf1ab554
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2588143034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2588143034
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.744041517
Short name T552
Test name
Test status
Simulation time 572356698 ps
CPU time 49.93 seconds
Started Jul 28 05:19:02 PM PDT 24
Finished Jul 28 05:19:52 PM PDT 24
Peak memory 256928 kb
Host smart-d281327c-715f-42f6-9415-875a925fad59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74404
1517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.744041517
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2868773990
Short name T650
Test name
Test status
Simulation time 822985429 ps
CPU time 46.14 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:19:51 PM PDT 24
Peak memory 256112 kb
Host smart-d0f4fdc3-91d0-46f9-a95a-1889dda0b166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28687
73990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2868773990
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3220366334
Short name T322
Test name
Test status
Simulation time 10192857094 ps
CPU time 1071.25 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:36:46 PM PDT 24
Peak memory 273396 kb
Host smart-cf57e654-4d53-4796-b969-88b46d14762e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220366334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3220366334
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.128774509
Short name T478
Test name
Test status
Simulation time 134014619501 ps
CPU time 804 seconds
Started Jul 28 05:19:23 PM PDT 24
Finished Jul 28 05:32:47 PM PDT 24
Peak memory 272492 kb
Host smart-64778794-b3e7-4b08-a125-805790211edb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128774509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.128774509
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.623662907
Short name T323
Test name
Test status
Simulation time 5049826424 ps
CPU time 210.59 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:22:26 PM PDT 24
Peak memory 248896 kb
Host smart-9d8f1c50-34d9-40b7-afa5-af59c1789271
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623662907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.623662907
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.710703814
Short name T512
Test name
Test status
Simulation time 1228223326 ps
CPU time 37.35 seconds
Started Jul 28 05:18:46 PM PDT 24
Finished Jul 28 05:19:24 PM PDT 24
Peak memory 255912 kb
Host smart-73572441-c80e-47e3-9f68-fd3afd766952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71070
3814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.710703814
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.503973006
Short name T602
Test name
Test status
Simulation time 1617212337 ps
CPU time 24.86 seconds
Started Jul 28 05:18:45 PM PDT 24
Finished Jul 28 05:19:11 PM PDT 24
Peak memory 248332 kb
Host smart-0e29b574-1740-49e3-b577-b61fb4d82226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50397
3006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.503973006
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.740235890
Short name T119
Test name
Test status
Simulation time 879129524 ps
CPU time 47.59 seconds
Started Jul 28 05:19:12 PM PDT 24
Finished Jul 28 05:19:59 PM PDT 24
Peak memory 248784 kb
Host smart-b49620b3-e060-4169-913c-76d942ce16d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74023
5890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.740235890
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3344574753
Short name T403
Test name
Test status
Simulation time 147181707 ps
CPU time 16.23 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:19:10 PM PDT 24
Peak memory 256612 kb
Host smart-6da30bdf-bf03-4a53-87d6-4d86106b08c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33445
74753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3344574753
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1466030158
Short name T601
Test name
Test status
Simulation time 16199022611 ps
CPU time 1653.91 seconds
Started Jul 28 05:18:56 PM PDT 24
Finished Jul 28 05:46:30 PM PDT 24
Peak memory 302880 kb
Host smart-dec46af4-c383-4c39-98a5-42a7389c71a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466030158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1466030158
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.739688026
Short name T244
Test name
Test status
Simulation time 22513562268 ps
CPU time 1325.87 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:41:14 PM PDT 24
Peak memory 273584 kb
Host smart-b53ddc2d-9db7-488e-8741-c2143aac2695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739688026 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.739688026
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1797720362
Short name T38
Test name
Test status
Simulation time 133004600 ps
CPU time 3.26 seconds
Started Jul 28 05:18:51 PM PDT 24
Finished Jul 28 05:18:55 PM PDT 24
Peak memory 249072 kb
Host smart-b13ad464-ffb5-4b93-a094-7d93d5e67b0d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1797720362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1797720362
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2194536216
Short name T406
Test name
Test status
Simulation time 49196803722 ps
CPU time 1836.95 seconds
Started Jul 28 05:19:02 PM PDT 24
Finished Jul 28 05:49:39 PM PDT 24
Peak memory 283408 kb
Host smart-5c2b99aa-24d8-4356-90ac-a2f32c5f0469
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194536216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2194536216
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3000660545
Short name T241
Test name
Test status
Simulation time 509699886 ps
CPU time 10.17 seconds
Started Jul 28 05:19:15 PM PDT 24
Finished Jul 28 05:19:25 PM PDT 24
Peak memory 248820 kb
Host smart-56a1cafe-1ca6-48af-bc4a-14e377de01e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3000660545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3000660545
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3733212385
Short name T689
Test name
Test status
Simulation time 1018165222 ps
CPU time 23.72 seconds
Started Jul 28 05:19:04 PM PDT 24
Finished Jul 28 05:19:28 PM PDT 24
Peak memory 248796 kb
Host smart-fb088735-9605-45e4-9eb1-7871bd0c43f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37332
12385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3733212385
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.4071172376
Short name T705
Test name
Test status
Simulation time 975279797 ps
CPU time 22.26 seconds
Started Jul 28 05:19:18 PM PDT 24
Finished Jul 28 05:19:40 PM PDT 24
Peak memory 248840 kb
Host smart-4dbf348a-a884-4800-acb2-de2259565288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40711
72376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.4071172376
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2505611590
Short name T332
Test name
Test status
Simulation time 125735439096 ps
CPU time 1702.89 seconds
Started Jul 28 05:19:17 PM PDT 24
Finished Jul 28 05:47:40 PM PDT 24
Peak memory 273164 kb
Host smart-61ffd6a2-a8c0-47d4-b9ef-d51dc18539ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505611590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2505611590
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3308470893
Short name T33
Test name
Test status
Simulation time 73970312695 ps
CPU time 1558.52 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:44:58 PM PDT 24
Peak memory 273392 kb
Host smart-1d006c8c-6652-4bdd-83d3-775cc5a357cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308470893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3308470893
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3546162645
Short name T312
Test name
Test status
Simulation time 102040057300 ps
CPU time 396.09 seconds
Started Jul 28 05:19:07 PM PDT 24
Finished Jul 28 05:25:43 PM PDT 24
Peak memory 248832 kb
Host smart-d048d8b3-f50c-4503-8430-d3053e2dd621
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546162645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3546162645
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3313137733
Short name T367
Test name
Test status
Simulation time 538965758 ps
CPU time 32.19 seconds
Started Jul 28 05:19:03 PM PDT 24
Finished Jul 28 05:19:36 PM PDT 24
Peak memory 256064 kb
Host smart-384af953-6551-4220-8297-94ddbfff8e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33131
37733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3313137733
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2001381774
Short name T49
Test name
Test status
Simulation time 5275158524 ps
CPU time 39.73 seconds
Started Jul 28 05:18:57 PM PDT 24
Finished Jul 28 05:19:37 PM PDT 24
Peak memory 248884 kb
Host smart-3a40fe63-e18e-4adb-ade1-28f44684f5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20013
81774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2001381774
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1226598138
Short name T446
Test name
Test status
Simulation time 86380890 ps
CPU time 7.75 seconds
Started Jul 28 05:19:07 PM PDT 24
Finished Jul 28 05:19:15 PM PDT 24
Peak memory 248824 kb
Host smart-a4e5962d-7679-4322-b181-942f550d9b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12265
98138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1226598138
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1622209053
Short name T499
Test name
Test status
Simulation time 595645986 ps
CPU time 16.6 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:19:25 PM PDT 24
Peak memory 256788 kb
Host smart-372496d3-3d16-4dc5-8cbc-50e90f7cea66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16222
09053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1622209053
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3665427337
Short name T258
Test name
Test status
Simulation time 47771420028 ps
CPU time 2601.01 seconds
Started Jul 28 05:19:01 PM PDT 24
Finished Jul 28 06:02:22 PM PDT 24
Peak memory 289676 kb
Host smart-49ae50cd-a4c9-48b3-8251-b42a5ec98c7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665427337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3665427337
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1720601254
Short name T214
Test name
Test status
Simulation time 173986398 ps
CPU time 3.6 seconds
Started Jul 28 05:19:01 PM PDT 24
Finished Jul 28 05:19:10 PM PDT 24
Peak memory 249008 kb
Host smart-33487912-fe68-4c74-b109-f4a3066c0dc7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1720601254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1720601254
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3150748418
Short name T242
Test name
Test status
Simulation time 136332292989 ps
CPU time 2415.25 seconds
Started Jul 28 05:19:08 PM PDT 24
Finished Jul 28 05:59:24 PM PDT 24
Peak memory 289580 kb
Host smart-96246b9e-04d3-46f2-8d41-1edb2ac3c412
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150748418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3150748418
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.738262200
Short name T198
Test name
Test status
Simulation time 188182499 ps
CPU time 11.48 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:19:06 PM PDT 24
Peak memory 248804 kb
Host smart-9fb849b9-9d4d-4611-9175-7521e4602779
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=738262200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.738262200
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1865798251
Short name T635
Test name
Test status
Simulation time 2335481113 ps
CPU time 144.47 seconds
Started Jul 28 05:19:20 PM PDT 24
Finished Jul 28 05:21:45 PM PDT 24
Peak memory 256152 kb
Host smart-4281625e-4ae1-4f41-a28e-b74f07b8fd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
98251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1865798251
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2378190023
Short name T536
Test name
Test status
Simulation time 368796338 ps
CPU time 28.74 seconds
Started Jul 28 05:19:12 PM PDT 24
Finished Jul 28 05:19:41 PM PDT 24
Peak memory 248480 kb
Host smart-7c1ecfd3-7d9f-449e-8f78-8d2dfcc01faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781
90023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2378190023
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2548445920
Short name T533
Test name
Test status
Simulation time 71844689312 ps
CPU time 2402.35 seconds
Started Jul 28 05:18:54 PM PDT 24
Finished Jul 28 05:58:57 PM PDT 24
Peak memory 289756 kb
Host smart-74cb2691-5116-4a6b-a854-3497a92f33bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548445920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2548445920
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.594978915
Short name T667
Test name
Test status
Simulation time 15301028667 ps
CPU time 654.69 seconds
Started Jul 28 05:19:19 PM PDT 24
Finished Jul 28 05:30:14 PM PDT 24
Peak memory 273420 kb
Host smart-6f8ba208-8d9e-45ac-ab1e-0666f2c6c9ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594978915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.594978915
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2555069789
Short name T320
Test name
Test status
Simulation time 6506860135 ps
CPU time 241.11 seconds
Started Jul 28 05:18:55 PM PDT 24
Finished Jul 28 05:22:56 PM PDT 24
Peak memory 248672 kb
Host smart-8ecb5f7c-376f-4b7f-9906-a1fca4ba0de9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555069789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2555069789
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.4139226568
Short name T612
Test name
Test status
Simulation time 728802515 ps
CPU time 31.67 seconds
Started Jul 28 05:19:05 PM PDT 24
Finished Jul 28 05:19:36 PM PDT 24
Peak memory 256148 kb
Host smart-816fabba-2f7e-43af-a975-5e3aed8e7d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41392
26568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.4139226568
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.907699872
Short name T48
Test name
Test status
Simulation time 2594889234 ps
CPU time 37.03 seconds
Started Jul 28 05:18:56 PM PDT 24
Finished Jul 28 05:19:33 PM PDT 24
Peak memory 256492 kb
Host smart-e5fb67d3-e9ef-4123-ad46-10d858d7286a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90769
9872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.907699872
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2432564354
Short name T296
Test name
Test status
Simulation time 691846394 ps
CPU time 13.41 seconds
Started Jul 28 05:19:06 PM PDT 24
Finished Jul 28 05:19:20 PM PDT 24
Peak memory 248776 kb
Host smart-e1ce0cd3-79c5-4f22-bd8b-7018fbc6106e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24325
64354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2432564354
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1849937558
Short name T510
Test name
Test status
Simulation time 12926095312 ps
CPU time 199.37 seconds
Started Jul 28 05:19:16 PM PDT 24
Finished Jul 28 05:22:36 PM PDT 24
Peak memory 257088 kb
Host smart-d376b794-5ebf-4137-982a-e797bc61b8d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849937558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1849937558
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%