Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	94293	1			T15	260		T5	82		T6	2724
class_i[0x1]	80344	1			T4	3119		T6	11		T17	6
class_i[0x2]	68822	1			T44	26		T4	3		T30	91
class_i[0x3]	32227	1			T5	422		T6	8		T30	1835

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	67740	1			T15	32		T44	9		T4	869
alert[0x1]	70618	1			T15	42		T44	1		T4	735
alert[0x2]	68323	1			T15	21		T44	7		T4	724
alert[0x3]	69005	1			T15	165		T44	9		T4	794

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

275413

1

T15

260

T44

26

T4

3122

esc_ping_fail

273

1

T17

5

T18

3

T19

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	67666	1			T15	32		T44	9		T4	869
esc_integrity_fail	alert[0x1]	70541	1			T15	42		T44	1		T4	735
esc_integrity_fail	alert[0x2]	68260	1			T15	21		T44	7		T4	724
esc_integrity_fail	alert[0x3]	68946	1			T15	165		T44	9		T4	794
esc_ping_fail	alert[0x0]	74	1			T17	1		T18	1		T19	1
esc_ping_fail	alert[0x1]	77	1			T17	1		T18	1		T19	1
esc_ping_fail	alert[0x2]	63	1			T17	2		T18	1		T19	3
esc_ping_fail	alert[0x3]	59	1			T17	1		T19	1		T189	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	94232	1			T15	260		T5	82		T6	2724
esc_integrity_fail	class_i[0x1]	80264	1			T4	3119		T6	11		T17	2
esc_integrity_fail	class_i[0x2]	68750	1			T44	26		T4	3		T30	91
esc_integrity_fail	class_i[0x3]	32167	1			T5	422		T6	8		T30	1835
esc_ping_fail	class_i[0x0]	61	1			T17	1		T304	1		T107	3
esc_ping_fail	class_i[0x1]	80	1			T17	4		T189	7		T108	1
esc_ping_fail	class_i[0x2]	72	1			T18	3		T19	6		T296	2
esc_ping_fail	class_i[0x3]	60	1			T304	4		T216	6		T218	12