Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	87	1			T4	1		T5	1		T30	3
class_index[0x1]	81	1			T25	2		T4	1		T30	2
class_index[0x2]	61	1			T5	1		T30	1		T37	1
class_index[0x3]	76	1			T5	2		T30	1		T26	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	101	1			T25	2		T4	2		T5	2
intr_timeout_cnt[1]	80	1			T5	1		T30	3		T26	2
intr_timeout_cnt[2]	30	1			T48	1		T71	1		T75	1
intr_timeout_cnt[3]	16	1			T37	1		T46	1		T263	1
intr_timeout_cnt[4]	11	1			T30	1		T26	1		T71	2
intr_timeout_cnt[5]	15	1			T51	2		T264	1		T223	1
intr_timeout_cnt[6]	14	1			T30	1		T37	1		T173	1
intr_timeout_cnt[7]	20	1			T5	1		T26	1		T55	1
intr_timeout_cnt[8]	6	1			T30	1		T77	1		T225	1
intr_timeout_cnt[9]	12	1			T51	1		T76	2		T54	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	40	1			T4	1		T5	1		T46	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T26	2		T73	1		T72	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T223	1		T265	1		T266	1
class_index[0x0]	intr_timeout_cnt[3]	7	1			T37	1		T223	1		T245	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T30	1		T71	2		T224	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T267	2		T268	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	3	1			T30	1		T183	1		T269	1
class_index[0x0]	intr_timeout_cnt[7]	5	1			T26	1		T270	1		T271	2
class_index[0x0]	intr_timeout_cnt[8]	2	1			T30	1		T77	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T76	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	29	1			T25	2		T4	1		T30	1
class_index[0x1]	intr_timeout_cnt[1]	24	1			T30	1		T37	1		T69	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T71	1		T267	1		T246	2
class_index[0x1]	intr_timeout_cnt[3]	3	1			T263	1		T61	1		T175	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T272	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	6	1			T51	1		T224	1		T273	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T55	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	5	1			T55	1		T254	1		T274	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T275	1		T269	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	5	1			T51	1		T85	3		T276	1
class_index[0x2]	intr_timeout_cnt[0]	13	1			T78	1		T277	1		T223	1
class_index[0x2]	intr_timeout_cnt[1]	19	1			T5	1		T30	1		T67	1
class_index[0x2]	intr_timeout_cnt[2]	13	1			T48	1		T75	1		T79	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T278	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	1	1			T279	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T223	1		T237	1		T246	1
class_index[0x2]	intr_timeout_cnt[6]	6	1			T37	1		T55	2		T183	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T104	1		T280	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T252	1		T184	1		T257	1
class_index[0x3]	intr_timeout_cnt[0]	19	1			T5	1		T68	1		T110	1
class_index[0x3]	intr_timeout_cnt[1]	22	1			T30	1		T75	1		T81	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T281	2		T60	2		T224	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T46	1		T282	1		T225	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T26	1		T214	1		T279	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T51	1		T264	1		T283	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T173	1		T55	1		T284	1
class_index[0x3]	intr_timeout_cnt[7]	8	1			T5	1		T61	2		T85	1
class_index[0x3]	intr_timeout_cnt[8]	2	1			T225	1		T285	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T54	1		T175	1		-	-