Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	363459	1			T1	27		T2	175		T3	21
all_values[1]	363459	1			T1	27		T2	175		T3	21
all_values[2]	363459	1			T1	27		T2	175		T3	21
all_values[3]	363459	1			T1	27		T2	175		T3	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

724006

1

T1

58

T2

348

T3

47

auto[1]

729830

1

T1

50

T2

352

T3

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

857891

1

T1

56

T2

352

T3

74

auto[1]

595945

1

T1

52

T2

348

T3

10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103208	1			T1	8		T2	42		T3	4
all_values[0]	auto[0]	auto[1]	77704	1			T1	7		T2	41		T3	4
all_values[0]	auto[1]	auto[0]	104433	1			T1	6		T2	46		T3	7
all_values[0]	auto[1]	auto[1]	78114	1			T1	6		T2	46		T3	6
all_values[1]	auto[0]	auto[0]	106943	1			T1	9		T2	46		T3	11
all_values[1]	auto[0]	auto[1]	73853	1			T1	8		T2	45		T7	296
all_values[1]	auto[1]	auto[0]	108428	1			T1	5		T2	42		T3	10
all_values[1]	auto[1]	auto[1]	74235	1			T1	5		T2	42		T7	345
all_values[2]	auto[0]	auto[0]	108643	1			T1	7		T2	42		T3	15
all_values[2]	auto[0]	auto[1]	72615	1			T1	7		T2	41		T7	297
all_values[2]	auto[1]	auto[0]	109882	1			T1	7		T2	46		T3	6
all_values[2]	auto[1]	auto[1]	72319	1			T1	6		T2	46		T7	344
all_values[3]	auto[0]	auto[0]	107471	1			T1	6		T2	46		T3	13
all_values[3]	auto[0]	auto[1]	73569	1			T1	6		T2	45		T7	385
all_values[3]	auto[1]	auto[0]	108883	1			T1	8		T2	42		T3	8
all_values[3]	auto[1]	auto[1]	73536	1			T1	7		T2	42		T7	380