Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	363459	1			T1	27		T2	175		T3	21
all_pins[1]	363459	1			T1	27		T2	175		T3	21
all_pins[2]	363459	1			T1	27		T2	175		T3	21
all_pins[3]	363459	1			T1	27		T2	175		T3	21

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1155632	1			T1	84		T2	524		T3	78
values[0x1]	298204	1			T1	24		T2	176		T3	6
transitions[0x0=>0x1]	197809	1			T1	13		T2	98		T3	6
transitions[0x1=>0x0]	198068	1			T1	14		T2	98		T3	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285345	1			T1	21		T2	129		T3	15
all_pins[0]	values[0x1]	78114	1			T1	6		T2	46		T3	6
all_pins[0]	transitions[0x0=>0x1]	77455	1			T1	5		T2	46		T3	6
all_pins[0]	transitions[0x1=>0x0]	73136	1			T1	7		T2	42		T7	380
all_pins[1]	values[0x0]	289224	1			T1	22		T2	133		T3	21
all_pins[1]	values[0x1]	74235	1			T1	5		T2	42		T7	345
all_pins[1]	transitions[0x0=>0x1]	40577	1			T1	1		T2	17		T7	178
all_pins[1]	transitions[0x1=>0x0]	44456	1			T1	2		T2	21		T3	6
all_pins[2]	values[0x0]	291140	1			T1	21		T2	129		T3	21
all_pins[2]	values[0x1]	72319	1			T1	6		T2	46		T7	344
all_pins[2]	transitions[0x0=>0x1]	39156	1			T1	4		T2	21		T7	218
all_pins[2]	transitions[0x1=>0x0]	41072	1			T1	3		T2	17		T7	219
all_pins[3]	values[0x0]	289923	1			T1	20		T2	133		T3	21
all_pins[3]	values[0x1]	73536	1			T1	7		T2	42		T7	380
all_pins[3]	transitions[0x0=>0x1]	40621	1			T1	3		T2	14		T7	218
all_pins[3]	transitions[0x1=>0x0]	39404	1			T1	2		T2	18		T7	182