Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T154	7		T155	7		T156	7
all_values[1]	278	1			T154	7		T155	7		T156	7
all_values[2]	278	1			T154	7		T155	7		T156	7
all_values[3]	278	1			T154	7		T155	7		T156	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577

1

T154

17

T155

11

T156

14

auto[1]

535

1

T154

11

T155

17

T156

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

424

1

T154

11

T155

13

T156

11

auto[1]

688

1

T154

17

T155

15

T156

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656

1

T154

17

T155

18

T156

17

auto[1]

456

1

T154

11

T155

10

T156

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

56

1

T154

1

T155

3

T156

2

all_values[0]

auto[0]

auto[0]

auto[1]

39

1

T154

3

T341

1

T342

1

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T154

1

T155

2

T156

2

all_values[0]

auto[0]

auto[1]

auto[1]

27

1

T156

1

T341

1

T222

2

all_values[0]

auto[1]

auto[0]

auto[1]

65

1

T155

1

T156

2

T341

2

all_values[0]

auto[1]

auto[1]

auto[1]

45

1

T154

2

T155

1

T222

1

all_values[1]

auto[0]

auto[0]

auto[0]

58

1

T154

5

T156

2

T341

1

all_values[1]

auto[0]

auto[0]

auto[1]

26

1

T155

2

T222

2

T343

2

all_values[1]

auto[0]

auto[1]

auto[0]

54

1

T154

2

T156

2

T341

3

all_values[1]

auto[0]

auto[1]

auto[1]

23

1

T344

2

T345

1

T346

2

all_values[1]

auto[1]

auto[0]

auto[1]

64

1

T155

3

T222

2

T344

1

all_values[1]

auto[1]

auto[1]

auto[1]

53

1

T155

2

T156

3

T343

2

all_values[2]

auto[0]

auto[0]

auto[0]

49

1

T155

1

T156

1

T222

2

all_values[2]

auto[0]

auto[0]

auto[1]

28

1

T154

1

T156

1

T345

1

all_values[2]

auto[0]

auto[1]

auto[0]

50

1

T155

3

T342

1

T343

2

all_values[2]

auto[0]

auto[1]

auto[1]

34

1

T154

1

T155

1

T341

1

all_values[2]

auto[1]

auto[0]

auto[1]

67

1

T154

5

T155

1

T156

2

all_values[2]

auto[1]

auto[1]

auto[1]

50

1

T155

1

T156

3

T341

2

all_values[3]

auto[0]

auto[0]

auto[0]

53

1

T154

2

T341

3

T222

3

all_values[3]

auto[0]

auto[0]

auto[1]

23

1

T156

4

T342

1

T343

2

all_values[3]

auto[0]

auto[1]

auto[0]

58

1

T155

4

T156

2

T222

1

all_values[3]

auto[0]

auto[1]

auto[1]

32

1

T154

1

T155

2

T343

1

all_values[3]

auto[1]

auto[0]

auto[1]

49

1

T341

1

T344

1

T345

2

all_values[3]

auto[1]

auto[1]

auto[1]

63

1

T154

4

T155

1

T156

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal