Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	91823	1			T7	177		T20	281		T4	96
accum_cnt_1000	238874	1			T2	58		T7	2197		T8	2058
accum_cnt_100	28776	1			T2	13		T7	152		T13	10
accum_cnt_50	66014	1			T1	23		T2	10		T3	12
accum_cnt_10	178216	1			T1	47		T2	91		T3	2
accum_cnt_0	428113	1			T1	14		T2	176		T3	42

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	268614	1			T1	21		T2	87		T3	14
class_index[0x1]	268614	1			T1	21		T2	87		T3	14
class_index[0x2]	268614	1			T1	21		T2	87		T3	14
class_index[0x3]	268614	1			T1	21		T2	87		T3	14

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	21945	1			T22	541		T43	560		T26	64
class_index[0x0]	accum_cnt_1000	61655	1			T2	58		T8	1015		T9	925
class_index[0x0]	accum_cnt_100	7448	1			T2	13		T13	10		T8	161
class_index[0x0]	accum_cnt_50	22547	1			T1	17		T2	10		T3	12
class_index[0x0]	accum_cnt_10	49810	1			T1	4		T2	5		T3	2
class_index[0x0]	accum_cnt_0	95243	1			T2	1		T7	2		T16	2
class_index[0x1]	accum_cnt_2000	24042	1			T20	281		T5	599		T6	79
class_index[0x1]	accum_cnt_1000	60506	1			T7	1165		T8	1043		T23	9
class_index[0x1]	accum_cnt_100	6163	1			T7	91		T8	185		T23	15
class_index[0x1]	accum_cnt_50	12762	1			T1	6		T7	52		T8	105
class_index[0x1]	accum_cnt_10	36873	1			T1	12		T7	16		T15	23
class_index[0x1]	accum_cnt_0	120157	1			T1	3		T2	87		T3	14
class_index[0x2]	accum_cnt_2000	22024	1			T22	575		T43	673		T32	62
class_index[0x2]	accum_cnt_1000	58473	1			T9	957		T4	819		T5	143
class_index[0x2]	accum_cnt_100	6720	1			T9	58		T4	55		T5	74
class_index[0x2]	accum_cnt_50	15370	1			T9	39		T24	56		T4	45
class_index[0x2]	accum_cnt_10	45352	1			T1	19		T7	1323		T15	25
class_index[0x2]	accum_cnt_0	108530	1			T1	2		T2	87		T3	14
class_index[0x3]	accum_cnt_2000	23812	1			T7	177		T4	96		T5	229
class_index[0x3]	accum_cnt_1000	58240	1			T7	1032		T9	816		T4	768
class_index[0x3]	accum_cnt_100	8445	1			T7	61		T9	125		T4	33
class_index[0x3]	accum_cnt_50	15335	1			T7	36		T9	115		T4	30
class_index[0x3]	accum_cnt_10	46181	1			T1	12		T2	86		T7	15
class_index[0x3]	accum_cnt_0	104183	1			T1	9		T2	1		T3	14