Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	12427	1			T19	1		T32	5		T189	1
alert[0x1]	9503	1			T6	5		T31	78		T32	4709
alert[0x2]	7001	1			T44	1		T6	1		T33	166
alert[0x3]	9089	1			T6	17		T29	83		T48	3
alert[0x4]	4787	1			T6	12		T31	179		T26	5
alert[0x5]	11872	1			T30	3		T63	1		T31	29
alert[0x6]	10773	1			T6	259		T31	25		T218	1
alert[0x7]	18317	1			T26	1		T19	1		T33	224
alert[0x8]	7821	1			T7	1		T5	14		T30	2
alert[0x9]	1723	1			T6	102		T31	14		T32	104
alert[0xa]	5117	1			T7	1		T6	1		T17	1
alert[0xb]	6158	1			T6	1987		T31	7		T26	1
alert[0xc]	6557	1			T5	87		T6	21		T31	105
alert[0xd]	8176	1			T5	36		T6	122		T31	30
alert[0xe]	2916	1			T26	1		T18	1		T33	1195
alert[0xf]	10079	1			T5	31		T31	536		T33	1055
alert[0x10]	4238	1			T4	2		T31	7		T46	43
alert[0x11]	13865	1			T44	1		T5	51		T6	1
alert[0x12]	6591	1			T6	8		T30	5		T31	476
alert[0x13]	5616	1			T5	30		T32	3		T87	19
alert[0x14]	6175	1			T5	1		T63	1		T31	574
alert[0x15]	5200	1			T9	1		T5	27		T17	1
alert[0x16]	11441	1			T7	1		T30	5		T31	139
alert[0x17]	6656	1			T6	39		T46	62		T29	313
alert[0x18]	9723	1			T5	1107		T6	120		T17	1
alert[0x19]	8082	1			T44	1		T5	295		T30	1
alert[0x1a]	4802	1			T44	2		T6	1458		T31	62
alert[0x1b]	5683	1			T5	154		T31	377		T19	1
alert[0x1c]	5008	1			T44	6		T31	136		T32	531
alert[0x1d]	10070	1			T8	1		T32	31		T33	45
alert[0x1e]	9490	1			T5	128		T18	1		T32	17
alert[0x1f]	14998	1			T19	1		T64	1		T33	478
alert[0x20]	10228	1			T5	76		T31	227		T26	2
alert[0x21]	19640	1			T7	1		T6	302		T19	1
alert[0x22]	9512	1			T8	2		T5	37		T6	982
alert[0x23]	3321	1			T4	3		T30	23		T31	390
alert[0x24]	6231	1			T4	2		T19	1		T48	2
alert[0x25]	4070	1			T17	1		T26	41		T32	189
alert[0x26]	4915	1			T4	1		T29	238		T72	4
alert[0x27]	3034	1			T31	12		T26	1		T46	35
alert[0x28]	8603	1			T63	1		T19	1		T33	425
alert[0x29]	4952	1			T5	65		T46	584		T29	229
alert[0x2a]	4350	1			T5	332		T6	77		T19	1
alert[0x2b]	11631	1			T5	141		T19	1		T32	27
alert[0x2c]	8588	1			T29	11		T218	1		T52	11
alert[0x2d]	2325	1			T5	16		T26	1		T19	1
alert[0x2e]	5581	1			T4	1		T31	49		T18	1
alert[0x2f]	8865	1			T6	9		T31	8		T32	162
alert[0x30]	4793	1			T7	3		T8	2		T21	1
alert[0x31]	7053	1			T6	9		T17	1		T31	1137
alert[0x32]	2170	1			T6	103		T32	26		T87	29
alert[0x33]	4182	1			T31	124		T26	3		T32	677
alert[0x34]	6630	1			T5	257		T6	108		T32	55
alert[0x35]	13925	1			T44	1		T5	199		T30	1
alert[0x36]	3830	1			T44	7		T6	837		T17	1
alert[0x37]	6854	1			T6	694		T31	6		T18	1
alert[0x38]	6366	1			T5	161		T30	1		T18	1
alert[0x39]	1481	1			T6	138		T32	73		T48	1
alert[0x3a]	1997	1			T5	21		T6	2		T26	4
alert[0x3b]	5995	1			T31	14		T26	1		T32	19
alert[0x3c]	3407	1			T5	44		T17	1		T18	1
alert[0x3d]	6821	1			T5	1088		T31	173		T18	1
alert[0x3e]	10376	1			T5	446		T30	13		T31	1863
alert[0x3f]	8153	1			T44	1		T5	3		T32	1
alert[0x40]	8208	1			T5	30		T31	26		T189	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	132654	1			T9	1		T4	2		T30	101
class_i[0x1]	92345	1			T4	5		T5	684		T6	55
class_i[0x2]	146960	1			T7	7		T8	5		T4	2
class_i[0x3]	106082	1			T21	1		T44	20		T5	5143

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

477411

1

T44

20

T4

9

T5

6643

alert_ping_fail

630

1

T7

7

T8

5

T9

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	12419	1			T32	5		T46	2266		T29	42
alert_integrity_fail	alert[0x1]	9496	1			T6	5		T31	78		T32	4709
alert_integrity_fail	alert[0x2]	6992	1			T44	1		T6	1		T33	166
alert_integrity_fail	alert[0x3]	9085	1			T6	17		T29	83		T48	3
alert_integrity_fail	alert[0x4]	4775	1			T6	12		T31	179		T26	5
alert_integrity_fail	alert[0x5]	11860	1			T30	3		T31	29		T46	19
alert_integrity_fail	alert[0x6]	10758	1			T6	259		T31	25		T50	1252
alert_integrity_fail	alert[0x7]	18302	1			T26	1		T33	224		T48	2
alert_integrity_fail	alert[0x8]	7811	1			T5	14		T30	2		T31	516
alert_integrity_fail	alert[0x9]	1718	1			T6	102		T31	14		T32	104
alert_integrity_fail	alert[0xa]	5104	1			T6	1		T32	33		T112	3
alert_integrity_fail	alert[0xb]	6152	1			T6	1987		T31	7		T26	1
alert_integrity_fail	alert[0xc]	6551	1			T5	87		T6	21		T31	105
alert_integrity_fail	alert[0xd]	8169	1			T5	36		T6	122		T31	30
alert_integrity_fail	alert[0xe]	2905	1			T26	1		T33	1195		T46	163
alert_integrity_fail	alert[0xf]	10072	1			T5	31		T31	536		T33	1055
alert_integrity_fail	alert[0x10]	4225	1			T4	2		T31	7		T46	43
alert_integrity_fail	alert[0x11]	13858	1			T44	1		T5	51		T6	1
alert_integrity_fail	alert[0x12]	6585	1			T6	8		T30	5		T31	476
alert_integrity_fail	alert[0x13]	5605	1			T5	30		T32	3		T87	19
alert_integrity_fail	alert[0x14]	6163	1			T5	1		T31	574		T32	83
alert_integrity_fail	alert[0x15]	5186	1			T5	27		T31	1		T32	151
alert_integrity_fail	alert[0x16]	11426	1			T30	5		T31	139		T26	4
alert_integrity_fail	alert[0x17]	6648	1			T6	39		T46	62		T29	313
alert_integrity_fail	alert[0x18]	9717	1			T5	1107		T6	120		T72	250
alert_integrity_fail	alert[0x19]	8076	1			T44	1		T5	295		T30	1
alert_integrity_fail	alert[0x1a]	4790	1			T44	2		T6	1458		T31	62
alert_integrity_fail	alert[0x1b]	5667	1			T5	154		T31	377		T32	1092
alert_integrity_fail	alert[0x1c]	5000	1			T44	6		T31	136		T32	531
alert_integrity_fail	alert[0x1d]	10064	1			T32	31		T33	45		T48	1
alert_integrity_fail	alert[0x1e]	9482	1			T5	128		T32	17		T46	33
alert_integrity_fail	alert[0x1f]	14988	1			T33	478		T29	2244		T72	567
alert_integrity_fail	alert[0x20]	10218	1			T5	76		T31	227		T26	2
alert_integrity_fail	alert[0x21]	19629	1			T6	302		T46	1141		T29	12
alert_integrity_fail	alert[0x22]	9501	1			T5	37		T6	982		T30	38
alert_integrity_fail	alert[0x23]	3308	1			T4	3		T30	23		T31	390
alert_integrity_fail	alert[0x24]	6224	1			T4	2		T48	2		T49	1
alert_integrity_fail	alert[0x25]	4063	1			T26	41		T32	189		T46	39
alert_integrity_fail	alert[0x26]	4911	1			T4	1		T29	238		T72	4
alert_integrity_fail	alert[0x27]	3025	1			T31	12		T26	1		T46	35
alert_integrity_fail	alert[0x28]	8592	1			T33	425		T48	24		T54	3
alert_integrity_fail	alert[0x29]	4943	1			T5	65		T46	584		T29	229
alert_integrity_fail	alert[0x2a]	4339	1			T5	332		T6	77		T33	733
alert_integrity_fail	alert[0x2b]	11617	1			T5	141		T32	27		T33	32
alert_integrity_fail	alert[0x2c]	8573	1			T29	11		T52	11		T289	2
alert_integrity_fail	alert[0x2d]	2315	1			T5	16		T26	1		T33	29
alert_integrity_fail	alert[0x2e]	5570	1			T4	1		T31	49		T29	65
alert_integrity_fail	alert[0x2f]	8853	1			T6	9		T31	8		T32	162
alert_integrity_fail	alert[0x30]	4774	1			T5	1766		T31	21		T46	33
alert_integrity_fail	alert[0x31]	7041	1			T6	9		T31	1137		T32	100
alert_integrity_fail	alert[0x32]	2161	1			T6	103		T32	26		T87	29
alert_integrity_fail	alert[0x33]	4172	1			T31	124		T26	3		T32	677
alert_integrity_fail	alert[0x34]	6622	1			T5	257		T6	108		T32	55
alert_integrity_fail	alert[0x35]	13917	1			T44	1		T5	199		T30	1
alert_integrity_fail	alert[0x36]	3821	1			T44	7		T6	837		T30	18
alert_integrity_fail	alert[0x37]	6845	1			T6	694		T31	6		T48	7
alert_integrity_fail	alert[0x38]	6356	1			T5	161		T30	1		T32	14
alert_integrity_fail	alert[0x39]	1473	1			T6	138		T32	73		T48	1
alert_integrity_fail	alert[0x3a]	1989	1			T5	21		T6	2		T26	4
alert_integrity_fail	alert[0x3b]	5988	1			T31	14		T26	1		T32	19
alert_integrity_fail	alert[0x3c]	3395	1			T5	44		T32	246		T33	110
alert_integrity_fail	alert[0x3d]	6816	1			T5	1088		T31	173		T32	128
alert_integrity_fail	alert[0x3e]	10361	1			T5	446		T30	13		T31	1863
alert_integrity_fail	alert[0x3f]	8150	1			T44	1		T5	3		T32	1
alert_integrity_fail	alert[0x40]	8200	1			T5	30		T31	26		T48	5
alert_ping_fail	alert[0x0]	8	1			T19	1		T189	1		T218	2
alert_ping_fail	alert[0x1]	7	1			T290	1		T291	1		T292	1
alert_ping_fail	alert[0x2]	9	1			T290	1		T293	1		T291	1
alert_ping_fail	alert[0x3]	4	1			T218	1		T294	1		T295	1
alert_ping_fail	alert[0x4]	12	1			T108	1		T296	1		T293	1
alert_ping_fail	alert[0x5]	12	1			T63	1		T286	1		T218	1
alert_ping_fail	alert[0x6]	15	1			T218	1		T293	1		T291	1
alert_ping_fail	alert[0x7]	15	1			T19	1		T216	1		T297	1
alert_ping_fail	alert[0x8]	10	1			T7	1		T216	1		T218	1
alert_ping_fail	alert[0x9]	5	1			T189	1		T107	1		T298	1
alert_ping_fail	alert[0xa]	13	1			T7	1		T17	1		T299	1
alert_ping_fail	alert[0xb]	6	1			T295	1		T300	1		T301	1
alert_ping_fail	alert[0xc]	6	1			T19	1		T108	1		T216	1
alert_ping_fail	alert[0xd]	7	1			T296	1		T302	1		T292	1
alert_ping_fail	alert[0xe]	11	1			T18	1		T107	1		T298	1
alert_ping_fail	alert[0xf]	7	1			T294	1		T292	1		T303	1
alert_ping_fail	alert[0x10]	13	1			T304	1		T218	2		T293	1
alert_ping_fail	alert[0x11]	7	1			T290	1		T296	1		T291	2
alert_ping_fail	alert[0x12]	6	1			T305	1		T291	1		T302	1
alert_ping_fail	alert[0x13]	11	1			T290	1		T306	1		T307	1
alert_ping_fail	alert[0x14]	12	1			T63	1		T286	1		T218	1
alert_ping_fail	alert[0x15]	14	1			T9	1		T17	1		T218	1
alert_ping_fail	alert[0x16]	15	1			T7	1		T107	1		T286	1
alert_ping_fail	alert[0x17]	8	1			T308	1		T309	1		T310	1
alert_ping_fail	alert[0x18]	6	1			T17	1		T294	1		T303	1
alert_ping_fail	alert[0x19]	6	1			T18	1		T189	1		T108	1
alert_ping_fail	alert[0x1a]	12	1			T19	1		T218	1		T308	2
alert_ping_fail	alert[0x1b]	16	1			T19	1		T189	1		T296	1
alert_ping_fail	alert[0x1c]	8	1			T311	1		T303	1		T295	1
alert_ping_fail	alert[0x1d]	6	1			T8	1		T218	1		T306	1
alert_ping_fail	alert[0x1e]	8	1			T18	1		T218	1		T293	1
alert_ping_fail	alert[0x1f]	10	1			T19	1		T64	1		T107	1
alert_ping_fail	alert[0x20]	10	1			T189	1		T304	1		T216	1
alert_ping_fail	alert[0x21]	11	1			T7	1		T19	1		T298	1
alert_ping_fail	alert[0x22]	11	1			T8	2		T218	1		T288	1
alert_ping_fail	alert[0x23]	13	1			T19	1		T189	1		T290	1
alert_ping_fail	alert[0x24]	7	1			T19	1		T290	1		T308	1
alert_ping_fail	alert[0x25]	7	1			T17	1		T302	1		T295	1
alert_ping_fail	alert[0x26]	4	1			T312	1		T313	1		T301	1
alert_ping_fail	alert[0x27]	9	1			T304	1		T216	1		T296	1
alert_ping_fail	alert[0x28]	11	1			T63	1		T19	1		T108	1
alert_ping_fail	alert[0x29]	9	1			T218	1		T314	1		T315	1
alert_ping_fail	alert[0x2a]	11	1			T19	1		T218	1		T316	1
alert_ping_fail	alert[0x2b]	14	1			T19	1		T216	1		T218	1
alert_ping_fail	alert[0x2c]	15	1			T218	1		T316	1		T303	1
alert_ping_fail	alert[0x2d]	10	1			T19	1		T304	1		T308	3
alert_ping_fail	alert[0x2e]	11	1			T18	1		T296	1		T316	1
alert_ping_fail	alert[0x2f]	12	1			T189	1		T305	2		T314	1
alert_ping_fail	alert[0x30]	19	1			T7	3		T8	2		T21	1
alert_ping_fail	alert[0x31]	12	1			T17	1		T304	1		T108	1
alert_ping_fail	alert[0x32]	9	1			T216	2		T308	1		T292	1
alert_ping_fail	alert[0x33]	10	1			T294	1		T314	1		T308	1
alert_ping_fail	alert[0x34]	8	1			T291	1		T311	1		T306	1
alert_ping_fail	alert[0x35]	8	1			T290	2		T308	1		T311	1
alert_ping_fail	alert[0x36]	9	1			T17	1		T216	1		T291	1
alert_ping_fail	alert[0x37]	9	1			T18	1		T296	1		T295	1
alert_ping_fail	alert[0x38]	10	1			T18	1		T291	1		T314	1
alert_ping_fail	alert[0x39]	8	1			T218	1		T294	1		T311	1
alert_ping_fail	alert[0x3a]	8	1			T311	1		T98	1		T315	1
alert_ping_fail	alert[0x3b]	7	1			T290	1		T308	1		T306	1
alert_ping_fail	alert[0x3c]	12	1			T17	1		T18	1		T306	1
alert_ping_fail	alert[0x3d]	5	1			T18	1		T303	1		T317	1
alert_ping_fail	alert[0x3e]	15	1			T218	1		T290	1		T291	1
alert_ping_fail	alert[0x3f]	3	1			T189	1		T291	1		T318	1
alert_ping_fail	alert[0x40]	8	1			T189	1		T308	1		T292	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	132474	1			T4	2		T30	101		T31	56
alert_integrity_fail	class_i[0x1]	92200	1			T4	5		T5	684		T6	55
alert_integrity_fail	class_i[0x2]	146822	1			T4	2		T5	816		T6	7359
alert_integrity_fail	class_i[0x3]	105915	1			T44	20		T5	5143		T30	1
alert_ping_fail	class_i[0x0]	180	1			T9	1		T107	3		T290	1
alert_ping_fail	class_i[0x1]	145	1			T17	2		T18	8		T19	2
alert_ping_fail	class_i[0x2]	138	1			T7	7		T8	5		T17	5
alert_ping_fail	class_i[0x3]	167	1			T21	1		T19	11		T64	1