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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.22 99.99 98.64 97.06 100.00 100.00 99.38 99.44


Total test records in report: 832
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T774 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.706210283 Aug 07 06:16:32 PM PDT 24 Aug 07 06:16:38 PM PDT 24 74139990 ps
T131 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2626546807 Aug 07 06:16:38 PM PDT 24 Aug 07 06:18:56 PM PDT 24 1996747317 ps
T775 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.878639742 Aug 07 06:16:18 PM PDT 24 Aug 07 06:16:20 PM PDT 24 8333141 ps
T776 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.853964227 Aug 07 06:16:19 PM PDT 24 Aug 07 06:16:24 PM PDT 24 258724873 ps
T777 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1804050657 Aug 07 06:16:51 PM PDT 24 Aug 07 06:16:53 PM PDT 24 27437668 ps
T132 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1203135318 Aug 07 06:16:20 PM PDT 24 Aug 07 06:31:43 PM PDT 24 12421620726 ps
T778 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1019694122 Aug 07 06:16:17 PM PDT 24 Aug 07 06:16:27 PM PDT 24 1220613015 ps
T145 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3096250132 Aug 07 06:16:41 PM PDT 24 Aug 07 06:24:34 PM PDT 24 43711071009 ps
T779 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.130471375 Aug 07 06:16:19 PM PDT 24 Aug 07 06:16:24 PM PDT 24 54201541 ps
T780 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2793103828 Aug 07 06:16:23 PM PDT 24 Aug 07 06:17:08 PM PDT 24 710448881 ps
T781 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1500890416 Aug 07 06:16:49 PM PDT 24 Aug 07 06:16:50 PM PDT 24 24696734 ps
T134 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3845410362 Aug 07 06:16:26 PM PDT 24 Aug 07 06:19:41 PM PDT 24 2010008761 ps
T140 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1808528691 Aug 07 06:16:44 PM PDT 24 Aug 07 06:18:33 PM PDT 24 1017558877 ps
T142 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3020762338 Aug 07 06:16:45 PM PDT 24 Aug 07 06:27:28 PM PDT 24 8629697405 ps
T782 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3766108245 Aug 07 06:16:52 PM PDT 24 Aug 07 06:16:54 PM PDT 24 11183495 ps
T783 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.982086999 Aug 07 06:16:29 PM PDT 24 Aug 07 06:16:31 PM PDT 24 8441170 ps
T784 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1688713122 Aug 07 06:16:49 PM PDT 24 Aug 07 06:16:51 PM PDT 24 14572937 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2124656779 Aug 07 06:16:20 PM PDT 24 Aug 07 06:16:44 PM PDT 24 951994670 ps
T261 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2307907463 Aug 07 06:16:42 PM PDT 24 Aug 07 06:17:27 PM PDT 24 1677768941 ps
T786 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1074200265 Aug 07 06:16:25 PM PDT 24 Aug 07 06:16:46 PM PDT 24 162432603 ps
T787 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1994381025 Aug 07 06:16:19 PM PDT 24 Aug 07 06:22:31 PM PDT 24 19048821524 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1831140472 Aug 07 06:16:23 PM PDT 24 Aug 07 06:16:28 PM PDT 24 206966117 ps
T789 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3034374311 Aug 07 06:16:44 PM PDT 24 Aug 07 06:16:49 PM PDT 24 108053789 ps
T790 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.403842444 Aug 07 06:16:36 PM PDT 24 Aug 07 06:16:44 PM PDT 24 378220507 ps
T117 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3753087465 Aug 07 06:16:23 PM PDT 24 Aug 07 06:37:51 PM PDT 24 112452508440 ps
T350 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2838928167 Aug 07 06:16:25 PM PDT 24 Aug 07 06:25:03 PM PDT 24 7200290636 ps
T791 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3331820696 Aug 07 06:16:27 PM PDT 24 Aug 07 06:16:31 PM PDT 24 27148352 ps
T792 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1642849478 Aug 07 06:16:43 PM PDT 24 Aug 07 06:16:52 PM PDT 24 57704854 ps
T162 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.666753248 Aug 07 06:16:43 PM PDT 24 Aug 07 06:17:54 PM PDT 24 1771665447 ps
T793 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3387882338 Aug 07 06:16:50 PM PDT 24 Aug 07 06:16:52 PM PDT 24 10709307 ps
T794 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.688155419 Aug 07 06:16:34 PM PDT 24 Aug 07 06:16:39 PM PDT 24 132247047 ps
T171 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3222082753 Aug 07 06:16:40 PM PDT 24 Aug 07 06:16:44 PM PDT 24 173586074 ps
T795 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3606891933 Aug 07 06:16:48 PM PDT 24 Aug 07 06:16:50 PM PDT 24 17242485 ps
T796 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2051444005 Aug 07 06:16:43 PM PDT 24 Aug 07 06:16:48 PM PDT 24 232519339 ps
T797 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4293903075 Aug 07 06:16:18 PM PDT 24 Aug 07 06:16:23 PM PDT 24 54972286 ps
T798 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.605559734 Aug 07 06:16:19 PM PDT 24 Aug 07 06:16:36 PM PDT 24 244944355 ps
T799 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2153667386 Aug 07 06:16:42 PM PDT 24 Aug 07 06:17:31 PM PDT 24 687550963 ps
T800 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1830975391 Aug 07 06:16:16 PM PDT 24 Aug 07 06:16:29 PM PDT 24 356115742 ps
T801 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1339751616 Aug 07 06:16:19 PM PDT 24 Aug 07 06:16:21 PM PDT 24 24165848 ps
T802 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1879150375 Aug 07 06:16:41 PM PDT 24 Aug 07 06:16:47 PM PDT 24 180103762 ps
T803 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.150794881 Aug 07 06:16:26 PM PDT 24 Aug 07 06:16:29 PM PDT 24 66744662 ps
T804 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1561142062 Aug 07 06:16:30 PM PDT 24 Aug 07 06:16:40 PM PDT 24 350127140 ps
T805 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.90901499 Aug 07 06:16:51 PM PDT 24 Aug 07 06:16:52 PM PDT 24 8708355 ps
T806 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1253889891 Aug 07 06:16:30 PM PDT 24 Aug 07 06:16:35 PM PDT 24 44944799 ps
T807 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2999266083 Aug 07 06:16:51 PM PDT 24 Aug 07 06:16:53 PM PDT 24 21829908 ps
T808 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1231958304 Aug 07 06:16:24 PM PDT 24 Aug 07 06:16:44 PM PDT 24 1020727257 ps
T809 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.585967504 Aug 07 06:16:26 PM PDT 24 Aug 07 06:16:28 PM PDT 24 8249864 ps
T810 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3707880225 Aug 07 06:16:47 PM PDT 24 Aug 07 06:16:48 PM PDT 24 6858077 ps
T811 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.208482532 Aug 07 06:16:29 PM PDT 24 Aug 07 06:16:31 PM PDT 24 12380314 ps
T118 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3244482764 Aug 07 06:16:10 PM PDT 24 Aug 07 06:19:41 PM PDT 24 2289776779 ps
T812 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2416395642 Aug 07 06:16:31 PM PDT 24 Aug 07 06:16:43 PM PDT 24 288205889 ps
T143 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1047498032 Aug 07 06:16:30 PM PDT 24 Aug 07 06:18:49 PM PDT 24 23776794816 ps
T147 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2340476278 Aug 07 06:16:46 PM PDT 24 Aug 07 06:27:28 PM PDT 24 5339959432 ps
T813 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3457424093 Aug 07 06:16:42 PM PDT 24 Aug 07 06:16:55 PM PDT 24 332753453 ps
T144 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3519337696 Aug 07 06:16:25 PM PDT 24 Aug 07 06:19:14 PM PDT 24 2617299600 ps
T814 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.866030330 Aug 07 06:16:23 PM PDT 24 Aug 07 06:16:47 PM PDT 24 615927058 ps
T149 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.509826661 Aug 07 06:16:38 PM PDT 24 Aug 07 06:23:39 PM PDT 24 24267030798 ps
T815 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1129506638 Aug 07 06:16:26 PM PDT 24 Aug 07 06:19:43 PM PDT 24 3334883088 ps
T163 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.965468960 Aug 07 06:16:30 PM PDT 24 Aug 07 06:17:53 PM PDT 24 6532638396 ps
T816 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2122616499 Aug 07 06:16:21 PM PDT 24 Aug 07 06:26:31 PM PDT 24 16773389025 ps
T817 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3647837733 Aug 07 06:16:38 PM PDT 24 Aug 07 06:16:39 PM PDT 24 8332038 ps
T164 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.17344557 Aug 07 06:16:37 PM PDT 24 Aug 07 06:17:01 PM PDT 24 629044408 ps
T818 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2845421017 Aug 07 06:16:48 PM PDT 24 Aug 07 06:16:50 PM PDT 24 15706450 ps
T819 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2900557741 Aug 07 06:16:23 PM PDT 24 Aug 07 06:16:29 PM PDT 24 244498779 ps
T157 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3546700528 Aug 07 06:16:16 PM PDT 24 Aug 07 06:16:37 PM PDT 24 520598431 ps
T150 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2500877368 Aug 07 06:16:39 PM PDT 24 Aug 07 06:19:06 PM PDT 24 3207226823 ps
T820 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.840214114 Aug 07 06:16:34 PM PDT 24 Aug 07 06:16:43 PM PDT 24 64460914 ps
T821 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4089402420 Aug 07 06:16:21 PM PDT 24 Aug 07 06:16:33 PM PDT 24 186908454 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1073492304 Aug 07 06:16:18 PM PDT 24 Aug 07 06:16:45 PM PDT 24 191523972 ps
T121 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2918950671 Aug 07 06:16:32 PM PDT 24 Aug 07 06:27:07 PM PDT 24 23252621397 ps
T823 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3133143519 Aug 07 06:16:28 PM PDT 24 Aug 07 06:16:37 PM PDT 24 442387335 ps
T146 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1214319183 Aug 07 06:16:16 PM PDT 24 Aug 07 06:18:54 PM PDT 24 2249587304 ps
T824 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4242398904 Aug 07 06:16:26 PM PDT 24 Aug 07 06:16:35 PM PDT 24 496255097 ps
T825 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3293393194 Aug 07 06:16:44 PM PDT 24 Aug 07 06:17:24 PM PDT 24 512442246 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1336853945 Aug 07 06:16:20 PM PDT 24 Aug 07 06:21:09 PM PDT 24 4298219285 ps
T148 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3262010691 Aug 07 06:16:40 PM PDT 24 Aug 07 06:33:47 PM PDT 24 30618704961 ps
T827 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2581432944 Aug 07 06:16:16 PM PDT 24 Aug 07 06:16:36 PM PDT 24 531319236 ps
T828 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1910806681 Aug 07 06:16:31 PM PDT 24 Aug 07 06:16:38 PM PDT 24 386296258 ps
T829 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.219932630 Aug 07 06:16:20 PM PDT 24 Aug 07 06:16:26 PM PDT 24 64413871 ps
T830 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.674116820 Aug 07 06:16:52 PM PDT 24 Aug 07 06:16:53 PM PDT 24 9568566 ps
T831 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1857465122 Aug 07 06:16:19 PM PDT 24 Aug 07 06:20:15 PM PDT 24 46516952338 ps
T832 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3494444803 Aug 07 06:16:26 PM PDT 24 Aug 07 06:16:34 PM PDT 24 365131111 ps

Test location /workspace/coverage/default/7.alert_handler_random_classes.2548998367
Short name T1
Test name
Test status
Simulation time 1199769462 ps
CPU time 27.32 seconds
Started Aug 07 07:15:20 PM PDT 24
Finished Aug 07 07:15:47 PM PDT 24
Peak memory 256124 kb
Host smart-feed80ef-c7ba-470b-8fdc-f50562f924ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25489
98367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2548998367
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.895439764
Short name T5
Test name
Test status
Simulation time 177322075053 ps
CPU time 6065.96 seconds
Started Aug 07 07:19:54 PM PDT 24
Finished Aug 07 09:01:01 PM PDT 24
Peak memory 333036 kb
Host smart-d2ccd30e-ca84-4f65-8811-6c8c86a6446d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895439764 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.895439764
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1545958524
Short name T11
Test name
Test status
Simulation time 1850472067 ps
CPU time 25.22 seconds
Started Aug 07 07:15:05 PM PDT 24
Finished Aug 07 07:15:31 PM PDT 24
Peak memory 269832 kb
Host smart-407524ae-a2dc-4160-9077-93972a93720f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1545958524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1545958524
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1634132922
Short name T61
Test name
Test status
Simulation time 525798675171 ps
CPU time 5614.06 seconds
Started Aug 07 07:18:44 PM PDT 24
Finished Aug 07 08:52:18 PM PDT 24
Peak memory 317076 kb
Host smart-6252e7a1-74e3-4e61-b81b-762cc5ad7775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634132922 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1634132922
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2024322288
Short name T30
Test name
Test status
Simulation time 145239950583 ps
CPU time 2356.17 seconds
Started Aug 07 07:15:27 PM PDT 24
Finished Aug 07 07:54:44 PM PDT 24
Peak memory 289000 kb
Host smart-2fdf26a9-68a0-42c7-9d63-dfb4bdd9ac10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024322288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2024322288
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.489191084
Short name T151
Test name
Test status
Simulation time 501672670 ps
CPU time 35.15 seconds
Started Aug 07 06:16:44 PM PDT 24
Finished Aug 07 06:17:20 PM PDT 24
Peak memory 237908 kb
Host smart-55c7cc93-09b2-46f8-b497-ca7fb6d10215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=489191084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.489191084
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1420952685
Short name T8
Test name
Test status
Simulation time 55154689086 ps
CPU time 3364.33 seconds
Started Aug 07 07:21:25 PM PDT 24
Finished Aug 07 08:17:30 PM PDT 24
Peak memory 289040 kb
Host smart-59278651-cdc6-451a-9ef2-57f7c0088849
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420952685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1420952685
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.4168893676
Short name T29
Test name
Test status
Simulation time 86686266127 ps
CPU time 1531.83 seconds
Started Aug 07 07:17:57 PM PDT 24
Finished Aug 07 07:43:29 PM PDT 24
Peak memory 273172 kb
Host smart-4aed16c4-d8af-4f6d-b7f6-17a9ca7ee9fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168893676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.4168893676
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1101783485
Short name T116
Test name
Test status
Simulation time 4823309945 ps
CPU time 228.08 seconds
Started Aug 07 06:16:28 PM PDT 24
Finished Aug 07 06:20:17 PM PDT 24
Peak memory 265652 kb
Host smart-4e4c8762-306f-4fed-995d-8c57e5d621d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1101783485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1101783485
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3424334697
Short name T26
Test name
Test status
Simulation time 201939322547 ps
CPU time 4045.53 seconds
Started Aug 07 07:19:23 PM PDT 24
Finished Aug 07 08:26:49 PM PDT 24
Peak memory 304712 kb
Host smart-97a41e42-095d-4aaa-a9f9-90b9881bf67e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424334697 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3424334697
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.41422158
Short name T124
Test name
Test status
Simulation time 66939018733 ps
CPU time 1127.48 seconds
Started Aug 07 06:16:22 PM PDT 24
Finished Aug 07 06:35:10 PM PDT 24
Peak memory 265952 kb
Host smart-27b79241-1b1d-470b-b9d1-3dec8e3f27f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41422158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.41422158
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2743258863
Short name T273
Test name
Test status
Simulation time 111011499573 ps
CPU time 2253.91 seconds
Started Aug 07 07:16:03 PM PDT 24
Finished Aug 07 07:53:38 PM PDT 24
Peak memory 287124 kb
Host smart-f8888edf-6851-418c-96e9-d0496b5fff72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743258863 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2743258863
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.763778681
Short name T186
Test name
Test status
Simulation time 4495069692 ps
CPU time 43.14 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 07:15:50 PM PDT 24
Peak memory 248528 kb
Host smart-4b3839aa-2782-45a0-8282-486a2e62fee2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=763778681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.763778681
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1203135318
Short name T132
Test name
Test status
Simulation time 12421620726 ps
CPU time 922.74 seconds
Started Aug 07 06:16:20 PM PDT 24
Finished Aug 07 06:31:43 PM PDT 24
Peak memory 265636 kb
Host smart-20f61da6-adae-4380-b865-d5e5c4b4f0c0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203135318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1203135318
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2801019270
Short name T48
Test name
Test status
Simulation time 60232690976 ps
CPU time 1214.26 seconds
Started Aug 07 07:15:38 PM PDT 24
Finished Aug 07 07:35:52 PM PDT 24
Peak memory 286100 kb
Host smart-d7802435-3869-4c1c-9c2b-eb9f3ba7ba37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801019270 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2801019270
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3545182120
Short name T114
Test name
Test status
Simulation time 6501989076 ps
CPU time 200.4 seconds
Started Aug 07 06:16:24 PM PDT 24
Finished Aug 07 06:19:45 PM PDT 24
Peak memory 265884 kb
Host smart-798df2de-f48f-4d7c-b321-d53a6c229e9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3545182120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3545182120
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4265180372
Short name T7
Test name
Test status
Simulation time 52638961604 ps
CPU time 3371.86 seconds
Started Aug 07 07:21:16 PM PDT 24
Finished Aug 07 08:17:28 PM PDT 24
Peak memory 287884 kb
Host smart-82bbfff0-e396-4445-ac45-0ac3fb9279ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265180372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4265180372
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3622414467
Short name T346
Test name
Test status
Simulation time 12478987 ps
CPU time 1.35 seconds
Started Aug 07 06:16:27 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 236732 kb
Host smart-32f892d2-109e-4b8c-9501-409b421bc6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3622414467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3622414467
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.4265844622
Short name T218
Test name
Test status
Simulation time 13403488349 ps
CPU time 550.84 seconds
Started Aug 07 07:19:34 PM PDT 24
Finished Aug 07 07:28:45 PM PDT 24
Peak memory 248612 kb
Host smart-451c9ea3-0d48-4688-b6b9-ea75715acaf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265844622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.4265844622
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3262010691
Short name T148
Test name
Test status
Simulation time 30618704961 ps
CPU time 1026.48 seconds
Started Aug 07 06:16:40 PM PDT 24
Finished Aug 07 06:33:47 PM PDT 24
Peak memory 266624 kb
Host smart-a33d596b-4322-44be-8a15-7b1176b5e199
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262010691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3262010691
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.888491995
Short name T326
Test name
Test status
Simulation time 81137506621 ps
CPU time 2469.56 seconds
Started Aug 07 07:16:14 PM PDT 24
Finished Aug 07 07:57:24 PM PDT 24
Peak memory 289440 kb
Host smart-8785cf4b-b3c2-4678-8240-2f6ce1416163
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888491995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.888491995
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.159480253
Short name T296
Test name
Test status
Simulation time 19334966626 ps
CPU time 195.51 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 07:22:10 PM PDT 24
Peak memory 248604 kb
Host smart-11280906-515c-4fbf-b629-6aa106575fb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159480253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.159480253
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3246258546
Short name T113
Test name
Test status
Simulation time 1621525864 ps
CPU time 199.72 seconds
Started Aug 07 06:16:43 PM PDT 24
Finished Aug 07 06:20:03 PM PDT 24
Peak memory 270968 kb
Host smart-d1c8a97f-b0cb-42cb-ab52-4ebff6abcfca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3246258546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3246258546
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3287203107
Short name T262
Test name
Test status
Simulation time 348735475 ps
CPU time 45.76 seconds
Started Aug 07 06:16:27 PM PDT 24
Finished Aug 07 06:17:12 PM PDT 24
Peak memory 237708 kb
Host smart-b300ee29-13d0-4a3b-8aca-e63c7bdf8b68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3287203107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3287203107
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1245889394
Short name T9
Test name
Test status
Simulation time 56047225724 ps
CPU time 1212.7 seconds
Started Aug 07 07:16:53 PM PDT 24
Finished Aug 07 07:37:06 PM PDT 24
Peak memory 282960 kb
Host smart-d234d388-9b1f-41e4-b060-ba143ab5944f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245889394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1245889394
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1885141496
Short name T638
Test name
Test status
Simulation time 52042122690 ps
CPU time 556.25 seconds
Started Aug 07 07:20:21 PM PDT 24
Finished Aug 07 07:29:37 PM PDT 24
Peak memory 248552 kb
Host smart-eb9a158b-b6b7-4577-8096-f9820c034672
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885141496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1885141496
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3753087465
Short name T117
Test name
Test status
Simulation time 112452508440 ps
CPU time 1287.59 seconds
Started Aug 07 06:16:23 PM PDT 24
Finished Aug 07 06:37:51 PM PDT 24
Peak memory 265624 kb
Host smart-c1752b87-0930-4270-a209-215edc4db215
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753087465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3753087465
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3057110298
Short name T223
Test name
Test status
Simulation time 215969423877 ps
CPU time 4148.3 seconds
Started Aug 07 07:16:43 PM PDT 24
Finished Aug 07 08:25:53 PM PDT 24
Peak memory 306084 kb
Host smart-1f066a86-a0db-46fa-a922-3876d2da0390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057110298 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3057110298
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3493813078
Short name T20
Test name
Test status
Simulation time 42704946573 ps
CPU time 1443.13 seconds
Started Aug 07 07:14:54 PM PDT 24
Finished Aug 07 07:38:58 PM PDT 24
Peak memory 273180 kb
Host smart-ac36c941-775e-4944-86b6-05c2bd4e5d0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493813078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3493813078
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4109527947
Short name T63
Test name
Test status
Simulation time 278624924081 ps
CPU time 2277.4 seconds
Started Aug 07 07:16:43 PM PDT 24
Finished Aug 07 07:54:40 PM PDT 24
Peak memory 272424 kb
Host smart-0814e601-2d35-4001-99f8-069be9c9580d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109527947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4109527947
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3651647066
Short name T301
Test name
Test status
Simulation time 73878854616 ps
CPU time 614.45 seconds
Started Aug 07 07:18:02 PM PDT 24
Finished Aug 07 07:28:17 PM PDT 24
Peak memory 248616 kb
Host smart-cbbbd6fc-b595-4207-8401-8afa961087b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651647066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3651647066
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3845410362
Short name T134
Test name
Test status
Simulation time 2010008761 ps
CPU time 194.49 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:19:41 PM PDT 24
Peak memory 265528 kb
Host smart-fa624dd7-2ccb-454b-9c89-33be4659be7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3845410362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3845410362
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2574709546
Short name T189
Test name
Test status
Simulation time 6391565384 ps
CPU time 259.72 seconds
Started Aug 07 07:16:29 PM PDT 24
Finished Aug 07 07:20:49 PM PDT 24
Peak memory 248424 kb
Host smart-3b128d39-4429-402f-a915-e88aa931b877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574709546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2574709546
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.928644225
Short name T343
Test name
Test status
Simulation time 25152782 ps
CPU time 1.43 seconds
Started Aug 07 06:16:48 PM PDT 24
Finished Aug 07 06:16:50 PM PDT 24
Peak memory 236752 kb
Host smart-4ef34e95-b670-44b9-bcb5-6b561cf3e62b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=928644225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.928644225
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2780737080
Short name T327
Test name
Test status
Simulation time 156306894114 ps
CPU time 1478.36 seconds
Started Aug 07 07:17:03 PM PDT 24
Finished Aug 07 07:41:42 PM PDT 24
Peak memory 273112 kb
Host smart-7aec8b96-14be-40e4-b15b-ab1385c01fb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780737080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2780737080
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.793260802
Short name T55
Test name
Test status
Simulation time 77170156718 ps
CPU time 1101.75 seconds
Started Aug 07 07:21:47 PM PDT 24
Finished Aug 07 07:40:09 PM PDT 24
Peak memory 272708 kb
Host smart-674e3e63-414b-475a-924d-b2359051117d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793260802 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.793260802
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3687234393
Short name T6
Test name
Test status
Simulation time 38477740465 ps
CPU time 980.47 seconds
Started Aug 07 07:17:26 PM PDT 24
Finished Aug 07 07:33:47 PM PDT 24
Peak memory 283120 kb
Host smart-80f52e28-3cf8-433c-aaed-02c86e18973a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687234393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3687234393
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2584496651
Short name T136
Test name
Test status
Simulation time 2772045768 ps
CPU time 194.98 seconds
Started Aug 07 06:16:39 PM PDT 24
Finished Aug 07 06:19:54 PM PDT 24
Peak memory 265676 kb
Host smart-3a37b1e3-7355-4438-864f-455c5cd307ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2584496651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2584496651
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1412466281
Short name T236
Test name
Test status
Simulation time 118095079589 ps
CPU time 5824.16 seconds
Started Aug 07 07:19:14 PM PDT 24
Finished Aug 07 08:56:18 PM PDT 24
Peak memory 338324 kb
Host smart-454af27b-395d-49b1-96f8-a4b3b45df2d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412466281 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1412466281
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.225343505
Short name T295
Test name
Test status
Simulation time 106442431984 ps
CPU time 530.44 seconds
Started Aug 07 07:19:14 PM PDT 24
Finished Aug 07 07:28:04 PM PDT 24
Peak memory 248560 kb
Host smart-57a357f4-dbdd-4b13-a967-5987bf2a2304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225343505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.225343505
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1442463139
Short name T122
Test name
Test status
Simulation time 12276954595 ps
CPU time 519.32 seconds
Started Aug 07 06:16:41 PM PDT 24
Finished Aug 07 06:25:20 PM PDT 24
Peak memory 265624 kb
Host smart-f5f584cf-ddd7-475e-915b-26a9b6f77966
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442463139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1442463139
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.581281915
Short name T252
Test name
Test status
Simulation time 45641603029 ps
CPU time 1828.61 seconds
Started Aug 07 07:15:35 PM PDT 24
Finished Aug 07 07:46:04 PM PDT 24
Peak memory 302128 kb
Host smart-9d9fe3e0-17d1-4a3a-a26a-99a813bb2f9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581281915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.581281915
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1200360999
Short name T320
Test name
Test status
Simulation time 96077525652 ps
CPU time 1450.07 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:40:16 PM PDT 24
Peak memory 273128 kb
Host smart-7564c0fd-55d0-43e5-80d9-06925762a662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200360999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1200360999
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.172664318
Short name T60
Test name
Test status
Simulation time 313324606602 ps
CPU time 5025.43 seconds
Started Aug 07 07:16:54 PM PDT 24
Finished Aug 07 08:40:40 PM PDT 24
Peak memory 305872 kb
Host smart-b5a86c61-2e15-4256-b551-0c6a081d9e6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172664318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.172664318
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1714951363
Short name T633
Test name
Test status
Simulation time 40632437899 ps
CPU time 420.9 seconds
Started Aug 07 07:17:45 PM PDT 24
Finished Aug 07 07:24:46 PM PDT 24
Peak memory 247448 kb
Host smart-edd6061d-2ea9-4f1d-94fb-1981c91626a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714951363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1714951363
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2834242827
Short name T248
Test name
Test status
Simulation time 34420384742 ps
CPU time 374.37 seconds
Started Aug 07 07:20:55 PM PDT 24
Finished Aug 07 07:27:10 PM PDT 24
Peak memory 248560 kb
Host smart-2b6fe072-bb20-48e6-8432-4010bd3f7250
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834242827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2834242827
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2124205209
Short name T332
Test name
Test status
Simulation time 49290027145 ps
CPU time 2921.73 seconds
Started Aug 07 07:15:27 PM PDT 24
Finished Aug 07 08:04:10 PM PDT 24
Peak memory 281316 kb
Host smart-86d73113-9408-4438-842d-e3bd6e79dc8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124205209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2124205209
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1271360412
Short name T126
Test name
Test status
Simulation time 23301545362 ps
CPU time 751.85 seconds
Started Aug 07 06:16:31 PM PDT 24
Finished Aug 07 06:29:03 PM PDT 24
Peak memory 265616 kb
Host smart-68b01524-5ecf-4e3b-b44f-c51d1e218bdc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271360412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1271360412
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1652311577
Short name T199
Test name
Test status
Simulation time 267248649 ps
CPU time 3.34 seconds
Started Aug 07 07:14:51 PM PDT 24
Finished Aug 07 07:14:55 PM PDT 24
Peak memory 248668 kb
Host smart-e2df4e2a-0670-4e40-9293-3f66eb0238b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1652311577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1652311577
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.852776542
Short name T193
Test name
Test status
Simulation time 57159529 ps
CPU time 3.13 seconds
Started Aug 07 07:14:57 PM PDT 24
Finished Aug 07 07:15:00 PM PDT 24
Peak memory 248700 kb
Host smart-d2aae040-51e1-42a7-b691-3f76edc2ddf6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=852776542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.852776542
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.939603986
Short name T195
Test name
Test status
Simulation time 25571479 ps
CPU time 2.79 seconds
Started Aug 07 07:16:24 PM PDT 24
Finished Aug 07 07:16:26 PM PDT 24
Peak memory 248716 kb
Host smart-e636ee7e-a130-44b4-a390-a8975e92b8ca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=939603986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.939603986
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.337991907
Short name T192
Test name
Test status
Simulation time 29374419 ps
CPU time 2.64 seconds
Started Aug 07 07:16:56 PM PDT 24
Finished Aug 07 07:16:59 PM PDT 24
Peak memory 248732 kb
Host smart-28a0556d-5404-42b4-83be-b20daaf5e938
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=337991907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.337991907
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3827592425
Short name T21
Test name
Test status
Simulation time 299347461064 ps
CPU time 1647.9 seconds
Started Aug 07 07:16:46 PM PDT 24
Finished Aug 07 07:44:14 PM PDT 24
Peak memory 273156 kb
Host smart-f078fac5-fd94-435a-aa3e-7fcb5b090cc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827592425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3827592425
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3700119758
Short name T268
Test name
Test status
Simulation time 87617147015 ps
CPU time 6444.28 seconds
Started Aug 07 07:17:57 PM PDT 24
Finished Aug 07 09:05:22 PM PDT 24
Peak memory 322468 kb
Host smart-816b4e0e-4964-4d5e-9f3d-350cf9926108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700119758 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3700119758
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3904004010
Short name T275
Test name
Test status
Simulation time 66766767803 ps
CPU time 1527.12 seconds
Started Aug 07 07:18:02 PM PDT 24
Finished Aug 07 07:43:30 PM PDT 24
Peak memory 289232 kb
Host smart-ea3e0838-a967-431a-995c-a9077bd2c4ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904004010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3904004010
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3411529027
Short name T338
Test name
Test status
Simulation time 39223256151 ps
CPU time 2245.94 seconds
Started Aug 07 07:15:07 PM PDT 24
Finished Aug 07 07:52:33 PM PDT 24
Peak memory 288684 kb
Host smart-f3882930-0ef1-4358-a18e-0995f3951a7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411529027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3411529027
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2853854006
Short name T51
Test name
Test status
Simulation time 40313321334 ps
CPU time 2410.04 seconds
Started Aug 07 07:18:42 PM PDT 24
Finished Aug 07 07:58:53 PM PDT 24
Peak memory 289632 kb
Host smart-b9329c35-e3d2-4a2f-9f68-38c1e4a4b314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853854006 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2853854006
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3659386194
Short name T303
Test name
Test status
Simulation time 53442107450 ps
CPU time 376.36 seconds
Started Aug 07 07:21:16 PM PDT 24
Finished Aug 07 07:27:33 PM PDT 24
Peak memory 248584 kb
Host smart-42b28f17-10dc-4d27-8c6e-eb9f366423b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659386194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3659386194
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2685992563
Short name T238
Test name
Test status
Simulation time 176161654551 ps
CPU time 2470.33 seconds
Started Aug 07 07:15:20 PM PDT 24
Finished Aug 07 07:56:31 PM PDT 24
Peak memory 289588 kb
Host smart-7c2d1a5e-8f52-4231-8ad7-1de2625fe4cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685992563 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2685992563
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2178636737
Short name T153
Test name
Test status
Simulation time 92499947 ps
CPU time 5.16 seconds
Started Aug 07 06:16:24 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 238120 kb
Host smart-11b2a3b7-e665-4fc4-8149-e2d6481b9a2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2178636737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2178636737
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1504761795
Short name T259
Test name
Test status
Simulation time 152014196528 ps
CPU time 2732.84 seconds
Started Aug 07 07:19:44 PM PDT 24
Finished Aug 07 08:05:17 PM PDT 24
Peak memory 289608 kb
Host smart-0555ab26-1d76-4bec-8928-13e05ae63f69
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504761795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1504761795
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3714476152
Short name T120
Test name
Test status
Simulation time 3417705166 ps
CPU time 103.01 seconds
Started Aug 07 06:16:27 PM PDT 24
Finished Aug 07 06:18:10 PM PDT 24
Peak memory 265588 kb
Host smart-ced2cc9f-3a51-4cc9-b741-b525198e49dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3714476152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3714476152
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.965468960
Short name T163
Test name
Test status
Simulation time 6532638396 ps
CPU time 82.91 seconds
Started Aug 07 06:16:30 PM PDT 24
Finished Aug 07 06:17:53 PM PDT 24
Peak memory 240652 kb
Host smart-789134de-1afb-4b89-a0cd-5de3f57054cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=965468960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.965468960
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1047498032
Short name T143
Test name
Test status
Simulation time 23776794816 ps
CPU time 139.32 seconds
Started Aug 07 06:16:30 PM PDT 24
Finished Aug 07 06:18:49 PM PDT 24
Peak memory 265584 kb
Host smart-01fe03f7-2647-44ec-b79f-f6adce442d6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1047498032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1047498032
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2750167774
Short name T154
Test name
Test status
Simulation time 11579137 ps
CPU time 1.41 seconds
Started Aug 07 06:16:46 PM PDT 24
Finished Aug 07 06:16:48 PM PDT 24
Peak memory 237700 kb
Host smart-381aedf2-06df-4edf-bd8d-6fd728e7d778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2750167774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2750167774
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2015801357
Short name T49
Test name
Test status
Simulation time 155196541295 ps
CPU time 891.54 seconds
Started Aug 07 07:14:54 PM PDT 24
Finished Aug 07 07:29:46 PM PDT 24
Peak memory 273168 kb
Host smart-228e95c8-d988-4e52-baee-45d3fcd77b3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015801357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2015801357
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2042375662
Short name T279
Test name
Test status
Simulation time 49430640961 ps
CPU time 5025.53 seconds
Started Aug 07 07:16:13 PM PDT 24
Finished Aug 07 08:39:59 PM PDT 24
Peak memory 354564 kb
Host smart-fe1bee32-5608-44bf-92c0-11e9b40acba6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042375662 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2042375662
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3796139713
Short name T416
Test name
Test status
Simulation time 962238162 ps
CPU time 16.74 seconds
Started Aug 07 07:15:09 PM PDT 24
Finished Aug 07 07:15:26 PM PDT 24
Peak memory 247824 kb
Host smart-fe3f3f10-aac0-4629-9ae4-b3cf0b8d3a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37961
39713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3796139713
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1805487812
Short name T235
Test name
Test status
Simulation time 415139484656 ps
CPU time 2216.65 seconds
Started Aug 07 07:16:53 PM PDT 24
Finished Aug 07 07:53:50 PM PDT 24
Peak memory 289464 kb
Host smart-31c193bf-05f2-4398-b7b1-2a6eb77b5d4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805487812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1805487812
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2771088703
Short name T54
Test name
Test status
Simulation time 71656915453 ps
CPU time 4057.94 seconds
Started Aug 07 07:17:05 PM PDT 24
Finished Aug 07 08:24:43 PM PDT 24
Peak memory 305368 kb
Host smart-100b3757-61ec-45cc-bbc6-839fc0d8c318
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771088703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2771088703
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.180103221
Short name T285
Test name
Test status
Simulation time 585986441 ps
CPU time 20.93 seconds
Started Aug 07 07:17:03 PM PDT 24
Finished Aug 07 07:17:24 PM PDT 24
Peak memory 248424 kb
Host smart-2f3f1ed7-1a95-433d-b856-c087cdf1112e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18010
3221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.180103221
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1744977263
Short name T272
Test name
Test status
Simulation time 699315298 ps
CPU time 42.72 seconds
Started Aug 07 07:17:14 PM PDT 24
Finished Aug 07 07:17:57 PM PDT 24
Peak memory 256008 kb
Host smart-e460b5f8-c7bb-482a-ad5d-5d510fc469b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17449
77263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1744977263
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3445213225
Short name T280
Test name
Test status
Simulation time 25668264008 ps
CPU time 1834.55 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 07:48:38 PM PDT 24
Peak memory 281540 kb
Host smart-265fa175-4af4-4f98-8965-f8965dde4cb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445213225 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3445213225
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2416714722
Short name T256
Test name
Test status
Simulation time 36122366914 ps
CPU time 820.38 seconds
Started Aug 07 07:18:37 PM PDT 24
Finished Aug 07 07:32:17 PM PDT 24
Peak memory 273076 kb
Host smart-b8e2fa23-f5c4-4c66-ac77-a301df84ee27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416714722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2416714722
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2768483728
Short name T96
Test name
Test status
Simulation time 105909184468 ps
CPU time 3220.4 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 08:08:46 PM PDT 24
Peak memory 289544 kb
Host smart-9ac1d310-f071-4da3-951d-2b1024e72135
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768483728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2768483728
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.908351244
Short name T184
Test name
Test status
Simulation time 49895593411 ps
CPU time 3302.6 seconds
Started Aug 07 07:19:24 PM PDT 24
Finished Aug 07 08:14:27 PM PDT 24
Peak memory 289052 kb
Host smart-b5eab963-0a8f-408a-bb3d-7fb0dee57b05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908351244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.908351244
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3314478528
Short name T278
Test name
Test status
Simulation time 2558470173 ps
CPU time 38.08 seconds
Started Aug 07 07:22:30 PM PDT 24
Finished Aug 07 07:23:08 PM PDT 24
Peak memory 255892 kb
Host smart-10580143-df54-46ff-9db7-9bcf163ecede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33144
78528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3314478528
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.616796629
Short name T258
Test name
Test status
Simulation time 19230140563 ps
CPU time 840.68 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 07:29:27 PM PDT 24
Peak memory 272692 kb
Host smart-02cb84cb-c755-4731-bb12-2f3053a98671
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616796629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.616796629
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.871738318
Short name T76
Test name
Test status
Simulation time 22338611447 ps
CPU time 1517.43 seconds
Started Aug 07 07:15:28 PM PDT 24
Finished Aug 07 07:40:46 PM PDT 24
Peak memory 284244 kb
Host smart-e1fbf8a8-767a-4b22-bc33-8aa79f03aab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871738318 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.871738318
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3295758902
Short name T160
Test name
Test status
Simulation time 607227595 ps
CPU time 47.77 seconds
Started Aug 07 06:16:21 PM PDT 24
Finished Aug 07 06:17:09 PM PDT 24
Peak memory 237836 kb
Host smart-c90aaff1-e08d-4d85-a22c-8dd86311a884
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3295758902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3295758902
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2439979290
Short name T137
Test name
Test status
Simulation time 5235407606 ps
CPU time 88.56 seconds
Started Aug 07 06:16:41 PM PDT 24
Finished Aug 07 06:18:10 PM PDT 24
Peak memory 265984 kb
Host smart-8edac39f-4a6e-4209-9ff5-6910d6f9d85f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2439979290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2439979290
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1214319183
Short name T146
Test name
Test status
Simulation time 2249587304 ps
CPU time 158.07 seconds
Started Aug 07 06:16:16 PM PDT 24
Finished Aug 07 06:18:54 PM PDT 24
Peak memory 265600 kb
Host smart-fcede7a3-c683-4d7b-b7b8-c061d2f8f410
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1214319183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1214319183
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1845758732
Short name T128
Test name
Test status
Simulation time 4372389486 ps
CPU time 292.3 seconds
Started Aug 07 06:16:38 PM PDT 24
Finished Aug 07 06:21:30 PM PDT 24
Peak memory 265668 kb
Host smart-abafe87a-38d3-4968-ac76-a8d8b5360b0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1845758732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1845758732
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.666753248
Short name T162
Test name
Test status
Simulation time 1771665447 ps
CPU time 70.88 seconds
Started Aug 07 06:16:43 PM PDT 24
Finished Aug 07 06:17:54 PM PDT 24
Peak memory 237836 kb
Host smart-8ed8e015-8d07-400d-8582-1f014e105ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=666753248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.666753248
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.248793931
Short name T165
Test name
Test status
Simulation time 188546509 ps
CPU time 23.14 seconds
Started Aug 07 06:16:20 PM PDT 24
Finished Aug 07 06:16:43 PM PDT 24
Peak memory 237756 kb
Host smart-4c2ab6ef-9959-40b6-a015-3c30c3c1cd5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=248793931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.248793931
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2918950671
Short name T121
Test name
Test status
Simulation time 23252621397 ps
CPU time 635.59 seconds
Started Aug 07 06:16:32 PM PDT 24
Finished Aug 07 06:27:07 PM PDT 24
Peak memory 265632 kb
Host smart-aae47d62-d0e6-4042-8eab-158def642f30
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918950671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2918950671
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.860172420
Short name T159
Test name
Test status
Simulation time 495488163 ps
CPU time 39.65 seconds
Started Aug 07 06:16:41 PM PDT 24
Finished Aug 07 06:17:20 PM PDT 24
Peak memory 240632 kb
Host smart-475eba64-800d-4cc0-aac4-894d952c5a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=860172420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.860172420
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3071397318
Short name T152
Test name
Test status
Simulation time 103185662 ps
CPU time 2.89 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 237716 kb
Host smart-5c71ff88-d3bd-4fe4-a065-c200d2fed14d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3071397318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3071397318
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3546700528
Short name T157
Test name
Test status
Simulation time 520598431 ps
CPU time 20.98 seconds
Started Aug 07 06:16:16 PM PDT 24
Finished Aug 07 06:16:37 PM PDT 24
Peak memory 240568 kb
Host smart-9ab06b74-8055-48eb-a09f-28b943873933
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3546700528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3546700528
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3709363569
Short name T170
Test name
Test status
Simulation time 33442495 ps
CPU time 2.18 seconds
Started Aug 07 06:16:40 PM PDT 24
Finished Aug 07 06:16:43 PM PDT 24
Peak memory 237704 kb
Host smart-8a0f5c99-ad30-4bfd-b69b-5719bdc3590d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3709363569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3709363569
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.17344557
Short name T164
Test name
Test status
Simulation time 629044408 ps
CPU time 23.16 seconds
Started Aug 07 06:16:37 PM PDT 24
Finished Aug 07 06:17:01 PM PDT 24
Peak memory 246136 kb
Host smart-5fdaee02-57f7-4487-a7ec-317f160d4fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=17344557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.17344557
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3222082753
Short name T171
Test name
Test status
Simulation time 173586074 ps
CPU time 3.74 seconds
Started Aug 07 06:16:40 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 238000 kb
Host smart-ae99506b-b5e2-4547-8577-725e96c722e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3222082753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3222082753
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3034642298
Short name T158
Test name
Test status
Simulation time 55512340 ps
CPU time 3.61 seconds
Started Aug 07 06:16:41 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 237704 kb
Host smart-be74c866-c41a-4627-86bf-138a3b91b672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3034642298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3034642298
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.4087616752
Short name T161
Test name
Test status
Simulation time 109061389 ps
CPU time 2.63 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:16:45 PM PDT 24
Peak memory 237720 kb
Host smart-0bf872fd-9916-4651-ba24-c93201d1c9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4087616752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.4087616752
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2002191772
Short name T166
Test name
Test status
Simulation time 593785466 ps
CPU time 38.88 seconds
Started Aug 07 06:16:20 PM PDT 24
Finished Aug 07 06:16:59 PM PDT 24
Peak memory 240556 kb
Host smart-1590bf24-1cb2-4b7b-9f24-b237cf552f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2002191772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2002191772
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1251057497
Short name T27
Test name
Test status
Simulation time 945798460 ps
CPU time 54.86 seconds
Started Aug 07 07:21:05 PM PDT 24
Finished Aug 07 07:22:00 PM PDT 24
Peak memory 256616 kb
Host smart-1ea1d878-7fd7-45cf-9878-5122362c4b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12510
57497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1251057497
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3444262704
Short name T736
Test name
Test status
Simulation time 2151455540 ps
CPU time 145.71 seconds
Started Aug 07 06:16:17 PM PDT 24
Finished Aug 07 06:18:43 PM PDT 24
Peak memory 237736 kb
Host smart-1c2d5be3-4c79-4d2b-9c88-c652d508e958
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3444262704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3444262704
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1857465122
Short name T831
Test name
Test status
Simulation time 46516952338 ps
CPU time 235.26 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:20:15 PM PDT 24
Peak memory 236796 kb
Host smart-cb90a992-d4ab-4afe-89f2-91883b4030b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1857465122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1857465122
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2436926448
Short name T716
Test name
Test status
Simulation time 208995284 ps
CPU time 5.02 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:24 PM PDT 24
Peak memory 248812 kb
Host smart-4deda4aa-9213-44ed-9f3f-50ae2f4e68f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2436926448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2436926448
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4293903075
Short name T797
Test name
Test status
Simulation time 54972286 ps
CPU time 4.82 seconds
Started Aug 07 06:16:18 PM PDT 24
Finished Aug 07 06:16:23 PM PDT 24
Peak memory 251484 kb
Host smart-ea908462-1060-4733-91d0-db2f816a4147
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293903075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.4293903075
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.853964227
Short name T776
Test name
Test status
Simulation time 258724873 ps
CPU time 5.34 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:24 PM PDT 24
Peak memory 237668 kb
Host smart-7272c4eb-8f50-4def-9b64-1a7945db8a1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=853964227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.853964227
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1339751616
Short name T801
Test name
Test status
Simulation time 24165848 ps
CPU time 2.08 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:21 PM PDT 24
Peak memory 236704 kb
Host smart-e8d94a36-985d-450f-8d60-bf5f869185bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1339751616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1339751616
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2581432944
Short name T827
Test name
Test status
Simulation time 531319236 ps
CPU time 20.03 seconds
Started Aug 07 06:16:16 PM PDT 24
Finished Aug 07 06:16:36 PM PDT 24
Peak memory 245892 kb
Host smart-bc2ef5dc-1630-4c14-8fc4-cdb1254087be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2581432944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2581432944
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3244482764
Short name T118
Test name
Test status
Simulation time 2289776779 ps
CPU time 211.06 seconds
Started Aug 07 06:16:10 PM PDT 24
Finished Aug 07 06:19:41 PM PDT 24
Peak memory 265688 kb
Host smart-5eda27d8-d02d-4bb6-be76-a55a5fa43302
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3244482764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3244482764
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1832509869
Short name T127
Test name
Test status
Simulation time 5117123774 ps
CPU time 293.15 seconds
Started Aug 07 06:16:14 PM PDT 24
Finished Aug 07 06:21:07 PM PDT 24
Peak memory 265648 kb
Host smart-a20db090-8db2-4e28-9387-ee77cf2f4b0c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832509869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1832509869
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1805224030
Short name T712
Test name
Test status
Simulation time 68435360 ps
CPU time 10.36 seconds
Started Aug 07 06:16:22 PM PDT 24
Finished Aug 07 06:16:32 PM PDT 24
Peak memory 248896 kb
Host smart-c833de4d-eb49-4f20-a20f-998c27386275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1805224030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1805224030
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1073492304
Short name T822
Test name
Test status
Simulation time 191523972 ps
CPU time 26.19 seconds
Started Aug 07 06:16:18 PM PDT 24
Finished Aug 07 06:16:45 PM PDT 24
Peak memory 240620 kb
Host smart-aec68315-3a43-464e-b7e2-a9410a30e8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1073492304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1073492304
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1336853945
Short name T826
Test name
Test status
Simulation time 4298219285 ps
CPU time 289.11 seconds
Started Aug 07 06:16:20 PM PDT 24
Finished Aug 07 06:21:09 PM PDT 24
Peak memory 240668 kb
Host smart-8e95c755-41ca-4fdb-bb58-6058d0d5b8ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1336853945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1336853945
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1994381025
Short name T787
Test name
Test status
Simulation time 19048821524 ps
CPU time 371.1 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:22:31 PM PDT 24
Peak memory 237808 kb
Host smart-177a7408-b2ae-43a7-acd0-279937e489d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1994381025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1994381025
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.219932630
Short name T829
Test name
Test status
Simulation time 64413871 ps
CPU time 5.48 seconds
Started Aug 07 06:16:20 PM PDT 24
Finished Aug 07 06:16:26 PM PDT 24
Peak memory 248820 kb
Host smart-65cba8f0-f7c5-41ef-898e-7f205c0b3175
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=219932630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.219932630
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2891534690
Short name T763
Test name
Test status
Simulation time 189766560 ps
CPU time 8.73 seconds
Started Aug 07 06:16:17 PM PDT 24
Finished Aug 07 06:16:26 PM PDT 24
Peak memory 250060 kb
Host smart-28cddfbc-e7c6-4d75-a220-625f0db980a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891534690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2891534690
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.130471375
Short name T779
Test name
Test status
Simulation time 54201541 ps
CPU time 4.79 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:24 PM PDT 24
Peak memory 237692 kb
Host smart-8d932344-a101-41c1-abff-f55c35da2d1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=130471375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.130471375
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.878639742
Short name T775
Test name
Test status
Simulation time 8333141 ps
CPU time 1.54 seconds
Started Aug 07 06:16:18 PM PDT 24
Finished Aug 07 06:16:20 PM PDT 24
Peak memory 235684 kb
Host smart-5f3894d9-40b6-45bf-85e1-5b1fa5f82aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=878639742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.878639742
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1830975391
Short name T800
Test name
Test status
Simulation time 356115742 ps
CPU time 12.23 seconds
Started Aug 07 06:16:16 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 240644 kb
Host smart-ee81c894-cc42-4487-a6c6-eb578f5f5446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1830975391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1830975391
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1811461880
Short name T139
Test name
Test status
Simulation time 32437832072 ps
CPU time 500.18 seconds
Started Aug 07 06:16:17 PM PDT 24
Finished Aug 07 06:24:38 PM PDT 24
Peak memory 265564 kb
Host smart-c14b0037-9c12-4754-ba0c-aca2614d351d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811461880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1811461880
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.605559734
Short name T798
Test name
Test status
Simulation time 244944355 ps
CPU time 17.12 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:36 PM PDT 24
Peak memory 248584 kb
Host smart-b43d559d-663f-46ee-94cc-4204b7555c63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=605559734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.605559734
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3025017965
Short name T756
Test name
Test status
Simulation time 137520053 ps
CPU time 11 seconds
Started Aug 07 06:16:33 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 240704 kb
Host smart-12b7f267-a9fa-4521-a634-594ed3f626af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025017965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3025017965
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1005109981
Short name T179
Test name
Test status
Simulation time 562429610 ps
CPU time 6.35 seconds
Started Aug 07 06:16:32 PM PDT 24
Finished Aug 07 06:16:38 PM PDT 24
Peak memory 237552 kb
Host smart-35603beb-670a-4698-a5f4-4d3809b7b414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1005109981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1005109981
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1718851411
Short name T741
Test name
Test status
Simulation time 7278554 ps
CPU time 1.45 seconds
Started Aug 07 06:16:34 PM PDT 24
Finished Aug 07 06:16:35 PM PDT 24
Peak memory 235740 kb
Host smart-b993eba4-dc4a-4ef1-9524-c00204d5d1c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1718851411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1718851411
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1340724280
Short name T730
Test name
Test status
Simulation time 89673821 ps
CPU time 11.98 seconds
Started Aug 07 06:16:30 PM PDT 24
Finished Aug 07 06:16:43 PM PDT 24
Peak memory 245900 kb
Host smart-f9e28b45-ba0a-4382-a2a7-6961d760b4ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1340724280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1340724280
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1518042940
Short name T135
Test name
Test status
Simulation time 8374474922 ps
CPU time 592.37 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:26:17 PM PDT 24
Peak memory 269080 kb
Host smart-04780e1c-a3fc-415b-b3e4-c8596779d58f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518042940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1518042940
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3525582760
Short name T233
Test name
Test status
Simulation time 884470094 ps
CPU time 14.2 seconds
Started Aug 07 06:16:37 PM PDT 24
Finished Aug 07 06:16:51 PM PDT 24
Peak memory 256924 kb
Host smart-e102b13e-f3b3-45f4-a2b5-5557d1de580e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3525582760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3525582760
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2040483076
Short name T349
Test name
Test status
Simulation time 156119235 ps
CPU time 11.44 seconds
Started Aug 07 06:16:28 PM PDT 24
Finished Aug 07 06:16:39 PM PDT 24
Peak memory 252288 kb
Host smart-e386866d-fc55-4070-856a-a1666c868d4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040483076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2040483076
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1254201366
Short name T726
Test name
Test status
Simulation time 57834409 ps
CPU time 3.69 seconds
Started Aug 07 06:16:40 PM PDT 24
Finished Aug 07 06:16:43 PM PDT 24
Peak memory 237688 kb
Host smart-f6eade1f-80ea-4abf-981d-72ad9749a419
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1254201366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1254201366
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3053663097
Short name T760
Test name
Test status
Simulation time 11479137 ps
CPU time 1.36 seconds
Started Aug 07 06:16:33 PM PDT 24
Finished Aug 07 06:16:35 PM PDT 24
Peak memory 237712 kb
Host smart-08cbe016-6e16-4195-b4a1-f90a33bedcb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3053663097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3053663097
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2056022139
Short name T178
Test name
Test status
Simulation time 455104427 ps
CPU time 12.6 seconds
Started Aug 07 06:16:31 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 248828 kb
Host smart-b134bc15-088f-4689-ab06-9c5f8475a50c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2056022139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2056022139
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.688155419
Short name T794
Test name
Test status
Simulation time 132247047 ps
CPU time 4.61 seconds
Started Aug 07 06:16:34 PM PDT 24
Finished Aug 07 06:16:39 PM PDT 24
Peak memory 248428 kb
Host smart-92ab7e0f-5189-499f-a2ba-d55d82361490
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=688155419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.688155419
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3285860578
Short name T765
Test name
Test status
Simulation time 306280880 ps
CPU time 25.02 seconds
Started Aug 07 06:16:38 PM PDT 24
Finished Aug 07 06:17:03 PM PDT 24
Peak memory 240632 kb
Host smart-39925698-c93a-4597-bf98-3906542b4b56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3285860578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3285860578
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.706210283
Short name T774
Test name
Test status
Simulation time 74139990 ps
CPU time 5.93 seconds
Started Aug 07 06:16:32 PM PDT 24
Finished Aug 07 06:16:38 PM PDT 24
Peak memory 238772 kb
Host smart-a94eb727-bd63-4ffa-9337-236173ad49ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706210283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.706210283
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1879150375
Short name T802
Test name
Test status
Simulation time 180103762 ps
CPU time 5.25 seconds
Started Aug 07 06:16:41 PM PDT 24
Finished Aug 07 06:16:47 PM PDT 24
Peak memory 237904 kb
Host smart-6718aeff-1264-4fde-bb6b-270f0c758a55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1879150375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1879150375
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2352280221
Short name T747
Test name
Test status
Simulation time 6586687 ps
CPU time 1.52 seconds
Started Aug 07 06:16:29 PM PDT 24
Finished Aug 07 06:16:30 PM PDT 24
Peak memory 237684 kb
Host smart-2a0eb3bf-b071-4cca-8b2d-67674cc7d864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352280221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2352280221
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3490604032
Short name T743
Test name
Test status
Simulation time 178813547 ps
CPU time 14.27 seconds
Started Aug 07 06:16:32 PM PDT 24
Finished Aug 07 06:16:46 PM PDT 24
Peak memory 248836 kb
Host smart-d1269b36-3042-4c6f-899a-2b5516ebfcca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3490604032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3490604032
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2500877368
Short name T150
Test name
Test status
Simulation time 3207226823 ps
CPU time 147.42 seconds
Started Aug 07 06:16:39 PM PDT 24
Finished Aug 07 06:19:06 PM PDT 24
Peak memory 265608 kb
Host smart-440616d6-01cb-48f9-a939-b9e5e8335eb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2500877368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2500877368
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.174363714
Short name T733
Test name
Test status
Simulation time 357855266 ps
CPU time 6.12 seconds
Started Aug 07 06:16:32 PM PDT 24
Finished Aug 07 06:16:38 PM PDT 24
Peak memory 248596 kb
Host smart-1b813653-8523-443d-91db-b097fcd30728
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=174363714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.174363714
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.840214114
Short name T820
Test name
Test status
Simulation time 64460914 ps
CPU time 9.6 seconds
Started Aug 07 06:16:34 PM PDT 24
Finished Aug 07 06:16:43 PM PDT 24
Peak memory 256220 kb
Host smart-a33c138c-d743-4e21-a531-f63272f85b92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840214114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.840214114
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3603103516
Short name T351
Test name
Test status
Simulation time 275556368 ps
CPU time 4.52 seconds
Started Aug 07 06:16:35 PM PDT 24
Finished Aug 07 06:16:39 PM PDT 24
Peak memory 236780 kb
Host smart-bf281ec7-1d17-4449-beef-79cc94d9dea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3603103516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3603103516
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.102285006
Short name T742
Test name
Test status
Simulation time 6478369 ps
CPU time 1.44 seconds
Started Aug 07 06:16:38 PM PDT 24
Finished Aug 07 06:16:40 PM PDT 24
Peak memory 235720 kb
Host smart-89a34f19-37c8-4d48-a809-9aaf2a422ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=102285006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.102285006
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2913121815
Short name T739
Test name
Test status
Simulation time 1509989052 ps
CPU time 49.64 seconds
Started Aug 07 06:16:30 PM PDT 24
Finished Aug 07 06:17:20 PM PDT 24
Peak memory 245844 kb
Host smart-2af8114f-e61c-478a-acff-339604180d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2913121815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2913121815
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2626546807
Short name T131
Test name
Test status
Simulation time 1996747317 ps
CPU time 138.39 seconds
Started Aug 07 06:16:38 PM PDT 24
Finished Aug 07 06:18:56 PM PDT 24
Peak memory 265392 kb
Host smart-a8490510-b035-40e4-821f-4fb6bd1fd768
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2626546807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2626546807
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2062351492
Short name T123
Test name
Test status
Simulation time 17878056515 ps
CPU time 635 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:27:17 PM PDT 24
Peak memory 265652 kb
Host smart-58cbc5f7-f60a-4b7a-accb-badff408fad9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062351492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2062351492
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1561142062
Short name T804
Test name
Test status
Simulation time 350127140 ps
CPU time 9.24 seconds
Started Aug 07 06:16:30 PM PDT 24
Finished Aug 07 06:16:40 PM PDT 24
Peak memory 248136 kb
Host smart-f5456bb0-b05d-47bf-acb5-0bde5de67b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1561142062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1561142062
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3647613792
Short name T347
Test name
Test status
Simulation time 248415893 ps
CPU time 11.48 seconds
Started Aug 07 06:16:41 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 254216 kb
Host smart-974ff201-6a69-4256-ae81-9ca23f530cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647613792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3647613792
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3030384869
Short name T773
Test name
Test status
Simulation time 96171853 ps
CPU time 7.1 seconds
Started Aug 07 06:16:37 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 236820 kb
Host smart-60f99706-450e-4cb6-a933-28ae8ef3bbc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3030384869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3030384869
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3143206578
Short name T728
Test name
Test status
Simulation time 9483125 ps
CPU time 1.4 seconds
Started Aug 07 06:16:39 PM PDT 24
Finished Aug 07 06:16:40 PM PDT 24
Peak memory 236836 kb
Host smart-3e9827d1-ed49-48d8-97c7-e6753780cb45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3143206578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3143206578
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2153667386
Short name T799
Test name
Test status
Simulation time 687550963 ps
CPU time 48.86 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:17:31 PM PDT 24
Peak memory 248864 kb
Host smart-89db129f-0275-405f-a590-10db5c52f419
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2153667386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2153667386
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3252206533
Short name T125
Test name
Test status
Simulation time 1480227738 ps
CPU time 164.67 seconds
Started Aug 07 06:16:44 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 272976 kb
Host smart-cd303123-e536-4c89-bb20-6b04572afa22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3252206533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3252206533
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.112561702
Short name T717
Test name
Test status
Simulation time 293128355 ps
CPU time 12.95 seconds
Started Aug 07 06:16:41 PM PDT 24
Finished Aug 07 06:16:54 PM PDT 24
Peak memory 254088 kb
Host smart-8776e961-9a2d-4160-93f3-15b115aa5472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=112561702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.112561702
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.403842444
Short name T790
Test name
Test status
Simulation time 378220507 ps
CPU time 8.01 seconds
Started Aug 07 06:16:36 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 240708 kb
Host smart-6f37d9e3-682c-48f9-bd1a-6e22e6cea6e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403842444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.403842444
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.467633288
Short name T177
Test name
Test status
Simulation time 22577262 ps
CPU time 3.52 seconds
Started Aug 07 06:16:37 PM PDT 24
Finished Aug 07 06:16:41 PM PDT 24
Peak memory 236784 kb
Host smart-8e6e3e17-5f1e-409c-b21b-0910f155a833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=467633288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.467633288
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3647837733
Short name T817
Test name
Test status
Simulation time 8332038 ps
CPU time 1.58 seconds
Started Aug 07 06:16:38 PM PDT 24
Finished Aug 07 06:16:39 PM PDT 24
Peak memory 237556 kb
Host smart-5836cda4-5ad2-444d-be09-ac086e9579f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3647837733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3647837733
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1884418584
Short name T744
Test name
Test status
Simulation time 86068223 ps
CPU time 13.82 seconds
Started Aug 07 06:16:38 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 240508 kb
Host smart-0594f5e3-6a60-462b-9c65-a7df83892768
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1884418584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1884418584
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.509826661
Short name T149
Test name
Test status
Simulation time 24267030798 ps
CPU time 420.29 seconds
Started Aug 07 06:16:38 PM PDT 24
Finished Aug 07 06:23:39 PM PDT 24
Peak memory 265616 kb
Host smart-54956f09-b329-4775-aa34-a8662dde497e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509826661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.509826661
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.4048009890
Short name T764
Test name
Test status
Simulation time 1614601755 ps
CPU time 14.39 seconds
Started Aug 07 06:16:44 PM PDT 24
Finished Aug 07 06:17:00 PM PDT 24
Peak memory 248708 kb
Host smart-7f9d65d4-3a33-43c5-919c-05ed1b3a35bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4048009890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.4048009890
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1642849478
Short name T792
Test name
Test status
Simulation time 57704854 ps
CPU time 8.69 seconds
Started Aug 07 06:16:43 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 252428 kb
Host smart-c7ea6f24-3340-4eb8-abc9-d61d312d54bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642849478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1642849478
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2051444005
Short name T796
Test name
Test status
Simulation time 232519339 ps
CPU time 4.93 seconds
Started Aug 07 06:16:43 PM PDT 24
Finished Aug 07 06:16:48 PM PDT 24
Peak memory 239600 kb
Host smart-56d49753-cb16-4c84-a630-ddf27c98fee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2051444005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2051444005
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2872294698
Short name T725
Test name
Test status
Simulation time 1770318529 ps
CPU time 22.18 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:17:05 PM PDT 24
Peak memory 245856 kb
Host smart-c2f65942-9ae7-4bb1-b0d7-9eacab81a903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2872294698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2872294698
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3096250132
Short name T145
Test name
Test status
Simulation time 43711071009 ps
CPU time 473.2 seconds
Started Aug 07 06:16:41 PM PDT 24
Finished Aug 07 06:24:34 PM PDT 24
Peak memory 265616 kb
Host smart-9a062f56-478b-471e-ad66-52ed9909e1a4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096250132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3096250132
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1122684167
Short name T762
Test name
Test status
Simulation time 1513210152 ps
CPU time 22.98 seconds
Started Aug 07 06:16:41 PM PDT 24
Finished Aug 07 06:17:04 PM PDT 24
Peak memory 248968 kb
Host smart-84abc8c5-948e-4f1f-9b38-f263f65fe455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1122684167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1122684167
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3504844232
Short name T737
Test name
Test status
Simulation time 166722025 ps
CPU time 11.95 seconds
Started Aug 07 06:16:43 PM PDT 24
Finished Aug 07 06:16:55 PM PDT 24
Peak memory 243084 kb
Host smart-db9a45e9-01ec-43c6-880a-0a6db201f572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504844232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3504844232
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3034374311
Short name T789
Test name
Test status
Simulation time 108053789 ps
CPU time 4.77 seconds
Started Aug 07 06:16:44 PM PDT 24
Finished Aug 07 06:16:49 PM PDT 24
Peak memory 240656 kb
Host smart-5287db67-6c53-424f-8a47-52c64e64a255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3034374311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3034374311
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3514066796
Short name T749
Test name
Test status
Simulation time 9853936 ps
CPU time 1.61 seconds
Started Aug 07 06:16:45 PM PDT 24
Finished Aug 07 06:16:47 PM PDT 24
Peak memory 236820 kb
Host smart-b8163777-bb67-4144-878d-de9e257a0194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3514066796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3514066796
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3457424093
Short name T813
Test name
Test status
Simulation time 332753453 ps
CPU time 12.69 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:16:55 PM PDT 24
Peak memory 245912 kb
Host smart-e94be8d2-f01a-4962-bbb2-de4f0a07ae7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3457424093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3457424093
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1808528691
Short name T140
Test name
Test status
Simulation time 1017558877 ps
CPU time 109.62 seconds
Started Aug 07 06:16:44 PM PDT 24
Finished Aug 07 06:18:33 PM PDT 24
Peak memory 264540 kb
Host smart-fbb88b2e-16b1-4ebf-a5b8-022d6346b752
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1808528691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1808528691
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3020762338
Short name T142
Test name
Test status
Simulation time 8629697405 ps
CPU time 642.32 seconds
Started Aug 07 06:16:45 PM PDT 24
Finished Aug 07 06:27:28 PM PDT 24
Peak memory 265644 kb
Host smart-89dce7af-7bba-44f6-bb37-5b5bfff04e2e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020762338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3020762338
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3125133796
Short name T753
Test name
Test status
Simulation time 3523327797 ps
CPU time 21.84 seconds
Started Aug 07 06:16:45 PM PDT 24
Finished Aug 07 06:17:07 PM PDT 24
Peak memory 248904 kb
Host smart-9021437b-77f2-4a41-a521-69b50996dadd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3125133796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3125133796
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3169044520
Short name T724
Test name
Test status
Simulation time 68726626 ps
CPU time 9.43 seconds
Started Aug 07 06:16:43 PM PDT 24
Finished Aug 07 06:16:53 PM PDT 24
Peak memory 256780 kb
Host smart-9308b030-ba91-4495-9f9d-886ee25f668d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169044520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3169044520
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.4261692393
Short name T769
Test name
Test status
Simulation time 656411215 ps
CPU time 8.24 seconds
Started Aug 07 06:16:43 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 236708 kb
Host smart-a21b25d4-db13-4f06-be27-c0b0cb5ef5a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4261692393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.4261692393
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4164649445
Short name T156
Test name
Test status
Simulation time 16156231 ps
CPU time 1.58 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 237708 kb
Host smart-37594b2b-9730-46d6-9a5a-eb28ff10ba84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4164649445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.4164649445
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3293393194
Short name T825
Test name
Test status
Simulation time 512442246 ps
CPU time 39.17 seconds
Started Aug 07 06:16:44 PM PDT 24
Finished Aug 07 06:17:24 PM PDT 24
Peak memory 248824 kb
Host smart-8f4da186-3a7b-4441-9663-92a0c0f39a92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3293393194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3293393194
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3778771328
Short name T711
Test name
Test status
Simulation time 1592838117 ps
CPU time 13.84 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:16:56 PM PDT 24
Peak memory 248800 kb
Host smart-0ed1b74c-8978-490f-9e49-9ca336be100b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3778771328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3778771328
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2307907463
Short name T261
Test name
Test status
Simulation time 1677768941 ps
CPU time 45.29 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:17:27 PM PDT 24
Peak memory 240656 kb
Host smart-84ce27d2-3690-4b3d-a7a3-12a57089a3f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2307907463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2307907463
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1888322963
Short name T732
Test name
Test status
Simulation time 849071656 ps
CPU time 11.8 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:16:54 PM PDT 24
Peak memory 251980 kb
Host smart-b7a917a4-556a-448e-b962-e0dbf646da1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888322963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1888322963
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2056697157
Short name T232
Test name
Test status
Simulation time 456515290 ps
CPU time 8.12 seconds
Started Aug 07 06:16:46 PM PDT 24
Finished Aug 07 06:16:54 PM PDT 24
Peak memory 236820 kb
Host smart-e0407807-2fa0-4132-800f-76dc1a176c0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2056697157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2056697157
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2997678991
Short name T766
Test name
Test status
Simulation time 69906927 ps
CPU time 1.38 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:16:43 PM PDT 24
Peak memory 237488 kb
Host smart-5d0ea19d-51f3-4678-902d-ffbb160b7dd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2997678991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2997678991
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1225579167
Short name T168
Test name
Test status
Simulation time 1573280295 ps
CPU time 36.63 seconds
Started Aug 07 06:16:45 PM PDT 24
Finished Aug 07 06:17:22 PM PDT 24
Peak memory 245924 kb
Host smart-8e106ef4-c304-4386-803c-dae474a22bba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1225579167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1225579167
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2340476278
Short name T147
Test name
Test status
Simulation time 5339959432 ps
CPU time 642.39 seconds
Started Aug 07 06:16:46 PM PDT 24
Finished Aug 07 06:27:28 PM PDT 24
Peak memory 273036 kb
Host smart-43e4448e-d23b-4df2-809f-32851af35cc1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340476278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2340476278
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2543443045
Short name T771
Test name
Test status
Simulation time 211111722 ps
CPU time 8.22 seconds
Started Aug 07 06:16:47 PM PDT 24
Finished Aug 07 06:16:55 PM PDT 24
Peak memory 248912 kb
Host smart-2aca073b-55fe-4392-96cc-49178425e70e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2543443045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2543443045
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3812784507
Short name T180
Test name
Test status
Simulation time 84249548677 ps
CPU time 276.65 seconds
Started Aug 07 06:16:16 PM PDT 24
Finished Aug 07 06:20:53 PM PDT 24
Peak memory 240756 kb
Host smart-46055780-2606-4e0b-a5b0-3376a0c3aacc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3812784507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3812784507
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3359409759
Short name T176
Test name
Test status
Simulation time 15481087775 ps
CPU time 445.6 seconds
Started Aug 07 06:16:17 PM PDT 24
Finished Aug 07 06:23:43 PM PDT 24
Peak memory 240764 kb
Host smart-453bdfbf-5a85-4100-b9fb-fadd3a49539d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3359409759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3359409759
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3796453468
Short name T226
Test name
Test status
Simulation time 127824762 ps
CPU time 9.82 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 248880 kb
Host smart-a187807c-7284-4267-be19-b99cd5ff0e74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3796453468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3796453468
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1253889891
Short name T806
Test name
Test status
Simulation time 44944799 ps
CPU time 5.54 seconds
Started Aug 07 06:16:30 PM PDT 24
Finished Aug 07 06:16:35 PM PDT 24
Peak memory 240712 kb
Host smart-3d1a18ce-ba8f-4c72-b6a1-cb32d761ff36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253889891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1253889891
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1019694122
Short name T778
Test name
Test status
Simulation time 1220613015 ps
CPU time 10.28 seconds
Started Aug 07 06:16:17 PM PDT 24
Finished Aug 07 06:16:27 PM PDT 24
Peak memory 237688 kb
Host smart-acb929e0-acbe-4824-b511-759a0b9fea5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1019694122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1019694122
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4251011848
Short name T344
Test name
Test status
Simulation time 10958859 ps
CPU time 1.67 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:21 PM PDT 24
Peak memory 237716 kb
Host smart-169cfc18-4282-47dd-b4a3-ca7cfe412038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4251011848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4251011848
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.283434996
Short name T746
Test name
Test status
Simulation time 1650906391 ps
CPU time 36.89 seconds
Started Aug 07 06:16:21 PM PDT 24
Finished Aug 07 06:16:58 PM PDT 24
Peak memory 245016 kb
Host smart-3d42d687-6c62-47b3-99f1-5227a3788842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=283434996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.283434996
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1267128455
Short name T119
Test name
Test status
Simulation time 6529199077 ps
CPU time 411.49 seconds
Started Aug 07 06:16:18 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 265528 kb
Host smart-49f6c9d7-b6f0-4ffc-8ccb-2c3e8e4639e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1267128455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1267128455
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2122616499
Short name T816
Test name
Test status
Simulation time 16773389025 ps
CPU time 609.77 seconds
Started Aug 07 06:16:21 PM PDT 24
Finished Aug 07 06:26:31 PM PDT 24
Peak memory 265836 kb
Host smart-567504f8-e491-464c-892f-cf671307ee82
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122616499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2122616499
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1663364717
Short name T713
Test name
Test status
Simulation time 266357641 ps
CPU time 9.83 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 248804 kb
Host smart-784d1588-4440-4ac6-8613-da3c561e028a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1663364717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1663364717
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1134374890
Short name T721
Test name
Test status
Simulation time 20590433 ps
CPU time 2.03 seconds
Started Aug 07 06:16:42 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 237704 kb
Host smart-74967985-a501-446c-8504-d92f59afe268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1134374890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1134374890
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2441024474
Short name T341
Test name
Test status
Simulation time 16485658 ps
CPU time 1.38 seconds
Started Aug 07 06:16:50 PM PDT 24
Finished Aug 07 06:16:51 PM PDT 24
Peak memory 237716 kb
Host smart-9cb8c316-4b46-4744-ac8b-ec05540faeca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2441024474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2441024474
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.90901499
Short name T805
Test name
Test status
Simulation time 8708355 ps
CPU time 1.25 seconds
Started Aug 07 06:16:51 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 236832 kb
Host smart-53f0a9c2-db28-4c9f-b70f-d840e21956fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=90901499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.90901499
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1688713122
Short name T784
Test name
Test status
Simulation time 14572937 ps
CPU time 1.35 seconds
Started Aug 07 06:16:49 PM PDT 24
Finished Aug 07 06:16:51 PM PDT 24
Peak memory 236848 kb
Host smart-947e7eff-fa1f-403d-a2a6-9a45c1ba6605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1688713122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1688713122
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1245275734
Short name T723
Test name
Test status
Simulation time 9937455 ps
CPU time 1.45 seconds
Started Aug 07 06:16:50 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 237720 kb
Host smart-e883c961-024d-4f55-a6d4-556cf5cc8345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1245275734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1245275734
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1003877336
Short name T738
Test name
Test status
Simulation time 8689015 ps
CPU time 1.53 seconds
Started Aug 07 06:16:49 PM PDT 24
Finished Aug 07 06:16:50 PM PDT 24
Peak memory 237708 kb
Host smart-eabb6c7e-adef-4f67-814d-d518fcf31da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1003877336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1003877336
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1197190822
Short name T342
Test name
Test status
Simulation time 6838703 ps
CPU time 1.33 seconds
Started Aug 07 06:16:48 PM PDT 24
Finished Aug 07 06:16:50 PM PDT 24
Peak memory 237724 kb
Host smart-519b8096-db95-4eaf-af78-27c432939b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1197190822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1197190822
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1804050657
Short name T777
Test name
Test status
Simulation time 27437668 ps
CPU time 1.53 seconds
Started Aug 07 06:16:51 PM PDT 24
Finished Aug 07 06:16:53 PM PDT 24
Peak memory 237688 kb
Host smart-ac835d90-5d55-46b8-951f-5cd05d1ce7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1804050657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1804050657
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1586225776
Short name T155
Test name
Test status
Simulation time 12240678 ps
CPU time 1.52 seconds
Started Aug 07 06:16:52 PM PDT 24
Finished Aug 07 06:16:53 PM PDT 24
Peak memory 237704 kb
Host smart-d1347233-14c5-4fb4-b0a8-80b503dce3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1586225776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1586225776
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2999266083
Short name T807
Test name
Test status
Simulation time 21829908 ps
CPU time 1.59 seconds
Started Aug 07 06:16:51 PM PDT 24
Finished Aug 07 06:16:53 PM PDT 24
Peak memory 237920 kb
Host smart-21c9d1eb-a218-42a8-a7d7-2fa10f80de57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2999266083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2999266083
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3470004112
Short name T734
Test name
Test status
Simulation time 2330712849 ps
CPU time 173.33 seconds
Started Aug 07 06:16:20 PM PDT 24
Finished Aug 07 06:19:14 PM PDT 24
Peak memory 240860 kb
Host smart-279a4283-596d-49fe-a982-c99d82347fa6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3470004112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3470004112
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1116313145
Short name T755
Test name
Test status
Simulation time 17112589024 ps
CPU time 272.86 seconds
Started Aug 07 06:16:21 PM PDT 24
Finished Aug 07 06:20:54 PM PDT 24
Peak memory 240968 kb
Host smart-f2cca3fa-cd6a-4213-b491-09e3276823fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1116313145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1116313145
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3376697575
Short name T752
Test name
Test status
Simulation time 666122757 ps
CPU time 5.44 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:25 PM PDT 24
Peak memory 248816 kb
Host smart-3ca93dda-68fc-45ed-9c2f-d0bb698e1675
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3376697575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3376697575
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3797434924
Short name T768
Test name
Test status
Simulation time 64578570 ps
CPU time 9.48 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:16:34 PM PDT 24
Peak memory 257068 kb
Host smart-66d61e53-199f-4c0c-a17b-81b2a92d8665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797434924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3797434924
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2318304119
Short name T735
Test name
Test status
Simulation time 71259767 ps
CPU time 5.56 seconds
Started Aug 07 06:16:21 PM PDT 24
Finished Aug 07 06:16:26 PM PDT 24
Peak memory 240612 kb
Host smart-6eb150a1-5239-4ceb-ad7d-3f5674f77f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2318304119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2318304119
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.956211966
Short name T770
Test name
Test status
Simulation time 14776249 ps
CPU time 1.43 seconds
Started Aug 07 06:16:23 PM PDT 24
Finished Aug 07 06:16:25 PM PDT 24
Peak memory 236728 kb
Host smart-3b6d4a67-7ef2-452d-b3b5-9b7e7d9a8f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=956211966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.956211966
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2793103828
Short name T780
Test name
Test status
Simulation time 710448881 ps
CPU time 44.96 seconds
Started Aug 07 06:16:23 PM PDT 24
Finished Aug 07 06:17:08 PM PDT 24
Peak memory 245844 kb
Host smart-73fa64c5-a15e-4496-9b74-230974182fca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2793103828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2793103828
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2944173093
Short name T129
Test name
Test status
Simulation time 4346981581 ps
CPU time 185.67 seconds
Started Aug 07 06:16:21 PM PDT 24
Finished Aug 07 06:19:27 PM PDT 24
Peak memory 269300 kb
Host smart-fa36a353-8027-463e-acd9-9c4021c0aa1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2944173093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2944173093
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3990866851
Short name T759
Test name
Test status
Simulation time 194616784 ps
CPU time 6.99 seconds
Started Aug 07 06:16:23 PM PDT 24
Finished Aug 07 06:16:30 PM PDT 24
Peak memory 248844 kb
Host smart-4ea40575-187f-4ad2-95b1-cbc3de427336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3990866851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3990866851
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3721837031
Short name T260
Test name
Test status
Simulation time 3706882081 ps
CPU time 61.34 seconds
Started Aug 07 06:16:20 PM PDT 24
Finished Aug 07 06:17:22 PM PDT 24
Peak memory 238856 kb
Host smart-698757c1-007d-49a8-baee-6ec0d9b97ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3721837031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3721837031
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4265097495
Short name T767
Test name
Test status
Simulation time 45478639 ps
CPU time 1.3 seconds
Started Aug 07 06:16:49 PM PDT 24
Finished Aug 07 06:16:50 PM PDT 24
Peak memory 236840 kb
Host smart-2b551e8e-46e7-4d0a-8c24-d14e23fd66cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4265097495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.4265097495
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3928543018
Short name T761
Test name
Test status
Simulation time 11710045 ps
CPU time 1.68 seconds
Started Aug 07 06:16:50 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 237684 kb
Host smart-1378de50-11c4-47cd-9cbe-bd68c85c0b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3928543018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3928543018
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.132252350
Short name T222
Test name
Test status
Simulation time 11501814 ps
CPU time 1.47 seconds
Started Aug 07 06:16:52 PM PDT 24
Finished Aug 07 06:16:54 PM PDT 24
Peak memory 237704 kb
Host smart-b4b7793c-4a1f-4836-94ae-c51bcf8057d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=132252350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.132252350
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.690944107
Short name T729
Test name
Test status
Simulation time 7534444 ps
CPU time 1.48 seconds
Started Aug 07 06:16:48 PM PDT 24
Finished Aug 07 06:16:50 PM PDT 24
Peak memory 235784 kb
Host smart-5eee0ac2-4a30-421f-a2b7-63942a0179de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=690944107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.690944107
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3606891933
Short name T795
Test name
Test status
Simulation time 17242485 ps
CPU time 1.46 seconds
Started Aug 07 06:16:48 PM PDT 24
Finished Aug 07 06:16:50 PM PDT 24
Peak memory 237712 kb
Host smart-88909680-7aa5-4bdd-a9c0-6d53a7b9eb3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3606891933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3606891933
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2845421017
Short name T818
Test name
Test status
Simulation time 15706450 ps
CPU time 1.27 seconds
Started Aug 07 06:16:48 PM PDT 24
Finished Aug 07 06:16:50 PM PDT 24
Peak memory 236808 kb
Host smart-4390a6b9-cf21-435c-91e1-1ca33727827a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2845421017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2845421017
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.674116820
Short name T830
Test name
Test status
Simulation time 9568566 ps
CPU time 1.46 seconds
Started Aug 07 06:16:52 PM PDT 24
Finished Aug 07 06:16:53 PM PDT 24
Peak memory 237760 kb
Host smart-0b3a144e-2671-4713-8adf-773fbb0805c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=674116820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.674116820
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3707880225
Short name T810
Test name
Test status
Simulation time 6858077 ps
CPU time 1.47 seconds
Started Aug 07 06:16:47 PM PDT 24
Finished Aug 07 06:16:48 PM PDT 24
Peak memory 236764 kb
Host smart-ada8ee60-4fd9-4d7e-b6ef-c046cce73b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3707880225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3707880225
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2308859950
Short name T345
Test name
Test status
Simulation time 22926673 ps
CPU time 1.45 seconds
Started Aug 07 06:16:50 PM PDT 24
Finished Aug 07 06:16:51 PM PDT 24
Peak memory 236744 kb
Host smart-0577c279-15ac-48cc-a99f-f87f1d5480e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2308859950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2308859950
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3357854007
Short name T719
Test name
Test status
Simulation time 2094258325 ps
CPU time 143.42 seconds
Started Aug 07 06:16:21 PM PDT 24
Finished Aug 07 06:18:45 PM PDT 24
Peak memory 240532 kb
Host smart-3a79bc1f-fec0-46a1-9886-331f45d0812d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3357854007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3357854007
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1129506638
Short name T815
Test name
Test status
Simulation time 3334883088 ps
CPU time 197.78 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:19:43 PM PDT 24
Peak memory 240628 kb
Host smart-daa68f1c-9fbe-4773-a306-5da516edf368
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1129506638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1129506638
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1831140472
Short name T788
Test name
Test status
Simulation time 206966117 ps
CPU time 4.86 seconds
Started Aug 07 06:16:23 PM PDT 24
Finished Aug 07 06:16:28 PM PDT 24
Peak memory 248820 kb
Host smart-c6cd1375-262d-4ddb-b4ff-e451583b4f9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1831140472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1831140472
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1910806681
Short name T828
Test name
Test status
Simulation time 386296258 ps
CPU time 6.95 seconds
Started Aug 07 06:16:31 PM PDT 24
Finished Aug 07 06:16:38 PM PDT 24
Peak memory 240896 kb
Host smart-69277543-5858-44de-af5c-652a603a62ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910806681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1910806681
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1705730335
Short name T745
Test name
Test status
Simulation time 64552920 ps
CPU time 5.49 seconds
Started Aug 07 06:16:24 PM PDT 24
Finished Aug 07 06:16:30 PM PDT 24
Peak memory 240568 kb
Host smart-0e872c90-a997-44f8-b6d2-46a4d6167ca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1705730335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1705730335
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.982086999
Short name T783
Test name
Test status
Simulation time 8441170 ps
CPU time 1.45 seconds
Started Aug 07 06:16:29 PM PDT 24
Finished Aug 07 06:16:31 PM PDT 24
Peak memory 237628 kb
Host smart-e329bde2-2b9b-4f44-9cce-e483ee5b45a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=982086999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.982086999
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2124656779
Short name T785
Test name
Test status
Simulation time 951994670 ps
CPU time 23.73 seconds
Started Aug 07 06:16:20 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 245904 kb
Host smart-1add3102-73cf-4e8b-8392-f5c379a58ad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2124656779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2124656779
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.786236566
Short name T710
Test name
Test status
Simulation time 203210406 ps
CPU time 4.84 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:16:30 PM PDT 24
Peak memory 251200 kb
Host smart-72ce6e8e-9f77-4e83-9d9e-1479f531e938
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=786236566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.786236566
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2853722936
Short name T718
Test name
Test status
Simulation time 12038890 ps
CPU time 1.4 seconds
Started Aug 07 06:16:47 PM PDT 24
Finished Aug 07 06:16:49 PM PDT 24
Peak memory 237720 kb
Host smart-f7c325a8-e44f-4025-98a6-3d681883cf8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2853722936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2853722936
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3849989861
Short name T714
Test name
Test status
Simulation time 14556803 ps
CPU time 1.41 seconds
Started Aug 07 06:16:50 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 236732 kb
Host smart-14232de8-75fc-472a-8e62-5b25a9094289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3849989861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3849989861
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3766108245
Short name T782
Test name
Test status
Simulation time 11183495 ps
CPU time 1.68 seconds
Started Aug 07 06:16:52 PM PDT 24
Finished Aug 07 06:16:54 PM PDT 24
Peak memory 237728 kb
Host smart-f842c50f-4e7c-4e0c-8939-4744ea724c77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3766108245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3766108245
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3387882338
Short name T793
Test name
Test status
Simulation time 10709307 ps
CPU time 1.39 seconds
Started Aug 07 06:16:50 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 236812 kb
Host smart-79628675-bd2b-4316-95e9-cab754e3e06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3387882338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3387882338
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.619798341
Short name T715
Test name
Test status
Simulation time 7574499 ps
CPU time 1.48 seconds
Started Aug 07 06:16:49 PM PDT 24
Finished Aug 07 06:16:50 PM PDT 24
Peak memory 236824 kb
Host smart-ab1260f9-c9a1-4f43-8696-61d1e175ad2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=619798341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.619798341
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3988983340
Short name T720
Test name
Test status
Simulation time 20558087 ps
CPU time 1.45 seconds
Started Aug 07 06:16:50 PM PDT 24
Finished Aug 07 06:16:52 PM PDT 24
Peak memory 237736 kb
Host smart-86754d13-3e19-44a9-bc5a-bc11da3fd081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3988983340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3988983340
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.67789554
Short name T772
Test name
Test status
Simulation time 16739927 ps
CPU time 1.46 seconds
Started Aug 07 06:16:54 PM PDT 24
Finished Aug 07 06:16:56 PM PDT 24
Peak memory 237700 kb
Host smart-af478a69-a335-4321-be82-0abf058f65dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=67789554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.67789554
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1500890416
Short name T781
Test name
Test status
Simulation time 24696734 ps
CPU time 1.29 seconds
Started Aug 07 06:16:49 PM PDT 24
Finished Aug 07 06:16:50 PM PDT 24
Peak memory 235820 kb
Host smart-db9df292-3407-4bd3-a29d-f05054a1e824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1500890416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1500890416
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2541378489
Short name T758
Test name
Test status
Simulation time 21849470 ps
CPU time 2.05 seconds
Started Aug 07 06:16:58 PM PDT 24
Finished Aug 07 06:17:00 PM PDT 24
Peak memory 237708 kb
Host smart-6e02faa3-7003-4207-8d6b-5d91350c48db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2541378489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2541378489
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.260913233
Short name T740
Test name
Test status
Simulation time 69289380 ps
CPU time 3.53 seconds
Started Aug 07 06:16:54 PM PDT 24
Finished Aug 07 06:16:58 PM PDT 24
Peak memory 237680 kb
Host smart-89443cea-ca32-4759-bec6-8d54f925ca7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=260913233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.260913233
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1435979691
Short name T750
Test name
Test status
Simulation time 949505775 ps
CPU time 11.2 seconds
Started Aug 07 06:16:21 PM PDT 24
Finished Aug 07 06:16:33 PM PDT 24
Peak memory 252376 kb
Host smart-7cba484c-42c6-47a9-892b-4fbd1fa68e21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435979691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1435979691
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2900557741
Short name T819
Test name
Test status
Simulation time 244498779 ps
CPU time 5.39 seconds
Started Aug 07 06:16:23 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 237668 kb
Host smart-28d57605-cf99-48ba-b829-1b6352efb175
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2900557741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2900557741
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2541668239
Short name T727
Test name
Test status
Simulation time 11992466 ps
CPU time 1.32 seconds
Started Aug 07 06:16:19 PM PDT 24
Finished Aug 07 06:16:20 PM PDT 24
Peak memory 237592 kb
Host smart-7e2f1547-08ea-440a-bc07-7f8c47238d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2541668239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2541668239
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.711679900
Short name T169
Test name
Test status
Simulation time 681126495 ps
CPU time 22.29 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:16:48 PM PDT 24
Peak memory 245828 kb
Host smart-98627b22-f182-40cc-a113-4d99da3071ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=711679900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.711679900
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2147092474
Short name T748
Test name
Test status
Simulation time 1694332245 ps
CPU time 21.89 seconds
Started Aug 07 06:16:22 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 248896 kb
Host smart-3332e93d-7cd1-4943-ac1a-000da5949805
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2147092474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2147092474
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3281940236
Short name T731
Test name
Test status
Simulation time 167768438 ps
CPU time 6.17 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:16:32 PM PDT 24
Peak memory 252332 kb
Host smart-d938ccbf-5b01-43fd-9f79-eb5b39ea707b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281940236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3281940236
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1585926110
Short name T348
Test name
Test status
Simulation time 52565725 ps
CPU time 4.88 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:16:30 PM PDT 24
Peak memory 240568 kb
Host smart-71e1870b-5e9d-42c5-9370-6903d98c77e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1585926110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1585926110
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.208482532
Short name T811
Test name
Test status
Simulation time 12380314 ps
CPU time 1.61 seconds
Started Aug 07 06:16:29 PM PDT 24
Finished Aug 07 06:16:31 PM PDT 24
Peak memory 236756 kb
Host smart-1ced4f6c-bb65-4bde-be91-5a5389806eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=208482532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.208482532
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.698994719
Short name T167
Test name
Test status
Simulation time 322973839 ps
CPU time 22.3 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:16:47 PM PDT 24
Peak memory 248736 kb
Host smart-89720410-93c5-4652-acfd-e25d86285712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=698994719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.698994719
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2657793844
Short name T141
Test name
Test status
Simulation time 7161083262 ps
CPU time 102.5 seconds
Started Aug 07 06:16:30 PM PDT 24
Finished Aug 07 06:18:13 PM PDT 24
Peak memory 266600 kb
Host smart-f970592a-c23d-4745-9676-f0d7bf41fb68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2657793844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2657793844
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3810492147
Short name T133
Test name
Test status
Simulation time 24977876873 ps
CPU time 505.19 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 265608 kb
Host smart-d6be17d3-5f96-4bcf-aed8-1eeeb44f5afe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810492147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3810492147
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4089402420
Short name T821
Test name
Test status
Simulation time 186908454 ps
CPU time 11.66 seconds
Started Aug 07 06:16:21 PM PDT 24
Finished Aug 07 06:16:33 PM PDT 24
Peak memory 255744 kb
Host smart-9e3840a0-63d7-45c1-8dc4-6c4920e9f85a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4089402420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.4089402420
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2239902049
Short name T754
Test name
Test status
Simulation time 620453374 ps
CPU time 13.97 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:16:39 PM PDT 24
Peak memory 256720 kb
Host smart-0733cae4-0d30-4137-a274-2bb3a3ca329d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239902049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2239902049
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3133143519
Short name T823
Test name
Test status
Simulation time 442387335 ps
CPU time 8.6 seconds
Started Aug 07 06:16:28 PM PDT 24
Finished Aug 07 06:16:37 PM PDT 24
Peak memory 236808 kb
Host smart-afce65c8-97ff-4d40-b385-29dcf18e9272
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3133143519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3133143519
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1074200265
Short name T786
Test name
Test status
Simulation time 162432603 ps
CPU time 21.27 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:16:46 PM PDT 24
Peak memory 245908 kb
Host smart-0b6a01ab-bdc7-45ca-9e3b-68f0b428a34c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1074200265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1074200265
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3519337696
Short name T144
Test name
Test status
Simulation time 2617299600 ps
CPU time 168.23 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:19:14 PM PDT 24
Peak memory 257464 kb
Host smart-a4cf77be-a20f-48c9-b810-b6279711f072
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3519337696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3519337696
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3131396666
Short name T115
Test name
Test status
Simulation time 8025693677 ps
CPU time 543.9 seconds
Started Aug 07 06:16:27 PM PDT 24
Finished Aug 07 06:25:31 PM PDT 24
Peak memory 265532 kb
Host smart-d0efa21a-9848-445c-9210-8f083790b8d6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131396666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3131396666
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3331820696
Short name T791
Test name
Test status
Simulation time 27148352 ps
CPU time 4.19 seconds
Started Aug 07 06:16:27 PM PDT 24
Finished Aug 07 06:16:31 PM PDT 24
Peak memory 251996 kb
Host smart-634aeeab-c2b2-45ab-bc34-1774fe71bb59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3331820696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3331820696
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4242398904
Short name T824
Test name
Test status
Simulation time 496255097 ps
CPU time 9.1 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:16:35 PM PDT 24
Peak memory 240672 kb
Host smart-0dae360b-15c3-44cf-918d-6b9192f75183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242398904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4242398904
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.150794881
Short name T803
Test name
Test status
Simulation time 66744662 ps
CPU time 3.66 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 240596 kb
Host smart-e1e446b9-ca16-4ff2-9dfe-2ff277680bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=150794881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.150794881
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1075777485
Short name T722
Test name
Test status
Simulation time 9106534 ps
CPU time 1.32 seconds
Started Aug 07 06:16:27 PM PDT 24
Finished Aug 07 06:16:28 PM PDT 24
Peak memory 237744 kb
Host smart-9bdfd717-0cbb-4b9c-be5b-b16df2449de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1075777485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1075777485
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.666693132
Short name T757
Test name
Test status
Simulation time 726534415 ps
CPU time 28.68 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:16:55 PM PDT 24
Peak memory 248824 kb
Host smart-99b4c47b-ed33-4c07-9538-d8b531c7b928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=666693132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.666693132
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2838928167
Short name T350
Test name
Test status
Simulation time 7200290636 ps
CPU time 517.19 seconds
Started Aug 07 06:16:25 PM PDT 24
Finished Aug 07 06:25:03 PM PDT 24
Peak memory 265704 kb
Host smart-43c85116-89f0-4694-84ad-a7214cb54d8e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838928167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2838928167
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1231958304
Short name T808
Test name
Test status
Simulation time 1020727257 ps
CPU time 19.52 seconds
Started Aug 07 06:16:24 PM PDT 24
Finished Aug 07 06:16:44 PM PDT 24
Peak memory 248968 kb
Host smart-b1eeb1d6-8b89-4aff-964d-55703fee6175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1231958304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1231958304
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2416395642
Short name T812
Test name
Test status
Simulation time 288205889 ps
CPU time 12.39 seconds
Started Aug 07 06:16:31 PM PDT 24
Finished Aug 07 06:16:43 PM PDT 24
Peak memory 251872 kb
Host smart-5e7a0913-75c9-493d-8e69-65d1451bd859
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416395642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2416395642
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3494444803
Short name T832
Test name
Test status
Simulation time 365131111 ps
CPU time 8.29 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:16:34 PM PDT 24
Peak memory 237696 kb
Host smart-65fc81ae-5b76-48f6-9ec1-28c8f753d32d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3494444803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3494444803
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.585967504
Short name T809
Test name
Test status
Simulation time 8249864 ps
CPU time 1.42 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:16:28 PM PDT 24
Peak memory 237752 kb
Host smart-2add1fb9-a722-4252-be02-75c269c4f6cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=585967504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.585967504
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3010486675
Short name T751
Test name
Test status
Simulation time 210341880 ps
CPU time 12.94 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:16:39 PM PDT 24
Peak memory 248848 kb
Host smart-c7b74146-0758-4656-acd9-6e0025e77e18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3010486675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3010486675
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1874238074
Short name T130
Test name
Test status
Simulation time 7514765361 ps
CPU time 108.74 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:18:15 PM PDT 24
Peak memory 265556 kb
Host smart-bc0b2614-d7b7-4d2f-be58-481ada9885df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1874238074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1874238074
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2514420722
Short name T138
Test name
Test status
Simulation time 12217046695 ps
CPU time 469.44 seconds
Started Aug 07 06:16:26 PM PDT 24
Finished Aug 07 06:24:16 PM PDT 24
Peak memory 270492 kb
Host smart-5ae688d2-b1e1-41aa-9128-d4acb08398cb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514420722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2514420722
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.866030330
Short name T814
Test name
Test status
Simulation time 615927058 ps
CPU time 24.34 seconds
Started Aug 07 06:16:23 PM PDT 24
Finished Aug 07 06:16:47 PM PDT 24
Peak memory 248536 kb
Host smart-ba37db3d-3086-4569-8b3a-059e561ae4f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=866030330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.866030330
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.190208081
Short name T659
Test name
Test status
Simulation time 2009701252 ps
CPU time 36.79 seconds
Started Aug 07 07:14:52 PM PDT 24
Finished Aug 07 07:15:28 PM PDT 24
Peak memory 248408 kb
Host smart-12d9db9b-b133-4ac2-8421-43260b3d103a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=190208081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.190208081
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1590643019
Short name T215
Test name
Test status
Simulation time 1304941064 ps
CPU time 93.19 seconds
Started Aug 07 07:14:48 PM PDT 24
Finished Aug 07 07:16:21 PM PDT 24
Peak memory 256196 kb
Host smart-05ddc214-7f9a-4b09-a908-cdd4dba62bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15906
43019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1590643019
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4058293315
Short name T481
Test name
Test status
Simulation time 4082445248 ps
CPU time 39.45 seconds
Started Aug 07 07:14:45 PM PDT 24
Finished Aug 07 07:15:25 PM PDT 24
Peak memory 248268 kb
Host smart-edfd4c71-00ea-4f4d-b0fd-dd11d6be8bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40582
93315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4058293315
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2809392360
Short name T41
Test name
Test status
Simulation time 108603028195 ps
CPU time 1563.84 seconds
Started Aug 07 07:14:55 PM PDT 24
Finished Aug 07 07:40:59 PM PDT 24
Peak memory 288804 kb
Host smart-ce7e32db-fff2-4fb7-85a8-37f07b3ddff1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809392360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2809392360
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3661970635
Short name T380
Test name
Test status
Simulation time 87575903836 ps
CPU time 623.84 seconds
Started Aug 07 07:14:54 PM PDT 24
Finished Aug 07 07:25:18 PM PDT 24
Peak memory 268044 kb
Host smart-808a2b44-25e6-426e-bafe-15ef159bba3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661970635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3661970635
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2306094994
Short name T467
Test name
Test status
Simulation time 14990817972 ps
CPU time 153.02 seconds
Started Aug 07 07:14:53 PM PDT 24
Finished Aug 07 07:17:26 PM PDT 24
Peak memory 248908 kb
Host smart-52437054-d388-4523-95e6-9acc5a6f2276
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306094994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2306094994
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.77713091
Short name T387
Test name
Test status
Simulation time 1416378514 ps
CPU time 39.55 seconds
Started Aug 07 07:14:48 PM PDT 24
Finished Aug 07 07:15:28 PM PDT 24
Peak memory 248536 kb
Host smart-cb93f3ad-c561-4ae6-9b14-aeed3ff835ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77713
091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.77713091
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1046314203
Short name T487
Test name
Test status
Simulation time 1673400670 ps
CPU time 43.95 seconds
Started Aug 07 07:14:47 PM PDT 24
Finished Aug 07 07:15:31 PM PDT 24
Peak memory 256204 kb
Host smart-c0bf4ef7-c3d8-4167-b6f0-701ddb33537c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10463
14203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1046314203
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2768959208
Short name T35
Test name
Test status
Simulation time 500198730 ps
CPU time 11.58 seconds
Started Aug 07 07:14:54 PM PDT 24
Finished Aug 07 07:15:06 PM PDT 24
Peak memory 278484 kb
Host smart-db49fc39-722c-4483-adb1-39391450c337
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2768959208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2768959208
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1910108100
Short name T695
Test name
Test status
Simulation time 74688220 ps
CPU time 10.13 seconds
Started Aug 07 07:14:53 PM PDT 24
Finished Aug 07 07:15:03 PM PDT 24
Peak memory 247916 kb
Host smart-5503eb35-c89c-4a31-8709-dd61bc0373ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19101
08100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1910108100
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2403063143
Short name T549
Test name
Test status
Simulation time 387552313 ps
CPU time 20.97 seconds
Started Aug 07 07:14:45 PM PDT 24
Finished Aug 07 07:15:06 PM PDT 24
Peak memory 256584 kb
Host smart-b4b25550-7d8d-439f-828c-3d08d38e5a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24030
63143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2403063143
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.756834124
Short name T106
Test name
Test status
Simulation time 47177029360 ps
CPU time 1019.84 seconds
Started Aug 07 07:14:52 PM PDT 24
Finished Aug 07 07:31:52 PM PDT 24
Peak memory 273104 kb
Host smart-52843a7f-77cd-4fe6-b7b6-fb1401c3eb9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756834124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.756834124
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2018099886
Short name T33
Test name
Test status
Simulation time 56163080910 ps
CPU time 1386.05 seconds
Started Aug 07 07:14:54 PM PDT 24
Finished Aug 07 07:38:00 PM PDT 24
Peak memory 289492 kb
Host smart-34cc08bd-d46f-493a-b88c-ead4110fed0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018099886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2018099886
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.4289202796
Short name T389
Test name
Test status
Simulation time 4372072838 ps
CPU time 46.1 seconds
Started Aug 07 07:14:55 PM PDT 24
Finished Aug 07 07:15:41 PM PDT 24
Peak memory 248524 kb
Host smart-85a4a4cd-94b0-4f06-9b24-f31f142e30c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4289202796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.4289202796
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1705501976
Short name T450
Test name
Test status
Simulation time 5819926155 ps
CPU time 23.44 seconds
Started Aug 07 07:14:53 PM PDT 24
Finished Aug 07 07:15:17 PM PDT 24
Peak memory 256088 kb
Host smart-ed1f5597-44ec-44ae-8e89-85b58706d6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17055
01976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1705501976
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3609479227
Short name T649
Test name
Test status
Simulation time 1293191094 ps
CPU time 42.22 seconds
Started Aug 07 07:14:52 PM PDT 24
Finished Aug 07 07:15:34 PM PDT 24
Peak memory 248136 kb
Host smart-8f36d92e-48b7-4f08-ae0a-70dbd48c22b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36094
79227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3609479227
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3948533278
Short name T590
Test name
Test status
Simulation time 220923903134 ps
CPU time 1755.76 seconds
Started Aug 07 07:14:54 PM PDT 24
Finished Aug 07 07:44:10 PM PDT 24
Peak memory 289216 kb
Host smart-0d8bc4da-7820-49cd-9b2c-cd7f2f15a135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948533278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3948533278
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3274439475
Short name T292
Test name
Test status
Simulation time 26568038577 ps
CPU time 520.6 seconds
Started Aug 07 07:14:55 PM PDT 24
Finished Aug 07 07:23:35 PM PDT 24
Peak memory 247452 kb
Host smart-b332f99a-a124-4ae8-9d5b-01896173961f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274439475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3274439475
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3703307669
Short name T569
Test name
Test status
Simulation time 640343799 ps
CPU time 32.39 seconds
Started Aug 07 07:14:57 PM PDT 24
Finished Aug 07 07:15:29 PM PDT 24
Peak memory 255944 kb
Host smart-b8dd0021-5c7a-4cc3-94a2-2c44a7a354e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37033
07669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3703307669
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2336655354
Short name T550
Test name
Test status
Simulation time 528318052 ps
CPU time 35.62 seconds
Started Aug 07 07:14:54 PM PDT 24
Finished Aug 07 07:15:29 PM PDT 24
Peak memory 248012 kb
Host smart-f47f2ffb-05bf-4b41-9e94-35d4c851dc93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23366
55354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2336655354
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1384359140
Short name T12
Test name
Test status
Simulation time 2002886855 ps
CPU time 26.37 seconds
Started Aug 07 07:14:52 PM PDT 24
Finished Aug 07 07:15:19 PM PDT 24
Peak memory 276844 kb
Host smart-a05e56e0-0e14-4074-ba84-f854cde3f4f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1384359140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1384359140
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2114001518
Short name T110
Test name
Test status
Simulation time 1969588837 ps
CPU time 14.19 seconds
Started Aug 07 07:14:57 PM PDT 24
Finished Aug 07 07:15:11 PM PDT 24
Peak memory 248496 kb
Host smart-1d91bc60-afb1-4a21-96e4-fef2858d88aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21140
01518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2114001518
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.322602495
Short name T531
Test name
Test status
Simulation time 604100516 ps
CPU time 20.55 seconds
Started Aug 07 07:14:54 PM PDT 24
Finished Aug 07 07:15:14 PM PDT 24
Peak memory 256624 kb
Host smart-3f37f6e9-13bf-4cb4-88b6-961110160282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260
2495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.322602495
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3273445875
Short name T282
Test name
Test status
Simulation time 29671763416 ps
CPU time 1166.01 seconds
Started Aug 07 07:14:57 PM PDT 24
Finished Aug 07 07:34:23 PM PDT 24
Peak memory 289560 kb
Host smart-dba21820-5bc3-44e7-b23b-7e8a6ee9064c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273445875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3273445875
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3003542547
Short name T204
Test name
Test status
Simulation time 80543899 ps
CPU time 3.6 seconds
Started Aug 07 07:15:39 PM PDT 24
Finished Aug 07 07:15:43 PM PDT 24
Peak memory 248660 kb
Host smart-8164900f-551d-4a21-ace6-1f9dcc2a1e4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3003542547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3003542547
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.603120082
Short name T570
Test name
Test status
Simulation time 61008428644 ps
CPU time 1502.35 seconds
Started Aug 07 07:15:39 PM PDT 24
Finished Aug 07 07:40:42 PM PDT 24
Peak memory 288576 kb
Host smart-9e772119-c8bf-4b42-96f0-d38f01a62629
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603120082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.603120082
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1509965138
Short name T610
Test name
Test status
Simulation time 247805025 ps
CPU time 7.2 seconds
Started Aug 07 07:15:34 PM PDT 24
Finished Aug 07 07:15:41 PM PDT 24
Peak memory 248488 kb
Host smart-a6029abf-59ef-48d9-a152-cfaa8e96df53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1509965138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1509965138
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1100471588
Short name T648
Test name
Test status
Simulation time 479191309 ps
CPU time 16.64 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 07:15:43 PM PDT 24
Peak memory 255068 kb
Host smart-a67864aa-bfef-4c7c-b5fd-ebeff4881cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11004
71588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1100471588
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2686908420
Short name T701
Test name
Test status
Simulation time 2892535497 ps
CPU time 81.76 seconds
Started Aug 07 07:15:27 PM PDT 24
Finished Aug 07 07:16:49 PM PDT 24
Peak memory 248252 kb
Host smart-48ea8064-e44b-483c-bb2e-468d590613d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26869
08420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2686908420
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2168300550
Short name T321
Test name
Test status
Simulation time 16478107721 ps
CPU time 1457.97 seconds
Started Aug 07 07:15:36 PM PDT 24
Finished Aug 07 07:39:54 PM PDT 24
Peak memory 288344 kb
Host smart-a56a77c4-b11b-4cfc-9e24-c4dcfa266207
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168300550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2168300550
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2524186958
Short name T392
Test name
Test status
Simulation time 33424595037 ps
CPU time 1733.8 seconds
Started Aug 07 07:15:38 PM PDT 24
Finished Aug 07 07:44:32 PM PDT 24
Peak memory 272472 kb
Host smart-fe2eba1b-63cb-4fa1-bc21-8bfa92608a5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524186958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2524186958
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1230349354
Short name T707
Test name
Test status
Simulation time 26536557008 ps
CPU time 291.12 seconds
Started Aug 07 07:15:38 PM PDT 24
Finished Aug 07 07:20:29 PM PDT 24
Peak memory 255196 kb
Host smart-31bc2b74-8207-4895-8e6a-173d9133e35e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230349354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1230349354
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2955071671
Short name T230
Test name
Test status
Simulation time 4102666578 ps
CPU time 53.22 seconds
Started Aug 07 07:15:24 PM PDT 24
Finished Aug 07 07:16:18 PM PDT 24
Peak memory 256056 kb
Host smart-7db713f0-926d-4384-97c6-d6c23f872f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29550
71671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2955071671
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1005765438
Short name T243
Test name
Test status
Simulation time 9042689494 ps
CPU time 40.34 seconds
Started Aug 07 07:15:28 PM PDT 24
Finished Aug 07 07:16:09 PM PDT 24
Peak memory 256316 kb
Host smart-e597f9f9-cff1-4c07-ad19-1149a8a0c1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10057
65438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1005765438
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.973381951
Short name T85
Test name
Test status
Simulation time 1137987871 ps
CPU time 31.82 seconds
Started Aug 07 07:15:37 PM PDT 24
Finished Aug 07 07:16:09 PM PDT 24
Peak memory 255732 kb
Host smart-d6f54803-d497-4691-99d1-33fc3399c350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97338
1951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.973381951
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4281178228
Short name T484
Test name
Test status
Simulation time 1117974457 ps
CPU time 25.81 seconds
Started Aug 07 07:15:24 PM PDT 24
Finished Aug 07 07:15:50 PM PDT 24
Peak memory 256608 kb
Host smart-b507615e-93c1-404c-adcb-587e960e93a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42811
78228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4281178228
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3903683887
Short name T612
Test name
Test status
Simulation time 242948966 ps
CPU time 4.49 seconds
Started Aug 07 07:15:43 PM PDT 24
Finished Aug 07 07:15:48 PM PDT 24
Peak memory 248692 kb
Host smart-9b7f44b6-3729-49d4-a472-dc535d00da3f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3903683887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3903683887
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1775666850
Short name T412
Test name
Test status
Simulation time 67421370532 ps
CPU time 2005.72 seconds
Started Aug 07 07:15:45 PM PDT 24
Finished Aug 07 07:49:11 PM PDT 24
Peak memory 273140 kb
Host smart-91b9d610-7a32-4d94-85fc-8c58e1e1e542
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775666850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1775666850
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1688539054
Short name T483
Test name
Test status
Simulation time 2604984497 ps
CPU time 16.75 seconds
Started Aug 07 07:15:44 PM PDT 24
Finished Aug 07 07:16:01 PM PDT 24
Peak memory 248524 kb
Host smart-8290a4c7-95b8-45d1-9a2f-8b950133c303
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1688539054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1688539054
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3863166082
Short name T499
Test name
Test status
Simulation time 13127622608 ps
CPU time 185.41 seconds
Started Aug 07 07:15:40 PM PDT 24
Finished Aug 07 07:18:45 PM PDT 24
Peak memory 256668 kb
Host smart-ce36aee5-3b8b-4177-a76e-8192fcfa5b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38631
66082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3863166082
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3703070777
Short name T421
Test name
Test status
Simulation time 346979282 ps
CPU time 32.68 seconds
Started Aug 07 07:15:35 PM PDT 24
Finished Aug 07 07:16:07 PM PDT 24
Peak memory 248440 kb
Host smart-40a3e2fd-87d0-41a0-9cee-fd04164eec94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37030
70777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3703070777
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2749716035
Short name T643
Test name
Test status
Simulation time 9280040131 ps
CPU time 863.02 seconds
Started Aug 07 07:15:45 PM PDT 24
Finished Aug 07 07:30:08 PM PDT 24
Peak memory 272512 kb
Host smart-2b2a1fe3-5ed4-425b-8975-21bbb53fa48e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749716035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2749716035
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3130628
Short name T22
Test name
Test status
Simulation time 16560797915 ps
CPU time 1509.4 seconds
Started Aug 07 07:15:44 PM PDT 24
Finished Aug 07 07:40:54 PM PDT 24
Peak memory 287460 kb
Host smart-051d603a-2cba-4cf8-81b0-28fc45cd4478
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3130628
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2695035981
Short name T315
Test name
Test status
Simulation time 10249459617 ps
CPU time 396.61 seconds
Started Aug 07 07:15:45 PM PDT 24
Finished Aug 07 07:22:22 PM PDT 24
Peak memory 254760 kb
Host smart-3e006ffa-3260-4c02-9366-a49005d7c808
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695035981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2695035981
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1752885913
Short name T631
Test name
Test status
Simulation time 398613121 ps
CPU time 37.89 seconds
Started Aug 07 07:15:51 PM PDT 24
Finished Aug 07 07:16:29 PM PDT 24
Peak memory 256600 kb
Host smart-e6dcdd58-1734-40d0-b2f4-47da18593676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528
85913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1752885913
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3882965278
Short name T511
Test name
Test status
Simulation time 1380400669 ps
CPU time 37.3 seconds
Started Aug 07 07:15:39 PM PDT 24
Finished Aug 07 07:16:16 PM PDT 24
Peak memory 256164 kb
Host smart-30df939d-2f8e-4921-93da-2efa1532471b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38829
65278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3882965278
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2812860666
Short name T112
Test name
Test status
Simulation time 410339067 ps
CPU time 23.03 seconds
Started Aug 07 07:15:44 PM PDT 24
Finished Aug 07 07:16:08 PM PDT 24
Peak memory 248028 kb
Host smart-8b550a70-fe0f-4277-9b00-35427277b29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28128
60666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2812860666
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2243647155
Short name T581
Test name
Test status
Simulation time 354852833 ps
CPU time 36.76 seconds
Started Aug 07 07:15:37 PM PDT 24
Finished Aug 07 07:16:14 PM PDT 24
Peak memory 256580 kb
Host smart-9a62af1d-016f-4c47-a380-c165eb9cafc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22436
47155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2243647155
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2942507715
Short name T615
Test name
Test status
Simulation time 11273282926 ps
CPU time 1077.84 seconds
Started Aug 07 07:15:44 PM PDT 24
Finished Aug 07 07:33:42 PM PDT 24
Peak memory 288576 kb
Host smart-2303b231-61c3-4149-a50a-d62a1ff4f793
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942507715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2942507715
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.4013109911
Short name T663
Test name
Test status
Simulation time 68670286338 ps
CPU time 1485.37 seconds
Started Aug 07 07:15:41 PM PDT 24
Finished Aug 07 07:40:27 PM PDT 24
Peak memory 297920 kb
Host smart-d852f988-7ab5-49ba-ada3-fca5c00d2f70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013109911 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.4013109911
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3784965877
Short name T203
Test name
Test status
Simulation time 143509854 ps
CPU time 2.79 seconds
Started Aug 07 07:15:51 PM PDT 24
Finished Aug 07 07:15:54 PM PDT 24
Peak memory 248712 kb
Host smart-65ae15c8-5b8e-457e-830d-30af3ba1784e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3784965877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3784965877
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2140280917
Short name T31
Test name
Test status
Simulation time 10844115215 ps
CPU time 1134.83 seconds
Started Aug 07 07:15:56 PM PDT 24
Finished Aug 07 07:34:51 PM PDT 24
Peak memory 282540 kb
Host smart-109a8be1-1b52-497b-a4df-78e748f83abc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140280917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2140280917
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2486348680
Short name T468
Test name
Test status
Simulation time 278494401 ps
CPU time 15.79 seconds
Started Aug 07 07:15:56 PM PDT 24
Finished Aug 07 07:16:12 PM PDT 24
Peak memory 248464 kb
Host smart-3e479329-a287-4b4b-b846-38ba7f7cc156
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2486348680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2486348680
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.705485912
Short name T371
Test name
Test status
Simulation time 2929971202 ps
CPU time 163.66 seconds
Started Aug 07 07:15:54 PM PDT 24
Finished Aug 07 07:18:38 PM PDT 24
Peak memory 256792 kb
Host smart-fe3e07f4-8528-45fe-97fd-03102d68baee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70548
5912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.705485912
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.514152198
Short name T78
Test name
Test status
Simulation time 1124786812 ps
CPU time 32.56 seconds
Started Aug 07 07:15:54 PM PDT 24
Finished Aug 07 07:16:27 PM PDT 24
Peak memory 256304 kb
Host smart-9e2689dd-59ba-45a6-a43f-5c07ee83dfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51415
2198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.514152198
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.286322213
Short name T227
Test name
Test status
Simulation time 27708223783 ps
CPU time 1697.1 seconds
Started Aug 07 07:15:55 PM PDT 24
Finished Aug 07 07:44:12 PM PDT 24
Peak memory 272508 kb
Host smart-260c4d6b-1aa3-4db8-94ab-192543b08191
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286322213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.286322213
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3344041282
Short name T209
Test name
Test status
Simulation time 41012261070 ps
CPU time 1055.54 seconds
Started Aug 07 07:15:53 PM PDT 24
Finished Aug 07 07:33:29 PM PDT 24
Peak memory 288692 kb
Host smart-94144945-5c84-4f5b-a0fa-1941f987c3fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344041282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3344041282
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1486481835
Short name T306
Test name
Test status
Simulation time 22459690386 ps
CPU time 483.41 seconds
Started Aug 07 07:15:54 PM PDT 24
Finished Aug 07 07:23:58 PM PDT 24
Peak memory 247456 kb
Host smart-0b7a7407-c5b9-449d-8eb1-e9e02e2a3936
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486481835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1486481835
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2280983424
Short name T465
Test name
Test status
Simulation time 2685488135 ps
CPU time 35.75 seconds
Started Aug 07 07:15:44 PM PDT 24
Finished Aug 07 07:16:19 PM PDT 24
Peak memory 256256 kb
Host smart-2d79427b-6eb0-4ecc-a34d-2e124b77888f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22809
83424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2280983424
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3722800668
Short name T265
Test name
Test status
Simulation time 335688693 ps
CPU time 10.82 seconds
Started Aug 07 07:15:53 PM PDT 24
Finished Aug 07 07:16:04 PM PDT 24
Peak memory 254580 kb
Host smart-b170f3ec-bf8b-4c90-bfc5-3c017b3ea46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37228
00668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3722800668
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1631999021
Short name T59
Test name
Test status
Simulation time 28444653 ps
CPU time 4.98 seconds
Started Aug 07 07:15:57 PM PDT 24
Finished Aug 07 07:16:02 PM PDT 24
Peak memory 239580 kb
Host smart-31c406d5-eb88-467b-83be-50b02765cf2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16319
99021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1631999021
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2787543333
Short name T83
Test name
Test status
Simulation time 5254282401 ps
CPU time 65.98 seconds
Started Aug 07 07:15:45 PM PDT 24
Finished Aug 07 07:16:51 PM PDT 24
Peak memory 256432 kb
Host smart-566a8996-352e-4c8b-be49-0b5c41e74cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27875
43333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2787543333
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1155933844
Short name T507
Test name
Test status
Simulation time 232040891109 ps
CPU time 3623.98 seconds
Started Aug 07 07:15:57 PM PDT 24
Finished Aug 07 08:16:21 PM PDT 24
Peak memory 288648 kb
Host smart-433aa2d2-4a33-4db7-9889-80f1fa495dd6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155933844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1155933844
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.427556560
Short name T200
Test name
Test status
Simulation time 19918189 ps
CPU time 2.84 seconds
Started Aug 07 07:16:04 PM PDT 24
Finished Aug 07 07:16:07 PM PDT 24
Peak memory 248632 kb
Host smart-0e5d2776-0db4-4605-97e2-f1449a9482e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=427556560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.427556560
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1869230144
Short name T682
Test name
Test status
Simulation time 56864203131 ps
CPU time 1013.75 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:32:59 PM PDT 24
Peak memory 289248 kb
Host smart-2cf0215c-b615-4713-a26b-99f911e30c6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869230144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1869230144
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3868975706
Short name T486
Test name
Test status
Simulation time 1991980378 ps
CPU time 27.4 seconds
Started Aug 07 07:16:07 PM PDT 24
Finished Aug 07 07:16:35 PM PDT 24
Peak memory 248472 kb
Host smart-519cfb08-7c61-4cad-91f1-1d2d475ede48
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3868975706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3868975706
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2987126875
Short name T24
Test name
Test status
Simulation time 5461453455 ps
CPU time 107.86 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:17:53 PM PDT 24
Peak memory 256728 kb
Host smart-0a006922-2b51-46a1-95ff-4fb7428963ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29871
26875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2987126875
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3663989481
Short name T685
Test name
Test status
Simulation time 349792312 ps
CPU time 28.01 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:16:34 PM PDT 24
Peak memory 248268 kb
Host smart-f8731f8d-2a75-4cf2-af72-68f48a469acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36639
89481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3663989481
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2035165457
Short name T560
Test name
Test status
Simulation time 81540955188 ps
CPU time 1210.66 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:36:16 PM PDT 24
Peak memory 272236 kb
Host smart-85b4c747-0a99-488d-8333-dd4317308a26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035165457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2035165457
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3992585534
Short name T312
Test name
Test status
Simulation time 19165939754 ps
CPU time 194.23 seconds
Started Aug 07 07:16:04 PM PDT 24
Finished Aug 07 07:19:19 PM PDT 24
Peak memory 248584 kb
Host smart-b97a5da3-0c66-430f-aef7-8d98d48987e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992585534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3992585534
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3274361087
Short name T414
Test name
Test status
Simulation time 1241417463 ps
CPU time 78.82 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:17:24 PM PDT 24
Peak memory 248420 kb
Host smart-504cd6d7-af57-408d-a0b2-6120e90a1c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32743
61087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3274361087
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2510869022
Short name T680
Test name
Test status
Simulation time 463853025 ps
CPU time 28.35 seconds
Started Aug 07 07:16:04 PM PDT 24
Finished Aug 07 07:16:32 PM PDT 24
Peak memory 248028 kb
Host smart-e83667af-a5c2-460b-bb00-31c0f3ed78b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25108
69022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2510869022
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.611621247
Short name T703
Test name
Test status
Simulation time 265714413 ps
CPU time 28.6 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:16:34 PM PDT 24
Peak memory 248448 kb
Host smart-8c27729b-50fa-4fa1-aa67-27ef31778966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61162
1247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.611621247
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.480798857
Short name T395
Test name
Test status
Simulation time 715780259 ps
CPU time 19.32 seconds
Started Aug 07 07:15:55 PM PDT 24
Finished Aug 07 07:16:15 PM PDT 24
Peak memory 256636 kb
Host smart-56ca599e-d2f0-47c8-839d-4ff21c9bad9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48079
8857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.480798857
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.33408328
Short name T95
Test name
Test status
Simulation time 71979738537 ps
CPU time 2201.55 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:52:47 PM PDT 24
Peak memory 289148 kb
Host smart-0d82e0b4-eb0a-4fef-a1c2-5aa40afd2099
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33408328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_hand
ler_stress_all.33408328
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.343540545
Short name T14
Test name
Test status
Simulation time 54651157 ps
CPU time 4.38 seconds
Started Aug 07 07:16:13 PM PDT 24
Finished Aug 07 07:16:18 PM PDT 24
Peak memory 248720 kb
Host smart-57d3f2e9-c826-4c3a-a3d1-9f2fdee85418
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=343540545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.343540545
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2306817728
Short name T592
Test name
Test status
Simulation time 23387109103 ps
CPU time 1561.46 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:42:07 PM PDT 24
Peak memory 273008 kb
Host smart-bbfa3a6b-f3f4-470b-90a7-74018c58da04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306817728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2306817728
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.575790835
Short name T579
Test name
Test status
Simulation time 6287587679 ps
CPU time 52.81 seconds
Started Aug 07 07:16:13 PM PDT 24
Finished Aug 07 07:17:06 PM PDT 24
Peak memory 248524 kb
Host smart-a3d97f6a-b7ee-4e18-9320-03f97e799afd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=575790835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.575790835
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2239612123
Short name T505
Test name
Test status
Simulation time 4084964168 ps
CPU time 71.71 seconds
Started Aug 07 07:16:04 PM PDT 24
Finished Aug 07 07:17:16 PM PDT 24
Peak memory 256672 kb
Host smart-52cd600c-2a0b-4262-9d92-cd92adec3808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22396
12123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2239612123
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3492916837
Short name T700
Test name
Test status
Simulation time 1066133135 ps
CPU time 73.67 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:17:19 PM PDT 24
Peak memory 248520 kb
Host smart-38477b76-fd5d-4fe4-a5c1-80c3bf0d6eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34929
16837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3492916837
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3130735501
Short name T319
Test name
Test status
Simulation time 61398305899 ps
CPU time 1235.41 seconds
Started Aug 07 07:16:14 PM PDT 24
Finished Aug 07 07:36:49 PM PDT 24
Peak memory 282616 kb
Host smart-3f43d8b5-99c1-4635-af1f-af742bc5e394
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130735501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3130735501
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1717947165
Short name T396
Test name
Test status
Simulation time 49402892295 ps
CPU time 2263.92 seconds
Started Aug 07 07:16:14 PM PDT 24
Finished Aug 07 07:53:59 PM PDT 24
Peak memory 273180 kb
Host smart-108b7146-617d-43fa-818e-71e3185d46e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717947165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1717947165
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.222215121
Short name T311
Test name
Test status
Simulation time 18994965975 ps
CPU time 198.82 seconds
Started Aug 07 07:16:15 PM PDT 24
Finished Aug 07 07:19:34 PM PDT 24
Peak memory 254588 kb
Host smart-e80f2525-bfa4-471a-9474-7a98d4e726a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222215121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.222215121
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2563311403
Short name T439
Test name
Test status
Simulation time 1478450353 ps
CPU time 13.63 seconds
Started Aug 07 07:16:13 PM PDT 24
Finished Aug 07 07:16:27 PM PDT 24
Peak memory 248488 kb
Host smart-7ef44e4e-4aae-4cac-a548-af6e2975c93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25633
11403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2563311403
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3028810192
Short name T578
Test name
Test status
Simulation time 1465528262 ps
CPU time 35.12 seconds
Started Aug 07 07:16:03 PM PDT 24
Finished Aug 07 07:16:38 PM PDT 24
Peak memory 256080 kb
Host smart-2839a8a8-d8da-4133-894f-9e54431308ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30288
10192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3028810192
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1767328465
Short name T478
Test name
Test status
Simulation time 112575812 ps
CPU time 13.51 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:16:19 PM PDT 24
Peak memory 255628 kb
Host smart-affed372-9571-4d67-b103-c56342b55a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17673
28465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1767328465
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2136242695
Short name T654
Test name
Test status
Simulation time 737076555 ps
CPU time 20.45 seconds
Started Aug 07 07:16:05 PM PDT 24
Finished Aug 07 07:16:26 PM PDT 24
Peak memory 255628 kb
Host smart-e5f0a538-aab0-447a-8355-d404247162ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21362
42695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2136242695
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2616276389
Short name T270
Test name
Test status
Simulation time 67042942774 ps
CPU time 4218.49 seconds
Started Aug 07 07:16:13 PM PDT 24
Finished Aug 07 08:26:33 PM PDT 24
Peak memory 289240 kb
Host smart-86963aa0-3b8e-4590-9fd7-f0bc1317561b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616276389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2616276389
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2432482017
Short name T36
Test name
Test status
Simulation time 19523217 ps
CPU time 2.82 seconds
Started Aug 07 07:16:15 PM PDT 24
Finished Aug 07 07:16:18 PM PDT 24
Peak memory 248716 kb
Host smart-815c9135-814c-4f38-ba1b-9de1b01061b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2432482017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2432482017
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2640161060
Short name T417
Test name
Test status
Simulation time 103725942132 ps
CPU time 3316.42 seconds
Started Aug 07 07:16:12 PM PDT 24
Finished Aug 07 08:11:29 PM PDT 24
Peak memory 289276 kb
Host smart-c24707c9-6775-4202-877d-0029d715a106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640161060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2640161060
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2093119590
Short name T641
Test name
Test status
Simulation time 79585042 ps
CPU time 6.15 seconds
Started Aug 07 07:16:15 PM PDT 24
Finished Aug 07 07:16:21 PM PDT 24
Peak memory 248448 kb
Host smart-3ebcfcc7-bf86-4252-be2e-a695d722e89d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2093119590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2093119590
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3008438205
Short name T436
Test name
Test status
Simulation time 2642054571 ps
CPU time 134.59 seconds
Started Aug 07 07:16:14 PM PDT 24
Finished Aug 07 07:18:29 PM PDT 24
Peak memory 256164 kb
Host smart-90aad7f6-7f13-4cd4-9837-f5ead4ad8304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30084
38205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3008438205
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3580713432
Short name T442
Test name
Test status
Simulation time 935003511 ps
CPU time 28.05 seconds
Started Aug 07 07:16:16 PM PDT 24
Finished Aug 07 07:16:44 PM PDT 24
Peak memory 256184 kb
Host smart-18fa09a2-fdbf-48ef-8698-8bf702d62009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35807
13432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3580713432
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3952543392
Short name T188
Test name
Test status
Simulation time 142532020091 ps
CPU time 2424.49 seconds
Started Aug 07 07:16:16 PM PDT 24
Finished Aug 07 07:56:41 PM PDT 24
Peak memory 273160 kb
Host smart-273a6c5d-9846-4afb-8f9b-fa76df005c5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952543392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3952543392
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.653872156
Short name T681
Test name
Test status
Simulation time 19384482063 ps
CPU time 365.87 seconds
Started Aug 07 07:16:16 PM PDT 24
Finished Aug 07 07:22:22 PM PDT 24
Peak memory 248528 kb
Host smart-c44afce5-dae8-4f5e-bf48-1b0cb82e4f1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653872156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.653872156
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.79322779
Short name T675
Test name
Test status
Simulation time 1803342213 ps
CPU time 32.94 seconds
Started Aug 07 07:16:16 PM PDT 24
Finished Aug 07 07:16:49 PM PDT 24
Peak memory 248500 kb
Host smart-08bc8abf-3cf3-4bf1-8288-7d0f4db00586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79322
779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.79322779
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.427064162
Short name T105
Test name
Test status
Simulation time 241129506 ps
CPU time 29.57 seconds
Started Aug 07 07:16:14 PM PDT 24
Finished Aug 07 07:16:44 PM PDT 24
Peak memory 248008 kb
Host smart-8f23febf-3887-40e2-8ae5-5dca7b4455e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42706
4162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.427064162
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1576885395
Short name T609
Test name
Test status
Simulation time 277522409 ps
CPU time 16.4 seconds
Started Aug 07 07:16:14 PM PDT 24
Finished Aug 07 07:16:31 PM PDT 24
Peak memory 255260 kb
Host smart-b5cc828e-1ba2-4128-a91b-da140f1588ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15768
85395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1576885395
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1968322863
Short name T40
Test name
Test status
Simulation time 1131486924 ps
CPU time 27.51 seconds
Started Aug 07 07:16:14 PM PDT 24
Finished Aug 07 07:16:42 PM PDT 24
Peak memory 256648 kb
Host smart-064496e1-249a-4646-bc0a-724187fb0807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19683
22863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1968322863
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.4129247813
Short name T71
Test name
Test status
Simulation time 4176455133 ps
CPU time 339.16 seconds
Started Aug 07 07:16:14 PM PDT 24
Finished Aug 07 07:21:54 PM PDT 24
Peak memory 265040 kb
Host smart-6f456cde-9990-4406-8253-034afe7f9326
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129247813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.4129247813
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1309081346
Short name T634
Test name
Test status
Simulation time 345361057878 ps
CPU time 4097.58 seconds
Started Aug 07 07:16:16 PM PDT 24
Finished Aug 07 08:24:35 PM PDT 24
Peak memory 314880 kb
Host smart-025f2c1f-2e8f-4367-86cd-b898c6f2ea65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309081346 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1309081346
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1054433191
Short name T571
Test name
Test status
Simulation time 75979468385 ps
CPU time 1914.12 seconds
Started Aug 07 07:16:24 PM PDT 24
Finished Aug 07 07:48:19 PM PDT 24
Peak memory 289512 kb
Host smart-7c20f5c8-9d23-4a1f-8e67-02a12b71d38b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054433191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1054433191
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3687746814
Short name T573
Test name
Test status
Simulation time 9647864960 ps
CPU time 49.61 seconds
Started Aug 07 07:16:24 PM PDT 24
Finished Aug 07 07:17:14 PM PDT 24
Peak memory 248548 kb
Host smart-2cd6d6cc-b675-4411-90d3-23a06f7d76c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3687746814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3687746814
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3877700698
Short name T428
Test name
Test status
Simulation time 1271601402 ps
CPU time 24.1 seconds
Started Aug 07 07:16:24 PM PDT 24
Finished Aug 07 07:16:48 PM PDT 24
Peak memory 256224 kb
Host smart-684b666a-8f0b-4f2b-a8b8-048166c6295a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38777
00698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3877700698
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1473067895
Short name T687
Test name
Test status
Simulation time 835026271 ps
CPU time 28.72 seconds
Started Aug 07 07:16:25 PM PDT 24
Finished Aug 07 07:16:54 PM PDT 24
Peak memory 248056 kb
Host smart-1990af31-b29d-424a-866a-7ca3746c7a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14730
67895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1473067895
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3089580569
Short name T628
Test name
Test status
Simulation time 36662347477 ps
CPU time 1988.86 seconds
Started Aug 07 07:16:26 PM PDT 24
Finished Aug 07 07:49:36 PM PDT 24
Peak memory 287180 kb
Host smart-b7fb48a3-2748-4639-bb93-8c80a6d4fd2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089580569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3089580569
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.4136416242
Short name T100
Test name
Test status
Simulation time 135254681770 ps
CPU time 2394.78 seconds
Started Aug 07 07:16:24 PM PDT 24
Finished Aug 07 07:56:20 PM PDT 24
Peak memory 288864 kb
Host smart-a64c935e-3f9d-416f-aabb-34f16917ee8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136416242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.4136416242
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3562151083
Short name T3
Test name
Test status
Simulation time 378692350 ps
CPU time 18.45 seconds
Started Aug 07 07:16:16 PM PDT 24
Finished Aug 07 07:16:35 PM PDT 24
Peak memory 255968 kb
Host smart-52dcd6b3-8ba6-412d-a793-27b08b40a225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35621
51083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3562151083
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1385225085
Short name T217
Test name
Test status
Simulation time 1096638682 ps
CPU time 57.7 seconds
Started Aug 07 07:16:25 PM PDT 24
Finished Aug 07 07:17:23 PM PDT 24
Peak memory 248060 kb
Host smart-b962a4dd-6499-44c8-b9c0-9d73283f53ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13852
25085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1385225085
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1071889574
Short name T276
Test name
Test status
Simulation time 3365501294 ps
CPU time 62.77 seconds
Started Aug 07 07:16:25 PM PDT 24
Finished Aug 07 07:17:28 PM PDT 24
Peak memory 256192 kb
Host smart-f57d22bb-cd09-4430-95b5-83b56ee1037d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10718
89574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1071889574
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1390693518
Short name T446
Test name
Test status
Simulation time 1265395030 ps
CPU time 35.74 seconds
Started Aug 07 07:16:14 PM PDT 24
Finished Aug 07 07:16:50 PM PDT 24
Peak memory 255688 kb
Host smart-b6acc6f2-cec5-45cb-92ef-23a73a9c970a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13906
93518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1390693518
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.998026585
Short name T542
Test name
Test status
Simulation time 2554402895 ps
CPU time 162.19 seconds
Started Aug 07 07:16:27 PM PDT 24
Finished Aug 07 07:19:09 PM PDT 24
Peak memory 251252 kb
Host smart-4e840d1d-6f22-45a2-b3c2-a5cdc774da83
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998026585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.998026585
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3011549669
Short name T196
Test name
Test status
Simulation time 42600669 ps
CPU time 4.2 seconds
Started Aug 07 07:16:36 PM PDT 24
Finished Aug 07 07:16:40 PM PDT 24
Peak memory 248720 kb
Host smart-56ff3ec9-ebe2-4741-8828-d0e406c3a708
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3011549669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3011549669
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3363238079
Short name T574
Test name
Test status
Simulation time 24329531746 ps
CPU time 1449.24 seconds
Started Aug 07 07:16:25 PM PDT 24
Finished Aug 07 07:40:35 PM PDT 24
Peak memory 288816 kb
Host smart-6a282f1b-eb41-4ae2-82d2-658d39d61b14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363238079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3363238079
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1064882902
Short name T190
Test name
Test status
Simulation time 495678506 ps
CPU time 8.35 seconds
Started Aug 07 07:16:41 PM PDT 24
Finished Aug 07 07:16:50 PM PDT 24
Peak memory 248480 kb
Host smart-2b00a2d6-20b6-4036-92df-36fd20df7578
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1064882902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1064882902
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1178704560
Short name T249
Test name
Test status
Simulation time 11042228459 ps
CPU time 116.44 seconds
Started Aug 07 07:16:31 PM PDT 24
Finished Aug 07 07:18:27 PM PDT 24
Peak memory 256792 kb
Host smart-e925879b-1231-4c38-90bf-807d35a11690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11787
04560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1178704560
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3291991564
Short name T541
Test name
Test status
Simulation time 584519859 ps
CPU time 25.2 seconds
Started Aug 07 07:16:26 PM PDT 24
Finished Aug 07 07:16:51 PM PDT 24
Peak memory 255856 kb
Host smart-d0cc3092-bd3f-4478-8f70-4da34c8de141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32919
91564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3291991564
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.832854320
Short name T676
Test name
Test status
Simulation time 30026783373 ps
CPU time 1821.98 seconds
Started Aug 07 07:16:36 PM PDT 24
Finished Aug 07 07:46:58 PM PDT 24
Peak memory 273216 kb
Host smart-495daeae-1a91-41e3-a8bc-f0bf330b9c8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832854320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.832854320
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3297037547
Short name T523
Test name
Test status
Simulation time 36790967358 ps
CPU time 783.53 seconds
Started Aug 07 07:16:35 PM PDT 24
Finished Aug 07 07:29:39 PM PDT 24
Peak memory 272900 kb
Host smart-cae3d50e-11fe-4b10-89d1-99b9b8883bb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297037547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3297037547
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1600959344
Short name T480
Test name
Test status
Simulation time 2240784778 ps
CPU time 95.85 seconds
Started Aug 07 07:16:37 PM PDT 24
Finished Aug 07 07:18:13 PM PDT 24
Peak memory 253120 kb
Host smart-a2b0fd24-0b85-4062-a2c4-05d4ce6b3711
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600959344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1600959344
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1256421996
Short name T603
Test name
Test status
Simulation time 31774775 ps
CPU time 4.72 seconds
Started Aug 07 07:16:25 PM PDT 24
Finished Aug 07 07:16:30 PM PDT 24
Peak memory 251140 kb
Host smart-33a431f8-678a-4bc7-bdac-7adbbaa3466b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12564
21996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1256421996
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2434198279
Short name T445
Test name
Test status
Simulation time 1311367745 ps
CPU time 25.45 seconds
Started Aug 07 07:16:26 PM PDT 24
Finished Aug 07 07:16:51 PM PDT 24
Peak memory 255484 kb
Host smart-55c6f0fc-7347-4b63-82f8-08bf68c81059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24341
98279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2434198279
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3679268325
Short name T626
Test name
Test status
Simulation time 378435913 ps
CPU time 13.91 seconds
Started Aug 07 07:16:25 PM PDT 24
Finished Aug 07 07:16:39 PM PDT 24
Peak memory 248016 kb
Host smart-42555500-a53a-419a-924a-48d069a5e1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36792
68325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3679268325
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4119856279
Short name T38
Test name
Test status
Simulation time 679712081 ps
CPU time 39.66 seconds
Started Aug 07 07:16:24 PM PDT 24
Finished Aug 07 07:17:04 PM PDT 24
Peak memory 255724 kb
Host smart-3ae9dee4-6291-4b12-bf90-bcd2360eeb56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41198
56279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4119856279
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.511300657
Short name T608
Test name
Test status
Simulation time 13418379478 ps
CPU time 1311.41 seconds
Started Aug 07 07:16:35 PM PDT 24
Finished Aug 07 07:38:27 PM PDT 24
Peak memory 285988 kb
Host smart-538620cd-54a4-4f19-9c04-0834d9a7bbc8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511300657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.511300657
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.920454416
Short name T93
Test name
Test status
Simulation time 64470173420 ps
CPU time 6789.17 seconds
Started Aug 07 07:16:42 PM PDT 24
Finished Aug 07 09:09:52 PM PDT 24
Peak memory 355040 kb
Host smart-04ab6cd7-9662-4f95-9941-e97b8543763c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920454416 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.920454416
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2310094306
Short name T198
Test name
Test status
Simulation time 14891864 ps
CPU time 2.83 seconds
Started Aug 07 07:16:43 PM PDT 24
Finished Aug 07 07:16:46 PM PDT 24
Peak memory 248652 kb
Host smart-33bcb4e3-ea82-4824-8714-c33e594fa95b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2310094306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2310094306
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1608497712
Short name T449
Test name
Test status
Simulation time 53228940378 ps
CPU time 1353.48 seconds
Started Aug 07 07:16:33 PM PDT 24
Finished Aug 07 07:39:07 PM PDT 24
Peak memory 281380 kb
Host smart-3ffbef33-86c6-488c-bba5-8c2fc9d04ea0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608497712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1608497712
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.695328723
Short name T669
Test name
Test status
Simulation time 147816118 ps
CPU time 9.14 seconds
Started Aug 07 07:16:44 PM PDT 24
Finished Aug 07 07:16:53 PM PDT 24
Peak memory 248396 kb
Host smart-aac8c4ca-a4d9-4654-8661-95fab1ae28ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=695328723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.695328723
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3773535486
Short name T503
Test name
Test status
Simulation time 7741534628 ps
CPU time 144.02 seconds
Started Aug 07 07:16:35 PM PDT 24
Finished Aug 07 07:18:59 PM PDT 24
Peak memory 256792 kb
Host smart-7458da90-78a1-46a7-a130-38868bf59b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37735
35486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3773535486
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3972778534
Short name T68
Test name
Test status
Simulation time 76307700 ps
CPU time 8.85 seconds
Started Aug 07 07:16:34 PM PDT 24
Finished Aug 07 07:16:43 PM PDT 24
Peak memory 248416 kb
Host smart-fade68a7-7f68-4c93-ad30-d3c50b031791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39727
78534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3972778534
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.492243406
Short name T418
Test name
Test status
Simulation time 22107673762 ps
CPU time 1324.07 seconds
Started Aug 07 07:16:44 PM PDT 24
Finished Aug 07 07:38:49 PM PDT 24
Peak memory 264988 kb
Host smart-1e9da8f3-b900-414c-98db-deb0fc95b47c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492243406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.492243406
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3367802647
Short name T510
Test name
Test status
Simulation time 26892930710 ps
CPU time 279.3 seconds
Started Aug 07 07:16:41 PM PDT 24
Finished Aug 07 07:21:21 PM PDT 24
Peak memory 248604 kb
Host smart-ec87239b-c342-4dc3-b4ee-f5a12747c225
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367802647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3367802647
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1105776792
Short name T699
Test name
Test status
Simulation time 257316017 ps
CPU time 11.81 seconds
Started Aug 07 07:16:33 PM PDT 24
Finished Aug 07 07:16:45 PM PDT 24
Peak memory 248428 kb
Host smart-c640180a-1bd8-435f-8bc2-a437d56bce4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11057
76792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1105776792
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.45724549
Short name T635
Test name
Test status
Simulation time 9241373097 ps
CPU time 61.13 seconds
Started Aug 07 07:16:36 PM PDT 24
Finished Aug 07 07:17:37 PM PDT 24
Peak memory 256624 kb
Host smart-dabad68b-b3e5-4696-ac9c-6087319331a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45724
549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.45724549
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.517784445
Short name T419
Test name
Test status
Simulation time 1099634172 ps
CPU time 33.75 seconds
Started Aug 07 07:16:32 PM PDT 24
Finished Aug 07 07:17:06 PM PDT 24
Peak memory 248828 kb
Host smart-710f8801-d701-41a4-a051-5b0a0a6d9d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51778
4445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.517784445
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.493415158
Short name T630
Test name
Test status
Simulation time 1368907638 ps
CPU time 39.63 seconds
Started Aug 07 07:16:42 PM PDT 24
Finished Aug 07 07:17:21 PM PDT 24
Peak memory 255780 kb
Host smart-b79e2ce5-670e-49fd-9d4d-129b6adab59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49341
5158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.493415158
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1431207382
Short name T254
Test name
Test status
Simulation time 12037413120 ps
CPU time 687.28 seconds
Started Aug 07 07:16:43 PM PDT 24
Finished Aug 07 07:28:10 PM PDT 24
Peak memory 268768 kb
Host smart-ef4767fa-badc-473d-9694-b78f0231d590
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431207382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1431207382
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.4282868545
Short name T103
Test name
Test status
Simulation time 44352554608 ps
CPU time 876.2 seconds
Started Aug 07 07:16:46 PM PDT 24
Finished Aug 07 07:31:22 PM PDT 24
Peak memory 273032 kb
Host smart-44848b05-c70c-4513-a75d-dd86d97a3816
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282868545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4282868545
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3146560837
Short name T529
Test name
Test status
Simulation time 726197862 ps
CPU time 10.92 seconds
Started Aug 07 07:16:53 PM PDT 24
Finished Aug 07 07:17:04 PM PDT 24
Peak memory 248384 kb
Host smart-15aa3e8c-1832-4c09-8432-7113d3d95802
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3146560837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3146560837
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1233985647
Short name T388
Test name
Test status
Simulation time 1911974972 ps
CPU time 71.26 seconds
Started Aug 07 07:16:43 PM PDT 24
Finished Aug 07 07:17:54 PM PDT 24
Peak memory 256656 kb
Host smart-329bdd87-fa73-4f30-b2dc-4abd03aeff52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12339
85647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1233985647
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1902124656
Short name T447
Test name
Test status
Simulation time 2531924624 ps
CPU time 68.58 seconds
Started Aug 07 07:16:44 PM PDT 24
Finished Aug 07 07:17:52 PM PDT 24
Peak memory 248568 kb
Host smart-3f17a48f-275a-4cfc-a049-a5390f039e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19021
24656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1902124656
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2044169745
Short name T597
Test name
Test status
Simulation time 52523779003 ps
CPU time 3452.51 seconds
Started Aug 07 07:16:52 PM PDT 24
Finished Aug 07 08:14:26 PM PDT 24
Peak memory 288964 kb
Host smart-98091a22-2bc9-4f53-9daa-a79924193ebc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044169745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2044169745
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3202517143
Short name T537
Test name
Test status
Simulation time 230094220295 ps
CPU time 472.17 seconds
Started Aug 07 07:16:45 PM PDT 24
Finished Aug 07 07:24:37 PM PDT 24
Peak memory 248584 kb
Host smart-f5696f4e-3cb2-4bb4-bc89-89d617885ae1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202517143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3202517143
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2794486799
Short name T433
Test name
Test status
Simulation time 321578363 ps
CPU time 17.93 seconds
Started Aug 07 07:16:44 PM PDT 24
Finished Aug 07 07:17:02 PM PDT 24
Peak memory 248536 kb
Host smart-ed6db43f-6ada-4516-a5d3-985d6f7aae5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27944
86799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2794486799
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3691353180
Short name T58
Test name
Test status
Simulation time 869853507 ps
CPU time 51.15 seconds
Started Aug 07 07:16:45 PM PDT 24
Finished Aug 07 07:17:36 PM PDT 24
Peak memory 256012 kb
Host smart-47561d13-2680-4464-b37d-bc787c591282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36913
53180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3691353180
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1731860215
Short name T567
Test name
Test status
Simulation time 62629590 ps
CPU time 7.45 seconds
Started Aug 07 07:16:44 PM PDT 24
Finished Aug 07 07:16:52 PM PDT 24
Peak memory 248052 kb
Host smart-b36e8f72-6333-4f49-b04e-9d8eeeef92ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17318
60215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1731860215
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2369747877
Short name T474
Test name
Test status
Simulation time 979879214 ps
CPU time 61.56 seconds
Started Aug 07 07:16:43 PM PDT 24
Finished Aug 07 07:17:45 PM PDT 24
Peak memory 255836 kb
Host smart-9cb7be3a-c746-4a27-866f-65a832b23cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23697
47877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2369747877
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1191595426
Short name T172
Test name
Test status
Simulation time 153263571186 ps
CPU time 5555.78 seconds
Started Aug 07 07:16:57 PM PDT 24
Finished Aug 07 08:49:34 PM PDT 24
Peak memory 306020 kb
Host smart-7915158d-6df9-41c8-9d0d-fdbef426bd62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191595426 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1191595426
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2191002506
Short name T207
Test name
Test status
Simulation time 68532286 ps
CPU time 3.47 seconds
Started Aug 07 07:15:13 PM PDT 24
Finished Aug 07 07:15:17 PM PDT 24
Peak memory 248736 kb
Host smart-60a457d5-fd4b-4064-92d9-35a7486cd1ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2191002506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2191002506
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.4142467625
Short name T629
Test name
Test status
Simulation time 35500156193 ps
CPU time 1109.22 seconds
Started Aug 07 07:15:09 PM PDT 24
Finished Aug 07 07:33:39 PM PDT 24
Peak memory 264984 kb
Host smart-b95a36a5-7447-4286-9a09-34d5f91ef4b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142467625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.4142467625
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3441637871
Short name T548
Test name
Test status
Simulation time 330193460 ps
CPU time 18.16 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 07:15:24 PM PDT 24
Peak memory 248456 kb
Host smart-5baa30b5-f727-4420-bc6b-6066c9767bac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3441637871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3441637871
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1703256404
Short name T697
Test name
Test status
Simulation time 1076391687 ps
CPU time 99.52 seconds
Started Aug 07 07:15:09 PM PDT 24
Finished Aug 07 07:16:49 PM PDT 24
Peak memory 256208 kb
Host smart-278308cd-7d97-4c8a-8226-46b62a57a367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17032
56404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1703256404
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.201388646
Short name T74
Test name
Test status
Simulation time 885294807 ps
CPU time 55.16 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 07:16:01 PM PDT 24
Peak memory 248812 kb
Host smart-2bdd8727-f551-4ce5-920d-fdbe15b4da3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20138
8646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.201388646
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3562569677
Short name T672
Test name
Test status
Simulation time 148197823512 ps
CPU time 1296.66 seconds
Started Aug 07 07:15:08 PM PDT 24
Finished Aug 07 07:36:45 PM PDT 24
Peak memory 287824 kb
Host smart-a0effe6c-2874-4c85-8a3b-10747973a681
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562569677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3562569677
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1475678274
Short name T692
Test name
Test status
Simulation time 84282115441 ps
CPU time 1359.94 seconds
Started Aug 07 07:15:07 PM PDT 24
Finished Aug 07 07:37:47 PM PDT 24
Peak memory 264928 kb
Host smart-f1f04600-d1c0-4fa4-b697-0022943c8c4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475678274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1475678274
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4181679428
Short name T598
Test name
Test status
Simulation time 26058479378 ps
CPU time 266.18 seconds
Started Aug 07 07:15:05 PM PDT 24
Finished Aug 07 07:19:32 PM PDT 24
Peak memory 248596 kb
Host smart-08ced0b8-3a7b-4a15-bcb6-e597f6f3230e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181679428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4181679428
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3291693913
Short name T601
Test name
Test status
Simulation time 1264783309 ps
CPU time 26.18 seconds
Started Aug 07 07:14:52 PM PDT 24
Finished Aug 07 07:15:18 PM PDT 24
Peak memory 248512 kb
Host smart-ca23fd13-9b42-4b23-94a7-3b1337f36e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32916
93913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3291693913
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3270641810
Short name T652
Test name
Test status
Simulation time 125819917 ps
CPU time 7.18 seconds
Started Aug 07 07:14:54 PM PDT 24
Finished Aug 07 07:15:01 PM PDT 24
Peak memory 247800 kb
Host smart-39b34f0c-cae4-4982-8587-6f2c2f57112d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32706
41810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3270641810
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3170496435
Short name T479
Test name
Test status
Simulation time 197367584 ps
CPU time 19.92 seconds
Started Aug 07 07:14:53 PM PDT 24
Finished Aug 07 07:15:13 PM PDT 24
Peak memory 256644 kb
Host smart-fca2dea7-01b1-439f-a347-69c3eccf2496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31704
96435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3170496435
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3884116107
Short name T500
Test name
Test status
Simulation time 40463469184 ps
CPU time 2434.63 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 07:55:41 PM PDT 24
Peak memory 289544 kb
Host smart-5f88b26f-b8a3-4acd-840c-0e88df5c0f6a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884116107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3884116107
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2197501396
Short name T535
Test name
Test status
Simulation time 64979757824 ps
CPU time 5873.21 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 08:53:00 PM PDT 24
Peak memory 338516 kb
Host smart-520cc1f1-00f2-4c46-98a0-a4c22f244e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197501396 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2197501396
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2805125654
Short name T415
Test name
Test status
Simulation time 505997296 ps
CPU time 26.38 seconds
Started Aug 07 07:16:57 PM PDT 24
Finished Aug 07 07:17:24 PM PDT 24
Peak memory 256064 kb
Host smart-9bd552ea-0e9c-4d3e-b84a-7584ccf8b0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28051
25654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2805125654
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3490072181
Short name T277
Test name
Test status
Simulation time 1631594668 ps
CPU time 25.5 seconds
Started Aug 07 07:16:57 PM PDT 24
Finished Aug 07 07:17:23 PM PDT 24
Peak memory 255340 kb
Host smart-d629aa06-ee1c-4b92-a6a8-103d9f52debe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34900
72181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3490072181
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1009320227
Short name T456
Test name
Test status
Simulation time 28694235084 ps
CPU time 710.36 seconds
Started Aug 07 07:16:55 PM PDT 24
Finished Aug 07 07:28:46 PM PDT 24
Peak memory 273100 kb
Host smart-78573c50-481c-4899-afa5-f05c8f7cc1de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009320227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1009320227
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1031078511
Short name T302
Test name
Test status
Simulation time 8564011228 ps
CPU time 81.84 seconds
Started Aug 07 07:16:54 PM PDT 24
Finished Aug 07 07:18:16 PM PDT 24
Peak memory 247468 kb
Host smart-b52e5ca2-bb8c-449b-ac69-9dbc0e458159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031078511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1031078511
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3760630541
Short name T611
Test name
Test status
Simulation time 500126336 ps
CPU time 28.64 seconds
Started Aug 07 07:16:52 PM PDT 24
Finished Aug 07 07:17:21 PM PDT 24
Peak memory 248436 kb
Host smart-7ee19831-2f68-41eb-ab0f-b36c4e11eb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37606
30541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3760630541
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.4064583203
Short name T451
Test name
Test status
Simulation time 1412085801 ps
CPU time 47.78 seconds
Started Aug 07 07:16:54 PM PDT 24
Finished Aug 07 07:17:42 PM PDT 24
Peak memory 248496 kb
Host smart-65dd334e-66bf-4c64-8796-63c11059cfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40645
83203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.4064583203
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.281162990
Short name T432
Test name
Test status
Simulation time 276695524 ps
CPU time 18.04 seconds
Started Aug 07 07:16:54 PM PDT 24
Finished Aug 07 07:17:12 PM PDT 24
Peak memory 247824 kb
Host smart-785af781-8925-4885-b520-a3dce807593f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28116
2990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.281162990
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3989295774
Short name T364
Test name
Test status
Simulation time 1121162309 ps
CPU time 37.54 seconds
Started Aug 07 07:16:54 PM PDT 24
Finished Aug 07 07:17:32 PM PDT 24
Peak memory 255968 kb
Host smart-599a5b89-b378-47af-9c47-5d3c38bebdff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39892
95774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3989295774
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.4112269757
Short name T183
Test name
Test status
Simulation time 197310463696 ps
CPU time 9257.13 seconds
Started Aug 07 07:17:04 PM PDT 24
Finished Aug 07 09:51:22 PM PDT 24
Peak memory 362828 kb
Host smart-b1bb4597-c801-495a-b245-17093d478429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112269757 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.4112269757
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3808647937
Short name T372
Test name
Test status
Simulation time 113837943294 ps
CPU time 2106.71 seconds
Started Aug 07 07:17:04 PM PDT 24
Finished Aug 07 07:52:11 PM PDT 24
Peak memory 281288 kb
Host smart-fb04eb8c-14d0-4f84-9713-6d55c1166b7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808647937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3808647937
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.346145314
Short name T509
Test name
Test status
Simulation time 21393663842 ps
CPU time 330.74 seconds
Started Aug 07 07:17:06 PM PDT 24
Finished Aug 07 07:22:37 PM PDT 24
Peak memory 256340 kb
Host smart-185a8a40-875e-4cb2-b4e0-254a9f217a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34614
5314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.346145314
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2520730443
Short name T582
Test name
Test status
Simulation time 682113335 ps
CPU time 13.91 seconds
Started Aug 07 07:17:05 PM PDT 24
Finished Aug 07 07:17:19 PM PDT 24
Peak memory 248040 kb
Host smart-14ae2e9e-e186-4e6a-9d00-aec3fe36bb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25207
30443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2520730443
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1698486847
Short name T435
Test name
Test status
Simulation time 70834586681 ps
CPU time 2167.87 seconds
Started Aug 07 07:17:03 PM PDT 24
Finished Aug 07 07:53:11 PM PDT 24
Peak memory 284772 kb
Host smart-7c82878b-e4e7-40d8-97ba-910b791f7d67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698486847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1698486847
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2955188301
Short name T317
Test name
Test status
Simulation time 8877698007 ps
CPU time 371.95 seconds
Started Aug 07 07:17:06 PM PDT 24
Finished Aug 07 07:23:18 PM PDT 24
Peak memory 248556 kb
Host smart-58349bc8-e2de-4adf-84e7-f7e26bf2ea5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955188301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2955188301
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1286997727
Short name T213
Test name
Test status
Simulation time 6285714415 ps
CPU time 29.94 seconds
Started Aug 07 07:17:04 PM PDT 24
Finished Aug 07 07:17:34 PM PDT 24
Peak memory 256776 kb
Host smart-2061cf41-7bcf-4d4d-a525-73e3f6fe3852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12869
97727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1286997727
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3162578015
Short name T94
Test name
Test status
Simulation time 770833781 ps
CPU time 56.81 seconds
Started Aug 07 07:17:05 PM PDT 24
Finished Aug 07 07:18:02 PM PDT 24
Peak memory 248472 kb
Host smart-f6338966-27bb-4ce6-8c7e-197957ecf83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31625
78015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3162578015
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1699270127
Short name T683
Test name
Test status
Simulation time 228475614 ps
CPU time 20.44 seconds
Started Aug 07 07:17:02 PM PDT 24
Finished Aug 07 07:17:23 PM PDT 24
Peak memory 248436 kb
Host smart-93527a18-a795-4e5a-acf2-b78101c1cb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16992
70127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1699270127
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2582655697
Short name T97
Test name
Test status
Simulation time 26599408287 ps
CPU time 1280.82 seconds
Started Aug 07 07:17:05 PM PDT 24
Finished Aug 07 07:38:26 PM PDT 24
Peak memory 283816 kb
Host smart-47dc9d36-a180-47b6-a5dd-3d4d8a0d609a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582655697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2582655697
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.307427966
Short name T79
Test name
Test status
Simulation time 237782831435 ps
CPU time 4746.07 seconds
Started Aug 07 07:17:02 PM PDT 24
Finished Aug 07 08:36:08 PM PDT 24
Peak memory 322044 kb
Host smart-6fedc086-7bf2-4937-8cd0-ed8807fd68a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307427966 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.307427966
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1395716655
Short name T557
Test name
Test status
Simulation time 50244127010 ps
CPU time 3172.85 seconds
Started Aug 07 07:17:15 PM PDT 24
Finished Aug 07 08:10:09 PM PDT 24
Peak memory 287636 kb
Host smart-63763b95-7828-4477-b913-46aff97af6ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395716655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1395716655
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.914015115
Short name T585
Test name
Test status
Simulation time 10419801963 ps
CPU time 304 seconds
Started Aug 07 07:17:15 PM PDT 24
Finished Aug 07 07:22:19 PM PDT 24
Peak memory 256812 kb
Host smart-93323682-b07a-42fc-9fad-1e315ef6d884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91401
5115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.914015115
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.113567985
Short name T67
Test name
Test status
Simulation time 140044304 ps
CPU time 17.28 seconds
Started Aug 07 07:17:15 PM PDT 24
Finished Aug 07 07:17:32 PM PDT 24
Peak memory 256560 kb
Host smart-f92c31ef-5cb3-4577-8470-f5eaeb950d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11356
7985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.113567985
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1011555259
Short name T337
Test name
Test status
Simulation time 15109736338 ps
CPU time 1328.17 seconds
Started Aug 07 07:17:16 PM PDT 24
Finished Aug 07 07:39:24 PM PDT 24
Peak memory 289016 kb
Host smart-9f89d6d9-f115-478a-bacb-1b8a8af0a120
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011555259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1011555259
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1518680064
Short name T462
Test name
Test status
Simulation time 415074817935 ps
CPU time 1408.29 seconds
Started Aug 07 07:17:17 PM PDT 24
Finished Aug 07 07:40:45 PM PDT 24
Peak memory 273124 kb
Host smart-8e4bbaf2-1506-44dd-9300-f8aa323cc681
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518680064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1518680064
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.723680348
Short name T304
Test name
Test status
Simulation time 4518638045 ps
CPU time 154.59 seconds
Started Aug 07 07:17:18 PM PDT 24
Finished Aug 07 07:19:53 PM PDT 24
Peak memory 255896 kb
Host smart-3654eeb2-7a39-465c-be5f-e688d8a0f99f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723680348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.723680348
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3309311921
Short name T460
Test name
Test status
Simulation time 3612209038 ps
CPU time 60.89 seconds
Started Aug 07 07:17:04 PM PDT 24
Finished Aug 07 07:18:05 PM PDT 24
Peak memory 256356 kb
Host smart-d90c6551-8e51-4e69-933a-a6b5d6582758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33093
11921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3309311921
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2827337795
Short name T495
Test name
Test status
Simulation time 2481143990 ps
CPU time 18.58 seconds
Started Aug 07 07:17:03 PM PDT 24
Finished Aug 07 07:17:21 PM PDT 24
Peak memory 256372 kb
Host smart-11fe5eb1-46ae-4d6d-9765-e21e3f81a96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28273
37795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2827337795
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4243645407
Short name T670
Test name
Test status
Simulation time 537633979 ps
CPU time 38.39 seconds
Started Aug 07 07:17:17 PM PDT 24
Finished Aug 07 07:17:56 PM PDT 24
Peak memory 249540 kb
Host smart-7d643c32-5445-4f26-b5be-4bd319748030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42436
45407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4243645407
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3793472273
Short name T358
Test name
Test status
Simulation time 759194827 ps
CPU time 22.59 seconds
Started Aug 07 07:17:01 PM PDT 24
Finished Aug 07 07:17:24 PM PDT 24
Peak memory 248688 kb
Host smart-7b4abaed-8c52-4d58-9e9b-5e1126094717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37934
72273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3793472273
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.40649175
Short name T75
Test name
Test status
Simulation time 148814170350 ps
CPU time 2386.67 seconds
Started Aug 07 07:17:16 PM PDT 24
Finished Aug 07 07:57:03 PM PDT 24
Peak memory 289292 kb
Host smart-bdc9fe9d-fb56-4dc8-b55e-69454fae5752
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40649175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_hand
ler_stress_all.40649175
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1491808043
Short name T645
Test name
Test status
Simulation time 8386077017 ps
CPU time 622.26 seconds
Started Aug 07 07:17:17 PM PDT 24
Finished Aug 07 07:27:40 PM PDT 24
Peak memory 266008 kb
Host smart-ded71f77-d706-4c90-ac53-0014cb73a752
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491808043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1491808043
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1634809934
Short name T650
Test name
Test status
Simulation time 3839598529 ps
CPU time 105.78 seconds
Started Aug 07 07:17:16 PM PDT 24
Finished Aug 07 07:19:02 PM PDT 24
Peak memory 256796 kb
Host smart-a8da19bb-d56a-4945-847f-73fe401b5ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16348
09934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1634809934
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1467721177
Short name T696
Test name
Test status
Simulation time 1068806206 ps
CPU time 18.72 seconds
Started Aug 07 07:17:18 PM PDT 24
Finished Aug 07 07:17:37 PM PDT 24
Peak memory 247944 kb
Host smart-4df1daf7-1960-49a6-8b45-b7494b83f070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14677
21177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1467721177
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1508937928
Short name T583
Test name
Test status
Simulation time 45335988393 ps
CPU time 1483.48 seconds
Started Aug 07 07:17:25 PM PDT 24
Finished Aug 07 07:42:09 PM PDT 24
Peak memory 273008 kb
Host smart-34cb915f-704f-439a-bb7f-bd1f8241b35c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508937928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1508937928
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3329830074
Short name T558
Test name
Test status
Simulation time 27018398461 ps
CPU time 1701.1 seconds
Started Aug 07 07:17:24 PM PDT 24
Finished Aug 07 07:45:46 PM PDT 24
Peak memory 272972 kb
Host smart-aeb4760b-a077-4aa2-a8e7-e6344f2655ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329830074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3329830074
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1785015570
Short name T305
Test name
Test status
Simulation time 2650099957 ps
CPU time 115.23 seconds
Started Aug 07 07:17:25 PM PDT 24
Finished Aug 07 07:19:21 PM PDT 24
Peak memory 248624 kb
Host smart-e07019e7-01ff-4145-a4cc-c20463df9941
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785015570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1785015570
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.534149718
Short name T584
Test name
Test status
Simulation time 206982635 ps
CPU time 4.54 seconds
Started Aug 07 07:17:15 PM PDT 24
Finished Aug 07 07:17:19 PM PDT 24
Peak memory 248456 kb
Host smart-b0a7804b-ab9a-44e4-88e1-344f7add83ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53414
9718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.534149718
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2974441398
Short name T461
Test name
Test status
Simulation time 1432251460 ps
CPU time 25.44 seconds
Started Aug 07 07:17:16 PM PDT 24
Finished Aug 07 07:17:41 PM PDT 24
Peak memory 248040 kb
Host smart-f6b8c8ae-eb74-4d27-9d7e-1c67b7c70180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29744
41398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2974441398
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1530155769
Short name T408
Test name
Test status
Simulation time 263888904 ps
CPU time 7.36 seconds
Started Aug 07 07:17:16 PM PDT 24
Finished Aug 07 07:17:23 PM PDT 24
Peak memory 252548 kb
Host smart-71ad02fb-628c-4603-b992-514fbf3043f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15301
55769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1530155769
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3080077257
Short name T667
Test name
Test status
Simulation time 49976021687 ps
CPU time 1744.4 seconds
Started Aug 07 07:17:26 PM PDT 24
Finished Aug 07 07:46:31 PM PDT 24
Peak memory 289496 kb
Host smart-a324a91f-c8d5-4384-893a-4fccdec44cbe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080077257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3080077257
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1833465524
Short name T87
Test name
Test status
Simulation time 844442897176 ps
CPU time 2717.85 seconds
Started Aug 07 07:17:25 PM PDT 24
Finished Aug 07 08:02:43 PM PDT 24
Peak memory 288368 kb
Host smart-9437da9c-c56b-4c3f-96f5-39068a6e44a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833465524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1833465524
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.677342567
Short name T594
Test name
Test status
Simulation time 934783894 ps
CPU time 81.77 seconds
Started Aug 07 07:17:26 PM PDT 24
Finished Aug 07 07:18:47 PM PDT 24
Peak memory 255944 kb
Host smart-c0edfec6-2da4-4d91-a13a-6561ad189c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67734
2567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.677342567
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.903447998
Short name T538
Test name
Test status
Simulation time 2315983621 ps
CPU time 39.67 seconds
Started Aug 07 07:17:25 PM PDT 24
Finished Aug 07 07:18:05 PM PDT 24
Peak memory 256204 kb
Host smart-85f43399-bcdf-4253-8ae7-32836104a74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90344
7998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.903447998
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2452708406
Short name T299
Test name
Test status
Simulation time 27710368803 ps
CPU time 1767.42 seconds
Started Aug 07 07:17:26 PM PDT 24
Finished Aug 07 07:46:54 PM PDT 24
Peak memory 273096 kb
Host smart-b1f73a11-a919-47bc-a8f7-6163de708a9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452708406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2452708406
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3996954673
Short name T382
Test name
Test status
Simulation time 8350271463 ps
CPU time 814.47 seconds
Started Aug 07 07:17:25 PM PDT 24
Finished Aug 07 07:30:59 PM PDT 24
Peak memory 288528 kb
Host smart-b27e5da5-fe55-4178-b762-18557aef49b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996954673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3996954673
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3687239446
Short name T216
Test name
Test status
Simulation time 13808067031 ps
CPU time 285.06 seconds
Started Aug 07 07:17:26 PM PDT 24
Finished Aug 07 07:22:12 PM PDT 24
Peak memory 248512 kb
Host smart-5c461d5a-23d2-4c2f-ab10-f8624dee282f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687239446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3687239446
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.4076455154
Short name T516
Test name
Test status
Simulation time 877553141 ps
CPU time 46.98 seconds
Started Aug 07 07:17:25 PM PDT 24
Finished Aug 07 07:18:13 PM PDT 24
Peak memory 255972 kb
Host smart-0efed83d-097a-46dc-9e2c-374c2bd24653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40764
55154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4076455154
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2918127666
Short name T512
Test name
Test status
Simulation time 1461057777 ps
CPU time 37.2 seconds
Started Aug 07 07:17:26 PM PDT 24
Finished Aug 07 07:18:03 PM PDT 24
Peak memory 255712 kb
Host smart-07f29213-bddc-4410-91c4-42888c34ed07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29181
27666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2918127666
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3031160200
Short name T289
Test name
Test status
Simulation time 2275107764 ps
CPU time 37.01 seconds
Started Aug 07 07:17:24 PM PDT 24
Finished Aug 07 07:18:02 PM PDT 24
Peak memory 248540 kb
Host smart-e1a7299e-77de-483c-97e0-f2ae776a7f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30311
60200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3031160200
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.424942932
Short name T425
Test name
Test status
Simulation time 3327185690 ps
CPU time 47.34 seconds
Started Aug 07 07:17:26 PM PDT 24
Finished Aug 07 07:18:13 PM PDT 24
Peak memory 256784 kb
Host smart-45b053bf-1288-4a0d-b60a-2bf4d98253b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42494
2932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.424942932
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3465903853
Short name T99
Test name
Test status
Simulation time 42402762640 ps
CPU time 888.93 seconds
Started Aug 07 07:17:38 PM PDT 24
Finished Aug 07 07:32:27 PM PDT 24
Peak memory 271120 kb
Host smart-79c2ae36-9cb4-4172-912c-6d6384e07ab0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465903853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3465903853
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3323687738
Short name T422
Test name
Test status
Simulation time 852698413 ps
CPU time 70.56 seconds
Started Aug 07 07:17:36 PM PDT 24
Finished Aug 07 07:18:47 PM PDT 24
Peak memory 255820 kb
Host smart-f1a71a90-5f49-4434-bf55-ad09d50727f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33236
87738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3323687738
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.863731880
Short name T413
Test name
Test status
Simulation time 575290595 ps
CPU time 40.67 seconds
Started Aug 07 07:17:34 PM PDT 24
Finished Aug 07 07:18:15 PM PDT 24
Peak memory 248196 kb
Host smart-1e0cc939-5478-4654-8e2a-9c361ce35188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86373
1880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.863731880
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.821935316
Short name T335
Test name
Test status
Simulation time 24633551073 ps
CPU time 1110.47 seconds
Started Aug 07 07:17:35 PM PDT 24
Finished Aug 07 07:36:05 PM PDT 24
Peak memory 272480 kb
Host smart-e9b4d36d-7839-4567-b83c-469e9ef09b7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821935316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.821935316
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2252150897
Short name T65
Test name
Test status
Simulation time 143086800935 ps
CPU time 1965.81 seconds
Started Aug 07 07:17:37 PM PDT 24
Finished Aug 07 07:50:23 PM PDT 24
Peak memory 273172 kb
Host smart-eaf71305-9e88-40dd-bad9-82db76453813
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252150897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2252150897
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3254867971
Short name T108
Test name
Test status
Simulation time 5211587545 ps
CPU time 116.68 seconds
Started Aug 07 07:17:36 PM PDT 24
Finished Aug 07 07:19:32 PM PDT 24
Peak memory 248580 kb
Host smart-42b59fc8-ef17-49b7-96f3-b8944c390abe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254867971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3254867971
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.123913071
Short name T600
Test name
Test status
Simulation time 158005175 ps
CPU time 9.73 seconds
Started Aug 07 07:17:34 PM PDT 24
Finished Aug 07 07:17:43 PM PDT 24
Peak memory 248468 kb
Host smart-0547f5a1-bade-4753-b00d-4d231e935a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12391
3071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.123913071
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2869158342
Short name T473
Test name
Test status
Simulation time 200741347 ps
CPU time 6.65 seconds
Started Aug 07 07:17:37 PM PDT 24
Finished Aug 07 07:17:43 PM PDT 24
Peak memory 254344 kb
Host smart-da0b081c-14f9-4cd4-948b-cf452d3e3a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28691
58342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2869158342
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.812392980
Short name T430
Test name
Test status
Simulation time 146494092 ps
CPU time 15.81 seconds
Started Aug 07 07:17:34 PM PDT 24
Finished Aug 07 07:17:50 PM PDT 24
Peak memory 249056 kb
Host smart-62fa41b7-e0f3-4bb3-91cf-421f63acd125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81239
2980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.812392980
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1394036413
Short name T621
Test name
Test status
Simulation time 3508341690 ps
CPU time 60.47 seconds
Started Aug 07 07:17:33 PM PDT 24
Finished Aug 07 07:18:33 PM PDT 24
Peak memory 256700 kb
Host smart-fd029eaa-acf9-488f-85db-232b28413362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13940
36413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1394036413
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3510535854
Short name T283
Test name
Test status
Simulation time 120250506190 ps
CPU time 3944.39 seconds
Started Aug 07 07:17:35 PM PDT 24
Finished Aug 07 08:23:20 PM PDT 24
Peak memory 288988 kb
Host smart-c825e9b2-f4e5-4862-83a5-d6ef02c157c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510535854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3510535854
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3322701600
Short name T522
Test name
Test status
Simulation time 53739176444 ps
CPU time 4607.73 seconds
Started Aug 07 07:17:38 PM PDT 24
Finished Aug 07 08:34:26 PM PDT 24
Peak memory 305536 kb
Host smart-1a497828-3553-4efb-8b91-6d5c13c70126
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322701600 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3322701600
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.650733951
Short name T637
Test name
Test status
Simulation time 19200714006 ps
CPU time 1249.46 seconds
Started Aug 07 07:17:45 PM PDT 24
Finished Aug 07 07:38:35 PM PDT 24
Peak memory 289392 kb
Host smart-875ff291-b0c9-41d2-ae2e-ebd08fa3eda2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650733951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.650733951
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3308947721
Short name T655
Test name
Test status
Simulation time 5090501645 ps
CPU time 321 seconds
Started Aug 07 07:17:46 PM PDT 24
Finished Aug 07 07:23:07 PM PDT 24
Peak memory 251796 kb
Host smart-b89eee66-001e-4b2a-a305-ce2d54401c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33089
47721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3308947721
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1649384105
Short name T266
Test name
Test status
Simulation time 177478546 ps
CPU time 13.67 seconds
Started Aug 07 07:17:45 PM PDT 24
Finished Aug 07 07:17:58 PM PDT 24
Peak memory 253000 kb
Host smart-45685ef0-67c9-4ef6-9eff-c4ea964b8eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16493
84105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1649384105
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2645276201
Short name T329
Test name
Test status
Simulation time 13225991964 ps
CPU time 1226.23 seconds
Started Aug 07 07:17:44 PM PDT 24
Finished Aug 07 07:38:11 PM PDT 24
Peak memory 273184 kb
Host smart-24499517-780a-486c-83b6-074c0dc47f18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645276201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2645276201
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1814260594
Short name T508
Test name
Test status
Simulation time 62825649462 ps
CPU time 1411.57 seconds
Started Aug 07 07:17:44 PM PDT 24
Finished Aug 07 07:41:16 PM PDT 24
Peak memory 289312 kb
Host smart-5698aca5-0f39-4eed-9b5e-2c6dd45b7f64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814260594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1814260594
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.179018043
Short name T589
Test name
Test status
Simulation time 776755440 ps
CPU time 12.19 seconds
Started Aug 07 07:17:35 PM PDT 24
Finished Aug 07 07:17:47 PM PDT 24
Peak memory 256564 kb
Host smart-948013ba-ec98-4c2a-93e2-68a80ccb6bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17901
8043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.179018043
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2305297935
Short name T563
Test name
Test status
Simulation time 958054815 ps
CPU time 57.42 seconds
Started Aug 07 07:17:35 PM PDT 24
Finished Aug 07 07:18:33 PM PDT 24
Peak memory 256128 kb
Host smart-c0fa2f00-d3fa-49aa-9a6c-37aa4995d260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
97935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2305297935
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.197291129
Short name T409
Test name
Test status
Simulation time 104992272 ps
CPU time 11.55 seconds
Started Aug 07 07:17:46 PM PDT 24
Finished Aug 07 07:17:57 PM PDT 24
Peak memory 248816 kb
Host smart-a86229ba-0da9-4420-b7ac-a6d02bca3441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19729
1129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.197291129
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4003072219
Short name T698
Test name
Test status
Simulation time 1309110835 ps
CPU time 49.76 seconds
Started Aug 07 07:17:38 PM PDT 24
Finished Aug 07 07:18:28 PM PDT 24
Peak memory 255952 kb
Host smart-07f9937d-7a5c-476e-8416-f4184c99ce05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40030
72219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4003072219
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.913477515
Short name T492
Test name
Test status
Simulation time 612254077 ps
CPU time 36.03 seconds
Started Aug 07 07:17:44 PM PDT 24
Finished Aug 07 07:18:20 PM PDT 24
Peak memory 255220 kb
Host smart-f18bf035-6c0c-4297-a094-a5b5149d3346
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913477515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.913477515
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.716337597
Short name T690
Test name
Test status
Simulation time 1194535229 ps
CPU time 104.87 seconds
Started Aug 07 07:17:53 PM PDT 24
Finished Aug 07 07:19:38 PM PDT 24
Peak memory 256228 kb
Host smart-6db0bd31-23c0-4cb7-beb1-285cbb2d8a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71633
7597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.716337597
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.478620079
Short name T25
Test name
Test status
Simulation time 145347238 ps
CPU time 6.31 seconds
Started Aug 07 07:17:55 PM PDT 24
Finished Aug 07 07:18:01 PM PDT 24
Peak memory 247828 kb
Host smart-e958ee52-553c-4873-840e-5a3c49860063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47862
0079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.478620079
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3275422870
Short name T325
Test name
Test status
Simulation time 169873683780 ps
CPU time 2371.14 seconds
Started Aug 07 07:18:00 PM PDT 24
Finished Aug 07 07:57:32 PM PDT 24
Peak memory 288676 kb
Host smart-7450bc16-2f7b-469f-9a81-2c08471c9a77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275422870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3275422870
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2363941013
Short name T407
Test name
Test status
Simulation time 46405564827 ps
CPU time 1109.57 seconds
Started Aug 07 07:18:02 PM PDT 24
Finished Aug 07 07:36:32 PM PDT 24
Peak memory 288504 kb
Host smart-d68ee81d-546d-4b89-a9f9-69496632afed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363941013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2363941013
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.4059288233
Short name T291
Test name
Test status
Simulation time 58781485309 ps
CPU time 397.4 seconds
Started Aug 07 07:17:54 PM PDT 24
Finished Aug 07 07:24:32 PM PDT 24
Peak memory 255164 kb
Host smart-81d2b2d6-d4dc-4509-b21d-4f4f5c55e137
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059288233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.4059288233
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3434636445
Short name T694
Test name
Test status
Simulation time 5006805494 ps
CPU time 49.6 seconds
Started Aug 07 07:17:54 PM PDT 24
Finished Aug 07 07:18:44 PM PDT 24
Peak memory 256664 kb
Host smart-7a4b9f44-75db-4bef-88be-aa9b064f43bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34346
36445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3434636445
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.356558514
Short name T66
Test name
Test status
Simulation time 1836808804 ps
CPU time 36.63 seconds
Started Aug 07 07:17:54 PM PDT 24
Finished Aug 07 07:18:31 PM PDT 24
Peak memory 248520 kb
Host smart-c757c2eb-ba9c-4ce3-8210-d536d70a96e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35655
8514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.356558514
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2684232993
Short name T595
Test name
Test status
Simulation time 2001893090 ps
CPU time 33.82 seconds
Started Aug 07 07:17:54 PM PDT 24
Finished Aug 07 07:18:28 PM PDT 24
Peak memory 247812 kb
Host smart-99011731-24b1-4fb2-b085-f80efcc22020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26842
32993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2684232993
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.545986234
Short name T604
Test name
Test status
Simulation time 344100004 ps
CPU time 27.12 seconds
Started Aug 07 07:17:57 PM PDT 24
Finished Aug 07 07:18:25 PM PDT 24
Peak memory 256356 kb
Host smart-890d7465-a466-4c97-a02a-f5a1618869d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54598
6234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.545986234
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.458860207
Short name T81
Test name
Test status
Simulation time 23786545731 ps
CPU time 311.82 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 07:23:15 PM PDT 24
Peak memory 253716 kb
Host smart-dc4560ff-a59a-4e80-b040-1b2393b28f8b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458860207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.458860207
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3274310182
Short name T619
Test name
Test status
Simulation time 68190757617 ps
CPU time 3913.76 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 08:23:17 PM PDT 24
Peak memory 338180 kb
Host smart-c592e77d-55ca-4e2b-869b-8bc6999712c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274310182 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3274310182
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3010474259
Short name T70
Test name
Test status
Simulation time 35037845269 ps
CPU time 2319.84 seconds
Started Aug 07 07:18:05 PM PDT 24
Finished Aug 07 07:56:46 PM PDT 24
Peak memory 289156 kb
Host smart-ac8aa771-9bdb-4009-8a33-2eb75ff117c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010474259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3010474259
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4241743824
Short name T361
Test name
Test status
Simulation time 369850031 ps
CPU time 9.56 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 07:18:12 PM PDT 24
Peak memory 254744 kb
Host smart-02aef452-533b-4f3e-9156-5514adfc9465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42417
43824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4241743824
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3613478911
Short name T370
Test name
Test status
Simulation time 1433926203 ps
CPU time 22.07 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 07:18:25 PM PDT 24
Peak memory 248048 kb
Host smart-53412d18-648f-431d-837d-66628f71f5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36134
78911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3613478911
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1718844628
Short name T250
Test name
Test status
Simulation time 184067875930 ps
CPU time 2948.77 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 08:07:12 PM PDT 24
Peak memory 289208 kb
Host smart-eef18d5e-96ad-4688-a363-80c5211454a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718844628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1718844628
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.298959226
Short name T375
Test name
Test status
Simulation time 71268864245 ps
CPU time 1701.05 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 07:46:24 PM PDT 24
Peak memory 289504 kb
Host smart-6be178b1-6778-471a-8c0d-361ab4d12f91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298959226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.298959226
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2163475481
Short name T587
Test name
Test status
Simulation time 850451057 ps
CPU time 52.39 seconds
Started Aug 07 07:18:02 PM PDT 24
Finished Aug 07 07:18:54 PM PDT 24
Peak memory 255872 kb
Host smart-8f8e318d-4e83-405a-8b4b-5702a3351302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21634
75481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2163475481
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2682418379
Short name T528
Test name
Test status
Simulation time 227409399 ps
CPU time 13.77 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 07:18:17 PM PDT 24
Peak memory 248020 kb
Host smart-90fcf9f0-6473-4a32-b339-a4afcbf562ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26824
18379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2682418379
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4270190442
Short name T44
Test name
Test status
Simulation time 612472315 ps
CPU time 21.42 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 07:18:25 PM PDT 24
Peak memory 255976 kb
Host smart-94546f15-18b4-4bf3-b58a-5bdda8d7b440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42701
90442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4270190442
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2613435320
Short name T208
Test name
Test status
Simulation time 1228497343 ps
CPU time 20.47 seconds
Started Aug 07 07:18:01 PM PDT 24
Finished Aug 07 07:18:22 PM PDT 24
Peak memory 255360 kb
Host smart-9e51386b-df2d-42db-bcd3-f81a7750e0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26134
35320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2613435320
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3464360757
Short name T513
Test name
Test status
Simulation time 3889188920 ps
CPU time 44.06 seconds
Started Aug 07 07:18:17 PM PDT 24
Finished Aug 07 07:19:01 PM PDT 24
Peak memory 256796 kb
Host smart-9d28f0d8-12dd-4559-a1ba-66fcdc34420b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34643
60757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3464360757
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3103412734
Short name T366
Test name
Test status
Simulation time 2193454581 ps
CPU time 69.75 seconds
Started Aug 07 07:18:36 PM PDT 24
Finished Aug 07 07:19:46 PM PDT 24
Peak memory 248496 kb
Host smart-5c0031b5-6f74-493a-8c01-86bd78cdbb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31034
12734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3103412734
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2809669894
Short name T330
Test name
Test status
Simulation time 43213378566 ps
CPU time 1341.72 seconds
Started Aug 07 07:18:36 PM PDT 24
Finished Aug 07 07:40:58 PM PDT 24
Peak memory 288668 kb
Host smart-a705fec4-109f-468a-8b07-23d59fda91ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809669894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2809669894
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.678199060
Short name T490
Test name
Test status
Simulation time 108361795453 ps
CPU time 1806.94 seconds
Started Aug 07 07:18:41 PM PDT 24
Finished Aug 07 07:48:49 PM PDT 24
Peak memory 284268 kb
Host smart-5d89a537-2a41-44e3-8114-26fc264d7d89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678199060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.678199060
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3719454493
Short name T98
Test name
Test status
Simulation time 6661041994 ps
CPU time 270.62 seconds
Started Aug 07 07:18:16 PM PDT 24
Finished Aug 07 07:22:47 PM PDT 24
Peak memory 248584 kb
Host smart-b4a4d618-e193-492d-84f5-970de7666e54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719454493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3719454493
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1650534785
Short name T679
Test name
Test status
Simulation time 175372212 ps
CPU time 12.39 seconds
Started Aug 07 07:18:04 PM PDT 24
Finished Aug 07 07:18:16 PM PDT 24
Peak memory 248448 kb
Host smart-e6132d89-3886-46e7-9d6d-c4a49da9099e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16505
34785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1650534785
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1231522845
Short name T564
Test name
Test status
Simulation time 23201571 ps
CPU time 3.97 seconds
Started Aug 07 07:18:04 PM PDT 24
Finished Aug 07 07:18:08 PM PDT 24
Peak memory 239796 kb
Host smart-9d591bff-488b-4871-b922-ba3983e39ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
22845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1231522845
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.752710173
Short name T77
Test name
Test status
Simulation time 895322603 ps
CPU time 53.44 seconds
Started Aug 07 07:18:18 PM PDT 24
Finished Aug 07 07:19:12 PM PDT 24
Peak memory 256652 kb
Host smart-7f43e321-4c6d-4d2c-a293-c776b88d8437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75271
0173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.752710173
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.4061937087
Short name T489
Test name
Test status
Simulation time 474613399 ps
CPU time 37.29 seconds
Started Aug 07 07:18:03 PM PDT 24
Finished Aug 07 07:18:40 PM PDT 24
Peak memory 256600 kb
Host smart-dd094bfb-267b-4dde-91d8-608691c4cdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40619
37087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4061937087
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1013153574
Short name T453
Test name
Test status
Simulation time 14593001223 ps
CPU time 1166.73 seconds
Started Aug 07 07:18:44 PM PDT 24
Finished Aug 07 07:38:11 PM PDT 24
Peak memory 288568 kb
Host smart-eef6d85c-2803-4a0c-a7d9-972f4f757048
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013153574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1013153574
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.524307781
Short name T206
Test name
Test status
Simulation time 156436456 ps
CPU time 4.08 seconds
Started Aug 07 07:15:05 PM PDT 24
Finished Aug 07 07:15:10 PM PDT 24
Peak memory 248736 kb
Host smart-a847e9a1-dc0b-47f4-9a3f-a3c53582a82e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=524307781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.524307781
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1792784137
Short name T90
Test name
Test status
Simulation time 19692154213 ps
CPU time 1272.7 seconds
Started Aug 07 07:15:08 PM PDT 24
Finished Aug 07 07:36:21 PM PDT 24
Peak memory 288316 kb
Host smart-99957a81-57aa-4111-9f3c-b08769009134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792784137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1792784137
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3456524823
Short name T229
Test name
Test status
Simulation time 1042450672 ps
CPU time 76.7 seconds
Started Aug 07 07:15:05 PM PDT 24
Finished Aug 07 07:16:21 PM PDT 24
Peak memory 256124 kb
Host smart-681518e9-becd-4e37-8d2a-1f255ae113b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34565
24823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3456524823
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.258467860
Short name T376
Test name
Test status
Simulation time 221223650 ps
CPU time 6.02 seconds
Started Aug 07 07:15:09 PM PDT 24
Finished Aug 07 07:15:16 PM PDT 24
Peak memory 248128 kb
Host smart-82d6eeed-168e-4b59-b859-57ce2c581c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25846
7860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.258467860
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2822908930
Short name T88
Test name
Test status
Simulation time 15271864927 ps
CPU time 755.56 seconds
Started Aug 07 07:15:07 PM PDT 24
Finished Aug 07 07:27:43 PM PDT 24
Peak memory 272836 kb
Host smart-12dd7139-6e46-4cf6-bfd0-b1f24b5e78ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822908930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2822908930
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2278115250
Short name T18
Test name
Test status
Simulation time 10701607003 ps
CPU time 200.89 seconds
Started Aug 07 07:15:07 PM PDT 24
Finished Aug 07 07:18:28 PM PDT 24
Peak memory 248600 kb
Host smart-a6895b36-2136-46e3-98b3-3cdc44e22ef4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278115250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2278115250
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3120828251
Short name T455
Test name
Test status
Simulation time 517159006 ps
CPU time 12.03 seconds
Started Aug 07 07:15:09 PM PDT 24
Finished Aug 07 07:15:21 PM PDT 24
Peak memory 255052 kb
Host smart-3219e3c1-43b0-437c-9240-7e818e0c5aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31208
28251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3120828251
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4086502422
Short name T572
Test name
Test status
Simulation time 866453249 ps
CPU time 53.02 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 07:15:59 PM PDT 24
Peak memory 256116 kb
Host smart-c5556290-5eff-4fb6-8a72-cf8ca93bc4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40865
02422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4086502422
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1129793737
Short name T34
Test name
Test status
Simulation time 227258499 ps
CPU time 13.6 seconds
Started Aug 07 07:15:05 PM PDT 24
Finished Aug 07 07:15:19 PM PDT 24
Peak memory 273244 kb
Host smart-84b040f2-0bf2-4358-b34c-e966c0f30ae0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1129793737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1129793737
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1589254178
Short name T89
Test name
Test status
Simulation time 506725464 ps
CPU time 17.64 seconds
Started Aug 07 07:15:08 PM PDT 24
Finished Aug 07 07:15:25 PM PDT 24
Peak memory 248008 kb
Host smart-02975cf2-1a70-4d7d-a2d6-13d80d01fb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15892
54178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1589254178
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.437857165
Short name T656
Test name
Test status
Simulation time 1654538721 ps
CPU time 34.34 seconds
Started Aug 07 07:15:09 PM PDT 24
Finished Aug 07 07:15:44 PM PDT 24
Peak memory 256676 kb
Host smart-cc4dbb57-1174-4558-b4d3-af8354532ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43785
7165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.437857165
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2120695605
Short name T576
Test name
Test status
Simulation time 131275526027 ps
CPU time 3431.36 seconds
Started Aug 07 07:18:43 PM PDT 24
Finished Aug 07 08:15:55 PM PDT 24
Peak memory 289556 kb
Host smart-0f988a89-168c-443d-9741-3775865e87e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120695605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2120695605
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1250651719
Short name T532
Test name
Test status
Simulation time 9884268276 ps
CPU time 326.02 seconds
Started Aug 07 07:18:41 PM PDT 24
Finished Aug 07 07:24:07 PM PDT 24
Peak memory 256320 kb
Host smart-f491c4d5-7913-4576-99e2-fc69b73faccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506
51719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1250651719
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.830006991
Short name T373
Test name
Test status
Simulation time 1907658288 ps
CPU time 60.18 seconds
Started Aug 07 07:18:43 PM PDT 24
Finished Aug 07 07:19:43 PM PDT 24
Peak memory 248516 kb
Host smart-88409300-fea5-45fc-8e30-b84a5d6d4980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83000
6991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.830006991
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2264827600
Short name T287
Test name
Test status
Simulation time 98186004209 ps
CPU time 1622.86 seconds
Started Aug 07 07:18:45 PM PDT 24
Finished Aug 07 07:45:48 PM PDT 24
Peak memory 272472 kb
Host smart-26731d11-e017-45d4-b385-336351232af8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264827600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2264827600
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3630214605
Short name T533
Test name
Test status
Simulation time 91777824668 ps
CPU time 2757.15 seconds
Started Aug 07 07:18:44 PM PDT 24
Finished Aug 07 08:04:41 PM PDT 24
Peak memory 289204 kb
Host smart-2e19e472-5df4-4864-abc5-84a690b09323
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630214605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3630214605
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.837043363
Short name T482
Test name
Test status
Simulation time 10145562947 ps
CPU time 217.08 seconds
Started Aug 07 07:18:47 PM PDT 24
Finished Aug 07 07:22:24 PM PDT 24
Peak memory 247632 kb
Host smart-2dc6f30f-ca21-4431-ac61-0791961880cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837043363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.837043363
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.711322193
Short name T644
Test name
Test status
Simulation time 477480971 ps
CPU time 19.57 seconds
Started Aug 07 07:18:42 PM PDT 24
Finished Aug 07 07:19:02 PM PDT 24
Peak memory 255756 kb
Host smart-01cfd342-c41a-4247-bb66-a82ea1655293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71132
2193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.711322193
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2011091172
Short name T613
Test name
Test status
Simulation time 129219109 ps
CPU time 13.24 seconds
Started Aug 07 07:18:43 PM PDT 24
Finished Aug 07 07:18:57 PM PDT 24
Peak memory 256192 kb
Host smart-9a8bcd1b-3e22-415c-9573-5c90b9d8025a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20110
91172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2011091172
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.539542391
Short name T214
Test name
Test status
Simulation time 120882313 ps
CPU time 9.78 seconds
Started Aug 07 07:18:42 PM PDT 24
Finished Aug 07 07:18:52 PM PDT 24
Peak memory 253468 kb
Host smart-efa4da11-535a-42fc-93c6-f599d60d13ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53954
2391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.539542391
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3979398278
Short name T384
Test name
Test status
Simulation time 988126443 ps
CPU time 29.16 seconds
Started Aug 07 07:18:42 PM PDT 24
Finished Aug 07 07:19:11 PM PDT 24
Peak memory 248484 kb
Host smart-5b95fc81-77af-4196-b6b5-9012a8828acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39793
98278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3979398278
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3637483185
Short name T544
Test name
Test status
Simulation time 210779654 ps
CPU time 12.83 seconds
Started Aug 07 07:18:43 PM PDT 24
Finished Aug 07 07:18:56 PM PDT 24
Peak memory 247928 kb
Host smart-4acc6a5f-6e9f-4810-a894-e04b184cf81d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637483185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3637483185
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.183103989
Short name T477
Test name
Test status
Simulation time 42741785007 ps
CPU time 2883.29 seconds
Started Aug 07 07:18:53 PM PDT 24
Finished Aug 07 08:06:57 PM PDT 24
Peak memory 288780 kb
Host smart-49ecdd98-1633-47c9-b990-6fc3994186ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183103989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.183103989
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4219662812
Short name T614
Test name
Test status
Simulation time 1480820918 ps
CPU time 165.18 seconds
Started Aug 07 07:18:43 PM PDT 24
Finished Aug 07 07:21:29 PM PDT 24
Peak memory 256620 kb
Host smart-a3ad8d85-34da-4aa2-8b1e-72590bd30adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42196
62812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4219662812
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4248767155
Short name T458
Test name
Test status
Simulation time 914028111 ps
CPU time 53.07 seconds
Started Aug 07 07:18:43 PM PDT 24
Finished Aug 07 07:19:37 PM PDT 24
Peak memory 248200 kb
Host smart-bcb3d657-11ac-4964-80b3-74bc29360840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
67155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4248767155
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.843707740
Short name T316
Test name
Test status
Simulation time 33729267199 ps
CPU time 2020.52 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 07:52:35 PM PDT 24
Peak memory 273168 kb
Host smart-91688271-323b-41bc-bad1-2e7435a3efa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843707740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.843707740
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1793575483
Short name T212
Test name
Test status
Simulation time 21279425555 ps
CPU time 1329.34 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 07:41:04 PM PDT 24
Peak memory 273180 kb
Host smart-7fc6ab56-af23-43e8-95cb-6379767532e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793575483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1793575483
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1997636202
Short name T47
Test name
Test status
Simulation time 1639897901 ps
CPU time 26.26 seconds
Started Aug 07 07:18:44 PM PDT 24
Finished Aug 07 07:19:10 PM PDT 24
Peak memory 248516 kb
Host smart-e6389a6d-4911-4301-8883-ae7379ce4fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19976
36202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1997636202
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4021506600
Short name T518
Test name
Test status
Simulation time 324151066 ps
CPU time 30.55 seconds
Started Aug 07 07:18:41 PM PDT 24
Finished Aug 07 07:19:12 PM PDT 24
Peak memory 247936 kb
Host smart-3cdb9c46-9c34-4cac-ad76-f916e2924108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40215
06600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4021506600
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.4026354820
Short name T464
Test name
Test status
Simulation time 418732903 ps
CPU time 14.26 seconds
Started Aug 07 07:18:47 PM PDT 24
Finished Aug 07 07:19:02 PM PDT 24
Peak memory 247960 kb
Host smart-69fd237a-893f-4a7b-b617-2af04dbb03d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40263
54820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4026354820
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1094381682
Short name T219
Test name
Test status
Simulation time 828438531 ps
CPU time 55.37 seconds
Started Aug 07 07:18:42 PM PDT 24
Finished Aug 07 07:19:37 PM PDT 24
Peak memory 256636 kb
Host smart-f9502fe4-3fa4-434d-8d7b-27e7ce14dab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
81682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1094381682
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3353246535
Short name T32
Test name
Test status
Simulation time 112766412316 ps
CPU time 2059.23 seconds
Started Aug 07 07:18:52 PM PDT 24
Finished Aug 07 07:53:12 PM PDT 24
Peak memory 285276 kb
Host smart-769327a5-343e-4227-9468-b86f3402052d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353246535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3353246535
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.229985435
Short name T545
Test name
Test status
Simulation time 44937588985 ps
CPU time 4938.23 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 08:41:13 PM PDT 24
Peak memory 354928 kb
Host smart-a3b42823-f345-459e-b015-dd1aff36de13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229985435 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.229985435
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3709318719
Short name T580
Test name
Test status
Simulation time 8112935818 ps
CPU time 824.29 seconds
Started Aug 07 07:18:57 PM PDT 24
Finished Aug 07 07:32:42 PM PDT 24
Peak memory 272464 kb
Host smart-727eace6-50e5-46df-a10e-af175859f7ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709318719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3709318719
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1467790829
Short name T228
Test name
Test status
Simulation time 4996263415 ps
CPU time 255 seconds
Started Aug 07 07:18:53 PM PDT 24
Finished Aug 07 07:23:08 PM PDT 24
Peak memory 256048 kb
Host smart-7fb80a09-00a5-4524-a6fc-6a3caf3e0009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14677
90829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1467790829
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.65860622
Short name T636
Test name
Test status
Simulation time 3346357436 ps
CPU time 53.6 seconds
Started Aug 07 07:18:53 PM PDT 24
Finished Aug 07 07:19:47 PM PDT 24
Peak memory 248180 kb
Host smart-7faf955d-50c8-4f8c-9d77-5b08d911af40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65860
622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.65860622
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4084121281
Short name T339
Test name
Test status
Simulation time 28507157386 ps
CPU time 1486.14 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 07:43:40 PM PDT 24
Peak memory 273080 kb
Host smart-2558651c-7322-4a7e-a284-dad89f719752
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084121281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4084121281
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3162809247
Short name T639
Test name
Test status
Simulation time 51730086918 ps
CPU time 1108.05 seconds
Started Aug 07 07:18:55 PM PDT 24
Finished Aug 07 07:37:23 PM PDT 24
Peak memory 272976 kb
Host smart-5ad43f15-8309-418c-8dd8-933c8c73ad77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162809247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3162809247
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4283634536
Short name T565
Test name
Test status
Simulation time 10169047922 ps
CPU time 212.07 seconds
Started Aug 07 07:18:55 PM PDT 24
Finished Aug 07 07:22:27 PM PDT 24
Peak memory 248584 kb
Host smart-e3472ed1-e005-4b4c-8fb3-4e91a7a73e21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283634536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4283634536
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2377857039
Short name T627
Test name
Test status
Simulation time 202087259 ps
CPU time 13.47 seconds
Started Aug 07 07:18:52 PM PDT 24
Finished Aug 07 07:19:06 PM PDT 24
Peak memory 248472 kb
Host smart-9027f85e-e941-4f9a-a4b0-64895ff31547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23778
57039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2377857039
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1151061040
Short name T506
Test name
Test status
Simulation time 1505378930 ps
CPU time 42.08 seconds
Started Aug 07 07:18:52 PM PDT 24
Finished Aug 07 07:19:34 PM PDT 24
Peak memory 248372 kb
Host smart-dd2e76a7-c789-4b64-aa33-5741ed8b86b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11510
61040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1151061040
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.496656681
Short name T547
Test name
Test status
Simulation time 87174270 ps
CPU time 4.66 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 07:18:59 PM PDT 24
Peak memory 239636 kb
Host smart-59bdb10d-763d-4e65-8220-ce8a5ef1525f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49665
6681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.496656681
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1943497639
Short name T399
Test name
Test status
Simulation time 3766095042 ps
CPU time 43.33 seconds
Started Aug 07 07:18:57 PM PDT 24
Finished Aug 07 07:19:41 PM PDT 24
Peak memory 256760 kb
Host smart-c8689ef9-3b34-4c9d-ad0e-4397534f71ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19434
97639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1943497639
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1509370828
Short name T577
Test name
Test status
Simulation time 474685241761 ps
CPU time 2085.83 seconds
Started Aug 07 07:18:53 PM PDT 24
Finished Aug 07 07:53:39 PM PDT 24
Peak memory 273164 kb
Host smart-0bdc087a-b134-485e-8737-c6e957fb1e7d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509370828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1509370828
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3354084876
Short name T46
Test name
Test status
Simulation time 291460773791 ps
CPU time 8601.15 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 09:42:16 PM PDT 24
Peak memory 394432 kb
Host smart-c4a37ed1-600d-458a-b734-855a7ef9466b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354084876 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3354084876
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4287853601
Short name T255
Test name
Test status
Simulation time 11461783147 ps
CPU time 1113.49 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 07:37:28 PM PDT 24
Peak memory 273144 kb
Host smart-00625d9c-f95d-4543-9ee8-3cd3b253aa19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287853601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4287853601
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2417873480
Short name T365
Test name
Test status
Simulation time 366264704 ps
CPU time 39.82 seconds
Started Aug 07 07:18:53 PM PDT 24
Finished Aug 07 07:19:33 PM PDT 24
Peak memory 256680 kb
Host smart-0592de95-e880-4153-ae52-dd723454d5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24178
73480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2417873480
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3955005911
Short name T674
Test name
Test status
Simulation time 1051584111 ps
CPU time 56.98 seconds
Started Aug 07 07:18:53 PM PDT 24
Finished Aug 07 07:19:51 PM PDT 24
Peak memory 256272 kb
Host smart-a29588a5-8383-409e-bbba-fbd7ff54721e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
05911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3955005911
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.789137067
Short name T297
Test name
Test status
Simulation time 70560607435 ps
CPU time 1701.45 seconds
Started Aug 07 07:19:03 PM PDT 24
Finished Aug 07 07:47:25 PM PDT 24
Peak memory 288556 kb
Host smart-1a42e9b3-ad1e-4bd7-8d28-9bcb0336eb1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789137067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.789137067
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1977382335
Short name T240
Test name
Test status
Simulation time 122095788989 ps
CPU time 1138.39 seconds
Started Aug 07 07:19:05 PM PDT 24
Finished Aug 07 07:38:03 PM PDT 24
Peak memory 266012 kb
Host smart-bedbd0f9-1600-4bdc-a60b-895020bdb989
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977382335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1977382335
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1118097297
Short name T293
Test name
Test status
Simulation time 3205507319 ps
CPU time 133.94 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 07:21:08 PM PDT 24
Peak memory 255612 kb
Host smart-6503fc81-9e4f-43d9-90e5-13d30e8db408
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118097297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1118097297
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1864439231
Short name T705
Test name
Test status
Simulation time 1620367734 ps
CPU time 53.71 seconds
Started Aug 07 07:18:53 PM PDT 24
Finished Aug 07 07:19:47 PM PDT 24
Peak memory 248444 kb
Host smart-a64e8c65-54a8-4730-b8fb-ef76095089bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18644
39231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1864439231
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2102559135
Short name T661
Test name
Test status
Simulation time 199479228 ps
CPU time 12.98 seconds
Started Aug 07 07:18:53 PM PDT 24
Finished Aug 07 07:19:06 PM PDT 24
Peak memory 247612 kb
Host smart-9927d8ba-3fb5-4d03-90b7-b318746fbff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21025
59135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2102559135
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1489596713
Short name T271
Test name
Test status
Simulation time 3652669896 ps
CPU time 52.1 seconds
Started Aug 07 07:18:57 PM PDT 24
Finished Aug 07 07:19:50 PM PDT 24
Peak memory 248288 kb
Host smart-64403d14-23e9-4187-9e97-46987ca42e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14895
96713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1489596713
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4102904318
Short name T443
Test name
Test status
Simulation time 2386664724 ps
CPU time 38.98 seconds
Started Aug 07 07:18:54 PM PDT 24
Finished Aug 07 07:19:33 PM PDT 24
Peak memory 256272 kb
Host smart-a188094e-63dc-4d2d-8042-0bc579755836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
04318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4102904318
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3026558083
Short name T709
Test name
Test status
Simulation time 10788206454 ps
CPU time 623.13 seconds
Started Aug 07 07:19:04 PM PDT 24
Finished Aug 07 07:29:28 PM PDT 24
Peak memory 255948 kb
Host smart-c3f371f0-b7cb-41a5-aae5-657931c072bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026558083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3026558083
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3119023896
Short name T187
Test name
Test status
Simulation time 24722008260 ps
CPU time 1479.16 seconds
Started Aug 07 07:19:06 PM PDT 24
Finished Aug 07 07:43:45 PM PDT 24
Peak memory 264984 kb
Host smart-53d0fa16-f6ee-45cc-9e25-20d0b9f2f3a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119023896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3119023896
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3834023947
Short name T448
Test name
Test status
Simulation time 392291766 ps
CPU time 12.05 seconds
Started Aug 07 07:19:05 PM PDT 24
Finished Aug 07 07:19:17 PM PDT 24
Peak memory 256196 kb
Host smart-e7e724c8-d9b9-41dc-8e18-0d761de8e12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340
23947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3834023947
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3611982051
Short name T420
Test name
Test status
Simulation time 1009209209 ps
CPU time 39 seconds
Started Aug 07 07:19:05 PM PDT 24
Finished Aug 07 07:19:44 PM PDT 24
Peak memory 248316 kb
Host smart-78be4f28-4377-4c9b-83cc-c4becda06ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36119
82051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3611982051
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2338713452
Short name T64
Test name
Test status
Simulation time 301853921322 ps
CPU time 2210.34 seconds
Started Aug 07 07:19:09 PM PDT 24
Finished Aug 07 07:56:00 PM PDT 24
Peak memory 273184 kb
Host smart-a54a48e4-a498-46a6-9631-a7454355a567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338713452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2338713452
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2329377773
Short name T247
Test name
Test status
Simulation time 31148692662 ps
CPU time 1828.83 seconds
Started Aug 07 07:19:12 PM PDT 24
Finished Aug 07 07:49:42 PM PDT 24
Peak memory 288552 kb
Host smart-d65d28ae-2b0e-43f0-86f6-99511db20bae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329377773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2329377773
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.430292620
Short name T318
Test name
Test status
Simulation time 57144874726 ps
CPU time 595.98 seconds
Started Aug 07 07:19:10 PM PDT 24
Finished Aug 07 07:29:07 PM PDT 24
Peak memory 248556 kb
Host smart-dbfa2d09-c9fa-4d36-b990-51bfab68b461
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430292620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.430292620
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1650373581
Short name T16
Test name
Test status
Simulation time 186280751 ps
CPU time 9.66 seconds
Started Aug 07 07:19:04 PM PDT 24
Finished Aug 07 07:19:13 PM PDT 24
Peak memory 254448 kb
Host smart-365ccfbc-12bb-4d6d-b025-ebac99327933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16503
73581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1650373581
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1420144766
Short name T391
Test name
Test status
Simulation time 214072585 ps
CPU time 17.52 seconds
Started Aug 07 07:19:05 PM PDT 24
Finished Aug 07 07:19:23 PM PDT 24
Peak memory 247772 kb
Host smart-c59338fd-10c1-473d-baa0-bd8714ee9275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14201
44766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1420144766
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3150899850
Short name T264
Test name
Test status
Simulation time 1102115346 ps
CPU time 22.61 seconds
Started Aug 07 07:19:05 PM PDT 24
Finished Aug 07 07:19:28 PM PDT 24
Peak memory 247572 kb
Host smart-d90687c4-3c5f-4ae0-8b63-1b7aeb848475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31508
99850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3150899850
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.438038119
Short name T559
Test name
Test status
Simulation time 1704522849 ps
CPU time 61.69 seconds
Started Aug 07 07:19:05 PM PDT 24
Finished Aug 07 07:20:07 PM PDT 24
Peak memory 256508 kb
Host smart-1f804658-02f4-4fa4-8254-6537d8667826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43803
8119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.438038119
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4130594142
Short name T246
Test name
Test status
Simulation time 44297931900 ps
CPU time 2331.15 seconds
Started Aug 07 07:19:13 PM PDT 24
Finished Aug 07 07:58:05 PM PDT 24
Peak memory 289268 kb
Host smart-c7c5e184-b77c-4aaf-bf5c-0864a76bf88c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130594142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4130594142
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1165278695
Short name T86
Test name
Test status
Simulation time 70114679573 ps
CPU time 1235.71 seconds
Started Aug 07 07:19:12 PM PDT 24
Finished Aug 07 07:39:48 PM PDT 24
Peak memory 272568 kb
Host smart-a59c21d4-7bf2-41d9-ad59-769ae33a9bdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165278695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1165278695
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3954135116
Short name T357
Test name
Test status
Simulation time 1233371044 ps
CPU time 46.39 seconds
Started Aug 07 07:19:12 PM PDT 24
Finished Aug 07 07:19:58 PM PDT 24
Peak memory 256220 kb
Host smart-354d713f-9573-4615-a115-0ae43b330ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39541
35116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3954135116
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2287148833
Short name T504
Test name
Test status
Simulation time 1326395309 ps
CPU time 69.77 seconds
Started Aug 07 07:19:12 PM PDT 24
Finished Aug 07 07:20:22 PM PDT 24
Peak memory 255808 kb
Host smart-7a1560ac-3231-4f54-8a56-09c1cf661307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22871
48833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2287148833
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.685091660
Short name T309
Test name
Test status
Simulation time 172450582894 ps
CPU time 3222.21 seconds
Started Aug 07 07:19:10 PM PDT 24
Finished Aug 07 08:12:53 PM PDT 24
Peak memory 284888 kb
Host smart-6109acf1-d452-4a10-bbd9-1dd6df2301f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685091660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.685091660
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3266156211
Short name T369
Test name
Test status
Simulation time 24021953870 ps
CPU time 1013.57 seconds
Started Aug 07 07:19:24 PM PDT 24
Finished Aug 07 07:36:18 PM PDT 24
Peak memory 273040 kb
Host smart-4ee8f18f-ad60-4fcf-9df9-de6f1c77e229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266156211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3266156211
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.73963445
Short name T607
Test name
Test status
Simulation time 812001719 ps
CPU time 27.31 seconds
Started Aug 07 07:19:12 PM PDT 24
Finished Aug 07 07:19:39 PM PDT 24
Peak memory 248396 kb
Host smart-08ab40ca-76b5-48ab-b11d-aab125520386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73963
445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.73963445
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.359588966
Short name T242
Test name
Test status
Simulation time 970448512 ps
CPU time 53 seconds
Started Aug 07 07:19:12 PM PDT 24
Finished Aug 07 07:20:05 PM PDT 24
Peak memory 248920 kb
Host smart-b518d64f-0154-4da9-963f-6a8355c32270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35958
8966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.359588966
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3918864168
Short name T632
Test name
Test status
Simulation time 577806884 ps
CPU time 19.65 seconds
Started Aug 07 07:19:13 PM PDT 24
Finished Aug 07 07:19:33 PM PDT 24
Peak memory 255396 kb
Host smart-b9ae5eca-fec7-4700-8e6c-8289c8d2f461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39188
64168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3918864168
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.424361870
Short name T251
Test name
Test status
Simulation time 14293510961 ps
CPU time 1047.29 seconds
Started Aug 07 07:19:34 PM PDT 24
Finished Aug 07 07:37:02 PM PDT 24
Peak memory 281348 kb
Host smart-157fcc60-3509-4516-b62c-31e54e92b7ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424361870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.424361870
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.820502379
Short name T520
Test name
Test status
Simulation time 4222668546 ps
CPU time 94.25 seconds
Started Aug 07 07:19:35 PM PDT 24
Finished Aug 07 07:21:10 PM PDT 24
Peak memory 256304 kb
Host smart-311925ac-41bf-4d61-8146-96199158a103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82050
2379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.820502379
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.391826570
Short name T394
Test name
Test status
Simulation time 1110205907 ps
CPU time 24.46 seconds
Started Aug 07 07:19:34 PM PDT 24
Finished Aug 07 07:19:59 PM PDT 24
Peak memory 248412 kb
Host smart-1bcc5ddb-0b5c-4fda-8ad5-22c849b702bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39182
6570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.391826570
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4205982264
Short name T333
Test name
Test status
Simulation time 158781069146 ps
CPU time 2676.08 seconds
Started Aug 07 07:19:34 PM PDT 24
Finished Aug 07 08:04:11 PM PDT 24
Peak memory 283572 kb
Host smart-404efbdb-6082-4cff-b294-4915ace9ca75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205982264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4205982264
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.4069033378
Short name T397
Test name
Test status
Simulation time 9057888284 ps
CPU time 938.92 seconds
Started Aug 07 07:19:34 PM PDT 24
Finished Aug 07 07:35:13 PM PDT 24
Peak memory 272780 kb
Host smart-2dc53775-565b-4f6b-a92d-b4797e070483
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069033378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.4069033378
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.4074392775
Short name T378
Test name
Test status
Simulation time 849570878 ps
CPU time 49.72 seconds
Started Aug 07 07:19:23 PM PDT 24
Finished Aug 07 07:20:13 PM PDT 24
Peak memory 256424 kb
Host smart-961b9f13-07bf-4778-873c-ebec70a063b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40743
92775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.4074392775
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3584075666
Short name T438
Test name
Test status
Simulation time 4092977348 ps
CPU time 62.92 seconds
Started Aug 07 07:19:33 PM PDT 24
Finished Aug 07 07:20:36 PM PDT 24
Peak memory 248420 kb
Host smart-6442d87a-8040-415d-8917-482418321d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35840
75666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3584075666
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4105777258
Short name T102
Test name
Test status
Simulation time 313567747 ps
CPU time 21.33 seconds
Started Aug 07 07:19:35 PM PDT 24
Finished Aug 07 07:19:57 PM PDT 24
Peak memory 254936 kb
Host smart-b1d588af-fe51-4adf-88cc-dea61ea79ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41057
77258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4105777258
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.671545824
Short name T353
Test name
Test status
Simulation time 2222408735 ps
CPU time 71.51 seconds
Started Aug 07 07:19:23 PM PDT 24
Finished Aug 07 07:20:35 PM PDT 24
Peak memory 256700 kb
Host smart-6bedfd97-aae9-4a7f-b55d-dc554c201fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67154
5824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.671545824
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1485397557
Short name T175
Test name
Test status
Simulation time 1040428478601 ps
CPU time 8366.95 seconds
Started Aug 07 07:19:43 PM PDT 24
Finished Aug 07 09:39:11 PM PDT 24
Peak memory 348500 kb
Host smart-d6b89f69-6042-4559-a78c-caca0d412717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485397557 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1485397557
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.340397641
Short name T552
Test name
Test status
Simulation time 30358801068 ps
CPU time 2175.25 seconds
Started Aug 07 07:19:42 PM PDT 24
Finished Aug 07 07:55:58 PM PDT 24
Peak memory 280864 kb
Host smart-7adb84f6-5a4a-4452-8e6a-e79f7cce57dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340397641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.340397641
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.4040489495
Short name T498
Test name
Test status
Simulation time 3263221310 ps
CPU time 96.9 seconds
Started Aug 07 07:19:42 PM PDT 24
Finished Aug 07 07:21:19 PM PDT 24
Peak memory 256248 kb
Host smart-d79604d7-7ec3-40ee-9e91-d373282e78d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40404
89495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.4040489495
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.493729238
Short name T220
Test name
Test status
Simulation time 1216761730 ps
CPU time 80.16 seconds
Started Aug 07 07:19:42 PM PDT 24
Finished Aug 07 07:21:02 PM PDT 24
Peak memory 248200 kb
Host smart-1c0f904f-fe2e-4ffe-b3a4-ee39f93f98e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49372
9238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.493729238
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.429966950
Short name T322
Test name
Test status
Simulation time 249563690385 ps
CPU time 1800.51 seconds
Started Aug 07 07:19:43 PM PDT 24
Finished Aug 07 07:49:44 PM PDT 24
Peak memory 288744 kb
Host smart-42bb63f0-4a85-4ea0-80bd-0bda89ef8566
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429966950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.429966950
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1109429661
Short name T622
Test name
Test status
Simulation time 103348967176 ps
CPU time 3192.7 seconds
Started Aug 07 07:19:53 PM PDT 24
Finished Aug 07 08:13:06 PM PDT 24
Peak memory 281348 kb
Host smart-55a8b7ec-66a8-49d3-99f7-3208f672c6c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109429661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1109429661
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.360625938
Short name T562
Test name
Test status
Simulation time 37282199466 ps
CPU time 391.42 seconds
Started Aug 07 07:19:43 PM PDT 24
Finished Aug 07 07:26:14 PM PDT 24
Peak memory 248424 kb
Host smart-147e5f10-6d0d-425c-8564-c4f966f022c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360625938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.360625938
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.831795895
Short name T496
Test name
Test status
Simulation time 121180711 ps
CPU time 5.36 seconds
Started Aug 07 07:19:45 PM PDT 24
Finished Aug 07 07:19:50 PM PDT 24
Peak memory 248464 kb
Host smart-5168153d-839f-4e44-bbe2-0915a233c572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83179
5895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.831795895
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.843919159
Short name T211
Test name
Test status
Simulation time 81609013 ps
CPU time 9.4 seconds
Started Aug 07 07:19:44 PM PDT 24
Finished Aug 07 07:19:53 PM PDT 24
Peak memory 247796 kb
Host smart-81eabaa6-5d1e-4aa1-9a0d-256554630928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84391
9159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.843919159
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1428683741
Short name T37
Test name
Test status
Simulation time 381808630 ps
CPU time 24.33 seconds
Started Aug 07 07:19:44 PM PDT 24
Finished Aug 07 07:20:09 PM PDT 24
Peak memory 255860 kb
Host smart-ce578336-3752-498c-81a3-453bdadc5a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14286
83741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1428683741
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3808358710
Short name T434
Test name
Test status
Simulation time 593422589 ps
CPU time 24.44 seconds
Started Aug 07 07:19:43 PM PDT 24
Finished Aug 07 07:20:07 PM PDT 24
Peak memory 256368 kb
Host smart-cb5eb2f2-47c2-467b-b60c-7771fc877134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38083
58710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3808358710
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3364472398
Short name T244
Test name
Test status
Simulation time 339829854924 ps
CPU time 4746.75 seconds
Started Aug 07 07:19:59 PM PDT 24
Finished Aug 07 08:39:07 PM PDT 24
Peak memory 305960 kb
Host smart-817aab5d-6c68-4831-879a-12f768b6b56b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364472398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3364472398
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1018522703
Short name T463
Test name
Test status
Simulation time 186822618659 ps
CPU time 2713.33 seconds
Started Aug 07 07:19:52 PM PDT 24
Finished Aug 07 08:05:06 PM PDT 24
Peak memory 288652 kb
Host smart-5e36369e-67d7-41b0-b0a0-3933cd4ab36d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018522703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1018522703
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.859504501
Short name T406
Test name
Test status
Simulation time 1418700215 ps
CPU time 16.77 seconds
Started Aug 07 07:20:00 PM PDT 24
Finished Aug 07 07:20:16 PM PDT 24
Peak memory 253728 kb
Host smart-dfc26642-263a-44b8-b608-1607db58a070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85950
4501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.859504501
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1939039112
Short name T702
Test name
Test status
Simulation time 651579194 ps
CPU time 22.18 seconds
Started Aug 07 07:19:52 PM PDT 24
Finished Aug 07 07:20:15 PM PDT 24
Peak memory 248504 kb
Host smart-a0a36334-0904-4849-b1a7-b108470789fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19390
39112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1939039112
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2820153975
Short name T328
Test name
Test status
Simulation time 82415335337 ps
CPU time 1418.18 seconds
Started Aug 07 07:19:51 PM PDT 24
Finished Aug 07 07:43:30 PM PDT 24
Peak memory 272456 kb
Host smart-7d296bd1-be25-4d50-94c0-b2caeb3ef17d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820153975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2820153975
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3704438894
Short name T411
Test name
Test status
Simulation time 26450753393 ps
CPU time 1788.47 seconds
Started Aug 07 07:19:53 PM PDT 24
Finished Aug 07 07:49:43 PM PDT 24
Peak memory 271120 kb
Host smart-2077f4c3-bd65-4dcb-b0cf-3df75eb5ddd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704438894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3704438894
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.422417927
Short name T19
Test name
Test status
Simulation time 19973130243 ps
CPU time 428.28 seconds
Started Aug 07 07:19:52 PM PDT 24
Finished Aug 07 07:27:01 PM PDT 24
Peak memory 248276 kb
Host smart-6d3d1b67-d52a-4397-864f-26433e53f74d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422417927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.422417927
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2616569197
Short name T401
Test name
Test status
Simulation time 1096763531 ps
CPU time 33.56 seconds
Started Aug 07 07:20:00 PM PDT 24
Finished Aug 07 07:20:34 PM PDT 24
Peak memory 256076 kb
Host smart-8423eb67-61c3-485d-a301-f5115879d9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26165
69197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2616569197
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2524611079
Short name T586
Test name
Test status
Simulation time 4408284558 ps
CPU time 36.42 seconds
Started Aug 07 07:19:52 PM PDT 24
Finished Aug 07 07:20:29 PM PDT 24
Peak memory 247748 kb
Host smart-c43a2141-6021-4169-8bc4-b88f837ca9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25246
11079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2524611079
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1097380564
Short name T185
Test name
Test status
Simulation time 134871322 ps
CPU time 8.96 seconds
Started Aug 07 07:19:54 PM PDT 24
Finished Aug 07 07:20:03 PM PDT 24
Peak memory 248944 kb
Host smart-866de83b-df97-4efc-87d7-ae85b2f15229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10973
80564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1097380564
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.422480510
Short name T668
Test name
Test status
Simulation time 439696232 ps
CPU time 47.62 seconds
Started Aug 07 07:19:52 PM PDT 24
Finished Aug 07 07:20:40 PM PDT 24
Peak memory 248480 kb
Host smart-a1753799-d46c-4f36-b896-177eaea49eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42248
0510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.422480510
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.295341970
Short name T457
Test name
Test status
Simulation time 56166425763 ps
CPU time 1254.35 seconds
Started Aug 07 07:20:04 PM PDT 24
Finished Aug 07 07:40:59 PM PDT 24
Peak memory 288336 kb
Host smart-628062d7-4265-4e44-a1bb-c7c7710a44f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295341970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.295341970
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2894581903
Short name T245
Test name
Test status
Simulation time 85711434242 ps
CPU time 2961.53 seconds
Started Aug 07 07:20:02 PM PDT 24
Finished Aug 07 08:09:24 PM PDT 24
Peak memory 289620 kb
Host smart-e8d2a656-ac34-4fe9-8e8a-25f059997495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894581903 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2894581903
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2578899402
Short name T693
Test name
Test status
Simulation time 31828596379 ps
CPU time 765.7 seconds
Started Aug 07 07:20:12 PM PDT 24
Finished Aug 07 07:32:58 PM PDT 24
Peak memory 273176 kb
Host smart-37967d34-f8c6-474a-af4d-2a22c2d17d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578899402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2578899402
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2633902872
Short name T551
Test name
Test status
Simulation time 2349253113 ps
CPU time 138.39 seconds
Started Aug 07 07:20:13 PM PDT 24
Finished Aug 07 07:22:32 PM PDT 24
Peak memory 256316 kb
Host smart-cb136bd4-4520-4c0b-a807-17f846142094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26339
02872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2633902872
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.586753063
Short name T469
Test name
Test status
Simulation time 953020931 ps
CPU time 29.73 seconds
Started Aug 07 07:20:12 PM PDT 24
Finished Aug 07 07:20:41 PM PDT 24
Peak memory 247928 kb
Host smart-2a4d8b74-3c6e-437e-86b0-0617904b3e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58675
3063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.586753063
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3066542449
Short name T356
Test name
Test status
Simulation time 42819168994 ps
CPU time 1824.19 seconds
Started Aug 07 07:20:12 PM PDT 24
Finished Aug 07 07:50:37 PM PDT 24
Peak memory 273000 kb
Host smart-bad900ee-27fe-4018-8564-78bb1e999f8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066542449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3066542449
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1933085298
Short name T17
Test name
Test status
Simulation time 22722772907 ps
CPU time 219.65 seconds
Started Aug 07 07:20:13 PM PDT 24
Finished Aug 07 07:23:52 PM PDT 24
Peak memory 248756 kb
Host smart-1f02ac2c-4831-4d4c-89c9-14f31dd61efd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933085298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1933085298
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1569707928
Short name T13
Test name
Test status
Simulation time 852475541 ps
CPU time 62.81 seconds
Started Aug 07 07:20:02 PM PDT 24
Finished Aug 07 07:21:05 PM PDT 24
Peak memory 255828 kb
Host smart-20868e18-377a-4246-a0b8-830c5a297138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697
07928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1569707928
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.60664820
Short name T423
Test name
Test status
Simulation time 4403721109 ps
CPU time 44.28 seconds
Started Aug 07 07:20:03 PM PDT 24
Finished Aug 07 07:20:47 PM PDT 24
Peak memory 248284 kb
Host smart-0efa8e7e-8940-4dfa-85f6-769741650527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60664
820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.60664820
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.25706824
Short name T274
Test name
Test status
Simulation time 2597030673 ps
CPU time 35.81 seconds
Started Aug 07 07:20:11 PM PDT 24
Finished Aug 07 07:20:47 PM PDT 24
Peak memory 248228 kb
Host smart-97d8a898-6371-483d-8ba2-e66f7a339257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25706
824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.25706824
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2483941975
Short name T210
Test name
Test status
Simulation time 206023892 ps
CPU time 15.36 seconds
Started Aug 07 07:20:04 PM PDT 24
Finished Aug 07 07:20:20 PM PDT 24
Peak memory 255028 kb
Host smart-47d2d324-251f-480c-943e-1fa719be5b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24839
41975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2483941975
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3097728210
Short name T519
Test name
Test status
Simulation time 179712587361 ps
CPU time 2391.7 seconds
Started Aug 07 07:20:12 PM PDT 24
Finished Aug 07 08:00:04 PM PDT 24
Peak memory 288776 kb
Host smart-a8e28dd2-475e-4e50-9d15-933abca49df6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097728210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3097728210
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2752518525
Short name T225
Test name
Test status
Simulation time 58376113178 ps
CPU time 3943.52 seconds
Started Aug 07 07:20:11 PM PDT 24
Finished Aug 07 08:25:56 PM PDT 24
Peak memory 298924 kb
Host smart-28a74f96-a57d-449c-98ab-15ae83e212d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752518525 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2752518525
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1685630119
Short name T202
Test name
Test status
Simulation time 33369725 ps
CPU time 3.87 seconds
Started Aug 07 07:15:10 PM PDT 24
Finished Aug 07 07:15:14 PM PDT 24
Peak memory 248712 kb
Host smart-077574c5-25f3-4b3a-9256-10e1ae3af176
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1685630119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1685630119
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1074899409
Short name T28
Test name
Test status
Simulation time 51211859270 ps
CPU time 1230.41 seconds
Started Aug 07 07:15:08 PM PDT 24
Finished Aug 07 07:35:38 PM PDT 24
Peak memory 273084 kb
Host smart-cdffccb3-6e51-4470-b34c-42edaa2e69c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074899409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1074899409
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1209673089
Short name T677
Test name
Test status
Simulation time 227592849 ps
CPU time 12.91 seconds
Started Aug 07 07:15:13 PM PDT 24
Finished Aug 07 07:15:27 PM PDT 24
Peak memory 248472 kb
Host smart-32c958b5-26a0-439a-87cd-8de62cbd72ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1209673089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1209673089
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3249600840
Short name T555
Test name
Test status
Simulation time 5468787258 ps
CPU time 131.72 seconds
Started Aug 07 07:15:08 PM PDT 24
Finished Aug 07 07:17:20 PM PDT 24
Peak memory 256680 kb
Host smart-cc11f8d7-c329-4fa6-b1ed-6b5c26f784fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32496
00840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3249600840
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.753170096
Short name T234
Test name
Test status
Simulation time 437449245 ps
CPU time 34.84 seconds
Started Aug 07 07:15:10 PM PDT 24
Finished Aug 07 07:15:45 PM PDT 24
Peak memory 248124 kb
Host smart-06f5b1a9-6490-4273-a1f9-9fbaac9516a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75317
0096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.753170096
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3147581051
Short name T691
Test name
Test status
Simulation time 29137112213 ps
CPU time 1399.12 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 07:38:26 PM PDT 24
Peak memory 289096 kb
Host smart-a1aded78-0013-4724-a286-d4ef2982526b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147581051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3147581051
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1474846181
Short name T101
Test name
Test status
Simulation time 22204515747 ps
CPU time 1362.21 seconds
Started Aug 07 07:15:07 PM PDT 24
Finished Aug 07 07:37:49 PM PDT 24
Peak memory 273068 kb
Host smart-d82d2825-bb83-4cbb-a26b-f6b4acf9b201
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474846181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1474846181
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.4220900649
Short name T620
Test name
Test status
Simulation time 4158571664 ps
CPU time 179.58 seconds
Started Aug 07 07:15:08 PM PDT 24
Finished Aug 07 07:18:07 PM PDT 24
Peak memory 248596 kb
Host smart-4e093e4c-1270-4ded-89f3-e9882b8a2d13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220900649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.4220900649
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2924197319
Short name T381
Test name
Test status
Simulation time 119376206 ps
CPU time 9.05 seconds
Started Aug 07 07:15:05 PM PDT 24
Finished Aug 07 07:15:14 PM PDT 24
Peak memory 248488 kb
Host smart-de5b03bc-2fef-4cf4-8746-5a3418feeb3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29241
97319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2924197319
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1896099508
Short name T362
Test name
Test status
Simulation time 125023092 ps
CPU time 11.61 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 07:15:17 PM PDT 24
Peak memory 248008 kb
Host smart-454cfa0c-906b-4d5f-887f-df881afabaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18960
99508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1896099508
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.245134183
Short name T10
Test name
Test status
Simulation time 345156176 ps
CPU time 13.01 seconds
Started Aug 07 07:15:17 PM PDT 24
Finished Aug 07 07:15:30 PM PDT 24
Peak memory 269812 kb
Host smart-8f4444ce-1e8e-4b50-b6eb-029568316b91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=245134183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.245134183
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1301273451
Short name T688
Test name
Test status
Simulation time 853437486 ps
CPU time 45.44 seconds
Started Aug 07 07:15:07 PM PDT 24
Finished Aug 07 07:15:52 PM PDT 24
Peak memory 248840 kb
Host smart-7a3a0421-e986-4131-851c-b79ddc777d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13012
73451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1301273451
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3354845271
Short name T383
Test name
Test status
Simulation time 533185752 ps
CPU time 22.11 seconds
Started Aug 07 07:15:05 PM PDT 24
Finished Aug 07 07:15:28 PM PDT 24
Peak memory 248484 kb
Host smart-0ee2f970-7f8e-481a-9b76-3b69fc14a435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33548
45271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3354845271
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.4071952210
Short name T182
Test name
Test status
Simulation time 21299913748 ps
CPU time 1420.95 seconds
Started Aug 07 07:15:06 PM PDT 24
Finished Aug 07 07:38:47 PM PDT 24
Peak memory 284844 kb
Host smart-67e56443-ae04-40c6-bc9c-4f4a154bb05f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071952210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.4071952210
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1838225360
Short name T514
Test name
Test status
Simulation time 94549098846 ps
CPU time 1709.44 seconds
Started Aug 07 07:15:05 PM PDT 24
Finished Aug 07 07:43:34 PM PDT 24
Peak memory 289720 kb
Host smart-3ea41652-d730-46d4-be55-6dbcb8687c98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838225360 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1838225360
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.163083197
Short name T689
Test name
Test status
Simulation time 16151462581 ps
CPU time 1579.58 seconds
Started Aug 07 07:20:22 PM PDT 24
Finished Aug 07 07:46:42 PM PDT 24
Peak memory 288608 kb
Host smart-f87807ed-4d40-4b1c-a8b7-caf16fcf14c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163083197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.163083197
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.154312873
Short name T662
Test name
Test status
Simulation time 234844062 ps
CPU time 20.97 seconds
Started Aug 07 07:20:23 PM PDT 24
Finished Aug 07 07:20:44 PM PDT 24
Peak memory 256676 kb
Host smart-2de25105-d4cb-465f-9312-5ac5ad8aa0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15431
2873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.154312873
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.390596976
Short name T429
Test name
Test status
Simulation time 51500790 ps
CPU time 2.94 seconds
Started Aug 07 07:20:21 PM PDT 24
Finished Aug 07 07:20:24 PM PDT 24
Peak memory 239776 kb
Host smart-44af4815-dbca-4961-9c88-cc94c82f7b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39059
6976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.390596976
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3785143902
Short name T666
Test name
Test status
Simulation time 28063488845 ps
CPU time 1639.43 seconds
Started Aug 07 07:20:21 PM PDT 24
Finished Aug 07 07:47:41 PM PDT 24
Peak memory 272484 kb
Host smart-33c844f3-db7a-4742-b885-f076f09d914c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785143902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3785143902
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2178597639
Short name T686
Test name
Test status
Simulation time 9902594788 ps
CPU time 1032.9 seconds
Started Aug 07 07:20:21 PM PDT 24
Finished Aug 07 07:37:34 PM PDT 24
Peak memory 285212 kb
Host smart-19874c52-1d61-4185-b37f-cb3efdcee01c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178597639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2178597639
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.989815734
Short name T502
Test name
Test status
Simulation time 190332711 ps
CPU time 7.66 seconds
Started Aug 07 07:20:11 PM PDT 24
Finished Aug 07 07:20:19 PM PDT 24
Peak memory 254200 kb
Host smart-bd547485-8e99-4280-88b1-2faa21888438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98981
5734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.989815734
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.4290153967
Short name T390
Test name
Test status
Simulation time 462312896 ps
CPU time 41.73 seconds
Started Aug 07 07:20:22 PM PDT 24
Finished Aug 07 07:21:04 PM PDT 24
Peak memory 248500 kb
Host smart-0c3ce589-8593-4bf0-9259-07ddfd4aa464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42901
53967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.4290153967
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1635347444
Short name T241
Test name
Test status
Simulation time 486142113 ps
CPU time 28.54 seconds
Started Aug 07 07:20:21 PM PDT 24
Finished Aug 07 07:20:50 PM PDT 24
Peak memory 256640 kb
Host smart-93a14ff5-e577-4847-b52d-ac6466921481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16353
47444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1635347444
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.993356896
Short name T444
Test name
Test status
Simulation time 1237779847 ps
CPU time 63.54 seconds
Started Aug 07 07:20:16 PM PDT 24
Finished Aug 07 07:21:20 PM PDT 24
Peak memory 256504 kb
Host smart-cb0fb2aa-1904-4cd3-a293-25824777f3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99335
6896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.993356896
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2571421236
Short name T72
Test name
Test status
Simulation time 104225672554 ps
CPU time 3016.87 seconds
Started Aug 07 07:20:22 PM PDT 24
Finished Aug 07 08:10:39 PM PDT 24
Peak memory 289184 kb
Host smart-d3a56eb9-0f00-45c9-95b8-4a0aa634808a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571421236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2571421236
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.478392053
Short name T599
Test name
Test status
Simulation time 54955324658 ps
CPU time 2522.04 seconds
Started Aug 07 07:20:34 PM PDT 24
Finished Aug 07 08:02:37 PM PDT 24
Peak memory 289116 kb
Host smart-38ae5914-9480-40fd-8164-7a385e391159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478392053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.478392053
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3271002348
Short name T440
Test name
Test status
Simulation time 7572157170 ps
CPU time 167.94 seconds
Started Aug 07 07:20:35 PM PDT 24
Finished Aug 07 07:23:23 PM PDT 24
Peak memory 256796 kb
Host smart-78e34af8-1ee9-4e84-8141-2ed2933bd054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32710
02348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3271002348
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3500719486
Short name T471
Test name
Test status
Simulation time 547004511 ps
CPU time 34.71 seconds
Started Aug 07 07:20:21 PM PDT 24
Finished Aug 07 07:20:55 PM PDT 24
Peak memory 247928 kb
Host smart-afd9f8cb-7b45-4bf6-b1e8-52a062acc8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35007
19486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3500719486
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2920407752
Short name T336
Test name
Test status
Simulation time 169974161836 ps
CPU time 2676.18 seconds
Started Aug 07 07:20:32 PM PDT 24
Finished Aug 07 08:05:09 PM PDT 24
Peak memory 284436 kb
Host smart-cd59e3d2-0243-4021-8b06-0feebef71db9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920407752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2920407752
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1545018122
Short name T706
Test name
Test status
Simulation time 142727743191 ps
CPU time 2575.56 seconds
Started Aug 07 07:20:33 PM PDT 24
Finished Aug 07 08:03:29 PM PDT 24
Peak memory 272916 kb
Host smart-d87567de-f34e-4517-bde8-ef927cc6cb52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545018122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1545018122
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.461999870
Short name T494
Test name
Test status
Simulation time 21648090453 ps
CPU time 251.29 seconds
Started Aug 07 07:20:36 PM PDT 24
Finished Aug 07 07:24:47 PM PDT 24
Peak memory 248404 kb
Host smart-ac5b6188-acc6-4b45-ad8a-7724961a0cd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461999870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.461999870
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3969662027
Short name T493
Test name
Test status
Simulation time 4221427967 ps
CPU time 72.39 seconds
Started Aug 07 07:20:22 PM PDT 24
Finished Aug 07 07:21:34 PM PDT 24
Peak memory 256716 kb
Host smart-fe9882c5-e356-43d5-a5e5-cb4d9944ca4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39696
62027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3969662027
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3722597261
Short name T424
Test name
Test status
Simulation time 929024822 ps
CPU time 57.83 seconds
Started Aug 07 07:20:23 PM PDT 24
Finished Aug 07 07:21:21 PM PDT 24
Peak memory 255916 kb
Host smart-c3165014-b33c-4ae4-b0b1-c29ea9a0199b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37225
97261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3722597261
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3002060286
Short name T526
Test name
Test status
Simulation time 477454724 ps
CPU time 27.98 seconds
Started Aug 07 07:20:36 PM PDT 24
Finished Aug 07 07:21:04 PM PDT 24
Peak memory 249000 kb
Host smart-60525ded-0240-4f8c-ac52-aa3979a9ed41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30020
60286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3002060286
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3784127888
Short name T39
Test name
Test status
Simulation time 173595929 ps
CPU time 4.09 seconds
Started Aug 07 07:20:21 PM PDT 24
Finished Aug 07 07:20:25 PM PDT 24
Peak memory 250636 kb
Host smart-014dd8df-8e55-478e-a8b0-1fdd40f1fe0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37841
27888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3784127888
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3581751092
Short name T53
Test name
Test status
Simulation time 30872483903 ps
CPU time 420.52 seconds
Started Aug 07 07:20:34 PM PDT 24
Finished Aug 07 07:27:35 PM PDT 24
Peak memory 256712 kb
Host smart-8a2ba0a1-23e0-4b3f-acd5-e33936c4ff53
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581751092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3581751092
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2618262705
Short name T224
Test name
Test status
Simulation time 331569457314 ps
CPU time 1138.6 seconds
Started Aug 07 07:20:36 PM PDT 24
Finished Aug 07 07:39:35 PM PDT 24
Peak memory 283540 kb
Host smart-2ad6f98e-faa5-4b99-8d6e-f39ce9b174ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618262705 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2618262705
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3527513007
Short name T568
Test name
Test status
Simulation time 52440525753 ps
CPU time 1603.08 seconds
Started Aug 07 07:20:44 PM PDT 24
Finished Aug 07 07:47:27 PM PDT 24
Peak memory 268996 kb
Host smart-f3240e86-7696-4643-b526-7a65c30071b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527513007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3527513007
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2937756264
Short name T624
Test name
Test status
Simulation time 4827189341 ps
CPU time 80.06 seconds
Started Aug 07 07:20:35 PM PDT 24
Finished Aug 07 07:21:55 PM PDT 24
Peak memory 256080 kb
Host smart-ae4c9c3a-69c6-403f-8202-e6d9b8727095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29377
56264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2937756264
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3536231009
Short name T454
Test name
Test status
Simulation time 687554506 ps
CPU time 14.76 seconds
Started Aug 07 07:20:33 PM PDT 24
Finished Aug 07 07:20:48 PM PDT 24
Peak memory 248396 kb
Host smart-de1c4230-34f6-4c11-b239-e109a03506a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35362
31009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3536231009
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3599278589
Short name T307
Test name
Test status
Simulation time 168430617891 ps
CPU time 2562.96 seconds
Started Aug 07 07:20:44 PM PDT 24
Finished Aug 07 08:03:27 PM PDT 24
Peak memory 288492 kb
Host smart-956edceb-47a7-44dd-8ad5-2deb1f82e06f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599278589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3599278589
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1731561696
Short name T310
Test name
Test status
Simulation time 2402970768 ps
CPU time 105.74 seconds
Started Aug 07 07:20:45 PM PDT 24
Finished Aug 07 07:22:31 PM PDT 24
Peak memory 248624 kb
Host smart-70a23ff6-41bc-422e-8e1b-7fc41ec0b21e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731561696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1731561696
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3317203775
Short name T684
Test name
Test status
Simulation time 422763207 ps
CPU time 26.88 seconds
Started Aug 07 07:20:34 PM PDT 24
Finished Aug 07 07:21:01 PM PDT 24
Peak memory 256636 kb
Host smart-4a136654-c765-4b1b-9abf-5b06924e277a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33172
03775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3317203775
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.415119703
Short name T368
Test name
Test status
Simulation time 504227504 ps
CPU time 40.68 seconds
Started Aug 07 07:20:36 PM PDT 24
Finished Aug 07 07:21:17 PM PDT 24
Peak memory 248488 kb
Host smart-5e442db3-25ad-4062-9332-45d3ccbe54c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41511
9703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.415119703
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2699578823
Short name T15
Test name
Test status
Simulation time 1043902277 ps
CPU time 26.57 seconds
Started Aug 07 07:20:35 PM PDT 24
Finished Aug 07 07:21:02 PM PDT 24
Peak memory 256660 kb
Host smart-171e6469-d112-4358-a399-1f2a605503cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26995
78823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2699578823
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2712233086
Short name T80
Test name
Test status
Simulation time 4807112311 ps
CPU time 61.53 seconds
Started Aug 07 07:20:36 PM PDT 24
Finished Aug 07 07:21:38 PM PDT 24
Peak memory 249008 kb
Host smart-f1d55d79-bc7a-4f93-9609-4d616fd3c26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27122
33086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2712233086
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3347529618
Short name T561
Test name
Test status
Simulation time 159425570674 ps
CPU time 2710.01 seconds
Started Aug 07 07:20:44 PM PDT 24
Finished Aug 07 08:05:54 PM PDT 24
Peak memory 289036 kb
Host smart-49d21ec2-93d7-47be-9b67-332ff450460e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347529618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3347529618
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3045107505
Short name T174
Test name
Test status
Simulation time 330531002129 ps
CPU time 5004.66 seconds
Started Aug 07 07:20:44 PM PDT 24
Finished Aug 07 08:44:10 PM PDT 24
Peak memory 322472 kb
Host smart-4e97b73b-626a-464c-8488-cfa696ebb702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045107505 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3045107505
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3589825194
Short name T92
Test name
Test status
Simulation time 34944455801 ps
CPU time 982.28 seconds
Started Aug 07 07:20:55 PM PDT 24
Finished Aug 07 07:37:18 PM PDT 24
Peak memory 281408 kb
Host smart-441ed022-2d33-45bb-92a7-69233e433f21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589825194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3589825194
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.4156761255
Short name T23
Test name
Test status
Simulation time 2173097323 ps
CPU time 149.54 seconds
Started Aug 07 07:20:55 PM PDT 24
Finished Aug 07 07:23:25 PM PDT 24
Peak memory 256240 kb
Host smart-e88af20b-c522-4f3a-9886-7f9309699a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
61255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.4156761255
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1574429265
Short name T263
Test name
Test status
Simulation time 3032589904 ps
CPU time 53.26 seconds
Started Aug 07 07:20:58 PM PDT 24
Finished Aug 07 07:21:51 PM PDT 24
Peak memory 248576 kb
Host smart-2c59f915-5d7b-454a-8394-81aacf557f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15744
29265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1574429265
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1776165565
Short name T323
Test name
Test status
Simulation time 243088819161 ps
CPU time 1899.01 seconds
Started Aug 07 07:20:55 PM PDT 24
Finished Aug 07 07:52:35 PM PDT 24
Peak memory 272504 kb
Host smart-cefb3162-9cd5-41cc-a833-bc5bb5f1c5ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776165565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1776165565
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2002804282
Short name T43
Test name
Test status
Simulation time 13011457650 ps
CPU time 1146.11 seconds
Started Aug 07 07:21:05 PM PDT 24
Finished Aug 07 07:40:11 PM PDT 24
Peak memory 288744 kb
Host smart-cc68e817-f273-409b-9425-1019126e8021
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002804282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2002804282
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2194676723
Short name T647
Test name
Test status
Simulation time 400970611 ps
CPU time 35.59 seconds
Started Aug 07 07:20:57 PM PDT 24
Finished Aug 07 07:21:33 PM PDT 24
Peak memory 248496 kb
Host smart-61f7c1cd-ae08-4310-8335-95262eeee4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21946
76723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2194676723
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3774451731
Short name T485
Test name
Test status
Simulation time 329031655 ps
CPU time 36.9 seconds
Started Aug 07 07:20:55 PM PDT 24
Finished Aug 07 07:21:32 PM PDT 24
Peak memory 256108 kb
Host smart-fbcf8c04-acc3-4866-b5eb-d05fd1e18ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37744
51731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3774451731
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3656732468
Short name T57
Test name
Test status
Simulation time 27011695 ps
CPU time 3.94 seconds
Started Aug 07 07:20:55 PM PDT 24
Finished Aug 07 07:20:59 PM PDT 24
Peak memory 239636 kb
Host smart-d6fb8e99-d4a4-461b-92fe-338e5af4b563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36567
32468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3656732468
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.481779144
Short name T515
Test name
Test status
Simulation time 118984780 ps
CPU time 4.06 seconds
Started Aug 07 07:20:55 PM PDT 24
Finished Aug 07 07:20:59 PM PDT 24
Peak memory 250608 kb
Host smart-4040f8c4-0afc-4196-8e6f-56b4b254334a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48177
9144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.481779144
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1049807901
Short name T673
Test name
Test status
Simulation time 672073735128 ps
CPU time 3303.09 seconds
Started Aug 07 07:21:06 PM PDT 24
Finished Aug 07 08:16:10 PM PDT 24
Peak memory 288904 kb
Host smart-0d36c464-cef4-42b6-bb07-02e667a20f76
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049807901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1049807901
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.951082582
Short name T546
Test name
Test status
Simulation time 339319117754 ps
CPU time 1779.53 seconds
Started Aug 07 07:21:14 PM PDT 24
Finished Aug 07 07:50:53 PM PDT 24
Peak memory 284520 kb
Host smart-59900f13-56cd-4c88-aeb6-567669a35573
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951082582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.951082582
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.568110757
Short name T625
Test name
Test status
Simulation time 1878773441 ps
CPU time 139.42 seconds
Started Aug 07 07:21:05 PM PDT 24
Finished Aug 07 07:23:25 PM PDT 24
Peak memory 256680 kb
Host smart-2852784c-dff7-4722-8e6a-083dedc38f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56811
0757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.568110757
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1194579420
Short name T82
Test name
Test status
Simulation time 1972894316 ps
CPU time 18.96 seconds
Started Aug 07 07:21:04 PM PDT 24
Finished Aug 07 07:21:23 PM PDT 24
Peak memory 256212 kb
Host smart-4fe4a979-ecab-4327-a25e-4026b6db4b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11945
79420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1194579420
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.425090033
Short name T405
Test name
Test status
Simulation time 20735330697 ps
CPU time 1272.23 seconds
Started Aug 07 07:21:15 PM PDT 24
Finished Aug 07 07:42:27 PM PDT 24
Peak memory 272164 kb
Host smart-011927e7-d964-459b-8ffa-06f555f9ce9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425090033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.425090033
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2786730186
Short name T363
Test name
Test status
Simulation time 239347356 ps
CPU time 23.92 seconds
Started Aug 07 07:21:06 PM PDT 24
Finished Aug 07 07:21:30 PM PDT 24
Peak memory 248444 kb
Host smart-791e0564-7cbd-4405-8f84-a7bb603be6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
30186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2786730186
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1386499091
Short name T472
Test name
Test status
Simulation time 484765700 ps
CPU time 30.08 seconds
Started Aug 07 07:21:04 PM PDT 24
Finished Aug 07 07:21:34 PM PDT 24
Peak memory 256112 kb
Host smart-b9de0453-5deb-457a-9dde-8e2085499709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13864
99091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1386499091
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.902060541
Short name T588
Test name
Test status
Simulation time 1580814168 ps
CPU time 31.7 seconds
Started Aug 07 07:21:06 PM PDT 24
Finished Aug 07 07:21:37 PM PDT 24
Peak memory 256660 kb
Host smart-1dc53591-6d3f-47f7-aab1-c69bf0d577bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90206
0541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.902060541
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3120352639
Short name T91
Test name
Test status
Simulation time 42540729525 ps
CPU time 1684.57 seconds
Started Aug 07 07:21:16 PM PDT 24
Finished Aug 07 07:49:21 PM PDT 24
Peak memory 297624 kb
Host smart-424a535e-4c83-4a3c-8a6c-2ea59fd790eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120352639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3120352639
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1937469666
Short name T173
Test name
Test status
Simulation time 66094921134 ps
CPU time 1397.54 seconds
Started Aug 07 07:21:16 PM PDT 24
Finished Aug 07 07:44:34 PM PDT 24
Peak memory 285276 kb
Host smart-d56773ab-9ce3-4150-87ec-450c1db76d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937469666 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1937469666
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1927880839
Short name T45
Test name
Test status
Simulation time 436453794113 ps
CPU time 2188.52 seconds
Started Aug 07 07:21:24 PM PDT 24
Finished Aug 07 07:57:53 PM PDT 24
Peak memory 288864 kb
Host smart-4ca32216-cefe-4841-a131-2cb7879f32cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927880839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1927880839
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.492138423
Short name T517
Test name
Test status
Simulation time 20170179829 ps
CPU time 239.07 seconds
Started Aug 07 07:21:24 PM PDT 24
Finished Aug 07 07:25:23 PM PDT 24
Peak memory 256332 kb
Host smart-79e3bb44-4be6-4b92-898d-27814a37e476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49213
8423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.492138423
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.141413195
Short name T69
Test name
Test status
Simulation time 215350773 ps
CPU time 27.93 seconds
Started Aug 07 07:21:26 PM PDT 24
Finished Aug 07 07:21:55 PM PDT 24
Peak memory 256112 kb
Host smart-0ca98b7f-5b9f-4966-9457-0ade35f10a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14141
3195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.141413195
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1682649727
Short name T84
Test name
Test status
Simulation time 143540395794 ps
CPU time 2330.26 seconds
Started Aug 07 07:21:37 PM PDT 24
Finished Aug 07 08:00:28 PM PDT 24
Peak memory 272932 kb
Host smart-5946b964-e07a-4825-9afd-ba8278d4c2bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682649727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1682649727
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3959085953
Short name T298
Test name
Test status
Simulation time 15973223531 ps
CPU time 182.63 seconds
Started Aug 07 07:21:26 PM PDT 24
Finished Aug 07 07:24:28 PM PDT 24
Peak memory 248580 kb
Host smart-bd004cdd-126b-48c0-9a60-1a0b226d7ec3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959085953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3959085953
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.472839586
Short name T427
Test name
Test status
Simulation time 332944641 ps
CPU time 23.5 seconds
Started Aug 07 07:21:16 PM PDT 24
Finished Aug 07 07:21:39 PM PDT 24
Peak memory 255976 kb
Host smart-3b1b6799-952a-4ddb-83ee-e80772932d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47283
9586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.472839586
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2019936351
Short name T73
Test name
Test status
Simulation time 1248694838 ps
CPU time 72.14 seconds
Started Aug 07 07:21:24 PM PDT 24
Finished Aug 07 07:22:36 PM PDT 24
Peak memory 247876 kb
Host smart-91ac0bf3-aa45-4e48-99f1-57ffca61e9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20199
36351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2019936351
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.45585050
Short name T671
Test name
Test status
Simulation time 2866598299 ps
CPU time 49.65 seconds
Started Aug 07 07:21:24 PM PDT 24
Finished Aug 07 07:22:14 PM PDT 24
Peak memory 248544 kb
Host smart-18f2f99c-4706-4dfe-84fa-d67665c395fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45585
050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.45585050
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.4081151830
Short name T181
Test name
Test status
Simulation time 1829909757 ps
CPU time 37.18 seconds
Started Aug 07 07:21:16 PM PDT 24
Finished Aug 07 07:21:53 PM PDT 24
Peak memory 256660 kb
Host smart-cc761243-7f88-4ca7-917c-7b4702653599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40811
51830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4081151830
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1463603078
Short name T104
Test name
Test status
Simulation time 55338164637 ps
CPU time 1406.41 seconds
Started Aug 07 07:21:36 PM PDT 24
Finished Aug 07 07:45:03 PM PDT 24
Peak memory 289464 kb
Host smart-60e0ec61-c34e-48ac-9e52-ac51b98ce0dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463603078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1463603078
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1854841062
Short name T257
Test name
Test status
Simulation time 37401762214 ps
CPU time 3203.4 seconds
Started Aug 07 07:21:36 PM PDT 24
Finished Aug 07 08:15:00 PM PDT 24
Peak memory 278544 kb
Host smart-71025fd5-4d8e-457b-a5e9-2341fcb94a22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854841062 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1854841062
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.319426674
Short name T466
Test name
Test status
Simulation time 45247504317 ps
CPU time 2873.55 seconds
Started Aug 07 07:21:36 PM PDT 24
Finished Aug 07 08:09:30 PM PDT 24
Peak memory 289320 kb
Host smart-e88564d1-d066-41ce-b194-5da69ed6d4cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319426674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.319426674
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2199541500
Short name T359
Test name
Test status
Simulation time 4960259250 ps
CPU time 84.08 seconds
Started Aug 07 07:21:37 PM PDT 24
Finished Aug 07 07:23:01 PM PDT 24
Peak memory 256824 kb
Host smart-54ad1a4e-71bf-4377-86fc-a72fabab77cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21995
41500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2199541500
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1643841981
Short name T665
Test name
Test status
Simulation time 283900662 ps
CPU time 17.77 seconds
Started Aug 07 07:21:37 PM PDT 24
Finished Aug 07 07:21:55 PM PDT 24
Peak memory 247844 kb
Host smart-178aafce-2a51-486a-9bd4-a93193d2bf70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16438
41981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1643841981
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3745950382
Short name T340
Test name
Test status
Simulation time 11670814832 ps
CPU time 1042.69 seconds
Started Aug 07 07:21:46 PM PDT 24
Finished Aug 07 07:39:08 PM PDT 24
Peak memory 272560 kb
Host smart-081ff6eb-944a-4df5-a577-7fc0a077e7f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745950382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3745950382
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2469024309
Short name T708
Test name
Test status
Simulation time 7897106385 ps
CPU time 654.9 seconds
Started Aug 07 07:21:49 PM PDT 24
Finished Aug 07 07:32:44 PM PDT 24
Peak memory 272760 kb
Host smart-3476f74b-2181-408b-ad23-5ab8197b834d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469024309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2469024309
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3126162568
Short name T300
Test name
Test status
Simulation time 11141698704 ps
CPU time 496.08 seconds
Started Aug 07 07:21:44 PM PDT 24
Finished Aug 07 07:30:00 PM PDT 24
Peak memory 256068 kb
Host smart-8d7300bc-8736-4d48-a020-b1dc7fe95a17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126162568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3126162568
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3627381305
Short name T374
Test name
Test status
Simulation time 9020292814 ps
CPU time 59.92 seconds
Started Aug 07 07:21:36 PM PDT 24
Finished Aug 07 07:22:36 PM PDT 24
Peak memory 256700 kb
Host smart-5c30875c-4226-4acd-accd-05b0383eecd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36273
81305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3627381305
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1567668441
Short name T646
Test name
Test status
Simulation time 3477693885 ps
CPU time 55.55 seconds
Started Aug 07 07:21:36 PM PDT 24
Finished Aug 07 07:22:32 PM PDT 24
Peak memory 249624 kb
Host smart-8c296501-ca72-4a7a-8854-632124e3bfef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15676
68441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1567668441
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.4222400333
Short name T62
Test name
Test status
Simulation time 54673846 ps
CPU time 8.06 seconds
Started Aug 07 07:21:36 PM PDT 24
Finished Aug 07 07:21:44 PM PDT 24
Peak memory 252892 kb
Host smart-9a361bb9-080a-4e0a-a96b-638acd05a03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42224
00333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.4222400333
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2380164485
Short name T355
Test name
Test status
Simulation time 415302575 ps
CPU time 14.8 seconds
Started Aug 07 07:21:37 PM PDT 24
Finished Aug 07 07:21:52 PM PDT 24
Peak memory 254780 kb
Host smart-f0aef098-a3d7-4b8f-aff0-c1def4a44654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23801
64485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2380164485
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1603786872
Short name T596
Test name
Test status
Simulation time 113043617510 ps
CPU time 1432.9 seconds
Started Aug 07 07:21:45 PM PDT 24
Finished Aug 07 07:45:38 PM PDT 24
Peak memory 288764 kb
Host smart-b01e2710-964e-463e-8318-4a53694728b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603786872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1603786872
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3290149694
Short name T253
Test name
Test status
Simulation time 80863226529 ps
CPU time 1664.46 seconds
Started Aug 07 07:21:49 PM PDT 24
Finished Aug 07 07:49:34 PM PDT 24
Peak memory 289484 kb
Host smart-7d5996d9-9fe3-4991-b377-dd672095cd41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290149694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3290149694
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.801286406
Short name T352
Test name
Test status
Simulation time 71831950450 ps
CPU time 410.45 seconds
Started Aug 07 07:21:47 PM PDT 24
Finished Aug 07 07:28:37 PM PDT 24
Peak memory 256196 kb
Host smart-960f11ff-d2f5-4d1a-a433-492142b1c9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80128
6406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.801286406
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4107341063
Short name T221
Test name
Test status
Simulation time 1090790397 ps
CPU time 70.79 seconds
Started Aug 07 07:21:46 PM PDT 24
Finished Aug 07 07:22:57 PM PDT 24
Peak memory 248292 kb
Host smart-5bb19c44-510d-46f9-9c4c-3ad8ee88b8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41073
41063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4107341063
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2113268989
Short name T334
Test name
Test status
Simulation time 54602491192 ps
CPU time 1470.21 seconds
Started Aug 07 07:21:55 PM PDT 24
Finished Aug 07 07:46:26 PM PDT 24
Peak memory 289124 kb
Host smart-eb634921-9d96-4adf-a000-4e8700d480d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113268989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2113268989
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3253323830
Short name T704
Test name
Test status
Simulation time 24764242436 ps
CPU time 1463.2 seconds
Started Aug 07 07:21:54 PM PDT 24
Finished Aug 07 07:46:17 PM PDT 24
Peak memory 271848 kb
Host smart-4dcf1043-951b-4f41-a43e-30c0dda2fb50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253323830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3253323830
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2253333642
Short name T313
Test name
Test status
Simulation time 5896139672 ps
CPU time 240.94 seconds
Started Aug 07 07:21:53 PM PDT 24
Finished Aug 07 07:25:54 PM PDT 24
Peak memory 248580 kb
Host smart-5e158597-3060-4510-a193-a5470ec53513
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253333642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2253333642
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1710561094
Short name T556
Test name
Test status
Simulation time 2803985215 ps
CPU time 37.92 seconds
Started Aug 07 07:21:47 PM PDT 24
Finished Aug 07 07:22:25 PM PDT 24
Peak memory 255828 kb
Host smart-049ca804-0ab9-427c-9e53-7086e13904b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17105
61094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1710561094
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2092403931
Short name T239
Test name
Test status
Simulation time 347380896 ps
CPU time 32.52 seconds
Started Aug 07 07:21:46 PM PDT 24
Finished Aug 07 07:22:18 PM PDT 24
Peak memory 247776 kb
Host smart-b466c1e6-6b43-49c3-8ce1-4e34beea43fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20924
03931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2092403931
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2735376246
Short name T237
Test name
Test status
Simulation time 324849059 ps
CPU time 19.51 seconds
Started Aug 07 07:21:46 PM PDT 24
Finished Aug 07 07:22:05 PM PDT 24
Peak memory 255116 kb
Host smart-7b589749-f387-4916-8996-4bef1efca0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27353
76246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2735376246
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.4180187011
Short name T231
Test name
Test status
Simulation time 725905968 ps
CPU time 16.95 seconds
Started Aug 07 07:21:49 PM PDT 24
Finished Aug 07 07:22:06 PM PDT 24
Peak memory 256316 kb
Host smart-facb5d90-941b-43ec-b0c0-172d58246f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41801
87011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.4180187011
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1709200237
Short name T521
Test name
Test status
Simulation time 7948201006 ps
CPU time 489.8 seconds
Started Aug 07 07:21:54 PM PDT 24
Finished Aug 07 07:30:04 PM PDT 24
Peak memory 256732 kb
Host smart-01f3291c-6828-42c8-bafb-1c6a38dd1ac2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709200237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1709200237
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3134253219
Short name T618
Test name
Test status
Simulation time 12127295091 ps
CPU time 1398.91 seconds
Started Aug 07 07:21:54 PM PDT 24
Finished Aug 07 07:45:13 PM PDT 24
Peak memory 289436 kb
Host smart-cde56c2b-858d-42cc-9e29-038359a557f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134253219 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3134253219
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.683873165
Short name T527
Test name
Test status
Simulation time 139542451306 ps
CPU time 2292.71 seconds
Started Aug 07 07:22:10 PM PDT 24
Finished Aug 07 08:00:23 PM PDT 24
Peak memory 283612 kb
Host smart-ad396c26-13de-4a30-9d91-b09ac8bb3db7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683873165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.683873165
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3216370013
Short name T617
Test name
Test status
Simulation time 16682122330 ps
CPU time 86.45 seconds
Started Aug 07 07:22:05 PM PDT 24
Finished Aug 07 07:23:32 PM PDT 24
Peak memory 256300 kb
Host smart-9d253ab4-cb4a-4179-9626-629ba1f5ce36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32163
70013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3216370013
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1376609351
Short name T281
Test name
Test status
Simulation time 2701137004 ps
CPU time 46.83 seconds
Started Aug 07 07:22:05 PM PDT 24
Finished Aug 07 07:22:52 PM PDT 24
Peak memory 248328 kb
Host smart-452f6b30-09e2-4453-a625-9b983738234d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13766
09351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1376609351
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.92671039
Short name T286
Test name
Test status
Simulation time 157129784815 ps
CPU time 2931.54 seconds
Started Aug 07 07:22:16 PM PDT 24
Finished Aug 07 08:11:08 PM PDT 24
Peak memory 288764 kb
Host smart-b7f1ee57-4a8a-4b29-b1d4-d9fd64e93f43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92671039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.92671039
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.670151444
Short name T536
Test name
Test status
Simulation time 78890487644 ps
CPU time 2021.49 seconds
Started Aug 07 07:22:17 PM PDT 24
Finished Aug 07 07:55:59 PM PDT 24
Peak memory 284192 kb
Host smart-e2430f4d-82f5-4fee-9284-7f6a39a2a912
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670151444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.670151444
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.11057915
Short name T290
Test name
Test status
Simulation time 13626075137 ps
CPU time 297.68 seconds
Started Aug 07 07:22:03 PM PDT 24
Finished Aug 07 07:27:01 PM PDT 24
Peak memory 248600 kb
Host smart-f89191e9-3467-431d-8a3b-b019e439b166
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11057915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.11057915
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1950673269
Short name T525
Test name
Test status
Simulation time 217677698 ps
CPU time 5.03 seconds
Started Aug 07 07:22:06 PM PDT 24
Finished Aug 07 07:22:12 PM PDT 24
Peak memory 240240 kb
Host smart-7c15ab12-9cb6-4124-9c60-3bb1de08b560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19506
73269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1950673269
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1488002663
Short name T497
Test name
Test status
Simulation time 200558637 ps
CPU time 4.47 seconds
Started Aug 07 07:22:05 PM PDT 24
Finished Aug 07 07:22:10 PM PDT 24
Peak memory 240288 kb
Host smart-027e0198-42f5-4871-9059-678571f0a53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14880
02663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1488002663
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2943480422
Short name T554
Test name
Test status
Simulation time 409587698 ps
CPU time 13.97 seconds
Started Aug 07 07:22:04 PM PDT 24
Finished Aug 07 07:22:18 PM PDT 24
Peak memory 247904 kb
Host smart-3a8da51d-b80d-4d76-a110-470523bd2af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
80422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2943480422
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2195604924
Short name T441
Test name
Test status
Simulation time 1467251474 ps
CPU time 27.96 seconds
Started Aug 07 07:22:04 PM PDT 24
Finished Aug 07 07:22:32 PM PDT 24
Peak memory 256608 kb
Host smart-caf8c967-7467-417c-b16c-7e53ae9d2efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21956
04924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2195604924
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2827550244
Short name T606
Test name
Test status
Simulation time 10705961697 ps
CPU time 152.57 seconds
Started Aug 07 07:22:15 PM PDT 24
Finished Aug 07 07:24:48 PM PDT 24
Peak memory 256604 kb
Host smart-fba19478-14f2-4191-b0de-5758066f4906
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827550244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2827550244
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1720680627
Short name T640
Test name
Test status
Simulation time 23018761233 ps
CPU time 1144.41 seconds
Started Aug 07 07:22:29 PM PDT 24
Finished Aug 07 07:41:34 PM PDT 24
Peak memory 285180 kb
Host smart-95fd3480-cd38-4a7c-8528-e911691d91c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720680627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1720680627
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2292974396
Short name T623
Test name
Test status
Simulation time 9528967293 ps
CPU time 151.99 seconds
Started Aug 07 07:22:28 PM PDT 24
Finished Aug 07 07:25:00 PM PDT 24
Peak memory 256772 kb
Host smart-f247d95f-f115-4ea0-addd-d26496985a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22929
74396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2292974396
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2849961067
Short name T491
Test name
Test status
Simulation time 133162297 ps
CPU time 8.51 seconds
Started Aug 07 07:22:29 PM PDT 24
Finished Aug 07 07:22:38 PM PDT 24
Peak memory 247764 kb
Host smart-c1b296fc-19ae-4743-ae40-e245ab3b4916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28499
61067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2849961067
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1623496004
Short name T288
Test name
Test status
Simulation time 27685109598 ps
CPU time 1245.16 seconds
Started Aug 07 07:22:42 PM PDT 24
Finished Aug 07 07:43:28 PM PDT 24
Peak memory 288596 kb
Host smart-402e64c7-7a10-4251-9aa6-401613e45842
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623496004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1623496004
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2720971548
Short name T566
Test name
Test status
Simulation time 16756295447 ps
CPU time 915.89 seconds
Started Aug 07 07:22:41 PM PDT 24
Finished Aug 07 07:37:57 PM PDT 24
Peak memory 273108 kb
Host smart-f9fc5221-4e85-452e-bb11-7f5367daf8c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720971548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2720971548
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2034400716
Short name T107
Test name
Test status
Simulation time 14145663986 ps
CPU time 76.27 seconds
Started Aug 07 07:22:29 PM PDT 24
Finished Aug 07 07:23:45 PM PDT 24
Peak memory 248580 kb
Host smart-7cac9d77-e74f-4024-9c83-ec0076b37ba9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034400716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2034400716
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3065892522
Short name T591
Test name
Test status
Simulation time 780318443 ps
CPU time 25.86 seconds
Started Aug 07 07:22:16 PM PDT 24
Finished Aug 07 07:22:42 PM PDT 24
Peak memory 256000 kb
Host smart-5d60130d-b268-4c13-a2e2-c96119c71ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30658
92522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3065892522
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2006502785
Short name T602
Test name
Test status
Simulation time 76715195 ps
CPU time 6.29 seconds
Started Aug 07 07:22:16 PM PDT 24
Finished Aug 07 07:22:22 PM PDT 24
Peak memory 240268 kb
Host smart-8cea1cc9-aff1-43b8-b61d-83b40bbd91a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20065
02785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2006502785
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.4063715535
Short name T386
Test name
Test status
Simulation time 3598172622 ps
CPU time 39.31 seconds
Started Aug 07 07:22:17 PM PDT 24
Finished Aug 07 07:22:56 PM PDT 24
Peak memory 256504 kb
Host smart-b4dddd9a-67b4-45e4-9100-fe8f6f4c97fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40637
15535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.4063715535
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.216125598
Short name T267
Test name
Test status
Simulation time 934351788599 ps
CPU time 3255.71 seconds
Started Aug 07 07:22:41 PM PDT 24
Finished Aug 07 08:16:58 PM PDT 24
Peak memory 301428 kb
Host smart-3b369692-c32f-4323-abc2-0e92ceb6fb7c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216125598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.216125598
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.489355965
Short name T437
Test name
Test status
Simulation time 221544345235 ps
CPU time 5812.38 seconds
Started Aug 07 07:22:41 PM PDT 24
Finished Aug 07 08:59:34 PM PDT 24
Peak memory 347088 kb
Host smart-7fd7295b-eaac-4cc7-8fde-cfd47a7b6acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489355965 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.489355965
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3543379609
Short name T197
Test name
Test status
Simulation time 35762614 ps
CPU time 2.29 seconds
Started Aug 07 07:15:19 PM PDT 24
Finished Aug 07 07:15:21 PM PDT 24
Peak memory 248692 kb
Host smart-cdd6acca-878e-4816-b275-111c41aaee6d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3543379609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3543379609
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3577374709
Short name T42
Test name
Test status
Simulation time 112953357090 ps
CPU time 1486.86 seconds
Started Aug 07 07:15:19 PM PDT 24
Finished Aug 07 07:40:06 PM PDT 24
Peak memory 273148 kb
Host smart-7d8a9c40-1dd6-4f52-84fc-bfcef970b7ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577374709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3577374709
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.184118774
Short name T642
Test name
Test status
Simulation time 186542137 ps
CPU time 6.3 seconds
Started Aug 07 07:15:20 PM PDT 24
Finished Aug 07 07:15:27 PM PDT 24
Peak memory 248396 kb
Host smart-f02f3347-ecda-4def-b409-aa15d68ff90a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=184118774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.184118774
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2716760715
Short name T377
Test name
Test status
Simulation time 5947483348 ps
CPU time 327.16 seconds
Started Aug 07 07:15:16 PM PDT 24
Finished Aug 07 07:20:43 PM PDT 24
Peak memory 256748 kb
Host smart-6efb76e4-0a95-4480-9f12-69287fd63371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
60715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2716760715
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2474787646
Short name T367
Test name
Test status
Simulation time 3384476897 ps
CPU time 25.81 seconds
Started Aug 07 07:15:20 PM PDT 24
Finished Aug 07 07:15:46 PM PDT 24
Peak memory 248120 kb
Host smart-778c2414-cb90-4155-a855-c02620d65ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24747
87646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2474787646
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3603793124
Short name T324
Test name
Test status
Simulation time 289935071041 ps
CPU time 1441.75 seconds
Started Aug 07 07:15:15 PM PDT 24
Finished Aug 07 07:39:17 PM PDT 24
Peak memory 282468 kb
Host smart-39d908b4-4722-4a1a-aa6c-e0ae1b8fa39b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603793124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3603793124
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3966790065
Short name T109
Test name
Test status
Simulation time 135436805396 ps
CPU time 2311.52 seconds
Started Aug 07 07:15:20 PM PDT 24
Finished Aug 07 07:53:52 PM PDT 24
Peak memory 281204 kb
Host smart-3fbaffb8-64d7-4eef-8e67-a53eed6ff54a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966790065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3966790065
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2285367934
Short name T308
Test name
Test status
Simulation time 33917459792 ps
CPU time 483.77 seconds
Started Aug 07 07:15:15 PM PDT 24
Finished Aug 07 07:23:19 PM PDT 24
Peak memory 248408 kb
Host smart-3390238b-7aee-448c-bda3-841397cddb56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285367934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2285367934
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.152839105
Short name T539
Test name
Test status
Simulation time 1136448623 ps
CPU time 60.59 seconds
Started Aug 07 07:15:22 PM PDT 24
Finished Aug 07 07:16:23 PM PDT 24
Peak memory 255680 kb
Host smart-15318de0-d21c-4ca5-aac4-27299f800868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15283
9105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.152839105
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2592271248
Short name T524
Test name
Test status
Simulation time 1609143954 ps
CPU time 40.93 seconds
Started Aug 07 07:15:16 PM PDT 24
Finished Aug 07 07:15:57 PM PDT 24
Peak memory 247632 kb
Host smart-4782b089-82ca-4277-a1c8-5c125be54041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25922
71248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2592271248
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2664598975
Short name T385
Test name
Test status
Simulation time 357534376 ps
CPU time 24.07 seconds
Started Aug 07 07:15:15 PM PDT 24
Finished Aug 07 07:15:39 PM PDT 24
Peak memory 248436 kb
Host smart-9037b687-000b-4fc5-8699-d09dbe7dfb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26645
98975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2664598975
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3010811458
Short name T678
Test name
Test status
Simulation time 925823153 ps
CPU time 13.99 seconds
Started Aug 07 07:15:17 PM PDT 24
Finished Aug 07 07:15:31 PM PDT 24
Peak memory 254812 kb
Host smart-2ed2b436-e5e4-4b7b-a833-546a537ce61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30108
11458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3010811458
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2734796342
Short name T269
Test name
Test status
Simulation time 233319094763 ps
CPU time 3393.81 seconds
Started Aug 07 07:15:17 PM PDT 24
Finished Aug 07 08:11:51 PM PDT 24
Peak memory 297504 kb
Host smart-4b352692-6bc4-4815-848e-ccfe3f37203e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734796342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2734796342
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3253102541
Short name T194
Test name
Test status
Simulation time 33542880 ps
CPU time 3.54 seconds
Started Aug 07 07:15:19 PM PDT 24
Finished Aug 07 07:15:22 PM PDT 24
Peak memory 248672 kb
Host smart-9238e4c7-c238-4bd7-8d9f-c24e83ca3181
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3253102541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3253102541
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3660777784
Short name T50
Test name
Test status
Simulation time 14861288818 ps
CPU time 757.66 seconds
Started Aug 07 07:15:19 PM PDT 24
Finished Aug 07 07:27:57 PM PDT 24
Peak memory 265208 kb
Host smart-a020cde8-777c-441f-a6c8-887380a5f2cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660777784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3660777784
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1867564691
Short name T658
Test name
Test status
Simulation time 1752704333 ps
CPU time 21.64 seconds
Started Aug 07 07:15:16 PM PDT 24
Finished Aug 07 07:15:38 PM PDT 24
Peak memory 248468 kb
Host smart-32398176-d7cd-411d-8927-b3c3455f89b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1867564691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1867564691
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.346102717
Short name T400
Test name
Test status
Simulation time 222271323 ps
CPU time 7.49 seconds
Started Aug 07 07:15:20 PM PDT 24
Finished Aug 07 07:15:27 PM PDT 24
Peak memory 250896 kb
Host smart-63825557-eeef-4b8e-aa8c-81934f729205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34610
2717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.346102717
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2958230706
Short name T488
Test name
Test status
Simulation time 80876819 ps
CPU time 6.2 seconds
Started Aug 07 07:15:16 PM PDT 24
Finished Aug 07 07:15:23 PM PDT 24
Peak memory 251268 kb
Host smart-c0dd4f0f-74a1-4df3-90c8-6790d9f24c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29582
30706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2958230706
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.862558305
Short name T540
Test name
Test status
Simulation time 25570190535 ps
CPU time 1489.45 seconds
Started Aug 07 07:15:19 PM PDT 24
Finished Aug 07 07:40:09 PM PDT 24
Peak memory 272444 kb
Host smart-835d1bd9-f595-4f17-8daa-7f0a57e06e84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862558305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.862558305
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3855119094
Short name T402
Test name
Test status
Simulation time 75675018109 ps
CPU time 3462.04 seconds
Started Aug 07 07:15:16 PM PDT 24
Finished Aug 07 08:12:59 PM PDT 24
Peak memory 288800 kb
Host smart-4cd0ebab-9fd8-41df-85bb-990adde78c70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855119094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3855119094
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1252104600
Short name T314
Test name
Test status
Simulation time 98252232052 ps
CPU time 218.68 seconds
Started Aug 07 07:15:17 PM PDT 24
Finished Aug 07 07:18:56 PM PDT 24
Peak memory 248540 kb
Host smart-0e6e0cab-ae2d-43ac-8ec8-39ca293d039a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252104600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1252104600
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3727243983
Short name T475
Test name
Test status
Simulation time 880592834 ps
CPU time 9.4 seconds
Started Aug 07 07:15:15 PM PDT 24
Finished Aug 07 07:15:25 PM PDT 24
Peak memory 248516 kb
Host smart-919e7fcf-26a2-4600-a54c-75d22ce0db34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37272
43983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3727243983
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1784003618
Short name T431
Test name
Test status
Simulation time 919089094 ps
CPU time 26.27 seconds
Started Aug 07 07:15:15 PM PDT 24
Finished Aug 07 07:15:42 PM PDT 24
Peak memory 256092 kb
Host smart-05f308d0-808d-4af7-bc1d-6fd5081cf72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17840
03618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1784003618
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1363865844
Short name T410
Test name
Test status
Simulation time 48752846 ps
CPU time 6.95 seconds
Started Aug 07 07:15:21 PM PDT 24
Finished Aug 07 07:15:28 PM PDT 24
Peak memory 254588 kb
Host smart-8120625e-b56a-4051-9c55-7a52c9e8c4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13638
65844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1363865844
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3842113160
Short name T459
Test name
Test status
Simulation time 9702601131 ps
CPU time 66.01 seconds
Started Aug 07 07:15:16 PM PDT 24
Finished Aug 07 07:16:22 PM PDT 24
Peak memory 256768 kb
Host smart-db334cc5-9839-4f92-9322-9a9dc6974fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38421
13160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3842113160
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2164965897
Short name T664
Test name
Test status
Simulation time 55062366313 ps
CPU time 1090.87 seconds
Started Aug 07 07:15:17 PM PDT 24
Finished Aug 07 07:33:28 PM PDT 24
Peak memory 287532 kb
Host smart-640b24a5-d081-40d2-bc99-672352401697
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164965897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2164965897
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3769777640
Short name T191
Test name
Test status
Simulation time 77731013 ps
CPU time 2.86 seconds
Started Aug 07 07:15:17 PM PDT 24
Finished Aug 07 07:15:20 PM PDT 24
Peak memory 248696 kb
Host smart-44dfc921-cb9d-494a-8cff-d6cc950049f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3769777640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3769777640
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1001416864
Short name T653
Test name
Test status
Simulation time 105876185474 ps
CPU time 1666.74 seconds
Started Aug 07 07:15:21 PM PDT 24
Finished Aug 07 07:43:08 PM PDT 24
Peak memory 272488 kb
Host smart-1b2edead-c3bb-4705-a4ef-ae3153fecc5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001416864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1001416864
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2747591645
Short name T398
Test name
Test status
Simulation time 2877791844 ps
CPU time 62.21 seconds
Started Aug 07 07:15:19 PM PDT 24
Finished Aug 07 07:16:21 PM PDT 24
Peak memory 248564 kb
Host smart-f73ce69a-9c2a-48ee-901c-05d28c2ff5da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2747591645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2747591645
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.4154227349
Short name T403
Test name
Test status
Simulation time 268206591 ps
CPU time 22.54 seconds
Started Aug 07 07:15:18 PM PDT 24
Finished Aug 07 07:15:40 PM PDT 24
Peak memory 255844 kb
Host smart-74c1ced5-da7b-47b4-960a-33b461f495ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41542
27349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.4154227349
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2886961437
Short name T593
Test name
Test status
Simulation time 828349584 ps
CPU time 21.19 seconds
Started Aug 07 07:15:18 PM PDT 24
Finished Aug 07 07:15:39 PM PDT 24
Peak memory 255204 kb
Host smart-99d73802-e0f6-4f99-a6a5-9af1a95a23bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28869
61437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2886961437
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4049187479
Short name T331
Test name
Test status
Simulation time 44322319368 ps
CPU time 1235.85 seconds
Started Aug 07 07:15:19 PM PDT 24
Finished Aug 07 07:35:55 PM PDT 24
Peak memory 281400 kb
Host smart-8dfdb431-cd13-4fe5-9e45-d4bd63388c9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049187479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4049187479
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3108548505
Short name T543
Test name
Test status
Simulation time 5539467848 ps
CPU time 619.32 seconds
Started Aug 07 07:15:16 PM PDT 24
Finished Aug 07 07:25:36 PM PDT 24
Peak memory 273068 kb
Host smart-228994ff-f6a0-4d43-a771-521c40b1354d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108548505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3108548505
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3635137458
Short name T426
Test name
Test status
Simulation time 7316815866 ps
CPU time 288.99 seconds
Started Aug 07 07:15:21 PM PDT 24
Finished Aug 07 07:20:10 PM PDT 24
Peak memory 248556 kb
Host smart-2dc39d9a-3bf9-471a-86a2-03d273a686ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635137458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3635137458
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3255706809
Short name T379
Test name
Test status
Simulation time 2222855460 ps
CPU time 40.49 seconds
Started Aug 07 07:15:21 PM PDT 24
Finished Aug 07 07:16:01 PM PDT 24
Peak memory 255972 kb
Host smart-a9bea9ad-8ba1-4795-8672-98d3cf14b3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32557
06809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3255706809
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2112628600
Short name T284
Test name
Test status
Simulation time 462482949 ps
CPU time 29.76 seconds
Started Aug 07 07:15:15 PM PDT 24
Finished Aug 07 07:15:45 PM PDT 24
Peak memory 248816 kb
Host smart-e317be56-0c23-437c-8bc0-19d0d895b5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21126
28600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2112628600
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3493499393
Short name T360
Test name
Test status
Simulation time 7278460807 ps
CPU time 48.86 seconds
Started Aug 07 07:15:17 PM PDT 24
Finished Aug 07 07:16:06 PM PDT 24
Peak memory 255796 kb
Host smart-04d763c0-00b6-4857-942d-0563a1ac2b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34934
99393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3493499393
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3658969629
Short name T534
Test name
Test status
Simulation time 106846894199 ps
CPU time 1288.37 seconds
Started Aug 07 07:15:19 PM PDT 24
Finished Aug 07 07:36:48 PM PDT 24
Peak memory 285800 kb
Host smart-bfe3d304-8896-456a-91ef-94ac5f5dbdc1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658969629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3658969629
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3418767140
Short name T205
Test name
Test status
Simulation time 173180001 ps
CPU time 2.33 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 07:15:29 PM PDT 24
Peak memory 248724 kb
Host smart-1ce960c1-a4aa-439c-bba4-e11a10aba870
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3418767140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3418767140
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1818053318
Short name T657
Test name
Test status
Simulation time 25798428267 ps
CPU time 1303.78 seconds
Started Aug 07 07:15:28 PM PDT 24
Finished Aug 07 07:37:12 PM PDT 24
Peak memory 273088 kb
Host smart-0dfec20a-e680-47c4-b431-661f3ba81231
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818053318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1818053318
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1719297224
Short name T452
Test name
Test status
Simulation time 1119901751 ps
CPU time 14.74 seconds
Started Aug 07 07:15:28 PM PDT 24
Finished Aug 07 07:15:43 PM PDT 24
Peak memory 248388 kb
Host smart-db7327ff-9f81-4955-8c04-0fb92e370436
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1719297224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1719297224
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4177897561
Short name T660
Test name
Test status
Simulation time 1259788390 ps
CPU time 58.27 seconds
Started Aug 07 07:15:24 PM PDT 24
Finished Aug 07 07:16:23 PM PDT 24
Peak memory 256664 kb
Host smart-e6531392-d28e-424e-af5b-83c3b240a569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41778
97561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4177897561
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3592461237
Short name T470
Test name
Test status
Simulation time 694040285 ps
CPU time 37.77 seconds
Started Aug 07 07:15:25 PM PDT 24
Finished Aug 07 07:16:03 PM PDT 24
Peak memory 248520 kb
Host smart-f8bb86e6-76ff-499a-8f91-27b3b756de4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35924
61237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3592461237
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1669022707
Short name T605
Test name
Test status
Simulation time 163879218757 ps
CPU time 2697.05 seconds
Started Aug 07 07:15:28 PM PDT 24
Finished Aug 07 08:00:26 PM PDT 24
Peak memory 288708 kb
Host smart-3039bf69-3c98-4a64-88cf-4308d2f5db92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669022707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1669022707
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2928259109
Short name T294
Test name
Test status
Simulation time 26886262548 ps
CPU time 311.5 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 07:20:37 PM PDT 24
Peak memory 248492 kb
Host smart-8cab63e3-adc3-4ab8-bf83-af9589e6bd8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928259109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2928259109
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.4262421498
Short name T553
Test name
Test status
Simulation time 638218095 ps
CPU time 20.2 seconds
Started Aug 07 07:15:29 PM PDT 24
Finished Aug 07 07:15:50 PM PDT 24
Peak memory 248504 kb
Host smart-90e0a50e-830a-4995-8ab9-b7fcbcc11738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42624
21498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.4262421498
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1188467319
Short name T575
Test name
Test status
Simulation time 3128836187 ps
CPU time 39.93 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 07:16:06 PM PDT 24
Peak memory 256052 kb
Host smart-bd22877c-8006-4527-bf2c-83993dc5367e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11884
67319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1188467319
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.781245452
Short name T393
Test name
Test status
Simulation time 1201102225 ps
CPU time 20.95 seconds
Started Aug 07 07:15:25 PM PDT 24
Finished Aug 07 07:15:46 PM PDT 24
Peak memory 256160 kb
Host smart-0e1602dc-e3fe-42f8-b412-276a2d6be849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78124
5452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.781245452
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.10007551
Short name T404
Test name
Test status
Simulation time 861319071 ps
CPU time 51.84 seconds
Started Aug 07 07:15:16 PM PDT 24
Finished Aug 07 07:16:08 PM PDT 24
Peak memory 256572 kb
Host smart-8b3ebb0c-5bee-45a9-b73d-bedbf7bd3b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10007
551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.10007551
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.559491257
Short name T4
Test name
Test status
Simulation time 37243244502 ps
CPU time 2362.57 seconds
Started Aug 07 07:15:25 PM PDT 24
Finished Aug 07 07:54:48 PM PDT 24
Peak memory 272608 kb
Host smart-0cf89383-5670-49ab-b245-b33932736962
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559491257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.559491257
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2892220760
Short name T201
Test name
Test status
Simulation time 14537327 ps
CPU time 2.58 seconds
Started Aug 07 07:15:24 PM PDT 24
Finished Aug 07 07:15:27 PM PDT 24
Peak memory 248632 kb
Host smart-29495b5f-b83c-44c0-9c20-02c23f8b6d2e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2892220760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2892220760
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3653166536
Short name T52
Test name
Test status
Simulation time 68757420927 ps
CPU time 1228.05 seconds
Started Aug 07 07:15:25 PM PDT 24
Finished Aug 07 07:35:53 PM PDT 24
Peak memory 281372 kb
Host smart-6ba39ca3-fb74-48f5-86ea-418387624218
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653166536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3653166536
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2853024617
Short name T651
Test name
Test status
Simulation time 413952890 ps
CPU time 9.84 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 07:15:36 PM PDT 24
Peak memory 248476 kb
Host smart-55b1c6a8-bed3-4a14-bee9-43b4013ad85d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2853024617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2853024617
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3226048290
Short name T2
Test name
Test status
Simulation time 10729731055 ps
CPU time 322.74 seconds
Started Aug 07 07:15:30 PM PDT 24
Finished Aug 07 07:20:53 PM PDT 24
Peak memory 255956 kb
Host smart-b5f78f63-78e6-4ac3-8051-be49270fbe00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260
48290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3226048290
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1926235245
Short name T111
Test name
Test status
Simulation time 1059028160 ps
CPU time 56.46 seconds
Started Aug 07 07:15:27 PM PDT 24
Finished Aug 07 07:16:23 PM PDT 24
Peak memory 256696 kb
Host smart-afbde710-a808-419d-800b-6bb69ae3cb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19262
35245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1926235245
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2001269019
Short name T501
Test name
Test status
Simulation time 44410117151 ps
CPU time 2916.45 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 08:04:03 PM PDT 24
Peak memory 289348 kb
Host smart-fcb3ac3e-ae2c-483d-a0bf-44271b1ff326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001269019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2001269019
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3326181940
Short name T616
Test name
Test status
Simulation time 40674193546 ps
CPU time 223.67 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 07:19:10 PM PDT 24
Peak memory 248476 kb
Host smart-5a879e80-eb55-4b10-a60b-73ee5ac9dc74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326181940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3326181940
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2330517791
Short name T354
Test name
Test status
Simulation time 1747987315 ps
CPU time 32.42 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 07:15:58 PM PDT 24
Peak memory 256536 kb
Host smart-55d39195-cb69-4405-adfd-cea88e600ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23305
17791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2330517791
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.22979124
Short name T56
Test name
Test status
Simulation time 2912708413 ps
CPU time 60.6 seconds
Started Aug 07 07:15:27 PM PDT 24
Finished Aug 07 07:16:28 PM PDT 24
Peak memory 256340 kb
Host smart-c345005a-1c01-48ea-89db-f06de720eb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.22979124
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2363400606
Short name T476
Test name
Test status
Simulation time 1103649466 ps
CPU time 42.35 seconds
Started Aug 07 07:15:24 PM PDT 24
Finished Aug 07 07:16:06 PM PDT 24
Peak memory 255816 kb
Host smart-c26cd217-2b4e-4362-8fa5-7eb6b3d60184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23634
00606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2363400606
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.926434013
Short name T530
Test name
Test status
Simulation time 1041546189 ps
CPU time 16.69 seconds
Started Aug 07 07:15:26 PM PDT 24
Finished Aug 07 07:15:42 PM PDT 24
Peak memory 253288 kb
Host smart-bb67a0e8-0b0a-4ca9-acbf-c72f0c95af3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92643
4013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.926434013
Directory /workspace/9.alert_handler_smoke/latest
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