Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	73305	1			T11	19		T4	3689		T14	1
class_i[0x1]	57328	1			T12	316		T4	753		T14	1
class_i[0x2]	33065	1			T3	4		T11	8		T12	6
class_i[0x3]	34824	1			T3	5		T5	47		T49	7

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	50558	1			T3	1		T11	4		T12	253
alert[0x1]	49923	1			T11	11		T12	18		T4	1025
alert[0x2]	51130	1			T3	3		T11	2		T12	34
alert[0x3]	46911	1			T3	5		T11	10		T12	17

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

198241

1

T3

4

T11

19

T12

322

esc_ping_fail

281

1

T3

5

T11

8

T14

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	50482	1			T11	3		T12	253		T4	1066
esc_integrity_fail	alert[0x1]	49853	1			T11	8		T12	18		T4	1025
esc_integrity_fail	alert[0x2]	51059	1			T3	2		T11	1		T12	34
esc_integrity_fail	alert[0x3]	46847	1			T3	2		T11	7		T12	17
esc_ping_fail	alert[0x0]	76	1			T3	1		T11	1		T14	1
esc_ping_fail	alert[0x1]	70	1			T11	3		T14	1		T196	1
esc_ping_fail	alert[0x2]	71	1			T3	1		T11	1		T196	1
esc_ping_fail	alert[0x3]	64	1			T3	3		T11	3		T237	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	73241	1			T11	19		T4	3689		T5	8
esc_integrity_fail	class_i[0x1]	57223	1			T12	316		T4	753		T49	12
esc_integrity_fail	class_i[0x2]	33000	1			T3	4		T12	6		T4	444
esc_integrity_fail	class_i[0x3]	34777	1			T5	47		T49	7		T90	2
esc_ping_fail	class_i[0x0]	64	1			T14	1		T196	1		T320	1
esc_ping_fail	class_i[0x1]	105	1			T14	1		T196	2		T224	2
esc_ping_fail	class_i[0x2]	65	1			T11	8		T237	3		T226	7
esc_ping_fail	class_i[0x3]	47	1			T3	5		T320	8		T313	1