Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	60	1			T12	1		T4	1		T22	1
class_index[0x1]	41	1			T22	1		T31	1		T25	1
class_index[0x2]	55	1			T77	1		T25	1		T80	1
class_index[0x3]	41	1			T77	1		T31	2		T79	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	65	1			T77	1		T81	2		T28	2
intr_timeout_cnt[1]	63	1			T4	1		T22	1		T77	1
intr_timeout_cnt[2]	15	1			T22	1		T31	2		T32	1
intr_timeout_cnt[3]	11	1			T77	1		T86	1		T110	1
intr_timeout_cnt[4]	7	1			T31	1		T25	1		T55	1
intr_timeout_cnt[5]	14	1			T80	1		T84	1		T57	1
intr_timeout_cnt[6]	9	1			T82	1		T33	1		T191	2
intr_timeout_cnt[7]	5	1			T12	1		T192	1		T122	1
intr_timeout_cnt[8]	4	1			T255	1		T256	1		T257	1
intr_timeout_cnt[9]	4	1			T258	2		T259	1		T260	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	20	1			T81	1		T57	4		T58	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T4	1		T77	1		T50	2
class_index[0x0]	intr_timeout_cnt[2]	4	1			T22	1		T32	1		T261	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T192	1		T262	1		T263	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T55	1		T258	1		T264	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T95	2		T249	1		T260	1
class_index[0x0]	intr_timeout_cnt[6]	5	1			T191	2		T265	1		T266	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T12	1		T267	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T257	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T258	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	9	1			T57	1		T268	1		T269	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T22	1		T25	1		T28	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T31	1		T270	1		T271	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T110	1		T254	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	4	1			T84	1		T272	1		T273	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T82	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T192	1		T122	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T256	1		T274	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T259	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	20	1			T77	1		T81	1		T56	3
class_index[0x2]	intr_timeout_cnt[1]	18	1			T23	2		T275	1		T249	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T276	1		T277	1		T278	3
class_index[0x2]	intr_timeout_cnt[3]	4	1			T86	1		T122	1		T279	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T25	1		T265	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T80	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T33	1		T280	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T281	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T260	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	16	1			T28	2		T57	1		T33	1
class_index[0x3]	intr_timeout_cnt[1]	14	1			T79	1		T28	1		T126	1
class_index[0x3]	intr_timeout_cnt[2]	1	1			T31	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[3]	2	1			T77	1		T274	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T31	1		T120	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	4	1			T57	1		T282	1		T283	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T284	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T255	1		-	-		-	-