Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287806	1			T1	1117		T2	1157		T3	37
all_values[1]	287806	1			T1	1117		T2	1157		T3	37
all_values[2]	287806	1			T1	1117		T2	1157		T3	37
all_values[3]	287806	1			T1	1117		T2	1157		T3	37

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

572562

1

T1

2218

T2

2268

T10

66

auto[1]

578662

1

T1

2250

T2

2360

T3

148

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686308

1

T1

2971

T2

3613

T3

128

auto[1]

464916

1

T1

1497

T2

1015

T3

20

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	84140	1			T1	360		T2	532		T10	9
all_values[0]	auto[0]	auto[1]	59077	1			T1	214		T10	8		T17	3
all_values[0]	auto[1]	auto[0]	85254	1			T1	335		T2	625		T3	37
all_values[0]	auto[1]	auto[1]	59335	1			T1	208		T10	8		T11	10
all_values[1]	auto[0]	auto[0]	85361	1			T1	344		T2	424		T10	6
all_values[1]	auto[0]	auto[1]	57292	1			T1	204		T2	153		T10	6
all_values[1]	auto[1]	auto[0]	87564	1			T1	363		T2	423		T3	37
all_values[1]	auto[1]	auto[1]	57589	1			T1	206		T2	157		T10	9
all_values[2]	auto[0]	auto[0]	86120	1			T1	357		T2	352		T10	9
all_values[2]	auto[0]	auto[1]	57265	1			T1	198		T2	193		T10	9
all_values[2]	auto[1]	auto[0]	87249	1			T1	366		T2	373		T3	34
all_values[2]	auto[1]	auto[1]	57172	1			T1	196		T2	239		T3	3
all_values[3]	auto[0]	auto[0]	84881	1			T1	408		T2	477		T10	10
all_values[3]	auto[0]	auto[1]	58426	1			T1	133		T2	137		T10	9
all_values[3]	auto[1]	auto[0]	85739	1			T1	438		T2	407		T3	20
all_values[3]	auto[1]	auto[1]	58760	1			T1	138		T2	136		T3	17