Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	287806	1			T1	1117		T2	1157		T3	37
all_pins[1]	287806	1			T1	1117		T2	1157		T3	37
all_pins[2]	287806	1			T1	1117		T2	1157		T3	37
all_pins[3]	287806	1			T1	1117		T2	1157		T3	37

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	918368	1			T1	3720		T2	4096		T3	128
values[0x1]	232856	1			T1	748		T2	532		T3	20
transitions[0x0=>0x1]	155058	1			T1	550		T2	407		T3	18
transitions[0x1=>0x0]	155319	1			T1	550		T2	407		T3	18

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	228471	1			T1	909		T2	1157		T3	37
all_pins[0]	values[0x1]	59335	1			T1	208		T10	8		T11	10
all_pins[0]	transitions[0x0=>0x1]	58807	1			T1	208		T10	7		T11	10
all_pins[0]	transitions[0x1=>0x0]	58493	1			T1	138		T2	136		T3	17
all_pins[1]	values[0x0]	230217	1			T1	911		T2	1000		T3	37
all_pins[1]	values[0x1]	57589	1			T1	206		T2	157		T10	9
all_pins[1]	transitions[0x0=>0x1]	31883	1			T1	123		T2	157		T10	5
all_pins[1]	transitions[0x1=>0x0]	33629	1			T1	125		T10	4		T11	10
all_pins[2]	values[0x0]	230634	1			T1	921		T2	918		T3	34
all_pins[2]	values[0x1]	57172	1			T1	196		T2	239		T3	3
all_pins[2]	transitions[0x0=>0x1]	31533	1			T1	129		T2	170		T3	3
all_pins[2]	transitions[0x1=>0x0]	31950	1			T1	139		T2	88		T10	5
all_pins[3]	values[0x0]	229046	1			T1	979		T2	1021		T3	20
all_pins[3]	values[0x1]	58760	1			T1	138		T2	136		T3	17
all_pins[3]	transitions[0x0=>0x1]	32835	1			T1	90		T2	80		T3	15
all_pins[3]	transitions[0x1=>0x0]	31247	1			T1	148		T2	183		T3	1