Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 24 0 24 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 4 0 4 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 24 0 24 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 263 1 T171 7 T172 4 T173 7
all_values[1] 263 1 T171 7 T172 4 T173 7
all_values[2] 263 1 T171 7 T172 4 T173 7
all_values[3] 263 1 T171 7 T172 4 T173 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 561 1 T171 14 T172 9 T173 20
auto[1] 491 1 T171 14 T172 7 T173 8



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 454 1 T171 8 T172 8 T173 15
auto[1] 598 1 T171 20 T172 8 T173 13



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 646 1 T171 15 T172 11 T173 20
auto[1] 406 1 T171 13 T172 5 T173 8



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 24 0 24 100.00
Automatically Generated Cross Bins 24 0 24 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 65 1 T173 2 T231 2 T355 5
all_values[0] auto[0] auto[0] auto[1] 24 1 T171 1 T172 1 T231 2
all_values[0] auto[0] auto[1] auto[0] 54 1 T172 2 T173 1 T355 1
all_values[0] auto[0] auto[1] auto[1] 22 1 T171 2 T173 1 T356 1
all_values[0] auto[1] auto[0] auto[1] 59 1 T173 3 T231 2 T355 1
all_values[0] auto[1] auto[1] auto[1] 39 1 T171 4 T172 1 T231 1
all_values[1] auto[0] auto[0] auto[0] 63 1 T172 2 T173 4 T357 3
all_values[1] auto[0] auto[0] auto[1] 30 1 T171 2 T231 1 T355 4
all_values[1] auto[0] auto[1] auto[0] 44 1 T172 2 T173 2 T358 4
all_values[1] auto[0] auto[1] auto[1] 25 1 T171 1 T231 1 T357 1
all_values[1] auto[1] auto[0] auto[1] 58 1 T171 2 T173 1 T231 4
all_values[1] auto[1] auto[1] auto[1] 43 1 T171 2 T231 1 T355 1
all_values[2] auto[0] auto[0] auto[0] 47 1 T171 4 T172 1 T173 2
all_values[2] auto[0] auto[0] auto[1] 32 1 T172 1 T173 2 T231 1
all_values[2] auto[0] auto[1] auto[0] 59 1 T171 1 T173 1 T355 2
all_values[2] auto[0] auto[1] auto[1] 20 1 T231 2 T359 1 T360 1
all_values[2] auto[1] auto[0] auto[1] 52 1 T171 2 T172 2 T173 1
all_values[2] auto[1] auto[1] auto[1] 53 1 T173 1 T231 1 T355 2
all_values[3] auto[0] auto[0] auto[0] 65 1 T171 2 T173 2 T357 3
all_values[3] auto[0] auto[0] auto[1] 15 1 T173 1 T231 1 T355 1
all_values[3] auto[0] auto[1] auto[0] 57 1 T171 1 T172 1 T173 1
all_values[3] auto[0] auto[1] auto[1] 24 1 T171 1 T172 1 T173 1
all_values[3] auto[1] auto[0] auto[1] 51 1 T171 1 T172 2 T173 2
all_values[3] auto[1] auto[1] auto[1] 51 1 T171 2 T231 2 T358 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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