Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	82591	1			T4	1209		T13	1039		T5	891
accum_cnt_1000	177476	1			T1	1336		T2	532		T4	1394
accum_cnt_100	20547	1			T1	151		T2	182		T12	3
accum_cnt_50	59933	1			T1	141		T2	131		T10	56
accum_cnt_10	147028	1			T1	855		T2	1752		T3	9
accum_cnt_0	321126	1			T1	857		T2	883		T3	91

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	213206	1			T1	835		T2	870		T3	25
class_index[0x1]	213206	1			T1	835		T2	870		T3	25
class_index[0x2]	213206	1			T1	835		T2	870		T3	25
class_index[0x3]	213206	1			T1	835		T2	870		T3	25

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22229	1			T4	240		T13	239		T21	506
class_index[0x0]	accum_cnt_1000	45299	1			T1	677		T4	226		T13	525
class_index[0x0]	accum_cnt_100	5790	1			T1	67		T4	7		T13	28
class_index[0x0]	accum_cnt_50	17379	1			T1	64		T10	16		T11	5
class_index[0x0]	accum_cnt_10	33819	1			T1	21		T10	10		T11	32
class_index[0x0]	accum_cnt_0	73227	1			T1	6		T2	870		T3	25
class_index[0x1]	accum_cnt_2000	21038	1			T13	157		T5	380		T16	134
class_index[0x1]	accum_cnt_1000	43707	1			T4	70		T44	51		T13	597
class_index[0x1]	accum_cnt_100	4549	1			T12	3		T4	22		T44	20
class_index[0x1]	accum_cnt_50	17235	1			T12	14		T19	7		T20	10
class_index[0x1]	accum_cnt_10	27996	1			T2	866		T10	24		T12	4
class_index[0x1]	accum_cnt_0	88838	1			T1	835		T2	4		T3	25
class_index[0x2]	accum_cnt_2000	19974	1			T4	450		T13	273		T21	624
class_index[0x2]	accum_cnt_1000	42740	1			T1	659		T4	592		T44	46
class_index[0x2]	accum_cnt_100	5098	1			T1	84		T4	59		T44	23
class_index[0x2]	accum_cnt_50	12384	1			T1	77		T10	20		T12	9
class_index[0x2]	accum_cnt_10	47479	1			T1	12		T2	861		T3	3
class_index[0x2]	accum_cnt_0	76970	1			T1	3		T2	9		T3	22
class_index[0x3]	accum_cnt_2000	19350	1			T4	519		T13	370		T5	511
class_index[0x3]	accum_cnt_1000	45730	1			T2	532		T4	506		T13	404
class_index[0x3]	accum_cnt_100	5110	1			T2	182		T4	26		T13	18
class_index[0x3]	accum_cnt_50	12935	1			T2	131		T10	20		T17	4
class_index[0x3]	accum_cnt_10	37734	1			T1	822		T2	25		T3	6
class_index[0x3]	accum_cnt_0	82091	1			T1	13		T3	19		T10	2