Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7953	1			T4	10		T5	215		T31	30
alert[0x1]	7356	1			T31	1		T234	15		T81	65
alert[0x2]	3170	1			T78	634		T226	3		T310	41
alert[0x3]	7003	1			T4	9		T5	238		T49	126
alert[0x4]	17120	1			T3	1		T11	1		T78	5
alert[0x5]	8689	1			T11	1		T4	2		T49	57
alert[0x6]	13475	1			T5	268		T49	25		T74	597
alert[0x7]	4129	1			T5	7		T90	2		T31	15
alert[0x8]	4391	1			T11	1		T5	118		T49	29
alert[0x9]	8704	1			T64	4		T5	8		T78	42
alert[0xa]	3001	1			T1	1		T4	6		T5	4
alert[0xb]	7404	1			T4	1		T49	214		T116	3
alert[0xc]	4175	1			T11	1		T46	49		T64	3
alert[0xd]	2513	1			T3	1		T46	5		T5	248
alert[0xe]	2211	1			T75	24		T81	126		T32	132
alert[0xf]	3878	1			T3	1		T12	9		T49	58
alert[0x10]	5914	1			T74	46		T234	384		T242	470
alert[0x11]	1225	1			T11	1		T4	3		T49	30
alert[0x12]	8207	1			T49	164		T31	2		T74	48
alert[0x13]	3177	1			T3	1		T12	1		T4	5
alert[0x14]	3121	1			T11	2		T5	25		T78	243
alert[0x15]	3494	1			T12	2		T5	120		T49	1
alert[0x16]	4973	1			T3	1		T4	24		T46	8
alert[0x17]	11601	1			T12	23		T4	3		T49	134
alert[0x18]	6734	1			T5	102		T78	102		T74	14
alert[0x19]	7711	1			T49	229		T90	2		T31	2
alert[0x1a]	4010	1			T46	1		T49	21		T74	1050
alert[0x1b]	6070	1			T3	1		T64	7		T5	78
alert[0x1c]	5621	1			T11	1		T4	5		T5	39
alert[0x1d]	5843	1			T12	2		T4	122		T5	87
alert[0x1e]	3839	1			T12	8		T24	1		T74	118
alert[0x1f]	2726	1			T49	384		T31	4		T78	62
alert[0x20]	4498	1			T11	1		T12	1		T4	3
alert[0x21]	9697	1			T11	1		T4	5		T5	506
alert[0x22]	3969	1			T5	14		T31	1		T24	11
alert[0x23]	5571	1			T4	25		T5	41		T24	3
alert[0x24]	5408	1			T11	1		T31	3		T78	47
alert[0x25]	8404	1			T3	1		T5	27		T78	84
alert[0x26]	3253	1			T5	43		T74	65		T242	416
alert[0x27]	3715	1			T12	14		T49	171		T196	1
alert[0x28]	6054	1			T3	1		T5	43		T68	2
alert[0x29]	2881	1			T12	3		T5	231		T49	9
alert[0x2a]	5287	1			T3	1		T5	114		T197	1
alert[0x2b]	12081	1			T49	4		T78	521		T74	4
alert[0x2c]	6254	1			T49	39		T73	1		T78	8
alert[0x2d]	3083	1			T49	6		T77	3		T226	1
alert[0x2e]	2699	1			T14	1		T5	24		T90	2
alert[0x2f]	4710	1			T46	1		T90	4		T74	21
alert[0x30]	3178	1			T11	2		T49	25		T78	582
alert[0x31]	6603	1			T3	1		T11	1		T12	1
alert[0x32]	2567	1			T5	59		T49	26		T78	1076
alert[0x33]	4176	1			T11	1		T78	748		T51	1
alert[0x34]	3091	1			T12	2		T5	586		T78	242
alert[0x35]	3876	1			T14	1		T49	4		T74	25
alert[0x36]	1836	1			T11	1		T5	42		T49	21
alert[0x37]	8218	1			T5	278		T31	2		T234	849
alert[0x38]	8068	1			T14	1		T49	1735		T78	945
alert[0x39]	6138	1			T4	2		T78	2600		T50	3
alert[0x3a]	4798	1			T3	1		T49	28		T75	2343
alert[0x3b]	8605	1			T46	2		T5	239		T74	1106
alert[0x3c]	1859	1			T46	2		T49	66		T78	64
alert[0x3d]	3317	1			T11	1		T4	1		T5	93
alert[0x3e]	5185	1			T3	1		T12	3		T49	146
alert[0x3f]	9079	1			T3	1		T5	95		T49	302
alert[0x40]	10895	1			T5	1882		T49	234		T90	17

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	142605	1			T11	2		T12	24		T4	147
class_i[0x1]	58582	1			T1	1		T11	1		T12	25
class_i[0x2]	96063	1			T3	1		T12	4		T4	24
class_i[0x3]	71241	1			T3	12		T11	14		T12	16

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

367800

1

T12

69

T4

226

T46

71

alert_ping_fail

691

1

T1

1

T3

13

T11

17

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7941	1			T4	10		T5	215		T31	30
alert_integrity_fail	alert[0x1]	7341	1			T31	1		T234	15		T81	65
alert_integrity_fail	alert[0x2]	3155	1			T78	634		T310	41		T58	12
alert_integrity_fail	alert[0x3]	6990	1			T4	9		T5	238		T49	126
alert_integrity_fail	alert[0x4]	17112	1			T78	5		T74	3674		T50	3
alert_integrity_fail	alert[0x5]	8681	1			T4	2		T49	57		T78	57
alert_integrity_fail	alert[0x6]	13461	1			T5	268		T49	25		T74	597
alert_integrity_fail	alert[0x7]	4118	1			T5	7		T90	2		T31	15
alert_integrity_fail	alert[0x8]	4364	1			T5	118		T49	29		T78	37
alert_integrity_fail	alert[0x9]	8689	1			T64	4		T5	8		T78	42
alert_integrity_fail	alert[0xa]	2982	1			T4	6		T5	4		T49	155
alert_integrity_fail	alert[0xb]	7393	1			T4	1		T49	214		T116	3
alert_integrity_fail	alert[0xc]	4161	1			T46	49		T64	3		T24	11
alert_integrity_fail	alert[0xd]	2502	1			T46	5		T5	248		T68	16
alert_integrity_fail	alert[0xe]	2201	1			T75	24		T81	126		T32	132
alert_integrity_fail	alert[0xf]	3867	1			T12	9		T49	58		T74	67
alert_integrity_fail	alert[0x10]	5904	1			T74	46		T234	384		T242	470
alert_integrity_fail	alert[0x11]	1221	1			T4	3		T49	30		T78	87
alert_integrity_fail	alert[0x12]	8202	1			T49	164		T31	2		T74	48
alert_integrity_fail	alert[0x13]	3166	1			T12	1		T4	5		T5	2
alert_integrity_fail	alert[0x14]	3108	1			T5	25		T78	243		T74	11
alert_integrity_fail	alert[0x15]	3483	1			T12	2		T5	120		T49	1
alert_integrity_fail	alert[0x16]	4955	1			T4	24		T46	8		T5	15
alert_integrity_fail	alert[0x17]	11585	1			T12	23		T4	3		T49	134
alert_integrity_fail	alert[0x18]	6725	1			T5	102		T78	102		T74	14
alert_integrity_fail	alert[0x19]	7703	1			T49	229		T90	2		T31	2
alert_integrity_fail	alert[0x1a]	4001	1			T46	1		T49	21		T74	1050
alert_integrity_fail	alert[0x1b]	6060	1			T64	7		T5	78		T49	56
alert_integrity_fail	alert[0x1c]	5614	1			T4	5		T5	39		T49	2
alert_integrity_fail	alert[0x1d]	5838	1			T12	2		T4	122		T5	87
alert_integrity_fail	alert[0x1e]	3829	1			T12	8		T24	1		T74	118
alert_integrity_fail	alert[0x1f]	2715	1			T49	384		T31	4		T78	62
alert_integrity_fail	alert[0x20]	4488	1			T12	1		T4	3		T46	3
alert_integrity_fail	alert[0x21]	9689	1			T4	5		T5	506		T31	5
alert_integrity_fail	alert[0x22]	3964	1			T5	14		T31	1		T24	11
alert_integrity_fail	alert[0x23]	5564	1			T4	25		T5	41		T24	3
alert_integrity_fail	alert[0x24]	5400	1			T31	3		T78	47		T74	531
alert_integrity_fail	alert[0x25]	8395	1			T5	27		T78	84		T74	624
alert_integrity_fail	alert[0x26]	3244	1			T5	43		T74	65		T242	416
alert_integrity_fail	alert[0x27]	3701	1			T12	14		T49	171		T24	7
alert_integrity_fail	alert[0x28]	6040	1			T5	43		T68	2		T74	254
alert_integrity_fail	alert[0x29]	2866	1			T12	3		T5	231		T49	9
alert_integrity_fail	alert[0x2a]	5273	1			T5	114		T50	94		T25	2
alert_integrity_fail	alert[0x2b]	12069	1			T49	4		T78	521		T74	4
alert_integrity_fail	alert[0x2c]	6240	1			T49	39		T78	8		T234	159
alert_integrity_fail	alert[0x2d]	3071	1			T49	6		T77	3		T310	55
alert_integrity_fail	alert[0x2e]	2688	1			T5	24		T90	2		T31	9
alert_integrity_fail	alert[0x2f]	4702	1			T46	1		T90	4		T74	21
alert_integrity_fail	alert[0x30]	3168	1			T49	25		T78	582		T25	1
alert_integrity_fail	alert[0x31]	6592	1			T12	1		T31	3		T74	594
alert_integrity_fail	alert[0x32]	2553	1			T5	59		T49	26		T78	1076
alert_integrity_fail	alert[0x33]	4166	1			T78	748		T51	1		T234	53
alert_integrity_fail	alert[0x34]	3088	1			T12	2		T5	586		T78	242
alert_integrity_fail	alert[0x35]	3871	1			T49	4		T74	25		T80	1
alert_integrity_fail	alert[0x36]	1827	1			T5	42		T49	21		T90	1
alert_integrity_fail	alert[0x37]	8210	1			T5	278		T31	2		T234	849
alert_integrity_fail	alert[0x38]	8055	1			T49	1735		T78	945		T74	174
alert_integrity_fail	alert[0x39]	6127	1			T4	2		T78	2600		T50	3
alert_integrity_fail	alert[0x3a]	4789	1			T49	28		T75	2343		T105	8
alert_integrity_fail	alert[0x3b]	8597	1			T46	2		T5	239		T74	1106
alert_integrity_fail	alert[0x3c]	1851	1			T46	2		T49	66		T78	64
alert_integrity_fail	alert[0x3d]	3308	1			T4	1		T5	93		T90	1
alert_integrity_fail	alert[0x3e]	5174	1			T12	3		T49	146		T77	3
alert_integrity_fail	alert[0x3f]	9074	1			T5	95		T49	302		T75	4
alert_integrity_fail	alert[0x40]	10889	1			T5	1882		T49	234		T90	17
alert_ping_fail	alert[0x0]	12	1			T229	1		T311	1		T312	1
alert_ping_fail	alert[0x1]	15	1			T229	1		T313	1		T314	1
alert_ping_fail	alert[0x2]	15	1			T226	3		T315	1		T311	1
alert_ping_fail	alert[0x3]	13	1			T226	1		T313	2		T104	1
alert_ping_fail	alert[0x4]	8	1			T3	1		T11	1		T316	2
alert_ping_fail	alert[0x5]	8	1			T11	1		T243	1		T229	1
alert_ping_fail	alert[0x6]	14	1			T237	1		T317	1		T308	1
alert_ping_fail	alert[0x7]	11	1			T229	1		T314	1		T117	1
alert_ping_fail	alert[0x8]	27	1			T11	1		T224	1		T229	2
alert_ping_fail	alert[0x9]	15	1			T113	1		T316	1		T315	1
alert_ping_fail	alert[0xa]	19	1			T1	1		T237	1		T243	1
alert_ping_fail	alert[0xb]	11	1			T315	1		T318	1		T319	1
alert_ping_fail	alert[0xc]	14	1			T11	1		T320	1		T315	1
alert_ping_fail	alert[0xd]	11	1			T3	1		T196	1		T229	2
alert_ping_fail	alert[0xe]	10	1			T226	1		T316	1		T321	1
alert_ping_fail	alert[0xf]	11	1			T3	1		T229	1		T320	1
alert_ping_fail	alert[0x10]	10	1			T320	2		T316	1		T315	1
alert_ping_fail	alert[0x11]	4	1			T11	1		T322	1		T323	1
alert_ping_fail	alert[0x12]	5	1			T320	1		T316	1		T323	1
alert_ping_fail	alert[0x13]	11	1			T3	1		T235	2		T104	1
alert_ping_fail	alert[0x14]	13	1			T11	2		T320	1		T308	1
alert_ping_fail	alert[0x15]	11	1			T113	1		T237	1		T228	2
alert_ping_fail	alert[0x16]	18	1			T3	1		T243	1		T228	1
alert_ping_fail	alert[0x17]	16	1			T196	1		T237	1		T229	1
alert_ping_fail	alert[0x18]	9	1			T320	1		T313	1		T316	1
alert_ping_fail	alert[0x19]	8	1			T226	1		T320	1		T117	1
alert_ping_fail	alert[0x1a]	9	1			T104	1		T315	2		T117	1
alert_ping_fail	alert[0x1b]	10	1			T3	1		T313	1		T316	1
alert_ping_fail	alert[0x1c]	7	1			T11	1		T324	1		T117	1
alert_ping_fail	alert[0x1d]	5	1			T320	2		T325	1		T326	1
alert_ping_fail	alert[0x1e]	10	1			T312	1		T327	1		T328	1
alert_ping_fail	alert[0x1f]	11	1			T228	1		T316	1		T324	1
alert_ping_fail	alert[0x20]	10	1			T11	1		T321	1		T329	1
alert_ping_fail	alert[0x21]	8	1			T11	1		T313	1		T315	1
alert_ping_fail	alert[0x22]	5	1			T311	1		T312	1		T319	1
alert_ping_fail	alert[0x23]	7	1			T226	1		T104	1		T319	1
alert_ping_fail	alert[0x24]	8	1			T11	1		T229	1		T321	1
alert_ping_fail	alert[0x25]	9	1			T3	1		T226	1		T320	1
alert_ping_fail	alert[0x26]	9	1			T226	2		T320	1		T316	1
alert_ping_fail	alert[0x27]	14	1			T196	1		T313	1		T311	1
alert_ping_fail	alert[0x28]	14	1			T3	1		T229	1		T316	1
alert_ping_fail	alert[0x29]	15	1			T237	1		T313	1		T316	2
alert_ping_fail	alert[0x2a]	14	1			T3	1		T197	1		T243	1
alert_ping_fail	alert[0x2b]	12	1			T226	1		T320	2		T330	2
alert_ping_fail	alert[0x2c]	14	1			T73	1		T228	2		T313	1
alert_ping_fail	alert[0x2d]	12	1			T226	1		T229	1		T311	1
alert_ping_fail	alert[0x2e]	11	1			T14	1		T226	1		T229	1
alert_ping_fail	alert[0x2f]	8	1			T226	1		T316	1		T318	1
alert_ping_fail	alert[0x30]	10	1			T11	2		T226	1		T229	1
alert_ping_fail	alert[0x31]	11	1			T3	1		T11	1		T313	1
alert_ping_fail	alert[0x32]	14	1			T224	1		T226	1		T229	1
alert_ping_fail	alert[0x33]	10	1			T11	1		T313	1		T329	2
alert_ping_fail	alert[0x34]	3	1			T321	1		T331	1		T332	1
alert_ping_fail	alert[0x35]	5	1			T14	1		T333	1		T334	1
alert_ping_fail	alert[0x36]	9	1			T11	1		T226	1		T311	1
alert_ping_fail	alert[0x37]	8	1			T313	1		T328	1		T335	1
alert_ping_fail	alert[0x38]	13	1			T14	1		T226	2		T229	2
alert_ping_fail	alert[0x39]	11	1			T320	1		T117	1		T318	1
alert_ping_fail	alert[0x3a]	9	1			T3	1		T318	1		T336	1
alert_ping_fail	alert[0x3b]	8	1			T226	1		T324	1		T104	1
alert_ping_fail	alert[0x3c]	8	1			T226	1		T324	2		T321	1
alert_ping_fail	alert[0x3d]	9	1			T11	1		T196	1		T314	1
alert_ping_fail	alert[0x3e]	11	1			T3	1		T224	1		T229	1
alert_ping_fail	alert[0x3f]	5	1			T3	1		T226	1		T229	1
alert_ping_fail	alert[0x40]	6	1			T229	1		T336	1		T335	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	142388	1			T12	24		T4	147		T46	71
alert_integrity_fail	class_i[0x1]	58425	1			T12	25		T4	6		T49	10
alert_integrity_fail	class_i[0x2]	95924	1			T12	4		T4	24		T49	4953
alert_integrity_fail	class_i[0x3]	71063	1			T12	16		T4	49		T64	7
alert_ping_fail	class_i[0x0]	217	1			T11	2		T196	1		T73	1
alert_ping_fail	class_i[0x1]	157	1			T1	1		T11	1		T196	2
alert_ping_fail	class_i[0x2]	139	1			T3	1		T14	1		T196	1
alert_ping_fail	class_i[0x3]	178	1			T3	12		T11	14		T14	2