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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.99 98.77 97.09 100.00 100.00 99.38 99.52


Total test records in report: 823
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T773 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4078979841 Aug 12 04:33:20 PM PDT 24 Aug 12 04:33:39 PM PDT 24 284153871 ps
T774 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3030563625 Aug 12 04:33:32 PM PDT 24 Aug 12 04:33:57 PM PDT 24 1507942622 ps
T775 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3755968278 Aug 12 04:33:42 PM PDT 24 Aug 12 04:34:31 PM PDT 24 2935426408 ps
T158 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4202419278 Aug 12 04:33:02 PM PDT 24 Aug 12 04:43:58 PM PDT 24 5258872975 ps
T776 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.855094506 Aug 12 04:33:53 PM PDT 24 Aug 12 04:34:18 PM PDT 24 750273813 ps
T777 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4097415032 Aug 12 04:33:30 PM PDT 24 Aug 12 04:33:48 PM PDT 24 493079556 ps
T778 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2285890286 Aug 12 04:33:35 PM PDT 24 Aug 12 04:33:43 PM PDT 24 104303247 ps
T779 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2132811155 Aug 12 04:33:49 PM PDT 24 Aug 12 04:33:58 PM PDT 24 94314064 ps
T780 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3180300524 Aug 12 04:33:42 PM PDT 24 Aug 12 04:34:15 PM PDT 24 874787435 ps
T186 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1095295862 Aug 12 04:33:00 PM PDT 24 Aug 12 04:33:03 PM PDT 24 124181952 ps
T159 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3301336253 Aug 12 04:32:59 PM PDT 24 Aug 12 04:35:58 PM PDT 24 5314693030 ps
T781 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2395777458 Aug 12 04:33:35 PM PDT 24 Aug 12 04:33:41 PM PDT 24 35806424 ps
T782 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3476701120 Aug 12 04:33:12 PM PDT 24 Aug 12 04:33:20 PM PDT 24 70919858 ps
T154 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2378006248 Aug 12 04:33:32 PM PDT 24 Aug 12 04:48:54 PM PDT 24 12921860508 ps
T783 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3438365175 Aug 12 04:33:35 PM PDT 24 Aug 12 04:33:37 PM PDT 24 10514634 ps
T190 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2711530946 Aug 12 04:33:36 PM PDT 24 Aug 12 04:35:03 PM PDT 24 1946135083 ps
T784 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1815990143 Aug 12 04:33:45 PM PDT 24 Aug 12 04:34:10 PM PDT 24 1830754383 ps
T151 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1614560538 Aug 12 04:32:55 PM PDT 24 Aug 12 04:36:07 PM PDT 24 12200443396 ps
T785 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2422367778 Aug 12 04:33:16 PM PDT 24 Aug 12 04:33:18 PM PDT 24 8264919 ps
T786 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.590618703 Aug 12 04:33:12 PM PDT 24 Aug 12 04:33:17 PM PDT 24 222383923 ps
T787 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1849190055 Aug 12 04:33:43 PM PDT 24 Aug 12 04:33:45 PM PDT 24 26479328 ps
T788 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3688211234 Aug 12 04:33:44 PM PDT 24 Aug 12 04:33:46 PM PDT 24 7997480 ps
T789 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3218549524 Aug 12 04:33:31 PM PDT 24 Aug 12 04:33:40 PM PDT 24 619266002 ps
T790 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.310166854 Aug 12 04:32:57 PM PDT 24 Aug 12 04:33:10 PM PDT 24 389869964 ps
T791 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.819874058 Aug 12 04:33:38 PM PDT 24 Aug 12 04:34:06 PM PDT 24 410065230 ps
T792 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3304380285 Aug 12 04:33:39 PM PDT 24 Aug 12 04:33:59 PM PDT 24 1054678192 ps
T793 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3806814779 Aug 12 04:32:56 PM PDT 24 Aug 12 04:32:58 PM PDT 24 11571735 ps
T794 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.35455297 Aug 12 04:33:36 PM PDT 24 Aug 12 04:33:51 PM PDT 24 969689986 ps
T795 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2485544484 Aug 12 04:33:23 PM PDT 24 Aug 12 04:33:28 PM PDT 24 38879760 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2166914465 Aug 12 04:32:54 PM PDT 24 Aug 12 04:32:59 PM PDT 24 40525037 ps
T797 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2835922348 Aug 12 04:33:11 PM PDT 24 Aug 12 04:35:12 PM PDT 24 3414799031 ps
T798 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1636879819 Aug 12 04:33:38 PM PDT 24 Aug 12 04:33:43 PM PDT 24 50451436 ps
T184 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1120064952 Aug 12 04:33:12 PM PDT 24 Aug 12 04:34:41 PM PDT 24 6242898597 ps
T799 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1361647467 Aug 12 04:33:40 PM PDT 24 Aug 12 04:33:41 PM PDT 24 7599836 ps
T160 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.16231625 Aug 12 04:33:35 PM PDT 24 Aug 12 04:38:40 PM PDT 24 16156529570 ps
T147 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.936067692 Aug 12 04:32:54 PM PDT 24 Aug 12 04:38:19 PM PDT 24 4924270212 ps
T800 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.126401986 Aug 12 04:33:31 PM PDT 24 Aug 12 04:33:39 PM PDT 24 383047628 ps
T153 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2341479013 Aug 12 04:33:53 PM PDT 24 Aug 12 04:52:00 PM PDT 24 12729281682 ps
T801 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.804943302 Aug 12 04:33:40 PM PDT 24 Aug 12 04:33:48 PM PDT 24 54309093 ps
T802 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2132428971 Aug 12 04:33:15 PM PDT 24 Aug 12 04:33:20 PM PDT 24 146040295 ps
T803 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2135668071 Aug 12 04:33:08 PM PDT 24 Aug 12 04:33:09 PM PDT 24 9583000 ps
T804 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1669175351 Aug 12 04:33:37 PM PDT 24 Aug 12 04:33:39 PM PDT 24 11347787 ps
T805 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4019893882 Aug 12 04:33:42 PM PDT 24 Aug 12 04:37:33 PM PDT 24 8564778715 ps
T139 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3614295065 Aug 12 04:33:48 PM PDT 24 Aug 12 04:40:23 PM PDT 24 5419929499 ps
T806 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2239795244 Aug 12 04:33:39 PM PDT 24 Aug 12 04:33:41 PM PDT 24 10206688 ps
T179 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3188444290 Aug 12 04:32:56 PM PDT 24 Aug 12 04:32:58 PM PDT 24 139501620 ps
T176 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1692423980 Aug 12 04:33:51 PM PDT 24 Aug 12 04:34:41 PM PDT 24 1251704184 ps
T807 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1679853972 Aug 12 04:33:55 PM PDT 24 Aug 12 04:34:02 PM PDT 24 427324907 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4091472378 Aug 12 04:33:42 PM PDT 24 Aug 12 04:33:44 PM PDT 24 14093963 ps
T809 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.726554367 Aug 12 04:33:15 PM PDT 24 Aug 12 04:33:37 PM PDT 24 6665565746 ps
T161 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.274227834 Aug 12 04:33:35 PM PDT 24 Aug 12 04:39:16 PM PDT 24 17145289811 ps
T810 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3851362508 Aug 12 04:33:47 PM PDT 24 Aug 12 04:33:48 PM PDT 24 10768142 ps
T811 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1773563207 Aug 12 04:33:31 PM PDT 24 Aug 12 04:33:36 PM PDT 24 143860352 ps
T181 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.150326885 Aug 12 04:33:23 PM PDT 24 Aug 12 04:33:25 PM PDT 24 271071763 ps
T812 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1172922677 Aug 12 04:33:52 PM PDT 24 Aug 12 04:33:53 PM PDT 24 6190793 ps
T813 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.875372328 Aug 12 04:33:41 PM PDT 24 Aug 12 04:33:54 PM PDT 24 552449787 ps
T164 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1639516064 Aug 12 04:33:34 PM PDT 24 Aug 12 04:43:27 PM PDT 24 4430480256 ps
T167 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.891835771 Aug 12 04:33:38 PM PDT 24 Aug 12 04:43:13 PM PDT 24 18276737144 ps
T814 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1634365852 Aug 12 04:32:53 PM PDT 24 Aug 12 04:33:13 PM PDT 24 684241872 ps
T162 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3647538431 Aug 12 04:33:46 PM PDT 24 Aug 12 04:37:20 PM PDT 24 3281764470 ps
T165 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.585413162 Aug 12 04:33:30 PM PDT 24 Aug 12 04:43:36 PM PDT 24 17090908326 ps
T361 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3438794377 Aug 12 04:32:56 PM PDT 24 Aug 12 04:44:18 PM PDT 24 4452338948 ps
T815 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1694787786 Aug 12 04:33:34 PM PDT 24 Aug 12 04:33:36 PM PDT 24 27350791 ps
T174 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.753143336 Aug 12 04:32:59 PM PDT 24 Aug 12 04:33:06 PM PDT 24 112192308 ps
T816 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1149087274 Aug 12 04:33:06 PM PDT 24 Aug 12 04:33:16 PM PDT 24 206309153 ps
T817 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.192461121 Aug 12 04:33:38 PM PDT 24 Aug 12 04:33:39 PM PDT 24 16085429 ps
T818 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2414139687 Aug 12 04:33:40 PM PDT 24 Aug 12 04:33:41 PM PDT 24 9123922 ps
T819 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2524143022 Aug 12 04:33:50 PM PDT 24 Aug 12 04:33:58 PM PDT 24 336661132 ps
T820 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3135728449 Aug 12 04:33:35 PM PDT 24 Aug 12 04:33:36 PM PDT 24 11562485 ps
T821 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1851653750 Aug 12 04:33:51 PM PDT 24 Aug 12 04:33:56 PM PDT 24 32615582 ps
T166 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1365108803 Aug 12 04:33:36 PM PDT 24 Aug 12 04:37:03 PM PDT 24 8149402733 ps
T822 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.585549624 Aug 12 04:33:36 PM PDT 24 Aug 12 04:33:49 PM PDT 24 301074435 ps
T823 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1530928422 Aug 12 04:33:37 PM PDT 24 Aug 12 04:35:28 PM PDT 24 3546046300 ps

Test location /workspace/coverage/default/33.alert_handler_random_classes.1957351737
Short name T20
Test name
Test status
Simulation time 1096106466 ps
CPU time 29.51 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 04:35:26 PM PDT 24
Peak memory 248432 kb
Host smart-c3b3a6ec-f6d5-46e7-b3da-955abfb3b113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19573
51737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1957351737
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.459112617
Short name T4
Test name
Test status
Simulation time 70806284532 ps
CPU time 1676.14 seconds
Started Aug 12 04:35:07 PM PDT 24
Finished Aug 12 05:03:03 PM PDT 24
Peak memory 289728 kb
Host smart-3d6b304e-0e44-4af7-9cbf-1622ec320855
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459112617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.459112617
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3546386322
Short name T82
Test name
Test status
Simulation time 11408082611 ps
CPU time 188.16 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:37:05 PM PDT 24
Peak memory 265632 kb
Host smart-0cc085f9-0f86-4beb-9d73-73e716c6d033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546386322 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3546386322
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1046597923
Short name T8
Test name
Test status
Simulation time 630756490 ps
CPU time 11.11 seconds
Started Aug 12 04:34:16 PM PDT 24
Finished Aug 12 04:34:28 PM PDT 24
Peak memory 271332 kb
Host smart-8a56710c-05b8-4c58-a5db-401b6fca6981
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1046597923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1046597923
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1275111334
Short name T169
Test name
Test status
Simulation time 1246783063 ps
CPU time 43.69 seconds
Started Aug 12 04:33:29 PM PDT 24
Finished Aug 12 04:34:12 PM PDT 24
Peak memory 248312 kb
Host smart-f95c9cef-4d60-4f03-b1bc-c4e382b8133a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1275111334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1275111334
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.247348300
Short name T21
Test name
Test status
Simulation time 46550325800 ps
CPU time 2559.02 seconds
Started Aug 12 04:34:59 PM PDT 24
Finished Aug 12 05:17:39 PM PDT 24
Peak memory 281900 kb
Host smart-90dbad0f-21ba-45bd-91c8-ad0d9dd38e4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247348300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.247348300
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3988423531
Short name T28
Test name
Test status
Simulation time 30677004964 ps
CPU time 1766.35 seconds
Started Aug 12 04:35:07 PM PDT 24
Finished Aug 12 05:04:34 PM PDT 24
Peak memory 285732 kb
Host smart-7975aee8-3701-45e4-a4c0-6d439726a03d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988423531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3988423531
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1378799750
Short name T25
Test name
Test status
Simulation time 16376499169 ps
CPU time 1431.08 seconds
Started Aug 12 04:34:20 PM PDT 24
Finished Aug 12 04:58:11 PM PDT 24
Peak memory 289368 kb
Host smart-90de0081-ff60-4b93-a042-1827d5febb8d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378799750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1378799750
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3599086097
Short name T137
Test name
Test status
Simulation time 3318673868 ps
CPU time 236.14 seconds
Started Aug 12 04:33:43 PM PDT 24
Finished Aug 12 04:37:40 PM PDT 24
Peak memory 271536 kb
Host smart-c3fea42b-6628-4ea7-928e-0ff8a7749696
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3599086097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3599086097
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1941920362
Short name T97
Test name
Test status
Simulation time 14251146179 ps
CPU time 262.82 seconds
Started Aug 12 04:35:03 PM PDT 24
Finished Aug 12 04:39:26 PM PDT 24
Peak memory 267692 kb
Host smart-e13d8d17-85ff-4fbb-bd01-82c12519fde8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941920362 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1941920362
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2003553667
Short name T1
Test name
Test status
Simulation time 30964627239 ps
CPU time 1584.8 seconds
Started Aug 12 04:35:39 PM PDT 24
Finished Aug 12 05:02:04 PM PDT 24
Peak memory 273332 kb
Host smart-dbb40845-791b-4436-bf9f-f118b021369a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003553667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2003553667
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.440655273
Short name T33
Test name
Test status
Simulation time 197056432450 ps
CPU time 3476.06 seconds
Started Aug 12 04:33:53 PM PDT 24
Finished Aug 12 05:31:49 PM PDT 24
Peak memory 306172 kb
Host smart-02eae466-afc6-4d2f-a499-72624f095710
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440655273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.440655273
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.977371848
Short name T149
Test name
Test status
Simulation time 12695733847 ps
CPU time 872.23 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:47:30 PM PDT 24
Peak memory 265096 kb
Host smart-e9b34dec-c71d-45d4-b934-76b0aa9cfe78
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977371848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.977371848
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.821875011
Short name T50
Test name
Test status
Simulation time 173347441420 ps
CPU time 2791.24 seconds
Started Aug 12 04:34:08 PM PDT 24
Finished Aug 12 05:20:40 PM PDT 24
Peak memory 306444 kb
Host smart-6b179f82-d6bb-4cdb-9335-90c7f6e684a3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821875011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.821875011
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2341479013
Short name T153
Test name
Test status
Simulation time 12729281682 ps
CPU time 1086.93 seconds
Started Aug 12 04:33:53 PM PDT 24
Finished Aug 12 04:52:00 PM PDT 24
Peak memory 265180 kb
Host smart-a47bfed3-e058-4deb-945f-49466a6838ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341479013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2341479013
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.175093034
Short name T73
Test name
Test status
Simulation time 188099467404 ps
CPU time 2872.12 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 05:22:43 PM PDT 24
Peak memory 287424 kb
Host smart-a03029af-271d-4cc2-8c20-922d12e69014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175093034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.175093034
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.250427712
Short name T143
Test name
Test status
Simulation time 6207274507 ps
CPU time 180.75 seconds
Started Aug 12 04:33:01 PM PDT 24
Finished Aug 12 04:36:02 PM PDT 24
Peak memory 265096 kb
Host smart-0a43b9dd-2973-43c2-8851-7af07d11f43b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=250427712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.250427712
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2190096034
Short name T226
Test name
Test status
Simulation time 58431072852 ps
CPU time 592.27 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:44:39 PM PDT 24
Peak memory 247952 kb
Host smart-48aba34a-9d62-49be-a8c3-11a461e7b7f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190096034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2190096034
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.668668700
Short name T359
Test name
Test status
Simulation time 8823771 ps
CPU time 1.57 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:33:37 PM PDT 24
Peak memory 237120 kb
Host smart-ab77513f-0c32-4446-a11d-e4d259b1fb32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=668668700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.668668700
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.115347027
Short name T3
Test name
Test status
Simulation time 22105808213 ps
CPU time 329.68 seconds
Started Aug 12 04:35:12 PM PDT 24
Finished Aug 12 04:40:42 PM PDT 24
Peak memory 247940 kb
Host smart-dde52def-d762-4316-b5a8-f7ae64e75615
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115347027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.115347027
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1860310273
Short name T130
Test name
Test status
Simulation time 6989965444 ps
CPU time 265.66 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:37:22 PM PDT 24
Peak memory 265124 kb
Host smart-156d8e0b-b123-4e3f-9174-3fddd2b91898
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1860310273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1860310273
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2337302188
Short name T49
Test name
Test status
Simulation time 21486350111 ps
CPU time 1438.01 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:58:49 PM PDT 24
Peak memory 272460 kb
Host smart-a25f8f28-88d4-453a-840f-26374d0fac97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337302188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2337302188
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1526349591
Short name T197
Test name
Test status
Simulation time 80277287880 ps
CPU time 2252.41 seconds
Started Aug 12 04:34:38 PM PDT 24
Finished Aug 12 05:12:11 PM PDT 24
Peak memory 288548 kb
Host smart-a8badaea-1260-4d81-bd5d-665376515931
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526349591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1526349591
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1639516064
Short name T164
Test name
Test status
Simulation time 4430480256 ps
CPU time 592.88 seconds
Started Aug 12 04:33:34 PM PDT 24
Finished Aug 12 04:43:27 PM PDT 24
Peak memory 265176 kb
Host smart-2b292cd9-4750-4603-98c5-37f4a40dfab7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639516064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1639516064
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2014575191
Short name T554
Test name
Test status
Simulation time 10166617231 ps
CPU time 399.7 seconds
Started Aug 12 04:34:58 PM PDT 24
Finished Aug 12 04:41:38 PM PDT 24
Peak memory 248988 kb
Host smart-d038b3c5-ac39-46e4-a1a3-7f891aafec74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014575191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2014575191
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2378006248
Short name T154
Test name
Test status
Simulation time 12921860508 ps
CPU time 921.3 seconds
Started Aug 12 04:33:32 PM PDT 24
Finished Aug 12 04:48:54 PM PDT 24
Peak memory 265040 kb
Host smart-c73eb405-3296-4ad7-9c4a-ef08c73beac1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378006248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2378006248
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2877411678
Short name T301
Test name
Test status
Simulation time 16005944565 ps
CPU time 1218.41 seconds
Started Aug 12 04:34:55 PM PDT 24
Finished Aug 12 04:55:14 PM PDT 24
Peak memory 283908 kb
Host smart-897f0f92-339a-45d2-b329-8051d49d4db2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877411678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2877411678
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.367504536
Short name T81
Test name
Test status
Simulation time 14995852451 ps
CPU time 1489.29 seconds
Started Aug 12 04:35:38 PM PDT 24
Finished Aug 12 05:00:27 PM PDT 24
Peak memory 306400 kb
Host smart-9a3e410f-e9ea-4932-ad0d-0ff2fc61f41e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367504536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.367504536
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2829460719
Short name T5
Test name
Test status
Simulation time 57588103120 ps
CPU time 1451.6 seconds
Started Aug 12 04:34:48 PM PDT 24
Finished Aug 12 04:59:00 PM PDT 24
Peak memory 289428 kb
Host smart-0d750d55-ca33-4bf0-aa16-d23b95387f1a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829460719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2829460719
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2186159128
Short name T11
Test name
Test status
Simulation time 12535128677 ps
CPU time 524.3 seconds
Started Aug 12 04:35:55 PM PDT 24
Finished Aug 12 04:44:39 PM PDT 24
Peak memory 249140 kb
Host smart-df466a84-d0aa-48ef-a84b-14cd0b185d6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186159128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2186159128
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2112712787
Short name T152
Test name
Test status
Simulation time 13785552933 ps
CPU time 1079.81 seconds
Started Aug 12 04:33:22 PM PDT 24
Finished Aug 12 04:51:27 PM PDT 24
Peak memory 265104 kb
Host smart-ddd5e8c1-9150-42a1-9571-b728d42e3777
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112712787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2112712787
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.916930658
Short name T326
Test name
Test status
Simulation time 86308397586 ps
CPU time 2229.43 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 05:11:53 PM PDT 24
Peak memory 286812 kb
Host smart-b692779d-cd41-46f7-a83b-30a4a8a5b8df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916930658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.916930658
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1614560538
Short name T151
Test name
Test status
Simulation time 12200443396 ps
CPU time 192.48 seconds
Started Aug 12 04:32:55 PM PDT 24
Finished Aug 12 04:36:07 PM PDT 24
Peak memory 272976 kb
Host smart-8482e511-e240-4fc7-b4d4-442cb4718a8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1614560538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1614560538
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.205785087
Short name T173
Test name
Test status
Simulation time 12445430 ps
CPU time 1.51 seconds
Started Aug 12 04:33:41 PM PDT 24
Finished Aug 12 04:33:42 PM PDT 24
Peak memory 237100 kb
Host smart-d2ba3d0e-c066-4d89-89e1-1c9d22952a2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=205785087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.205785087
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1848052143
Short name T352
Test name
Test status
Simulation time 163218584844 ps
CPU time 2375.09 seconds
Started Aug 12 04:35:02 PM PDT 24
Finished Aug 12 05:14:38 PM PDT 24
Peak memory 289224 kb
Host smart-a676cc01-0fd5-44cd-b336-978f17c7af50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848052143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1848052143
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.97162941
Short name T274
Test name
Test status
Simulation time 73592049103 ps
CPU time 1523.4 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 05:00:20 PM PDT 24
Peak memory 289244 kb
Host smart-5b38213e-d049-4a3b-8cae-3775064aa741
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97162941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_hand
ler_stress_all.97162941
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.683220149
Short name T192
Test name
Test status
Simulation time 13306788401 ps
CPU time 444.56 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:42:05 PM PDT 24
Peak memory 268116 kb
Host smart-43a4b099-fd21-4f12-8eec-7ab728f1cd2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683220149 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.683220149
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3647538431
Short name T162
Test name
Test status
Simulation time 3281764470 ps
CPU time 213.57 seconds
Started Aug 12 04:33:46 PM PDT 24
Finished Aug 12 04:37:20 PM PDT 24
Peak memory 272760 kb
Host smart-76c07062-09d8-4663-871d-a4037e33649c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3647538431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3647538431
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.491572295
Short name T308
Test name
Test status
Simulation time 33889925485 ps
CPU time 1909.73 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 05:06:41 PM PDT 24
Peak memory 281788 kb
Host smart-a9664500-625f-4240-aab6-6548360b9cb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491572295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.491572295
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2676000394
Short name T57
Test name
Test status
Simulation time 73127803917 ps
CPU time 3775.75 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 05:37:45 PM PDT 24
Peak memory 305652 kb
Host smart-a754fb26-83e6-4866-9a04-67e914361bf4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676000394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2676000394
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2606041635
Short name T335
Test name
Test status
Simulation time 28378473448 ps
CPU time 294.17 seconds
Started Aug 12 04:35:19 PM PDT 24
Finished Aug 12 04:40:13 PM PDT 24
Peak memory 255936 kb
Host smart-f9bee351-0cc6-4e30-8a66-fbd97a6a0133
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606041635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2606041635
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1453845371
Short name T107
Test name
Test status
Simulation time 49739641142 ps
CPU time 3023.69 seconds
Started Aug 12 04:34:14 PM PDT 24
Finished Aug 12 05:24:38 PM PDT 24
Peak memory 289484 kb
Host smart-d88c0788-4736-46bb-859e-865e4a6971eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453845371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1453845371
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3783942664
Short name T277
Test name
Test status
Simulation time 37332468572 ps
CPU time 183.36 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:37:39 PM PDT 24
Peak memory 267872 kb
Host smart-f58a38c2-5c0b-4ff4-9027-0f395e80dda2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783942664 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3783942664
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1834297038
Short name T320
Test name
Test status
Simulation time 11990742012 ps
CPU time 504.58 seconds
Started Aug 12 04:34:23 PM PDT 24
Finished Aug 12 04:42:48 PM PDT 24
Peak memory 249024 kb
Host smart-5204e8f4-a2e3-4b29-965b-63ab11f39304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834297038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1834297038
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2425616911
Short name T175
Test name
Test status
Simulation time 301381893 ps
CPU time 4.17 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:33:39 PM PDT 24
Peak memory 237136 kb
Host smart-f499f044-b7c6-4f66-bde2-baa7b33bc81f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2425616911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2425616911
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3614295065
Short name T139
Test name
Test status
Simulation time 5419929499 ps
CPU time 394.81 seconds
Started Aug 12 04:33:48 PM PDT 24
Finished Aug 12 04:40:23 PM PDT 24
Peak memory 271044 kb
Host smart-d76dfedf-530a-4d66-95e9-5aeb3616d959
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3614295065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3614295065
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3438794377
Short name T361
Test name
Test status
Simulation time 4452338948 ps
CPU time 681.63 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:44:18 PM PDT 24
Peak memory 265044 kb
Host smart-250e9d5d-811a-4619-bf9b-d754bb5c66aa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438794377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3438794377
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1797934528
Short name T260
Test name
Test status
Simulation time 106754997025 ps
CPU time 2230.09 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 05:12:02 PM PDT 24
Peak memory 288764 kb
Host smart-fcfb4a91-999a-4739-8ecd-65215770f187
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797934528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1797934528
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1253280098
Short name T254
Test name
Test status
Simulation time 32668219478 ps
CPU time 848.65 seconds
Started Aug 12 04:34:48 PM PDT 24
Finished Aug 12 04:48:57 PM PDT 24
Peak memory 272488 kb
Host smart-0be521c6-1ed5-4e18-bca8-4ed404996abf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253280098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1253280098
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.262893113
Short name T31
Test name
Test status
Simulation time 1403099087 ps
CPU time 139.41 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:38:14 PM PDT 24
Peak memory 270300 kb
Host smart-15d3ed38-4ec1-4532-9e0b-68d537e1d0ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262893113 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.262893113
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4094116558
Short name T297
Test name
Test status
Simulation time 53484388790 ps
CPU time 1666.23 seconds
Started Aug 12 04:35:08 PM PDT 24
Finished Aug 12 05:02:54 PM PDT 24
Peak memory 283200 kb
Host smart-2c7c385e-9ae7-4c72-98c6-8f1ce8b30f32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094116558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4094116558
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3933206009
Short name T113
Test name
Test status
Simulation time 54569916583 ps
CPU time 2954.35 seconds
Started Aug 12 04:34:24 PM PDT 24
Finished Aug 12 05:23:39 PM PDT 24
Peak memory 286620 kb
Host smart-780de325-50d4-4567-829d-4d77d6e67c5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933206009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3933206009
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4006644717
Short name T156
Test name
Test status
Simulation time 8655392054 ps
CPU time 318.81 seconds
Started Aug 12 04:33:33 PM PDT 24
Finished Aug 12 04:38:52 PM PDT 24
Peak memory 265132 kb
Host smart-c7aee11d-892d-4f6c-bca0-58c13b4a0187
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006644717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.4006644717
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1027022158
Short name T168
Test name
Test status
Simulation time 4243399358 ps
CPU time 35.11 seconds
Started Aug 12 04:33:29 PM PDT 24
Finished Aug 12 04:34:05 PM PDT 24
Peak memory 246556 kb
Host smart-090e612d-1d4a-44c9-b3a9-23ae1a3de790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1027022158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1027022158
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4095655232
Short name T214
Test name
Test status
Simulation time 162902396 ps
CPU time 3.8 seconds
Started Aug 12 04:34:10 PM PDT 24
Finished Aug 12 04:34:14 PM PDT 24
Peak memory 249244 kb
Host smart-45c370a2-76cc-48b9-9bc5-3a3c3ef85fa9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4095655232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4095655232
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3219261284
Short name T218
Test name
Test status
Simulation time 43934544 ps
CPU time 3.59 seconds
Started Aug 12 04:33:46 PM PDT 24
Finished Aug 12 04:33:50 PM PDT 24
Peak memory 249164 kb
Host smart-ab62e3b3-a5ad-42de-b04e-d815859c4eaf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3219261284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3219261284
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.289608063
Short name T209
Test name
Test status
Simulation time 71723777 ps
CPU time 4.14 seconds
Started Aug 12 04:34:33 PM PDT 24
Finished Aug 12 04:34:37 PM PDT 24
Peak memory 249216 kb
Host smart-6afedc92-f2e6-4bcc-89d2-c56796267aff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=289608063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.289608063
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1537325556
Short name T211
Test name
Test status
Simulation time 184117472 ps
CPU time 3.28 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:34:52 PM PDT 24
Peak memory 249120 kb
Host smart-449ae5c6-a40d-4fd8-934a-a4d57853d87e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1537325556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1537325556
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1123607213
Short name T614
Test name
Test status
Simulation time 200102554701 ps
CPU time 1776.88 seconds
Started Aug 12 04:33:44 PM PDT 24
Finished Aug 12 05:03:22 PM PDT 24
Peak memory 272940 kb
Host smart-f38c6c5e-c3cf-41d8-956f-ac2588141643
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123607213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1123607213
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1018486086
Short name T333
Test name
Test status
Simulation time 79749826211 ps
CPU time 207.77 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:38:02 PM PDT 24
Peak memory 255428 kb
Host smart-65ae4e79-5a08-46e9-99b6-f1cdf4b16b3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018486086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1018486086
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1894201145
Short name T279
Test name
Test status
Simulation time 278811273 ps
CPU time 17.38 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 04:34:55 PM PDT 24
Peak memory 256328 kb
Host smart-04e0ee13-eb4c-4d81-b75a-66f282dbcf82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18942
01145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1894201145
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2093349796
Short name T319
Test name
Test status
Simulation time 49623251372 ps
CPU time 497.28 seconds
Started Aug 12 04:34:54 PM PDT 24
Finished Aug 12 04:43:12 PM PDT 24
Peak memory 249192 kb
Host smart-c8dbed1e-1802-46de-b270-eba366e35f8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093349796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2093349796
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.4217618966
Short name T483
Test name
Test status
Simulation time 619952325 ps
CPU time 18.71 seconds
Started Aug 12 04:35:13 PM PDT 24
Finished Aug 12 04:35:32 PM PDT 24
Peak memory 256736 kb
Host smart-caa161e3-0b23-4df5-8b52-5a9d5ecdc254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42176
18966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.4217618966
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2771454354
Short name T265
Test name
Test status
Simulation time 306235622 ps
CPU time 20.34 seconds
Started Aug 12 04:35:00 PM PDT 24
Finished Aug 12 04:35:21 PM PDT 24
Peak memory 255860 kb
Host smart-196ad24c-cd57-4957-9e60-37b9b9e5d9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27714
54354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2771454354
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.4116995083
Short name T258
Test name
Test status
Simulation time 5199402187 ps
CPU time 55.65 seconds
Started Aug 12 04:34:14 PM PDT 24
Finished Aug 12 04:35:09 PM PDT 24
Peak memory 248640 kb
Host smart-ece21731-b75c-4200-bbd6-b1dbc5ff7121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41169
95083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4116995083
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1611771140
Short name T68
Test name
Test status
Simulation time 272880518172 ps
CPU time 1272.93 seconds
Started Aug 12 04:35:44 PM PDT 24
Finished Aug 12 04:56:57 PM PDT 24
Peak memory 289272 kb
Host smart-76e97083-bfc0-48e0-940b-d796e36f34be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611771140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1611771140
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1365108803
Short name T166
Test name
Test status
Simulation time 8149402733 ps
CPU time 207.08 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:37:03 PM PDT 24
Peak memory 265096 kb
Host smart-f930cfaa-a82f-41b3-a705-4e90345d74ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1365108803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1365108803
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2550445069
Short name T132
Test name
Test status
Simulation time 33896829639 ps
CPU time 554.29 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:42:50 PM PDT 24
Peak memory 264032 kb
Host smart-bf713341-f917-4555-bc56-3cbdd1954fcb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550445069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2550445069
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2711530946
Short name T190
Test name
Test status
Simulation time 1946135083 ps
CPU time 86.33 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:35:03 PM PDT 24
Peak memory 240396 kb
Host smart-06438f97-c737-411b-b6f6-e06821ce7618
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2711530946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2711530946
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3417643388
Short name T332
Test name
Test status
Simulation time 59310183959 ps
CPU time 622.53 seconds
Started Aug 12 04:33:59 PM PDT 24
Finished Aug 12 04:44:22 PM PDT 24
Peak memory 249140 kb
Host smart-d358f4f7-facd-4f0b-8bb7-07d60d1bb9d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417643388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3417643388
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1222154728
Short name T257
Test name
Test status
Simulation time 345436069 ps
CPU time 25.26 seconds
Started Aug 12 04:34:32 PM PDT 24
Finished Aug 12 04:34:57 PM PDT 24
Peak memory 248912 kb
Host smart-4a02a0af-1fb8-413c-8ea0-8a54e596db4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12221
54728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1222154728
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1702919732
Short name T63
Test name
Test status
Simulation time 54386881120 ps
CPU time 2000.96 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 05:08:08 PM PDT 24
Peak memory 289784 kb
Host smart-f8c0052e-a13a-4e2c-a72c-55f639ffd1c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702919732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1702919732
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1220216529
Short name T80
Test name
Test status
Simulation time 1433333014 ps
CPU time 11.52 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 04:34:48 PM PDT 24
Peak memory 253600 kb
Host smart-6f699d16-58df-411c-837f-869ffabb0267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12202
16529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1220216529
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2565054137
Short name T267
Test name
Test status
Simulation time 1234098729 ps
CPU time 13.82 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:35:05 PM PDT 24
Peak memory 256536 kb
Host smart-3ff38895-0e06-4a65-a3c2-fe25c49506e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650
54137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2565054137
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3251754136
Short name T272
Test name
Test status
Simulation time 2676694331 ps
CPU time 315.99 seconds
Started Aug 12 04:34:35 PM PDT 24
Finished Aug 12 04:39:51 PM PDT 24
Peak memory 267328 kb
Host smart-bcd23054-7d45-4c1e-98d5-b675ba95acf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251754136 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3251754136
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1054123032
Short name T290
Test name
Test status
Simulation time 24475946119 ps
CPU time 666.77 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:45:47 PM PDT 24
Peak memory 273008 kb
Host smart-cb00d288-0ac7-4f64-b94d-d88b838d97f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054123032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1054123032
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2471407440
Short name T284
Test name
Test status
Simulation time 1089507337 ps
CPU time 23.76 seconds
Started Aug 12 04:35:44 PM PDT 24
Finished Aug 12 04:36:08 PM PDT 24
Peak memory 247896 kb
Host smart-6be6fd50-48cf-4227-b9cc-187b399d2770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24714
07440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2471407440
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.598698041
Short name T259
Test name
Test status
Simulation time 16507617242 ps
CPU time 502.72 seconds
Started Aug 12 04:35:01 PM PDT 24
Finished Aug 12 04:43:23 PM PDT 24
Peak memory 257192 kb
Host smart-86792976-a782-4d56-8ad2-d736c7f964e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598698041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.598698041
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2983275086
Short name T263
Test name
Test status
Simulation time 81343197570 ps
CPU time 2531.23 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 05:18:08 PM PDT 24
Peak memory 290024 kb
Host smart-08303a49-80d7-49e7-ba45-e417b33ca2d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983275086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2983275086
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2596877112
Short name T255
Test name
Test status
Simulation time 512765437 ps
CPU time 33.29 seconds
Started Aug 12 04:35:59 PM PDT 24
Finished Aug 12 04:36:32 PM PDT 24
Peak memory 256256 kb
Host smart-780f6e81-f9bf-410a-b735-bf27de51c163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
77112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2596877112
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.996492021
Short name T281
Test name
Test status
Simulation time 167140998 ps
CPU time 5.44 seconds
Started Aug 12 04:34:11 PM PDT 24
Finished Aug 12 04:34:17 PM PDT 24
Peak memory 240796 kb
Host smart-40cf9cd7-9dd3-43ff-b9c8-f43b2c7d3722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99649
2021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.996492021
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3244771914
Short name T27
Test name
Test status
Simulation time 42259809978 ps
CPU time 2602.47 seconds
Started Aug 12 04:34:53 PM PDT 24
Finished Aug 12 05:18:15 PM PDT 24
Peak memory 286644 kb
Host smart-52b3f604-c00d-4851-951e-9588c8ba8a92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244771914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3244771914
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.493089608
Short name T177
Test name
Test status
Simulation time 66881173 ps
CPU time 4.19 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:33:02 PM PDT 24
Peak memory 237124 kb
Host smart-7d44e096-2b12-468f-bb0b-78084cd69f85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=493089608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.493089608
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3188444290
Short name T179
Test name
Test status
Simulation time 139501620 ps
CPU time 2 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 236208 kb
Host smart-1dcbc482-8497-4fec-8ed3-5073a927e298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3188444290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3188444290
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3643503745
Short name T178
Test name
Test status
Simulation time 2529697240 ps
CPU time 34.82 seconds
Started Aug 12 04:33:33 PM PDT 24
Finished Aug 12 04:34:08 PM PDT 24
Peak memory 240104 kb
Host smart-92c48f5c-1836-4cb6-b411-8f78439f99da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3643503745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3643503745
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.150326885
Short name T181
Test name
Test status
Simulation time 271071763 ps
CPU time 2.71 seconds
Started Aug 12 04:33:23 PM PDT 24
Finished Aug 12 04:33:25 PM PDT 24
Peak memory 237068 kb
Host smart-6098c08c-2201-4996-90f8-40eb2859f32d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=150326885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.150326885
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1692423980
Short name T176
Test name
Test status
Simulation time 1251704184 ps
CPU time 49.49 seconds
Started Aug 12 04:33:51 PM PDT 24
Finished Aug 12 04:34:41 PM PDT 24
Peak memory 237232 kb
Host smart-6b817014-f020-41e3-9e5e-223e648d4450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1692423980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1692423980
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1120064952
Short name T184
Test name
Test status
Simulation time 6242898597 ps
CPU time 88.56 seconds
Started Aug 12 04:33:12 PM PDT 24
Finished Aug 12 04:34:41 PM PDT 24
Peak memory 240100 kb
Host smart-41b6f39d-3ab2-4394-9b9c-77fb62b66f23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1120064952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1120064952
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3589121731
Short name T182
Test name
Test status
Simulation time 102060023 ps
CPU time 5.47 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:33:08 PM PDT 24
Peak memory 237124 kb
Host smart-7534ec5a-23c5-440d-8efc-d577bd2225a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3589121731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3589121731
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.274227834
Short name T161
Test name
Test status
Simulation time 17145289811 ps
CPU time 341.02 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:39:16 PM PDT 24
Peak memory 273092 kb
Host smart-d2d466c6-094d-4215-843d-3cee2a1466f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=274227834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.274227834
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2493121760
Short name T157
Test name
Test status
Simulation time 16443763658 ps
CPU time 600.43 seconds
Started Aug 12 04:33:39 PM PDT 24
Finished Aug 12 04:43:40 PM PDT 24
Peak memory 265044 kb
Host smart-1f64bb98-96dd-458d-b623-3fa567ead650
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493121760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2493121760
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.16231625
Short name T160
Test name
Test status
Simulation time 16156529570 ps
CPU time 304.48 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:38:40 PM PDT 24
Peak memory 265108 kb
Host smart-dd770a97-ec6a-4ba6-86de-9311059b0757
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16231625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_error
s.16231625
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.124726200
Short name T180
Test name
Test status
Simulation time 942113670 ps
CPU time 63.59 seconds
Started Aug 12 04:33:39 PM PDT 24
Finished Aug 12 04:34:43 PM PDT 24
Peak memory 237396 kb
Host smart-eb2a3609-d0cf-49c2-b1f7-9a7a0b9cf8f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=124726200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.124726200
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.753143336
Short name T174
Test name
Test status
Simulation time 112192308 ps
CPU time 6.45 seconds
Started Aug 12 04:32:59 PM PDT 24
Finished Aug 12 04:33:06 PM PDT 24
Peak memory 237112 kb
Host smart-9568eefe-3752-4503-b656-e38d6adfe293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=753143336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.753143336
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1095295862
Short name T186
Test name
Test status
Simulation time 124181952 ps
CPU time 2.53 seconds
Started Aug 12 04:33:00 PM PDT 24
Finished Aug 12 04:33:03 PM PDT 24
Peak memory 237372 kb
Host smart-8a5ca676-ddca-44b8-ad2c-973370893bfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1095295862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1095295862
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3737495059
Short name T23
Test name
Test status
Simulation time 769322834 ps
CPU time 50.74 seconds
Started Aug 12 04:35:01 PM PDT 24
Finished Aug 12 04:35:52 PM PDT 24
Peak memory 256596 kb
Host smart-460c5ced-40e1-419e-b7df-ebaea9a845bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37374
95059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3737495059
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.785719549
Short name T22
Test name
Test status
Simulation time 3802499110 ps
CPU time 45.52 seconds
Started Aug 12 04:34:07 PM PDT 24
Finished Aug 12 04:34:53 PM PDT 24
Peak memory 257272 kb
Host smart-038952dc-39e7-4bec-a5cf-006bc5ecb8a5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785719549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.785719549
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3675079898
Short name T753
Test name
Test status
Simulation time 1113301463 ps
CPU time 163.01 seconds
Started Aug 12 04:33:06 PM PDT 24
Finished Aug 12 04:35:51 PM PDT 24
Peak memory 240096 kb
Host smart-a384bbb4-c611-4e17-bb0e-4aa66658ff80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3675079898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3675079898
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1244195045
Short name T199
Test name
Test status
Simulation time 21053393732 ps
CPU time 396.33 seconds
Started Aug 12 04:33:40 PM PDT 24
Finished Aug 12 04:40:17 PM PDT 24
Peak memory 236188 kb
Host smart-3b231cec-1a22-46d3-abb5-8b3081dc6d56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1244195045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1244195045
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3451301054
Short name T755
Test name
Test status
Simulation time 113882164 ps
CPU time 8.79 seconds
Started Aug 12 04:33:46 PM PDT 24
Finished Aug 12 04:33:55 PM PDT 24
Peak memory 240364 kb
Host smart-d21248bb-f539-4c32-b2d3-0520d0088967
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3451301054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3451301054
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1061870182
Short name T761
Test name
Test status
Simulation time 253299942 ps
CPU time 10.74 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:33:46 PM PDT 24
Peak memory 254028 kb
Host smart-0ef7efa5-32fe-4ee7-8c80-650d372a11d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061870182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1061870182
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.590618703
Short name T786
Test name
Test status
Simulation time 222383923 ps
CPU time 4.6 seconds
Started Aug 12 04:33:12 PM PDT 24
Finished Aug 12 04:33:17 PM PDT 24
Peak memory 236048 kb
Host smart-c38b510f-85b9-45ab-8e12-8c64520a1e72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=590618703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.590618703
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1857010334
Short name T707
Test name
Test status
Simulation time 9854143 ps
CPU time 1.36 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 235112 kb
Host smart-6e46891d-fe27-40d0-848e-6c37eabf7cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1857010334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1857010334
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1634365852
Short name T814
Test name
Test status
Simulation time 684241872 ps
CPU time 20.73 seconds
Started Aug 12 04:32:53 PM PDT 24
Finished Aug 12 04:33:13 PM PDT 24
Peak memory 245288 kb
Host smart-667a375a-2c9d-4c87-9029-6025ad2724a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1634365852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1634365852
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2310849752
Short name T142
Test name
Test status
Simulation time 3111194793 ps
CPU time 86.69 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:34:21 PM PDT 24
Peak memory 265108 kb
Host smart-cdfe3dce-1a97-438d-abf7-7b0055223e5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2310849752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2310849752
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3055698350
Short name T140
Test name
Test status
Simulation time 4521665087 ps
CPU time 350.68 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:38:48 PM PDT 24
Peak memory 265048 kb
Host smart-c3017e19-b350-4a0a-85df-98a6431adcf5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055698350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3055698350
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2132428971
Short name T802
Test name
Test status
Simulation time 146040295 ps
CPU time 5.43 seconds
Started Aug 12 04:33:15 PM PDT 24
Finished Aug 12 04:33:20 PM PDT 24
Peak memory 253632 kb
Host smart-3ba1deec-23ce-4c9f-b2bd-01a55276cf19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2132428971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2132428971
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2627260304
Short name T183
Test name
Test status
Simulation time 487986450 ps
CPU time 32.65 seconds
Started Aug 12 04:33:03 PM PDT 24
Finished Aug 12 04:33:36 PM PDT 24
Peak memory 239904 kb
Host smart-56cd531a-f77b-4cb8-a751-832c3a40d9e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2627260304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2627260304
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3887104351
Short name T771
Test name
Test status
Simulation time 2293137799 ps
CPU time 68.44 seconds
Started Aug 12 04:33:03 PM PDT 24
Finished Aug 12 04:34:12 PM PDT 24
Peak memory 237124 kb
Host smart-bd01bb3a-b220-4b99-af95-bd7e05b6f067
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3887104351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3887104351
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.490109230
Short name T708
Test name
Test status
Simulation time 31730303717 ps
CPU time 203.25 seconds
Started Aug 12 04:33:16 PM PDT 24
Finished Aug 12 04:36:40 PM PDT 24
Peak memory 240140 kb
Host smart-6147601c-87f2-4113-bfd2-b4c21e65bdf8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=490109230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.490109230
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2902929320
Short name T724
Test name
Test status
Simulation time 192757775 ps
CPU time 7.84 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:33:44 PM PDT 24
Peak memory 240128 kb
Host smart-4dbbd018-3c5f-456c-8cb6-6bebfb06f064
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2902929320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2902929320
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3767691256
Short name T756
Test name
Test status
Simulation time 93953391 ps
CPU time 7.58 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:33:04 PM PDT 24
Peak memory 240092 kb
Host smart-70cf8b0c-689a-467e-91f8-e45da232ee2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767691256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3767691256
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2166914465
Short name T796
Test name
Test status
Simulation time 40525037 ps
CPU time 4.84 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 239860 kb
Host smart-d0dd91bf-38d0-419e-9334-91141ffdf138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2166914465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2166914465
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.815039381
Short name T715
Test name
Test status
Simulation time 24901025 ps
CPU time 1.35 seconds
Started Aug 12 04:32:52 PM PDT 24
Finished Aug 12 04:32:54 PM PDT 24
Peak memory 237032 kb
Host smart-e9f6b468-7e71-41f2-90d2-76c5c606e8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=815039381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.815039381
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.569109071
Short name T721
Test name
Test status
Simulation time 377276362 ps
CPU time 20.9 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:33:17 PM PDT 24
Peak memory 245304 kb
Host smart-3095e415-b0a6-4d14-a855-6e0dc210dcde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=569109071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.569109071
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.936067692
Short name T147
Test name
Test status
Simulation time 4924270212 ps
CPU time 325.22 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:38:19 PM PDT 24
Peak memory 265996 kb
Host smart-7b8ca557-95e8-4f9e-98f8-11939a8035e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=936067692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.936067692
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4202419278
Short name T158
Test name
Test status
Simulation time 5258872975 ps
CPU time 655.32 seconds
Started Aug 12 04:33:02 PM PDT 24
Finished Aug 12 04:43:58 PM PDT 24
Peak memory 273296 kb
Host smart-ce8a0e71-66c7-4a80-b656-337b2244a2be
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202419278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4202419278
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2088573396
Short name T744
Test name
Test status
Simulation time 157440351 ps
CPU time 5.6 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:32:59 PM PDT 24
Peak memory 253428 kb
Host smart-9db5c97a-4ce1-4113-93ed-89806d7b1497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2088573396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2088573396
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1679853972
Short name T807
Test name
Test status
Simulation time 427324907 ps
CPU time 6.21 seconds
Started Aug 12 04:33:55 PM PDT 24
Finished Aug 12 04:34:02 PM PDT 24
Peak memory 239376 kb
Host smart-8b5b5290-7abd-4de4-afb7-b6c67c199556
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679853972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1679853972
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.464321759
Short name T733
Test name
Test status
Simulation time 256541980 ps
CPU time 3.47 seconds
Started Aug 12 04:33:34 PM PDT 24
Finished Aug 12 04:33:38 PM PDT 24
Peak memory 237088 kb
Host smart-111160e2-5670-4304-b78c-5a0a0235b9df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=464321759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.464321759
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3438365175
Short name T783
Test name
Test status
Simulation time 10514634 ps
CPU time 1.6 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:33:37 PM PDT 24
Peak memory 235228 kb
Host smart-aa8422e5-3080-41d2-aef7-c8314c0a195b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3438365175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3438365175
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1750802564
Short name T204
Test name
Test status
Simulation time 342280642 ps
CPU time 19.88 seconds
Started Aug 12 04:33:20 PM PDT 24
Finished Aug 12 04:33:40 PM PDT 24
Peak memory 244404 kb
Host smart-817ce4ac-2a15-4731-b5e5-1879a5b302fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1750802564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1750802564
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2377244205
Short name T146
Test name
Test status
Simulation time 11269561423 ps
CPU time 195.8 seconds
Started Aug 12 04:33:30 PM PDT 24
Finished Aug 12 04:36:46 PM PDT 24
Peak memory 267556 kb
Host smart-6b563b49-61c3-461e-a8d2-7bc2a2d0bb2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2377244205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2377244205
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2747478068
Short name T141
Test name
Test status
Simulation time 9792146576 ps
CPU time 608.51 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:43:45 PM PDT 24
Peak memory 265192 kb
Host smart-50387e58-f61b-411a-a3a9-f58e15dc81e7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747478068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2747478068
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2606744952
Short name T745
Test name
Test status
Simulation time 163125048 ps
CPU time 6.09 seconds
Started Aug 12 04:33:32 PM PDT 24
Finished Aug 12 04:33:38 PM PDT 24
Peak memory 248340 kb
Host smart-728feaaa-d245-49ab-8189-643ef33b3782
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2606744952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2606744952
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1164987705
Short name T170
Test name
Test status
Simulation time 186610215 ps
CPU time 4.27 seconds
Started Aug 12 04:33:28 PM PDT 24
Finished Aug 12 04:33:33 PM PDT 24
Peak memory 237168 kb
Host smart-f9603578-4cc4-4611-bb69-4f1ea087377d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1164987705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1164987705
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2132811155
Short name T779
Test name
Test status
Simulation time 94314064 ps
CPU time 8.28 seconds
Started Aug 12 04:33:49 PM PDT 24
Finished Aug 12 04:33:58 PM PDT 24
Peak memory 251388 kb
Host smart-bd787810-5278-48f7-b0c9-11c4019d1764
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132811155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2132811155
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1217900838
Short name T709
Test name
Test status
Simulation time 125683328 ps
CPU time 9.16 seconds
Started Aug 12 04:33:21 PM PDT 24
Finished Aug 12 04:33:30 PM PDT 24
Peak memory 240092 kb
Host smart-9ff2bd4f-f552-4ee2-a0db-c86dd04bc916
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1217900838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1217900838
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1634840394
Short name T740
Test name
Test status
Simulation time 1014097088 ps
CPU time 39.24 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:34:21 PM PDT 24
Peak memory 248272 kb
Host smart-21600f77-7e6a-491d-8f68-0b5aeaad323c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1634840394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1634840394
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3451621558
Short name T144
Test name
Test status
Simulation time 4083786593 ps
CPU time 309.63 seconds
Started Aug 12 04:33:16 PM PDT 24
Finished Aug 12 04:38:26 PM PDT 24
Peak memory 271148 kb
Host smart-2e26cb01-4b86-4ac2-9c0e-7fde1ad38fe6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3451621558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3451621558
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2485544484
Short name T795
Test name
Test status
Simulation time 38879760 ps
CPU time 4.98 seconds
Started Aug 12 04:33:23 PM PDT 24
Finished Aug 12 04:33:28 PM PDT 24
Peak memory 247852 kb
Host smart-93767581-12f9-40f8-9236-7e6d0c871ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2485544484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2485544484
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4111267133
Short name T752
Test name
Test status
Simulation time 54686050 ps
CPU time 5.13 seconds
Started Aug 12 04:33:48 PM PDT 24
Finished Aug 12 04:33:53 PM PDT 24
Peak memory 240072 kb
Host smart-12c8e88b-409a-400b-82df-9fc66cf6f749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111267133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.4111267133
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1636879819
Short name T798
Test name
Test status
Simulation time 50451436 ps
CPU time 4.53 seconds
Started Aug 12 04:33:38 PM PDT 24
Finished Aug 12 04:33:43 PM PDT 24
Peak memory 237124 kb
Host smart-2e5f82e0-c201-49b8-9708-3d766356c0f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1636879819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1636879819
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1015014636
Short name T714
Test name
Test status
Simulation time 8244863 ps
CPU time 1.54 seconds
Started Aug 12 04:33:44 PM PDT 24
Finished Aug 12 04:33:45 PM PDT 24
Peak memory 235124 kb
Host smart-c918bae1-6ebc-4ba3-9a69-f4281484a618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1015014636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1015014636
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3111317595
Short name T203
Test name
Test status
Simulation time 724111355 ps
CPU time 23.06 seconds
Started Aug 12 04:33:40 PM PDT 24
Finished Aug 12 04:34:03 PM PDT 24
Peak memory 245360 kb
Host smart-f16deb53-0676-45dc-97ff-787a1fdbf787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3111317595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3111317595
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3304380285
Short name T792
Test name
Test status
Simulation time 1054678192 ps
CPU time 20.22 seconds
Started Aug 12 04:33:39 PM PDT 24
Finished Aug 12 04:33:59 PM PDT 24
Peak memory 253708 kb
Host smart-b62388e6-af49-4bfa-9920-a0aec6d0e9e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3304380285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3304380285
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.875372328
Short name T813
Test name
Test status
Simulation time 552449787 ps
CPU time 13.01 seconds
Started Aug 12 04:33:41 PM PDT 24
Finished Aug 12 04:33:54 PM PDT 24
Peak memory 248208 kb
Host smart-e854ebe0-6065-4d67-b215-3cca177fe58b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875372328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.875372328
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1773563207
Short name T811
Test name
Test status
Simulation time 143860352 ps
CPU time 4.73 seconds
Started Aug 12 04:33:31 PM PDT 24
Finished Aug 12 04:33:36 PM PDT 24
Peak memory 236236 kb
Host smart-78b044ab-9e25-44e4-833d-17ee76f9c62d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1773563207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1773563207
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3278097776
Short name T356
Test name
Test status
Simulation time 12066376 ps
CPU time 1.4 seconds
Started Aug 12 04:33:38 PM PDT 24
Finished Aug 12 04:33:40 PM PDT 24
Peak memory 237116 kb
Host smart-9f5cb468-5b3c-47f9-af4c-2786c21ace33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3278097776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3278097776
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2242327605
Short name T735
Test name
Test status
Simulation time 5281867567 ps
CPU time 21.4 seconds
Started Aug 12 04:33:38 PM PDT 24
Finished Aug 12 04:33:59 PM PDT 24
Peak memory 245244 kb
Host smart-80c70fc3-99bd-4cd7-bf72-694299e7066f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2242327605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2242327605
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.47517196
Short name T133
Test name
Test status
Simulation time 11176860081 ps
CPU time 200.07 seconds
Started Aug 12 04:33:44 PM PDT 24
Finished Aug 12 04:37:04 PM PDT 24
Peak memory 265124 kb
Host smart-627e7eac-51cb-4f5c-ba34-99a563f42fcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47517196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_error
s.47517196
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1504346316
Short name T701
Test name
Test status
Simulation time 389817847 ps
CPU time 12.1 seconds
Started Aug 12 04:33:39 PM PDT 24
Finished Aug 12 04:33:52 PM PDT 24
Peak memory 248504 kb
Host smart-83cb1666-db95-4a91-9cd0-2843638f69a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1504346316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1504346316
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3180300524
Short name T780
Test name
Test status
Simulation time 874787435 ps
CPU time 32.82 seconds
Started Aug 12 04:33:42 PM PDT 24
Finished Aug 12 04:34:15 PM PDT 24
Peak memory 245268 kb
Host smart-b655f475-d32c-485d-98e0-e86711f29261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3180300524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3180300524
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.126401986
Short name T800
Test name
Test status
Simulation time 383047628 ps
CPU time 8.24 seconds
Started Aug 12 04:33:31 PM PDT 24
Finished Aug 12 04:33:39 PM PDT 24
Peak memory 240120 kb
Host smart-9149a6a7-a6d8-47e5-912f-f8f26588c2ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126401986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.126401986
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1522356123
Short name T729
Test name
Test status
Simulation time 356721807 ps
CPU time 8.37 seconds
Started Aug 12 04:33:34 PM PDT 24
Finished Aug 12 04:33:42 PM PDT 24
Peak memory 240036 kb
Host smart-7e091da8-388e-44dd-b223-9972bb15a797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1522356123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1522356123
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.594297544
Short name T759
Test name
Test status
Simulation time 12294067 ps
CPU time 1.32 seconds
Started Aug 12 04:33:29 PM PDT 24
Finished Aug 12 04:33:36 PM PDT 24
Peak memory 236224 kb
Host smart-a17a327e-6d99-4dbb-81ed-52b1aac2ff4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=594297544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.594297544
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.813662411
Short name T748
Test name
Test status
Simulation time 1878765776 ps
CPU time 37.95 seconds
Started Aug 12 04:33:40 PM PDT 24
Finished Aug 12 04:34:18 PM PDT 24
Peak memory 245300 kb
Host smart-60ff33f6-1274-4e50-90ff-fc7059e4e58d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=813662411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.813662411
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1871362038
Short name T155
Test name
Test status
Simulation time 5967583723 ps
CPU time 480.41 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:41:37 PM PDT 24
Peak memory 265080 kb
Host smart-d072edfd-f9e8-4e25-8024-91ca82015ba3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871362038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1871362038
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1693352889
Short name T699
Test name
Test status
Simulation time 309860915 ps
CPU time 8.55 seconds
Started Aug 12 04:33:46 PM PDT 24
Finished Aug 12 04:33:55 PM PDT 24
Peak memory 248288 kb
Host smart-06b702e5-19f2-42e7-ad7f-b6508994595f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1693352889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1693352889
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1772206743
Short name T742
Test name
Test status
Simulation time 155994553 ps
CPU time 6.18 seconds
Started Aug 12 04:33:37 PM PDT 24
Finished Aug 12 04:33:44 PM PDT 24
Peak memory 248320 kb
Host smart-3c16cc71-ba33-40a7-8124-5b05b91670f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772206743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1772206743
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2361037730
Short name T705
Test name
Test status
Simulation time 91224666 ps
CPU time 3.55 seconds
Started Aug 12 04:33:37 PM PDT 24
Finished Aug 12 04:33:41 PM PDT 24
Peak memory 237120 kb
Host smart-b97d8fad-b5bc-4f9d-a54f-972ea3b2a72a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2361037730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2361037730
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4171991109
Short name T738
Test name
Test status
Simulation time 9551601 ps
CPU time 1.44 seconds
Started Aug 12 04:33:40 PM PDT 24
Finished Aug 12 04:33:41 PM PDT 24
Peak memory 235132 kb
Host smart-e70266cd-a6de-471c-b808-d8106b34ab34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4171991109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.4171991109
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1762210081
Short name T205
Test name
Test status
Simulation time 93026045 ps
CPU time 12.64 seconds
Started Aug 12 04:33:37 PM PDT 24
Finished Aug 12 04:33:50 PM PDT 24
Peak memory 245020 kb
Host smart-82af0c2c-c05f-42a1-807c-252dd17fd6a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1762210081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1762210081
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1530928422
Short name T823
Test name
Test status
Simulation time 3546046300 ps
CPU time 110.38 seconds
Started Aug 12 04:33:37 PM PDT 24
Finished Aug 12 04:35:28 PM PDT 24
Peak memory 265176 kb
Host smart-79166d2d-3271-434f-ba58-4e48c2344048
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1530928422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1530928422
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3218549524
Short name T789
Test name
Test status
Simulation time 619266002 ps
CPU time 9.11 seconds
Started Aug 12 04:33:31 PM PDT 24
Finished Aug 12 04:33:40 PM PDT 24
Peak memory 248272 kb
Host smart-8638446d-50aa-44a5-b14c-8b45d63e94cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3218549524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3218549524
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1851653750
Short name T821
Test name
Test status
Simulation time 32615582 ps
CPU time 4.62 seconds
Started Aug 12 04:33:51 PM PDT 24
Finished Aug 12 04:33:56 PM PDT 24
Peak memory 253576 kb
Host smart-3760dc3e-69f3-4d3f-9c8e-664cf27e0b50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851653750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1851653750
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1105731182
Short name T187
Test name
Test status
Simulation time 94357198 ps
CPU time 5.44 seconds
Started Aug 12 04:33:29 PM PDT 24
Finished Aug 12 04:33:34 PM PDT 24
Peak memory 240032 kb
Host smart-0a40dedc-651d-4fb9-87cc-08d914753a1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1105731182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1105731182
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4091472378
Short name T808
Test name
Test status
Simulation time 14093963 ps
CPU time 1.69 seconds
Started Aug 12 04:33:42 PM PDT 24
Finished Aug 12 04:33:44 PM PDT 24
Peak memory 236204 kb
Host smart-b6795c66-c0c6-4a25-83e7-eb4c40806027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4091472378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4091472378
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1815990143
Short name T784
Test name
Test status
Simulation time 1830754383 ps
CPU time 25.68 seconds
Started Aug 12 04:33:45 PM PDT 24
Finished Aug 12 04:34:10 PM PDT 24
Peak memory 248160 kb
Host smart-18f14aa1-232c-4874-a3f2-5690b30c9c44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1815990143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1815990143
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.891835771
Short name T167
Test name
Test status
Simulation time 18276737144 ps
CPU time 575.59 seconds
Started Aug 12 04:33:38 PM PDT 24
Finished Aug 12 04:43:13 PM PDT 24
Peak memory 265076 kb
Host smart-88df317e-f60b-4362-8482-1e7cb7004766
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891835771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.891835771
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.35455297
Short name T794
Test name
Test status
Simulation time 969689986 ps
CPU time 15.21 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:33:51 PM PDT 24
Peak memory 248280 kb
Host smart-d95b2127-17b9-4a22-99ad-e87bad2d7525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=35455297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.35455297
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.585549624
Short name T822
Test name
Test status
Simulation time 301074435 ps
CPU time 12.34 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:33:49 PM PDT 24
Peak memory 251424 kb
Host smart-f4ecb193-7470-4b65-b3c1-4d2136e7bcaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585549624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.585549624
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2875460527
Short name T241
Test name
Test status
Simulation time 114216662 ps
CPU time 4.7 seconds
Started Aug 12 04:33:46 PM PDT 24
Finished Aug 12 04:33:50 PM PDT 24
Peak memory 240056 kb
Host smart-2ec1594c-21f9-433c-b91e-b8cfa2c4398a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2875460527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2875460527
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.792196619
Short name T171
Test name
Test status
Simulation time 14833500 ps
CPU time 1.34 seconds
Started Aug 12 04:33:34 PM PDT 24
Finished Aug 12 04:33:36 PM PDT 24
Peak memory 237140 kb
Host smart-571291f1-5359-4cbf-8dae-42bf97f72a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=792196619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.792196619
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1793571325
Short name T764
Test name
Test status
Simulation time 335629505 ps
CPU time 21.81 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:34:09 PM PDT 24
Peak memory 245236 kb
Host smart-ba1f267b-f92d-4be2-8731-9d925da4fd23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1793571325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1793571325
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3546990560
Short name T145
Test name
Test status
Simulation time 2722801184 ps
CPU time 308.22 seconds
Started Aug 12 04:33:31 PM PDT 24
Finished Aug 12 04:38:39 PM PDT 24
Peak memory 267924 kb
Host smart-9a8a9d37-cad2-42ab-a565-f3ccc7f62964
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546990560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3546990560
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3831141798
Short name T728
Test name
Test status
Simulation time 3566214663 ps
CPU time 14.17 seconds
Started Aug 12 04:33:33 PM PDT 24
Finished Aug 12 04:33:47 PM PDT 24
Peak memory 248356 kb
Host smart-992028da-13f0-4d06-bcaa-51fc879ab371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3831141798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3831141798
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2524143022
Short name T819
Test name
Test status
Simulation time 336661132 ps
CPU time 8.15 seconds
Started Aug 12 04:33:50 PM PDT 24
Finished Aug 12 04:33:58 PM PDT 24
Peak memory 240824 kb
Host smart-020d54a5-5cbe-4536-adbd-fe4252e33d5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524143022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2524143022
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2395777458
Short name T781
Test name
Test status
Simulation time 35806424 ps
CPU time 5.76 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:33:41 PM PDT 24
Peak memory 235920 kb
Host smart-bbba10d3-37b8-4cb6-a7e8-f15d724cc446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2395777458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2395777458
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.498757866
Short name T704
Test name
Test status
Simulation time 8040627 ps
CPU time 1.52 seconds
Started Aug 12 04:33:43 PM PDT 24
Finished Aug 12 04:33:45 PM PDT 24
Peak memory 236264 kb
Host smart-329890f3-1ff1-4867-88f1-deb286c21af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=498757866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.498757866
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3228995543
Short name T202
Test name
Test status
Simulation time 3083521097 ps
CPU time 42.04 seconds
Started Aug 12 04:33:31 PM PDT 24
Finished Aug 12 04:34:13 PM PDT 24
Peak memory 245384 kb
Host smart-2f4bdef0-81b9-4e68-9256-f11640ad1f9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3228995543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3228995543
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.82000745
Short name T136
Test name
Test status
Simulation time 6427782184 ps
CPU time 454.73 seconds
Started Aug 12 04:33:42 PM PDT 24
Finished Aug 12 04:41:17 PM PDT 24
Peak memory 265112 kb
Host smart-48871fe5-7782-4491-bb1a-6415e60d34b1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82000745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.82000745
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.819874058
Short name T791
Test name
Test status
Simulation time 410065230 ps
CPU time 27.94 seconds
Started Aug 12 04:33:38 PM PDT 24
Finished Aug 12 04:34:06 PM PDT 24
Peak memory 248200 kb
Host smart-72e4e760-4219-456e-883e-0554e1bd58eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=819874058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.819874058
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2920700771
Short name T285
Test name
Test status
Simulation time 944426249 ps
CPU time 34.89 seconds
Started Aug 12 04:33:40 PM PDT 24
Finished Aug 12 04:34:15 PM PDT 24
Peak memory 237192 kb
Host smart-075686d8-7f50-4566-91cd-57889e74f3d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2920700771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2920700771
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.804943302
Short name T801
Test name
Test status
Simulation time 54309093 ps
CPU time 7.36 seconds
Started Aug 12 04:33:40 PM PDT 24
Finished Aug 12 04:33:48 PM PDT 24
Peak memory 255848 kb
Host smart-c8293e68-6530-409d-aeb3-035a5b7a2f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804943302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.804943302
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2897504470
Short name T743
Test name
Test status
Simulation time 157709661 ps
CPU time 4.86 seconds
Started Aug 12 04:33:54 PM PDT 24
Finished Aug 12 04:33:59 PM PDT 24
Peak memory 236260 kb
Host smart-693a6d03-7579-496f-8c9b-3c2448487c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2897504470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2897504470
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.874684303
Short name T772
Test name
Test status
Simulation time 11780920 ps
CPU time 1.46 seconds
Started Aug 12 04:33:38 PM PDT 24
Finished Aug 12 04:33:39 PM PDT 24
Peak memory 237128 kb
Host smart-a4b6f348-5e13-4b72-9010-313c5779b4ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=874684303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.874684303
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.855094506
Short name T776
Test name
Test status
Simulation time 750273813 ps
CPU time 24.25 seconds
Started Aug 12 04:33:53 PM PDT 24
Finished Aug 12 04:34:18 PM PDT 24
Peak memory 245336 kb
Host smart-820b611e-2812-434a-8036-f536c1f9a30a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=855094506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.855094506
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3030563625
Short name T774
Test name
Test status
Simulation time 1507942622 ps
CPU time 24.83 seconds
Started Aug 12 04:33:32 PM PDT 24
Finished Aug 12 04:33:57 PM PDT 24
Peak memory 248056 kb
Host smart-6ad4bb25-739a-4d27-9d06-d18c8b170b97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3030563625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3030563625
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.551544462
Short name T198
Test name
Test status
Simulation time 6849260132 ps
CPU time 254.4 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:38:01 PM PDT 24
Peak memory 240064 kb
Host smart-239ecb78-eab8-47a2-ba81-5db43e7cffdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=551544462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.551544462
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4019893882
Short name T805
Test name
Test status
Simulation time 8564778715 ps
CPU time 231.12 seconds
Started Aug 12 04:33:42 PM PDT 24
Finished Aug 12 04:37:33 PM PDT 24
Peak memory 237196 kb
Host smart-4c074c82-fd78-4002-8e0e-741f73b283d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4019893882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.4019893882
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4059322005
Short name T711
Test name
Test status
Simulation time 227964964 ps
CPU time 8.77 seconds
Started Aug 12 04:33:12 PM PDT 24
Finished Aug 12 04:33:21 PM PDT 24
Peak memory 240300 kb
Host smart-34dcc655-9e7f-4e17-b475-3d454c052f72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4059322005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.4059322005
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.95309050
Short name T751
Test name
Test status
Simulation time 460497051 ps
CPU time 5.74 seconds
Started Aug 12 04:33:06 PM PDT 24
Finished Aug 12 04:33:12 PM PDT 24
Peak memory 256276 kb
Host smart-ee841a5c-217e-432a-b800-0a471a8c0b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95309050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.alert_handler_csr_mem_rw_with_rand_reset.95309050
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.5330195
Short name T754
Test name
Test status
Simulation time 64157326 ps
CPU time 4.99 seconds
Started Aug 12 04:33:20 PM PDT 24
Finished Aug 12 04:33:25 PM PDT 24
Peak memory 236284 kb
Host smart-2a17e8e4-0c56-4699-b0db-ec3aa2de532c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=5330195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.5330195
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2135668071
Short name T803
Test name
Test status
Simulation time 9583000 ps
CPU time 1.48 seconds
Started Aug 12 04:33:08 PM PDT 24
Finished Aug 12 04:33:09 PM PDT 24
Peak memory 237136 kb
Host smart-462e77a7-b635-4628-ab57-32758460870c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2135668071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2135668071
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1488480124
Short name T765
Test name
Test status
Simulation time 90707916 ps
CPU time 10.96 seconds
Started Aug 12 04:33:16 PM PDT 24
Finished Aug 12 04:33:27 PM PDT 24
Peak memory 244444 kb
Host smart-d4d65d73-8a79-4640-966b-ecbc64012406
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1488480124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1488480124
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2863998248
Short name T131
Test name
Test status
Simulation time 6465778582 ps
CPU time 189.88 seconds
Started Aug 12 04:32:54 PM PDT 24
Finished Aug 12 04:36:04 PM PDT 24
Peak memory 271452 kb
Host smart-a163dec9-c504-4517-bf93-7b96fb3990cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2863998248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2863998248
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.541353615
Short name T134
Test name
Test status
Simulation time 25194439059 ps
CPU time 566.76 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:42:25 PM PDT 24
Peak memory 265096 kb
Host smart-1edb9116-b956-40c2-a2e9-653258ae48af
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541353615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.541353615
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.762351264
Short name T734
Test name
Test status
Simulation time 216235848 ps
CPU time 13.01 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:33:11 PM PDT 24
Peak memory 247888 kb
Host smart-d0807333-214c-465c-ae71-f9d98106246a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=762351264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.762351264
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1149087274
Short name T816
Test name
Test status
Simulation time 206309153 ps
CPU time 9.37 seconds
Started Aug 12 04:33:06 PM PDT 24
Finished Aug 12 04:33:16 PM PDT 24
Peak memory 237136 kb
Host smart-216b9e00-a98d-4ec3-a6c2-26c4e9b1ed94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1149087274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1149087274
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2524150138
Short name T358
Test name
Test status
Simulation time 7608643 ps
CPU time 1.51 seconds
Started Aug 12 04:33:37 PM PDT 24
Finished Aug 12 04:33:38 PM PDT 24
Peak memory 235140 kb
Host smart-60e1bb7c-2955-4f88-8316-0c321769caaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2524150138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2524150138
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2344898542
Short name T717
Test name
Test status
Simulation time 16264090 ps
CPU time 1.21 seconds
Started Aug 12 04:33:50 PM PDT 24
Finished Aug 12 04:33:51 PM PDT 24
Peak memory 237096 kb
Host smart-0dfcbffc-387c-4f0a-8706-435a62cafcd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2344898542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2344898542
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4207055496
Short name T730
Test name
Test status
Simulation time 9518242 ps
CPU time 1.52 seconds
Started Aug 12 04:33:54 PM PDT 24
Finished Aug 12 04:33:56 PM PDT 24
Peak memory 237068 kb
Host smart-a96fb2bf-ec4c-4cbe-8dbe-7238154827ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4207055496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4207055496
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1375099497
Short name T766
Test name
Test status
Simulation time 10453538 ps
CPU time 1.25 seconds
Started Aug 12 04:33:48 PM PDT 24
Finished Aug 12 04:33:49 PM PDT 24
Peak memory 237116 kb
Host smart-4c7ba896-1c9e-4528-8d72-052342e1197c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1375099497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1375099497
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3688211234
Short name T788
Test name
Test status
Simulation time 7997480 ps
CPU time 1.51 seconds
Started Aug 12 04:33:44 PM PDT 24
Finished Aug 12 04:33:46 PM PDT 24
Peak memory 236144 kb
Host smart-100c05b7-7bc2-4c8e-b51e-b518d7d7091d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3688211234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3688211234
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3851362508
Short name T810
Test name
Test status
Simulation time 10768142 ps
CPU time 1.29 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:33:48 PM PDT 24
Peak memory 236104 kb
Host smart-3055f1af-aee3-4ece-961b-e615a6c70b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3851362508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3851362508
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3135728449
Short name T820
Test name
Test status
Simulation time 11562485 ps
CPU time 1.34 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:33:36 PM PDT 24
Peak memory 236256 kb
Host smart-886c463b-143c-41c8-be5b-28d2aa3a02e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3135728449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3135728449
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1849190055
Short name T787
Test name
Test status
Simulation time 26479328 ps
CPU time 1.5 seconds
Started Aug 12 04:33:43 PM PDT 24
Finished Aug 12 04:33:45 PM PDT 24
Peak memory 237208 kb
Host smart-ad1d523e-1044-40eb-85dd-37a04b787ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1849190055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1849190055
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2972129537
Short name T762
Test name
Test status
Simulation time 7355173 ps
CPU time 1.56 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:33:49 PM PDT 24
Peak memory 237208 kb
Host smart-0f79f5a5-7413-4411-9574-0e07a0e701a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2972129537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2972129537
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1694787786
Short name T815
Test name
Test status
Simulation time 27350791 ps
CPU time 1.38 seconds
Started Aug 12 04:33:34 PM PDT 24
Finished Aug 12 04:33:36 PM PDT 24
Peak memory 236232 kb
Host smart-a27a2edb-a44a-4dca-9d4b-1854b9677021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1694787786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1694787786
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4239474341
Short name T718
Test name
Test status
Simulation time 3812910476 ps
CPU time 255.41 seconds
Started Aug 12 04:33:04 PM PDT 24
Finished Aug 12 04:37:20 PM PDT 24
Peak memory 240432 kb
Host smart-536799cf-1239-40f4-83c7-c6ba8c7c0b1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4239474341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.4239474341
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1603610091
Short name T747
Test name
Test status
Simulation time 6465892292 ps
CPU time 376.58 seconds
Started Aug 12 04:33:33 PM PDT 24
Finished Aug 12 04:39:49 PM PDT 24
Peak memory 237192 kb
Host smart-e6c510f0-2592-46e3-8d43-05c8e32a8450
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1603610091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1603610091
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1093277895
Short name T201
Test name
Test status
Simulation time 209139588 ps
CPU time 5.58 seconds
Started Aug 12 04:33:03 PM PDT 24
Finished Aug 12 04:33:08 PM PDT 24
Peak memory 248196 kb
Host smart-8a5fd58c-1f77-4659-8fce-57f250b8d94b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1093277895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1093277895
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3295532971
Short name T188
Test name
Test status
Simulation time 74448812 ps
CPU time 6.13 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:33:02 PM PDT 24
Peak memory 240076 kb
Host smart-deeee577-06a3-41ef-ae7a-e1a339b7a9d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295532971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3295532971
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3286218879
Short name T722
Test name
Test status
Simulation time 155720082 ps
CPU time 9.31 seconds
Started Aug 12 04:33:11 PM PDT 24
Finished Aug 12 04:33:20 PM PDT 24
Peak memory 237112 kb
Host smart-9ab3a763-6005-4083-b061-51e3970ebe6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3286218879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3286218879
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3806814779
Short name T793
Test name
Test status
Simulation time 11571735 ps
CPU time 1.64 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:32:58 PM PDT 24
Peak memory 237468 kb
Host smart-b7f748ec-f0b4-4e02-a464-1dd7957441cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3806814779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3806814779
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3755968278
Short name T775
Test name
Test status
Simulation time 2935426408 ps
CPU time 48.51 seconds
Started Aug 12 04:33:42 PM PDT 24
Finished Aug 12 04:34:31 PM PDT 24
Peak memory 245388 kb
Host smart-68de60f2-d51c-46e0-8891-aa5bda56359c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3755968278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3755968278
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3301336253
Short name T159
Test name
Test status
Simulation time 5314693030 ps
CPU time 179.39 seconds
Started Aug 12 04:32:59 PM PDT 24
Finished Aug 12 04:35:58 PM PDT 24
Peak memory 265092 kb
Host smart-a5114cc0-3afb-4f30-9c0e-208cc62ab676
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3301336253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3301336253
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2670473781
Short name T163
Test name
Test status
Simulation time 2196180011 ps
CPU time 291.99 seconds
Started Aug 12 04:33:04 PM PDT 24
Finished Aug 12 04:37:56 PM PDT 24
Peak memory 264244 kb
Host smart-d0975c4c-2682-4313-8461-153c215bd64d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670473781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2670473781
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3476701120
Short name T782
Test name
Test status
Simulation time 70919858 ps
CPU time 7.85 seconds
Started Aug 12 04:33:12 PM PDT 24
Finished Aug 12 04:33:20 PM PDT 24
Peak memory 248292 kb
Host smart-b6f7fa2d-39b9-45ea-8970-b7f323466935
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3476701120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3476701120
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4124178489
Short name T706
Test name
Test status
Simulation time 15581862 ps
CPU time 1.29 seconds
Started Aug 12 04:33:48 PM PDT 24
Finished Aug 12 04:33:49 PM PDT 24
Peak memory 235048 kb
Host smart-1e68dbc1-0de0-4d24-ac2f-0b73a1b20eed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4124178489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.4124178489
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1834432133
Short name T727
Test name
Test status
Simulation time 10760370 ps
CPU time 1.25 seconds
Started Aug 12 04:33:49 PM PDT 24
Finished Aug 12 04:33:51 PM PDT 24
Peak memory 235196 kb
Host smart-319c75ce-cc94-4b8f-923c-8b07dd7dc661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1834432133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1834432133
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2550489636
Short name T357
Test name
Test status
Simulation time 12653615 ps
CPU time 1.44 seconds
Started Aug 12 04:33:51 PM PDT 24
Finished Aug 12 04:33:52 PM PDT 24
Peak memory 237104 kb
Host smart-f82c46a7-d8dd-4975-903f-9b73c40168b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2550489636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2550489636
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.342043081
Short name T723
Test name
Test status
Simulation time 9452205 ps
CPU time 1.32 seconds
Started Aug 12 04:33:41 PM PDT 24
Finished Aug 12 04:33:43 PM PDT 24
Peak memory 236216 kb
Host smart-fa4bc7ca-9909-4e94-9c3c-178b4a6cbe69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=342043081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.342043081
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.192461121
Short name T817
Test name
Test status
Simulation time 16085429 ps
CPU time 1.37 seconds
Started Aug 12 04:33:38 PM PDT 24
Finished Aug 12 04:33:39 PM PDT 24
Peak memory 236300 kb
Host smart-67e5eaf0-f0f1-43df-a36a-cc1a837fd76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=192461121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.192461121
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1433149207
Short name T710
Test name
Test status
Simulation time 7990167 ps
CPU time 1.49 seconds
Started Aug 12 04:33:42 PM PDT 24
Finished Aug 12 04:33:44 PM PDT 24
Peak memory 236248 kb
Host smart-62d17774-1c4c-4398-ba66-780133e5131a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1433149207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1433149207
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.708145964
Short name T763
Test name
Test status
Simulation time 9381288 ps
CPU time 1.6 seconds
Started Aug 12 04:33:36 PM PDT 24
Finished Aug 12 04:33:37 PM PDT 24
Peak memory 236276 kb
Host smart-26e11ec3-1611-4b91-9d2c-81bc1759a9a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=708145964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.708145964
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3724243085
Short name T360
Test name
Test status
Simulation time 19285703 ps
CPU time 1.28 seconds
Started Aug 12 04:33:41 PM PDT 24
Finished Aug 12 04:33:42 PM PDT 24
Peak memory 235100 kb
Host smart-c339935c-db57-4605-a071-b5922a461531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3724243085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3724243085
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1172922677
Short name T812
Test name
Test status
Simulation time 6190793 ps
CPU time 1.42 seconds
Started Aug 12 04:33:52 PM PDT 24
Finished Aug 12 04:33:53 PM PDT 24
Peak memory 237112 kb
Host smart-52deb5e2-820d-4307-a28c-27860541b4cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1172922677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1172922677
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2835922348
Short name T797
Test name
Test status
Simulation time 3414799031 ps
CPU time 120.48 seconds
Started Aug 12 04:33:11 PM PDT 24
Finished Aug 12 04:35:12 PM PDT 24
Peak memory 237196 kb
Host smart-0e5ae990-7d30-44de-9b06-3c06afbe5abc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2835922348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2835922348
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.345879889
Short name T732
Test name
Test status
Simulation time 14849833837 ps
CPU time 199.22 seconds
Started Aug 12 04:33:07 PM PDT 24
Finished Aug 12 04:36:27 PM PDT 24
Peak memory 236200 kb
Host smart-a8e8e60f-4e49-4f71-89a8-dcdd9a1b43c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=345879889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.345879889
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3069718833
Short name T716
Test name
Test status
Simulation time 40218681 ps
CPU time 3.8 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:33:01 PM PDT 24
Peak memory 248240 kb
Host smart-09da9dda-6589-48ed-a424-3d36e5301d6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3069718833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3069718833
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3356694690
Short name T725
Test name
Test status
Simulation time 64163856 ps
CPU time 10.33 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:33:08 PM PDT 24
Peak memory 254108 kb
Host smart-c8963a59-9a9b-49e1-8e3e-32b92f57c184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356694690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3356694690
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1154324668
Short name T189
Test name
Test status
Simulation time 129568104 ps
CPU time 9.45 seconds
Started Aug 12 04:32:59 PM PDT 24
Finished Aug 12 04:33:09 PM PDT 24
Peak memory 240024 kb
Host smart-0a6bf3f6-cbe3-4981-95f0-10f61b82651b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1154324668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1154324668
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3689517067
Short name T768
Test name
Test status
Simulation time 9642544 ps
CPU time 1.59 seconds
Started Aug 12 04:33:07 PM PDT 24
Finished Aug 12 04:33:09 PM PDT 24
Peak memory 236200 kb
Host smart-99274d54-8f36-4d20-a7b0-9df37808aa1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3689517067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3689517067
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3582962364
Short name T737
Test name
Test status
Simulation time 1117005891 ps
CPU time 33.8 seconds
Started Aug 12 04:33:11 PM PDT 24
Finished Aug 12 04:33:50 PM PDT 24
Peak memory 244392 kb
Host smart-bd6a904d-88bb-492d-893b-a5202997d55e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3582962364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3582962364
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3502015728
Short name T702
Test name
Test status
Simulation time 632156983 ps
CPU time 12.13 seconds
Started Aug 12 04:33:30 PM PDT 24
Finished Aug 12 04:33:43 PM PDT 24
Peak memory 252952 kb
Host smart-5ee36694-3451-42f8-8b55-1610d1e00130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3502015728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3502015728
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1719868562
Short name T712
Test name
Test status
Simulation time 8062436 ps
CPU time 1.58 seconds
Started Aug 12 04:33:55 PM PDT 24
Finished Aug 12 04:33:56 PM PDT 24
Peak memory 237064 kb
Host smart-59d81072-dee8-41b0-9463-8c4e344902cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1719868562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1719868562
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1623596137
Short name T741
Test name
Test status
Simulation time 18920061 ps
CPU time 1.52 seconds
Started Aug 12 04:33:45 PM PDT 24
Finished Aug 12 04:33:47 PM PDT 24
Peak memory 237160 kb
Host smart-05663f8f-c7c7-4601-bf79-f406f62d55cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1623596137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1623596137
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1361647467
Short name T799
Test name
Test status
Simulation time 7599836 ps
CPU time 1.26 seconds
Started Aug 12 04:33:40 PM PDT 24
Finished Aug 12 04:33:41 PM PDT 24
Peak memory 235152 kb
Host smart-ae741ccb-564d-4a84-8a4f-49112b8c0749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1361647467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1361647467
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1669175351
Short name T804
Test name
Test status
Simulation time 11347787 ps
CPU time 1.32 seconds
Started Aug 12 04:33:37 PM PDT 24
Finished Aug 12 04:33:39 PM PDT 24
Peak memory 237128 kb
Host smart-5aece4f4-6c0d-4453-8fa7-311fee03f18a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1669175351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1669175351
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2414139687
Short name T818
Test name
Test status
Simulation time 9123922 ps
CPU time 1.53 seconds
Started Aug 12 04:33:40 PM PDT 24
Finished Aug 12 04:33:41 PM PDT 24
Peak memory 235892 kb
Host smart-18df5429-71ce-410c-a9ed-df4be24237ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2414139687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2414139687
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.685276537
Short name T703
Test name
Test status
Simulation time 12028088 ps
CPU time 1.54 seconds
Started Aug 12 04:33:53 PM PDT 24
Finished Aug 12 04:33:54 PM PDT 24
Peak memory 236216 kb
Host smart-bf59ead6-942d-4cdc-98de-b3992b356a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=685276537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.685276537
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2998319980
Short name T231
Test name
Test status
Simulation time 6786253 ps
CPU time 1.45 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:33:49 PM PDT 24
Peak memory 236132 kb
Host smart-a535036f-e9e2-481c-80cc-de004b83d2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2998319980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2998319980
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3409493374
Short name T355
Test name
Test status
Simulation time 10146838 ps
CPU time 1.44 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:33:37 PM PDT 24
Peak memory 237124 kb
Host smart-d3dc42f5-568d-4a32-81ce-619bb02e849d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3409493374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3409493374
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1726830798
Short name T757
Test name
Test status
Simulation time 10496211 ps
CPU time 1.34 seconds
Started Aug 12 04:33:39 PM PDT 24
Finished Aug 12 04:33:40 PM PDT 24
Peak memory 236280 kb
Host smart-d16da693-aeb3-454f-980f-c26318551e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1726830798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1726830798
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1852297349
Short name T720
Test name
Test status
Simulation time 9324728 ps
CPU time 1.51 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:33:49 PM PDT 24
Peak memory 237144 kb
Host smart-b60e3422-c006-4664-b612-fb588009abf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1852297349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1852297349
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2832923943
Short name T769
Test name
Test status
Simulation time 137489424 ps
CPU time 9.42 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:33:07 PM PDT 24
Peak memory 239268 kb
Host smart-3c56d8b0-c3e5-4d91-ba50-6bb2b3177e0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832923943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2832923943
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3471196945
Short name T760
Test name
Test status
Simulation time 193568667 ps
CPU time 10.03 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:33:08 PM PDT 24
Peak memory 237108 kb
Host smart-8d6a9bf1-af7b-466b-a5ce-4f58256a4cf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3471196945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3471196945
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.301212849
Short name T739
Test name
Test status
Simulation time 13990854 ps
CPU time 1.34 seconds
Started Aug 12 04:33:03 PM PDT 24
Finished Aug 12 04:33:05 PM PDT 24
Peak memory 237128 kb
Host smart-e94fa7f7-07d5-4c5e-ae20-319db9ea9aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=301212849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.301212849
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.310166854
Short name T790
Test name
Test status
Simulation time 389869964 ps
CPU time 12.36 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:33:10 PM PDT 24
Peak memory 245328 kb
Host smart-6b612712-4aa1-42fd-9946-c5efd2698e7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=310166854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.310166854
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2130519599
Short name T138
Test name
Test status
Simulation time 3275298393 ps
CPU time 209.96 seconds
Started Aug 12 04:33:39 PM PDT 24
Finished Aug 12 04:37:09 PM PDT 24
Peak memory 273320 kb
Host smart-12307ccd-1d42-4942-a794-7538c377ddff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2130519599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2130519599
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2343133472
Short name T698
Test name
Test status
Simulation time 52490770 ps
CPU time 8.01 seconds
Started Aug 12 04:32:56 PM PDT 24
Finished Aug 12 04:33:04 PM PDT 24
Peak memory 248064 kb
Host smart-3367b3f9-d729-4454-a7be-9b9f85d7693b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2343133472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2343133472
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1644808536
Short name T750
Test name
Test status
Simulation time 516947278 ps
CPU time 7.42 seconds
Started Aug 12 04:33:08 PM PDT 24
Finished Aug 12 04:33:16 PM PDT 24
Peak memory 238024 kb
Host smart-89c804b0-5d5d-420e-a472-b7b2def53197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644808536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1644808536
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1675803816
Short name T200
Test name
Test status
Simulation time 257368783 ps
CPU time 5.11 seconds
Started Aug 12 04:33:32 PM PDT 24
Finished Aug 12 04:33:37 PM PDT 24
Peak memory 239024 kb
Host smart-65a5e3ca-800e-4ba0-8323-5dde739d3d33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1675803816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1675803816
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3719419317
Short name T172
Test name
Test status
Simulation time 12073188 ps
CPU time 1.35 seconds
Started Aug 12 04:33:12 PM PDT 24
Finished Aug 12 04:33:13 PM PDT 24
Peak memory 236288 kb
Host smart-83c48fc4-5b08-4dd7-9d17-c38e88429ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3719419317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3719419317
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.726554367
Short name T809
Test name
Test status
Simulation time 6665565746 ps
CPU time 21.96 seconds
Started Aug 12 04:33:15 PM PDT 24
Finished Aug 12 04:33:37 PM PDT 24
Peak memory 245256 kb
Host smart-8f90c24c-e8f6-427b-9155-f3dd727f0eeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=726554367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.726554367
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3207355268
Short name T135
Test name
Test status
Simulation time 2187358582 ps
CPU time 317.03 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:38:16 PM PDT 24
Peak memory 265064 kb
Host smart-65eaf193-b614-416d-92ad-34ae493829d7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207355268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3207355268
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2285890286
Short name T778
Test name
Test status
Simulation time 104303247 ps
CPU time 7.72 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:33:43 PM PDT 24
Peak memory 248444 kb
Host smart-274de8e2-497a-4d7d-8e3e-f37b95dc29d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2285890286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2285890286
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1919463808
Short name T749
Test name
Test status
Simulation time 582193229 ps
CPU time 11.33 seconds
Started Aug 12 04:33:18 PM PDT 24
Finished Aug 12 04:33:30 PM PDT 24
Peak memory 243224 kb
Host smart-b24d47dd-abbc-4a97-b0b5-92e5ed14cf5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919463808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1919463808
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.568061618
Short name T719
Test name
Test status
Simulation time 33496079 ps
CPU time 5.28 seconds
Started Aug 12 04:32:57 PM PDT 24
Finished Aug 12 04:33:03 PM PDT 24
Peak memory 240052 kb
Host smart-b587bef7-d884-4914-a800-ac9b8e3da6e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=568061618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.568061618
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2239795244
Short name T806
Test name
Test status
Simulation time 10206688 ps
CPU time 1.63 seconds
Started Aug 12 04:33:39 PM PDT 24
Finished Aug 12 04:33:41 PM PDT 24
Peak memory 237076 kb
Host smart-c73c01b9-f216-4dad-b64e-d457f73424f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2239795244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2239795244
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1554950618
Short name T746
Test name
Test status
Simulation time 857947883 ps
CPU time 17.81 seconds
Started Aug 12 04:33:29 PM PDT 24
Finished Aug 12 04:33:47 PM PDT 24
Peak memory 239984 kb
Host smart-a2bc9f16-a54e-484d-beaf-2121c79e341d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1554950618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1554950618
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3592617916
Short name T713
Test name
Test status
Simulation time 1249537153 ps
CPU time 18.82 seconds
Started Aug 12 04:32:58 PM PDT 24
Finished Aug 12 04:33:17 PM PDT 24
Peak memory 253592 kb
Host smart-5194b6d5-8a39-40e1-9bf5-a070f65beaad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3592617916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3592617916
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4174669204
Short name T240
Test name
Test status
Simulation time 357404649 ps
CPU time 7.77 seconds
Started Aug 12 04:33:23 PM PDT 24
Finished Aug 12 04:33:31 PM PDT 24
Peak memory 239432 kb
Host smart-03f6aec5-a052-4251-b948-94034d1cd9ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174669204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4174669204
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3601142295
Short name T726
Test name
Test status
Simulation time 364998976 ps
CPU time 7.4 seconds
Started Aug 12 04:33:27 PM PDT 24
Finished Aug 12 04:33:35 PM PDT 24
Peak memory 240056 kb
Host smart-fa92b183-c0ec-478a-99d7-055d719c86a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3601142295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3601142295
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2422367778
Short name T785
Test name
Test status
Simulation time 8264919 ps
CPU time 1.26 seconds
Started Aug 12 04:33:16 PM PDT 24
Finished Aug 12 04:33:18 PM PDT 24
Peak memory 234300 kb
Host smart-16247302-74b9-4f33-a7b4-c3ae4711c75f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2422367778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2422367778
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2456509188
Short name T767
Test name
Test status
Simulation time 2418721174 ps
CPU time 37.47 seconds
Started Aug 12 04:33:37 PM PDT 24
Finished Aug 12 04:34:15 PM PDT 24
Peak memory 248224 kb
Host smart-67af6b1d-ac27-46ab-9c35-abf4eefd8122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2456509188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2456509188
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.4175498220
Short name T150
Test name
Test status
Simulation time 2137131736 ps
CPU time 123.87 seconds
Started Aug 12 04:33:34 PM PDT 24
Finished Aug 12 04:35:38 PM PDT 24
Peak memory 257076 kb
Host smart-d9837623-6ea6-40d2-96f2-f873321e899a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4175498220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.4175498220
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.585413162
Short name T165
Test name
Test status
Simulation time 17090908326 ps
CPU time 605.65 seconds
Started Aug 12 04:33:30 PM PDT 24
Finished Aug 12 04:43:36 PM PDT 24
Peak memory 265132 kb
Host smart-9ffc51df-e071-4b9f-ab52-0aec35d56ceb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585413162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.585413162
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1573868393
Short name T700
Test name
Test status
Simulation time 1178058934 ps
CPU time 18.56 seconds
Started Aug 12 04:33:31 PM PDT 24
Finished Aug 12 04:33:50 PM PDT 24
Peak memory 254344 kb
Host smart-7591a8b9-293a-4e5d-ae61-7b361ffc5c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1573868393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1573868393
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.816669386
Short name T731
Test name
Test status
Simulation time 2183418812 ps
CPU time 74.73 seconds
Started Aug 12 04:33:31 PM PDT 24
Finished Aug 12 04:34:46 PM PDT 24
Peak memory 240056 kb
Host smart-e480f48a-22cc-4749-a053-d90fff15d9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=816669386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.816669386
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2528603605
Short name T770
Test name
Test status
Simulation time 97229697 ps
CPU time 7.89 seconds
Started Aug 12 04:33:17 PM PDT 24
Finished Aug 12 04:33:25 PM PDT 24
Peak memory 256492 kb
Host smart-66fe81e0-8931-469c-a949-044d452b1958
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528603605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2528603605
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1570423232
Short name T758
Test name
Test status
Simulation time 35215531 ps
CPU time 5.61 seconds
Started Aug 12 04:33:34 PM PDT 24
Finished Aug 12 04:33:40 PM PDT 24
Peak memory 237084 kb
Host smart-baba92f3-b6bc-4314-83ac-dcc2f73ca2ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1570423232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1570423232
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.645127036
Short name T736
Test name
Test status
Simulation time 11183522 ps
CPU time 1.36 seconds
Started Aug 12 04:33:21 PM PDT 24
Finished Aug 12 04:33:23 PM PDT 24
Peak memory 237124 kb
Host smart-399534ad-204e-4e3c-9664-fa0de3aafd1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=645127036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.645127036
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4078979841
Short name T773
Test name
Test status
Simulation time 284153871 ps
CPU time 18.24 seconds
Started Aug 12 04:33:20 PM PDT 24
Finished Aug 12 04:33:39 PM PDT 24
Peak memory 244424 kb
Host smart-1dc319a6-e8ae-4e9e-bbc1-039dc461625f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4078979841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4078979841
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.684518667
Short name T148
Test name
Test status
Simulation time 2419528923 ps
CPU time 167.33 seconds
Started Aug 12 04:33:35 PM PDT 24
Finished Aug 12 04:36:23 PM PDT 24
Peak memory 265472 kb
Host smart-89eb1731-a2e9-45d5-830c-4973a7d54779
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=684518667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.684518667
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4097415032
Short name T777
Test name
Test status
Simulation time 493079556 ps
CPU time 17.83 seconds
Started Aug 12 04:33:30 PM PDT 24
Finished Aug 12 04:33:48 PM PDT 24
Peak memory 250468 kb
Host smart-d9b2dc15-6772-45fa-b6e3-b155b97596f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4097415032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4097415032
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3327474244
Short name T59
Test name
Test status
Simulation time 327837040852 ps
CPU time 2673.1 seconds
Started Aug 12 04:34:03 PM PDT 24
Finished Aug 12 05:18:36 PM PDT 24
Peak memory 286016 kb
Host smart-611ba391-0c24-4791-b0c0-6e64dc1e5ddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327474244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3327474244
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1973018008
Short name T232
Test name
Test status
Simulation time 615685533 ps
CPU time 12.21 seconds
Started Aug 12 04:33:56 PM PDT 24
Finished Aug 12 04:34:08 PM PDT 24
Peak memory 249004 kb
Host smart-763213dd-dfad-4a12-8934-6acbf90c72f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1973018008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1973018008
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1960780239
Short name T530
Test name
Test status
Simulation time 3588412415 ps
CPU time 222.08 seconds
Started Aug 12 04:34:06 PM PDT 24
Finished Aug 12 04:37:48 PM PDT 24
Peak memory 256860 kb
Host smart-c443ed9c-8db7-42a3-902c-20621aeb404a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19607
80239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1960780239
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4012222493
Short name T668
Test name
Test status
Simulation time 479748454 ps
CPU time 13.66 seconds
Started Aug 12 04:33:58 PM PDT 24
Finished Aug 12 04:34:12 PM PDT 24
Peak memory 248552 kb
Host smart-f91dd357-0e09-4492-9777-3f841b5a81ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40122
22493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4012222493
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3888169491
Short name T342
Test name
Test status
Simulation time 158715341490 ps
CPU time 2485.45 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 286536 kb
Host smart-d8e5a0fd-c468-4750-852f-4557e079c386
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888169491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3888169491
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.4193364481
Short name T469
Test name
Test status
Simulation time 113637823680 ps
CPU time 1815.71 seconds
Started Aug 12 04:33:48 PM PDT 24
Finished Aug 12 05:04:04 PM PDT 24
Peak memory 290016 kb
Host smart-68eb0fcd-44f3-442f-91a7-c85ea0c1c834
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193364481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.4193364481
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3857553160
Short name T510
Test name
Test status
Simulation time 736271887 ps
CPU time 45.44 seconds
Started Aug 12 04:33:43 PM PDT 24
Finished Aug 12 04:34:34 PM PDT 24
Peak memory 256772 kb
Host smart-b2db08f5-9caa-486e-a34a-f5866955cdd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38575
53160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3857553160
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1803441650
Short name T429
Test name
Test status
Simulation time 1711936599 ps
CPU time 44.77 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:34:42 PM PDT 24
Peak memory 248400 kb
Host smart-c3edd858-fddf-44be-8838-fd6e524a6f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18034
41650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1803441650
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1464225387
Short name T34
Test name
Test status
Simulation time 2676026148 ps
CPU time 60.39 seconds
Started Aug 12 04:33:50 PM PDT 24
Finished Aug 12 04:34:50 PM PDT 24
Peak memory 269684 kb
Host smart-5b9891c3-6788-45c2-8ac9-8be6e76f4cea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1464225387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1464225387
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2306335848
Short name T612
Test name
Test status
Simulation time 4449438319 ps
CPU time 64.32 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:34:51 PM PDT 24
Peak memory 257276 kb
Host smart-36a57b39-57c6-4a15-9712-20653d29b27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23063
35848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2306335848
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2667017009
Short name T296
Test name
Test status
Simulation time 1837654754 ps
CPU time 29.24 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:34:27 PM PDT 24
Peak memory 257188 kb
Host smart-41da673f-74de-4260-91cf-e2b4b2a6d022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26670
17009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2667017009
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1477776632
Short name T120
Test name
Test status
Simulation time 281704318383 ps
CPU time 1894.6 seconds
Started Aug 12 04:34:07 PM PDT 24
Finished Aug 12 05:05:42 PM PDT 24
Peak memory 288432 kb
Host smart-59d0806a-ff69-433f-a269-b90b47fd9ed3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477776632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1477776632
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3129022605
Short name T298
Test name
Test status
Simulation time 39503055878 ps
CPU time 1424.17 seconds
Started Aug 12 04:34:01 PM PDT 24
Finished Aug 12 04:57:46 PM PDT 24
Peak memory 273292 kb
Host smart-ad52ccdc-a9be-499e-846e-676aaaa68e57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129022605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3129022605
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2262278893
Short name T550
Test name
Test status
Simulation time 435836117 ps
CPU time 19.56 seconds
Started Aug 12 04:34:13 PM PDT 24
Finished Aug 12 04:34:33 PM PDT 24
Peak memory 249008 kb
Host smart-9199b19a-7dd7-4b5f-b973-3f1ae8503523
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2262278893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2262278893
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.169150418
Short name T591
Test name
Test status
Simulation time 303327552 ps
CPU time 22.19 seconds
Started Aug 12 04:33:43 PM PDT 24
Finished Aug 12 04:34:05 PM PDT 24
Peak memory 256708 kb
Host smart-4be64b7c-3ab0-48eb-b47c-91a62f29fb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915
0418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.169150418
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.161257381
Short name T638
Test name
Test status
Simulation time 409229709 ps
CPU time 8.9 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:33:56 PM PDT 24
Peak memory 248568 kb
Host smart-82ef69a1-96fa-401d-bed5-e60cc7122a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16125
7381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.161257381
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3267132894
Short name T13
Test name
Test status
Simulation time 25021094793 ps
CPU time 727.37 seconds
Started Aug 12 04:34:11 PM PDT 24
Finished Aug 12 04:46:23 PM PDT 24
Peak memory 273660 kb
Host smart-86784335-bb90-498a-982f-19eee8e9df38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267132894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3267132894
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2361188305
Short name T448
Test name
Test status
Simulation time 11407253841 ps
CPU time 494.87 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:42:32 PM PDT 24
Peak memory 249044 kb
Host smart-4b58edbc-a7f0-4e83-9a17-37da163cdf8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361188305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2361188305
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.4053120515
Short name T247
Test name
Test status
Simulation time 1277027146 ps
CPU time 18.61 seconds
Started Aug 12 04:33:43 PM PDT 24
Finished Aug 12 04:34:02 PM PDT 24
Peak memory 249072 kb
Host smart-c51ecbb5-cd62-4222-8fc2-753094375e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40531
20515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.4053120515
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2144949523
Short name T47
Test name
Test status
Simulation time 590854721 ps
CPU time 27.47 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:34:15 PM PDT 24
Peak memory 248368 kb
Host smart-dda48094-640b-4448-bf24-9b600ed767fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21449
49523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2144949523
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.425141704
Short name T9
Test name
Test status
Simulation time 792541354 ps
CPU time 12.37 seconds
Started Aug 12 04:33:55 PM PDT 24
Finished Aug 12 04:34:08 PM PDT 24
Peak memory 276960 kb
Host smart-fc129762-564d-406b-9522-7137cf921bad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=425141704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.425141704
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1816118304
Short name T289
Test name
Test status
Simulation time 184621678 ps
CPU time 12.29 seconds
Started Aug 12 04:33:46 PM PDT 24
Finished Aug 12 04:33:58 PM PDT 24
Peak memory 248920 kb
Host smart-abc8fbb2-09a5-45f4-af10-520453e6bcb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18161
18304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1816118304
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.30227871
Short name T394
Test name
Test status
Simulation time 781493377 ps
CPU time 7.54 seconds
Started Aug 12 04:33:46 PM PDT 24
Finished Aug 12 04:33:54 PM PDT 24
Peak memory 249420 kb
Host smart-634ceeec-dfa5-4e27-be2b-4da136146d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30227
871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.30227871
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.718404327
Short name T212
Test name
Test status
Simulation time 44761745 ps
CPU time 3.74 seconds
Started Aug 12 04:34:35 PM PDT 24
Finished Aug 12 04:34:38 PM PDT 24
Peak memory 249116 kb
Host smart-2023ddfa-14b9-449d-9ae6-e4edf5c0803d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=718404327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.718404327
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1109173318
Short name T537
Test name
Test status
Simulation time 7225351654 ps
CPU time 574.46 seconds
Started Aug 12 04:34:30 PM PDT 24
Finished Aug 12 04:44:04 PM PDT 24
Peak memory 272884 kb
Host smart-60c53537-587d-4959-9ed3-a9d275a88a19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109173318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1109173318
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.677008146
Short name T454
Test name
Test status
Simulation time 850141563 ps
CPU time 11.79 seconds
Started Aug 12 04:34:31 PM PDT 24
Finished Aug 12 04:34:43 PM PDT 24
Peak memory 248996 kb
Host smart-ab936685-998f-4424-991d-7df6f447b630
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=677008146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.677008146
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3963602594
Short name T420
Test name
Test status
Simulation time 7581107430 ps
CPU time 233.77 seconds
Started Aug 12 04:34:31 PM PDT 24
Finished Aug 12 04:38:25 PM PDT 24
Peak memory 256992 kb
Host smart-6826b8b5-98c7-4c68-b698-57804fc77181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39636
02594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3963602594
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.866933415
Short name T128
Test name
Test status
Simulation time 204869684 ps
CPU time 5.43 seconds
Started Aug 12 04:34:24 PM PDT 24
Finished Aug 12 04:34:29 PM PDT 24
Peak memory 253216 kb
Host smart-4b8e13ed-4203-4ff9-a3d2-49c273d57dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86693
3415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.866933415
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2223301219
Short name T686
Test name
Test status
Simulation time 69817064177 ps
CPU time 1921.26 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 05:06:38 PM PDT 24
Peak memory 273652 kb
Host smart-bcced8c0-b89f-40a9-8ae2-f6261b2e8c03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223301219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2223301219
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2385876972
Short name T595
Test name
Test status
Simulation time 25694818313 ps
CPU time 1138.26 seconds
Started Aug 12 04:34:31 PM PDT 24
Finished Aug 12 04:53:30 PM PDT 24
Peak memory 273480 kb
Host smart-f8ed700b-93fa-466a-9c98-1a9e1ba61b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385876972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2385876972
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2510274676
Short name T602
Test name
Test status
Simulation time 7316417823 ps
CPU time 47.61 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:35:24 PM PDT 24
Peak memory 256860 kb
Host smart-79e5340e-ad9b-4405-a34a-d87f7cea21ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25102
74676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2510274676
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1839832389
Short name T622
Test name
Test status
Simulation time 1573171634 ps
CPU time 54.71 seconds
Started Aug 12 04:34:32 PM PDT 24
Finished Aug 12 04:35:27 PM PDT 24
Peak memory 248584 kb
Host smart-a8462e7f-af37-459b-8e0b-57d403093b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18398
32389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1839832389
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1404804060
Short name T264
Test name
Test status
Simulation time 100754832 ps
CPU time 10.72 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:34:47 PM PDT 24
Peak memory 249120 kb
Host smart-91f46330-9dbd-408e-b474-3134de7173bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14048
04060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1404804060
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.648150887
Short name T230
Test name
Test status
Simulation time 86827244 ps
CPU time 5.29 seconds
Started Aug 12 04:34:22 PM PDT 24
Finished Aug 12 04:34:27 PM PDT 24
Peak memory 254180 kb
Host smart-b8f8e662-cf22-4ee8-9ea1-57d7ed97c791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64815
0887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.648150887
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1652477421
Short name T630
Test name
Test status
Simulation time 46331045695 ps
CPU time 2614.62 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 05:18:11 PM PDT 24
Peak memory 289344 kb
Host smart-d81a0a36-5342-40db-9734-885e4385dca4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652477421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1652477421
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2247867795
Short name T687
Test name
Test status
Simulation time 4071225835 ps
CPU time 141.41 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:37:13 PM PDT 24
Peak memory 265752 kb
Host smart-e2e88c46-b915-472a-8b38-959908f4cb47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247867795 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2247867795
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.596957122
Short name T217
Test name
Test status
Simulation time 21110366 ps
CPU time 2.98 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:34:39 PM PDT 24
Peak memory 249168 kb
Host smart-f0d4c962-afe7-4f32-a5bc-5dbda68fe49a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=596957122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.596957122
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1526003764
Short name T456
Test name
Test status
Simulation time 27748334776 ps
CPU time 728.04 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 04:46:53 PM PDT 24
Peak memory 272964 kb
Host smart-97004ae2-e170-482b-b954-76888d3467e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526003764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1526003764
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2581665473
Short name T465
Test name
Test status
Simulation time 271237830 ps
CPU time 14.48 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:34:54 PM PDT 24
Peak memory 248916 kb
Host smart-f5ab35e9-e837-4372-8db2-73e03771f24c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2581665473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2581665473
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.356542755
Short name T400
Test name
Test status
Simulation time 1560655364 ps
CPU time 102.78 seconds
Started Aug 12 04:34:31 PM PDT 24
Finished Aug 12 04:36:14 PM PDT 24
Peak memory 256428 kb
Host smart-33fcce57-34a4-4115-a966-8589c0d720ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35654
2755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.356542755
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3273749912
Short name T634
Test name
Test status
Simulation time 4402001882 ps
CPU time 43.82 seconds
Started Aug 12 04:34:33 PM PDT 24
Finished Aug 12 04:35:17 PM PDT 24
Peak memory 255820 kb
Host smart-12e9466d-c5fb-4f5a-8447-472416e3d2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32737
49912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3273749912
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2527367892
Short name T235
Test name
Test status
Simulation time 70328587117 ps
CPU time 2309.15 seconds
Started Aug 12 04:34:33 PM PDT 24
Finished Aug 12 05:13:03 PM PDT 24
Peak memory 289192 kb
Host smart-e8dba688-afe6-4839-92bf-d55e643c21a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527367892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2527367892
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2170671822
Short name T108
Test name
Test status
Simulation time 183132181132 ps
CPU time 1890.63 seconds
Started Aug 12 04:34:42 PM PDT 24
Finished Aug 12 05:06:13 PM PDT 24
Peak memory 273132 kb
Host smart-2e79e0ae-1e0f-467f-a15c-b370318e8fa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170671822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2170671822
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2638352343
Short name T237
Test name
Test status
Simulation time 4757041045 ps
CPU time 93.51 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:36:10 PM PDT 24
Peak memory 249172 kb
Host smart-20eca485-d58f-4b4d-bb0a-03241a4a1883
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638352343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2638352343
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.669249933
Short name T386
Test name
Test status
Simulation time 1623390995 ps
CPU time 30.54 seconds
Started Aug 12 04:34:31 PM PDT 24
Finished Aug 12 04:35:02 PM PDT 24
Peak memory 249072 kb
Host smart-7dd8cbf6-c478-46f0-8921-43c72ea4aadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66924
9933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.669249933
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.269659345
Short name T683
Test name
Test status
Simulation time 1103463632 ps
CPU time 55.73 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:35:30 PM PDT 24
Peak memory 248376 kb
Host smart-56dfa476-03a8-49a6-99b1-6e4d951e9547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26965
9345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.269659345
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.86547176
Short name T422
Test name
Test status
Simulation time 613114710 ps
CPU time 37.9 seconds
Started Aug 12 04:34:39 PM PDT 24
Finished Aug 12 04:35:17 PM PDT 24
Peak memory 256332 kb
Host smart-6596b163-8693-41a1-b0a1-09072c143fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86547
176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.86547176
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2684487176
Short name T225
Test name
Test status
Simulation time 1121714852 ps
CPU time 25.77 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:35:06 PM PDT 24
Peak memory 256548 kb
Host smart-14cb5c88-549d-4d8f-b309-2b4a9d93207a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684487176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2684487176
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.4128461787
Short name T239
Test name
Test status
Simulation time 6590037036 ps
CPU time 101.36 seconds
Started Aug 12 04:34:44 PM PDT 24
Finished Aug 12 04:36:26 PM PDT 24
Peak memory 265532 kb
Host smart-7808a9d1-4134-49d2-83d1-a9cd93bb1ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128461787 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.4128461787
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3418997286
Short name T506
Test name
Test status
Simulation time 176767537228 ps
CPU time 2248.1 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 05:12:11 PM PDT 24
Peak memory 289028 kb
Host smart-7dd01284-66f1-45a4-adc5-5bebc36dbab0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418997286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3418997286
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2503016015
Short name T425
Test name
Test status
Simulation time 692943675 ps
CPU time 10.59 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:34:47 PM PDT 24
Peak memory 248972 kb
Host smart-ef874026-4c59-4a8a-a425-f044e841652e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2503016015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2503016015
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.525234899
Short name T632
Test name
Test status
Simulation time 1337514713 ps
CPU time 36.5 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:35:27 PM PDT 24
Peak memory 256712 kb
Host smart-0496460d-ceca-4e73-944c-523e34a1eb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52523
4899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.525234899
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2555533198
Short name T299
Test name
Test status
Simulation time 2592733399 ps
CPU time 38.48 seconds
Started Aug 12 04:34:31 PM PDT 24
Finished Aug 12 04:35:10 PM PDT 24
Peak memory 257028 kb
Host smart-e1c9d2ee-c99f-40e2-b68b-938582d1ee92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25555
33198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2555533198
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.597602377
Short name T354
Test name
Test status
Simulation time 24349094690 ps
CPU time 1449.18 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:58:59 PM PDT 24
Peak memory 289148 kb
Host smart-c2d26943-7f65-461e-b0cd-5f608ec5d261
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597602377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.597602377
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2594881275
Short name T236
Test name
Test status
Simulation time 137294017976 ps
CPU time 1744.81 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 05:03:50 PM PDT 24
Peak memory 273420 kb
Host smart-ac6b56df-7f30-4216-befc-c04b05ef18e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594881275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2594881275
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3970823162
Short name T664
Test name
Test status
Simulation time 57204326715 ps
CPU time 572.67 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:44:09 PM PDT 24
Peak memory 249028 kb
Host smart-e14d29bd-71b0-48a0-908b-cb9c3f3934c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970823162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3970823162
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1131145343
Short name T476
Test name
Test status
Simulation time 1645613957 ps
CPU time 51.24 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:35:26 PM PDT 24
Peak memory 257228 kb
Host smart-bd88b964-5b6c-479e-adb6-7eaa91ad39bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11311
45343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1131145343
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3236210586
Short name T631
Test name
Test status
Simulation time 230918468 ps
CPU time 18.62 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 04:35:00 PM PDT 24
Peak memory 256696 kb
Host smart-24a6890a-4084-4e62-b909-58fbe4f9c753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32362
10586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3236210586
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3917482664
Short name T487
Test name
Test status
Simulation time 2227086685 ps
CPU time 45.76 seconds
Started Aug 12 04:34:33 PM PDT 24
Finished Aug 12 04:35:19 PM PDT 24
Peak memory 249672 kb
Host smart-5cef1759-d06e-4d33-a3fb-aaca3fb3d817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39174
82664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3917482664
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.609375029
Short name T494
Test name
Test status
Simulation time 324001168 ps
CPU time 16.59 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:34:51 PM PDT 24
Peak memory 249112 kb
Host smart-8a9e6b21-8e92-4126-a553-82649d5c73d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60937
5029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.609375029
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3761089135
Short name T110
Test name
Test status
Simulation time 42269717913 ps
CPU time 2352.36 seconds
Started Aug 12 04:34:42 PM PDT 24
Finished Aug 12 05:13:54 PM PDT 24
Peak memory 290076 kb
Host smart-a92e91a9-94eb-4da0-992e-32124301f389
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761089135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3761089135
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.330920705
Short name T467
Test name
Test status
Simulation time 188815849 ps
CPU time 10.85 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:34:51 PM PDT 24
Peak memory 248988 kb
Host smart-681af748-751a-4c1f-85b6-9985fcd5a6b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=330920705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.330920705
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2462355061
Short name T291
Test name
Test status
Simulation time 615803530 ps
CPU time 56.98 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:35:37 PM PDT 24
Peak memory 257184 kb
Host smart-d17a1f82-b55f-4953-bec4-eda5b21825bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24623
55061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2462355061
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1851924616
Short name T424
Test name
Test status
Simulation time 8005370078 ps
CPU time 45.32 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 04:35:28 PM PDT 24
Peak memory 248600 kb
Host smart-74c2e72e-1df6-4f82-9698-e83cb84213ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18519
24616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1851924616
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.924610129
Short name T345
Test name
Test status
Simulation time 104308454171 ps
CPU time 1331.99 seconds
Started Aug 12 04:34:44 PM PDT 24
Finished Aug 12 04:56:56 PM PDT 24
Peak memory 289056 kb
Host smart-29b91267-21b3-427b-8f54-ef1d93bc90ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924610129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.924610129
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.199949456
Short name T623
Test name
Test status
Simulation time 44542068802 ps
CPU time 2459.11 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 05:15:35 PM PDT 24
Peak memory 290024 kb
Host smart-4067e611-c889-4aac-b8a4-fdcdc5f69e36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199949456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.199949456
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3652072803
Short name T328
Test name
Test status
Simulation time 12894522690 ps
CPU time 180.42 seconds
Started Aug 12 04:34:32 PM PDT 24
Finished Aug 12 04:37:33 PM PDT 24
Peak memory 255348 kb
Host smart-da3fe8a3-b256-401f-867f-e51ce75cf12e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652072803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3652072803
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3257866923
Short name T464
Test name
Test status
Simulation time 2497835634 ps
CPU time 42.66 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:35:19 PM PDT 24
Peak memory 256548 kb
Host smart-a6b0e334-2677-4277-971a-1c3d236ad572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32578
66923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3257866923
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3233291601
Short name T433
Test name
Test status
Simulation time 3432930264 ps
CPU time 52.6 seconds
Started Aug 12 04:34:32 PM PDT 24
Finished Aug 12 04:35:25 PM PDT 24
Peak memory 256612 kb
Host smart-b804f53e-d5c8-4ae8-b240-c566070f5f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32332
91601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3233291601
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.4027376849
Short name T455
Test name
Test status
Simulation time 2132257222 ps
CPU time 31.69 seconds
Started Aug 12 04:34:33 PM PDT 24
Finished Aug 12 04:35:05 PM PDT 24
Peak memory 256308 kb
Host smart-31ecc1e6-161d-4321-ab35-2ccf3d971604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40273
76849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4027376849
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.664619145
Short name T374
Test name
Test status
Simulation time 18855245744 ps
CPU time 274.95 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:39:15 PM PDT 24
Peak memory 257268 kb
Host smart-eb5a479f-6ad1-4c82-8b44-d4d22b43af46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664619145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.664619145
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.640726960
Short name T222
Test name
Test status
Simulation time 42333209 ps
CPU time 2.17 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:34:36 PM PDT 24
Peak memory 249144 kb
Host smart-f1516ab2-454f-4b9d-a2a9-1ef9827cfe2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=640726960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.640726960
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2154800989
Short name T41
Test name
Test status
Simulation time 23828864097 ps
CPU time 711.2 seconds
Started Aug 12 04:34:44 PM PDT 24
Finished Aug 12 04:46:40 PM PDT 24
Peak memory 273652 kb
Host smart-4aff5662-32a1-4ae8-a4c3-d095854980cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154800989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2154800989
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3406529680
Short name T545
Test name
Test status
Simulation time 1901074233 ps
CPU time 21.32 seconds
Started Aug 12 04:35:01 PM PDT 24
Finished Aug 12 04:35:22 PM PDT 24
Peak memory 248988 kb
Host smart-6528f6fc-9cab-4360-bd33-4c925de72d74
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3406529680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3406529680
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.468420825
Short name T391
Test name
Test status
Simulation time 322659999 ps
CPU time 9.47 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:34:56 PM PDT 24
Peak memory 255252 kb
Host smart-a35585f1-b038-4aba-afd3-c2ac654a652f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46842
0825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.468420825
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1751709712
Short name T86
Test name
Test status
Simulation time 6107177637 ps
CPU time 57.69 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:35:34 PM PDT 24
Peak memory 249000 kb
Host smart-d527203c-f37b-45ea-9c59-83bbe1186506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17517
09712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1751709712
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2960893818
Short name T651
Test name
Test status
Simulation time 57268853811 ps
CPU time 1322.44 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:56:39 PM PDT 24
Peak memory 284228 kb
Host smart-44188ecd-d251-4f7a-95c9-e58d468f67d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960893818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2960893818
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2395852301
Short name T692
Test name
Test status
Simulation time 111954701275 ps
CPU time 1007.59 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:51:24 PM PDT 24
Peak memory 273308 kb
Host smart-838b5fb3-bcdc-46a0-8c3c-c044566e390b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395852301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2395852301
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3390022470
Short name T334
Test name
Test status
Simulation time 52442673980 ps
CPU time 559 seconds
Started Aug 12 04:34:31 PM PDT 24
Finished Aug 12 04:43:50 PM PDT 24
Peak memory 249020 kb
Host smart-318976ae-bdec-406e-8c7d-d30120e2eb21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390022470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3390022470
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.65046901
Short name T287
Test name
Test status
Simulation time 145260121 ps
CPU time 14.85 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:34:52 PM PDT 24
Peak memory 248964 kb
Host smart-018c5eac-53ef-4d8a-9bb4-c34a1a3f10d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65046
901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.65046901
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1224656512
Short name T459
Test name
Test status
Simulation time 293593108 ps
CPU time 33.87 seconds
Started Aug 12 04:34:33 PM PDT 24
Finished Aug 12 04:35:07 PM PDT 24
Peak memory 249008 kb
Host smart-49f91a9a-f63c-4c28-b79e-4aa4b32d926d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12246
56512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1224656512
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4257406353
Short name T87
Test name
Test status
Simulation time 115455341 ps
CPU time 8.85 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:34:55 PM PDT 24
Peak memory 248332 kb
Host smart-66895d11-d7fe-4467-a19e-06ffafa01627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42574
06353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4257406353
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1787865633
Short name T65
Test name
Test status
Simulation time 301381266 ps
CPU time 8.8 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:34:45 PM PDT 24
Peak memory 255480 kb
Host smart-2e8f5dc4-8f1b-42b8-90cb-e76164bf693b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17878
65633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1787865633
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3167801040
Short name T56
Test name
Test status
Simulation time 16086644669 ps
CPU time 1325.48 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 04:56:49 PM PDT 24
Peak memory 289776 kb
Host smart-38e198e5-ae42-49a0-a84e-5d3a1458addf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167801040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3167801040
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2600616126
Short name T26
Test name
Test status
Simulation time 1330715012 ps
CPU time 26.25 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:35:18 PM PDT 24
Peak memory 266572 kb
Host smart-afc31c08-7196-42c3-831c-a6b5b5a108ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600616126 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2600616126
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.4134797736
Short name T215
Test name
Test status
Simulation time 39880265 ps
CPU time 2.09 seconds
Started Aug 12 04:34:28 PM PDT 24
Finished Aug 12 04:34:30 PM PDT 24
Peak memory 249156 kb
Host smart-d04fe1ec-e8cf-42b1-a53d-cea93a5457fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4134797736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.4134797736
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.543530949
Short name T654
Test name
Test status
Simulation time 152794853347 ps
CPU time 2577.55 seconds
Started Aug 12 04:34:53 PM PDT 24
Finished Aug 12 05:17:51 PM PDT 24
Peak memory 289568 kb
Host smart-4cf58f59-d6dc-42bd-b213-576286296064
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543530949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.543530949
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.44286105
Short name T695
Test name
Test status
Simulation time 382044060 ps
CPU time 12.04 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:35:03 PM PDT 24
Peak memory 249012 kb
Host smart-5ebd05a1-0a0f-4b9a-b9ae-02ed1b633d3a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=44286105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.44286105
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2347780650
Short name T671
Test name
Test status
Simulation time 16575198356 ps
CPU time 254.33 seconds
Started Aug 12 04:34:58 PM PDT 24
Finished Aug 12 04:39:13 PM PDT 24
Peak memory 256620 kb
Host smart-d71d64c6-52cc-4613-8196-995784834c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23477
80650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2347780650
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3777212532
Short name T436
Test name
Test status
Simulation time 3280314707 ps
CPU time 48.46 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:35:29 PM PDT 24
Peak memory 257240 kb
Host smart-ee7bc9f0-38af-4abb-9ea3-7a261ecb230b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37772
12532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3777212532
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3209871126
Short name T228
Test name
Test status
Simulation time 182302811077 ps
CPU time 2376.45 seconds
Started Aug 12 04:34:35 PM PDT 24
Finished Aug 12 05:14:12 PM PDT 24
Peak memory 273056 kb
Host smart-daee0dfb-4dd5-4292-86da-202dfd02b29a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209871126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3209871126
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1673531090
Short name T443
Test name
Test status
Simulation time 47469354800 ps
CPU time 2958.49 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 05:23:59 PM PDT 24
Peak memory 289456 kb
Host smart-c7924f17-f040-4460-b398-e926d2d01f27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673531090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1673531090
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.92366724
Short name T642
Test name
Test status
Simulation time 3489693170 ps
CPU time 142.94 seconds
Started Aug 12 04:34:48 PM PDT 24
Finished Aug 12 04:37:11 PM PDT 24
Peak memory 249044 kb
Host smart-d40ff7e4-f013-491e-a881-99f0cc42220a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92366724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.92366724
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2683490248
Short name T544
Test name
Test status
Simulation time 139115379 ps
CPU time 6.37 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:34:58 PM PDT 24
Peak memory 252976 kb
Host smart-edb9bd9b-8c6c-47ec-a05d-da4a2a8353d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26834
90248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2683490248
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2822737853
Short name T610
Test name
Test status
Simulation time 1106556680 ps
CPU time 64.28 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 04:35:42 PM PDT 24
Peak memory 256532 kb
Host smart-f8c1f1d0-c714-405a-991b-d1af347fd808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28227
37853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2822737853
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.4282330173
Short name T511
Test name
Test status
Simulation time 625300045 ps
CPU time 12.37 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:34:49 PM PDT 24
Peak memory 253864 kb
Host smart-b90ea24a-419c-4ab2-b29f-375976fb3972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42823
30173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.4282330173
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2752436944
Short name T393
Test name
Test status
Simulation time 1123452834 ps
CPU time 27.04 seconds
Started Aug 12 04:34:33 PM PDT 24
Finished Aug 12 04:35:01 PM PDT 24
Peak memory 249412 kb
Host smart-1e761cde-bb0c-453c-a172-d006168324cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27524
36944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2752436944
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1366689223
Short name T516
Test name
Test status
Simulation time 1638729563 ps
CPU time 162.51 seconds
Started Aug 12 04:34:39 PM PDT 24
Finished Aug 12 04:37:22 PM PDT 24
Peak memory 257220 kb
Host smart-e9f8412d-813a-4b25-a214-f8ac94d7ea0d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366689223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1366689223
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.87841786
Short name T619
Test name
Test status
Simulation time 585299093 ps
CPU time 63.37 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:35:55 PM PDT 24
Peak memory 265580 kb
Host smart-5a83cb1b-cf1a-460e-a8a1-765514deeadf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87841786 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.87841786
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4220256706
Short name T221
Test name
Test status
Simulation time 203027066 ps
CPU time 4.21 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 04:34:49 PM PDT 24
Peak memory 249112 kb
Host smart-46736810-e19f-410a-b638-74e5997b2e6e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4220256706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4220256706
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3975418157
Short name T563
Test name
Test status
Simulation time 41715896926 ps
CPU time 952.07 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:50:42 PM PDT 24
Peak memory 282452 kb
Host smart-fca4fcd9-d2df-4602-bd4a-6fec7e626cdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975418157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3975418157
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3766532669
Short name T558
Test name
Test status
Simulation time 64343799 ps
CPU time 5.96 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:34:40 PM PDT 24
Peak memory 248996 kb
Host smart-dc43d8b5-371e-4fdd-878e-cfe507b3d973
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3766532669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3766532669
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.573868235
Short name T479
Test name
Test status
Simulation time 3664327108 ps
CPU time 225.63 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:38:32 PM PDT 24
Peak memory 257344 kb
Host smart-3bb0fa6c-ee83-4b92-bda9-a79fb56468b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57386
8235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.573868235
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2777189402
Short name T548
Test name
Test status
Simulation time 3154342198 ps
CPU time 37.08 seconds
Started Aug 12 04:35:34 PM PDT 24
Finished Aug 12 04:36:12 PM PDT 24
Peak memory 247804 kb
Host smart-f095543f-d65e-4478-8da2-c2eabbd2ab1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27771
89402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2777189402
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2690410714
Short name T589
Test name
Test status
Simulation time 15401289964 ps
CPU time 1009.09 seconds
Started Aug 12 04:34:33 PM PDT 24
Finished Aug 12 04:51:22 PM PDT 24
Peak memory 265412 kb
Host smart-f83f359f-600b-4dc7-9c14-55480feef900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690410714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2690410714
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3053615554
Short name T318
Test name
Test status
Simulation time 106646365137 ps
CPU time 547.62 seconds
Started Aug 12 04:34:30 PM PDT 24
Finished Aug 12 04:43:38 PM PDT 24
Peak memory 249068 kb
Host smart-57b5163f-0afb-44b3-a6ef-f1cc74333ecc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053615554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3053615554
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.782244175
Short name T650
Test name
Test status
Simulation time 2305521900 ps
CPU time 45.67 seconds
Started Aug 12 04:34:35 PM PDT 24
Finished Aug 12 04:35:21 PM PDT 24
Peak memory 257248 kb
Host smart-7e57611b-25f7-42a4-8450-2b973f8d4be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78224
4175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.782244175
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1989510976
Short name T411
Test name
Test status
Simulation time 540865269 ps
CPU time 33.99 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:35:20 PM PDT 24
Peak memory 249120 kb
Host smart-4c3240ea-6a44-4469-b987-f136534d80e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
10976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1989510976
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1236969970
Short name T694
Test name
Test status
Simulation time 5623869649 ps
CPU time 34.86 seconds
Started Aug 12 04:34:47 PM PDT 24
Finished Aug 12 04:35:22 PM PDT 24
Peak memory 256328 kb
Host smart-cf8eefb1-65e8-4d32-aa92-a48e2e0c6964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12369
69970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1236969970
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1350403967
Short name T219
Test name
Test status
Simulation time 14924929 ps
CPU time 2.24 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:34:43 PM PDT 24
Peak memory 249240 kb
Host smart-a27cd3b7-9185-4ce5-9706-764cb71435ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1350403967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1350403967
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2820086140
Short name T437
Test name
Test status
Simulation time 242892456948 ps
CPU time 1402.56 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:57:59 PM PDT 24
Peak memory 273108 kb
Host smart-2b33b131-8cfe-4f01-b204-8eeec8f57e32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820086140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2820086140
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4283590453
Short name T675
Test name
Test status
Simulation time 1860124931 ps
CPU time 18.85 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:34:53 PM PDT 24
Peak memory 248900 kb
Host smart-f77c18c9-7bc7-4326-9f60-7f675ae5e8ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4283590453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4283590453
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1715741329
Short name T292
Test name
Test status
Simulation time 1795393740 ps
CPU time 124.28 seconds
Started Aug 12 04:34:35 PM PDT 24
Finished Aug 12 04:36:40 PM PDT 24
Peak memory 257140 kb
Host smart-9bf70ded-0f46-49db-8336-0bb9b03113a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17157
41329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1715741329
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3427872337
Short name T629
Test name
Test status
Simulation time 415620273 ps
CPU time 32.33 seconds
Started Aug 12 04:34:48 PM PDT 24
Finished Aug 12 04:35:20 PM PDT 24
Peak memory 249076 kb
Host smart-555c1fec-ccfe-46e4-aa4d-4e5349979be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34278
72337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3427872337
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2427525481
Short name T309
Test name
Test status
Simulation time 215866324023 ps
CPU time 2216.71 seconds
Started Aug 12 04:34:39 PM PDT 24
Finished Aug 12 05:11:36 PM PDT 24
Peak memory 287268 kb
Host smart-8ce6ce4d-6981-4893-b685-4af1829255fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427525481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2427525481
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.4278482733
Short name T644
Test name
Test status
Simulation time 16942530182 ps
CPU time 1565.2 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 05:00:40 PM PDT 24
Peak memory 289420 kb
Host smart-7ee2a4f0-399a-48fd-ade0-e9267491f95d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278482733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.4278482733
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.609476265
Short name T314
Test name
Test status
Simulation time 119953342485 ps
CPU time 402.6 seconds
Started Aug 12 04:35:44 PM PDT 24
Finished Aug 12 04:42:27 PM PDT 24
Peak memory 256548 kb
Host smart-a0f77c4f-70a9-4e4b-b177-4001c75ad13a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609476265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.609476265
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.4148740525
Short name T371
Test name
Test status
Simulation time 1491307937 ps
CPU time 33.3 seconds
Started Aug 12 04:34:48 PM PDT 24
Finished Aug 12 04:35:21 PM PDT 24
Peak memory 256208 kb
Host smart-ebd04e31-ec55-4e00-8971-40742dc55145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
40525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4148740525
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2348507381
Short name T62
Test name
Test status
Simulation time 308098543 ps
CPU time 18.16 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:35:10 PM PDT 24
Peak memory 255096 kb
Host smart-817dd627-3d8e-4ba2-9d28-a29d2e9f5a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23485
07381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2348507381
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.576856733
Short name T546
Test name
Test status
Simulation time 726901511 ps
CPU time 23.55 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 04:35:00 PM PDT 24
Peak memory 257244 kb
Host smart-00e792db-0410-446c-9e75-b1d9adaaba4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57685
6733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.576856733
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1590426829
Short name T250
Test name
Test status
Simulation time 44720839121 ps
CPU time 1066.45 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:52:20 PM PDT 24
Peak memory 281744 kb
Host smart-660274e0-6931-43db-9e1a-69ba7b37a4cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590426829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1590426829
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.816198398
Short name T191
Test name
Test status
Simulation time 10274332593 ps
CPU time 235.43 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 04:38:37 PM PDT 24
Peak memory 265920 kb
Host smart-d3190c58-1ebd-451a-bb1c-c2d09dd6c8d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816198398 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.816198398
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2157609747
Short name T213
Test name
Test status
Simulation time 610410757 ps
CPU time 3.11 seconds
Started Aug 12 04:34:47 PM PDT 24
Finished Aug 12 04:34:50 PM PDT 24
Peak memory 247724 kb
Host smart-34b4d159-234d-4b93-b5e4-39a25fb199c1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2157609747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2157609747
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1052391425
Short name T367
Test name
Test status
Simulation time 29595317817 ps
CPU time 1145.6 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:53:57 PM PDT 24
Peak memory 289732 kb
Host smart-d58ef69c-d64b-410f-899a-e637d02988b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052391425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1052391425
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1282373018
Short name T560
Test name
Test status
Simulation time 615869999 ps
CPU time 14.85 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 04:34:56 PM PDT 24
Peak memory 249008 kb
Host smart-5e79f7a6-8c96-4ca3-a714-cefe26844b77
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1282373018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1282373018
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2179127142
Short name T92
Test name
Test status
Simulation time 1287721963 ps
CPU time 74.28 seconds
Started Aug 12 04:35:44 PM PDT 24
Finished Aug 12 04:36:59 PM PDT 24
Peak memory 255996 kb
Host smart-122d3b24-21a1-421c-ba39-650b6ad6b8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21791
27142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2179127142
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4005781349
Short name T605
Test name
Test status
Simulation time 3374456294 ps
CPU time 48.82 seconds
Started Aug 12 04:35:44 PM PDT 24
Finished Aug 12 04:36:33 PM PDT 24
Peak memory 248760 kb
Host smart-05678406-b3d7-4cd0-97f0-a034499b7268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40057
81349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4005781349
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1339692238
Short name T468
Test name
Test status
Simulation time 24307253650 ps
CPU time 1228.54 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 04:55:10 PM PDT 24
Peak memory 271076 kb
Host smart-09b5d98a-1f99-4f87-8195-99cad650921c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339692238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1339692238
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2683949139
Short name T689
Test name
Test status
Simulation time 48128232306 ps
CPU time 2742.55 seconds
Started Aug 12 04:34:39 PM PDT 24
Finished Aug 12 05:20:22 PM PDT 24
Peak memory 281844 kb
Host smart-eb23eff6-7989-4c89-832a-9223623e578e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683949139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2683949139
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2538119093
Short name T435
Test name
Test status
Simulation time 12644006059 ps
CPU time 205.08 seconds
Started Aug 12 04:35:44 PM PDT 24
Finished Aug 12 04:39:09 PM PDT 24
Peak memory 247704 kb
Host smart-5c2bf424-8378-49c5-9f6c-afd908db70ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538119093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2538119093
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3369138285
Short name T417
Test name
Test status
Simulation time 1790823966 ps
CPU time 27.25 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:35:03 PM PDT 24
Peak memory 249076 kb
Host smart-8f65637d-8276-4ecd-9c8b-0e27f1cf17df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33691
38285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3369138285
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2329969873
Short name T368
Test name
Test status
Simulation time 2132132002 ps
CPU time 36.74 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:35:29 PM PDT 24
Peak memory 248628 kb
Host smart-223b4b49-9f4a-43c8-ba93-a6602f94510d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23299
69873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2329969873
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.273256566
Short name T278
Test name
Test status
Simulation time 518209702 ps
CPU time 23.48 seconds
Started Aug 12 04:34:35 PM PDT 24
Finished Aug 12 04:34:59 PM PDT 24
Peak memory 256840 kb
Host smart-2df85d54-f1e4-49ec-995e-432d8375cc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27325
6566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.273256566
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.827535974
Short name T649
Test name
Test status
Simulation time 786852945 ps
CPU time 50.56 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:35:27 PM PDT 24
Peak memory 257072 kb
Host smart-417cb911-a1b3-4293-8b2e-b73941144988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82753
5974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.827535974
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3014126178
Short name T6
Test name
Test status
Simulation time 1027382283 ps
CPU time 112.5 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 04:36:30 PM PDT 24
Peak memory 257200 kb
Host smart-c7a4d614-bc5e-4588-bc29-6a4d69cee2ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014126178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3014126178
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2895379423
Short name T88
Test name
Test status
Simulation time 55769563 ps
CPU time 4.11 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:34:56 PM PDT 24
Peak memory 249164 kb
Host smart-13dc6687-7495-4dbb-a392-d50fd0ab56be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2895379423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2895379423
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2044272230
Short name T549
Test name
Test status
Simulation time 33448507469 ps
CPU time 1985.1 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 05:07:55 PM PDT 24
Peak memory 288996 kb
Host smart-e6d42332-c4e1-4ede-8db2-d6b02405cc99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044272230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2044272230
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.903448507
Short name T244
Test name
Test status
Simulation time 1096776024 ps
CPU time 23.76 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:35:16 PM PDT 24
Peak memory 248912 kb
Host smart-f1b646f2-4656-4090-803a-ba9d93b2e98a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=903448507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.903448507
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1965101874
Short name T252
Test name
Test status
Simulation time 17046572372 ps
CPU time 263.66 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:39:13 PM PDT 24
Peak memory 256476 kb
Host smart-77859b7a-b01a-4990-a891-ec24b9025c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19651
01874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1965101874
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2734638130
Short name T517
Test name
Test status
Simulation time 387202597 ps
CPU time 35.78 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:35:27 PM PDT 24
Peak memory 256996 kb
Host smart-15a5a639-438c-4da6-9de6-112a9f86f16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27346
38130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2734638130
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.575007424
Short name T419
Test name
Test status
Simulation time 51633227000 ps
CPU time 1685.73 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 05:02:57 PM PDT 24
Peak memory 273640 kb
Host smart-fe34bc07-27b4-4319-a294-4df49b2ee33e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575007424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.575007424
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.4149863811
Short name T416
Test name
Test status
Simulation time 1363040389 ps
CPU time 32.25 seconds
Started Aug 12 04:34:47 PM PDT 24
Finished Aug 12 04:35:19 PM PDT 24
Peak memory 256448 kb
Host smart-88b06f95-24f4-416f-b707-dca0c3e96489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41498
63811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4149863811
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1611366973
Short name T457
Test name
Test status
Simulation time 887661894 ps
CPU time 29.69 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:35:22 PM PDT 24
Peak memory 249004 kb
Host smart-4d22fa4e-cf8c-462a-be1f-0816e6a88488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16113
66973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1611366973
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.854474424
Short name T498
Test name
Test status
Simulation time 127424500 ps
CPU time 17.43 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:34:52 PM PDT 24
Peak memory 248520 kb
Host smart-ee9679a7-21f8-4d78-9ba7-ebc156c3e048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85447
4424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.854474424
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3478074986
Short name T432
Test name
Test status
Simulation time 12350425444 ps
CPU time 77.84 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:36:07 PM PDT 24
Peak memory 257228 kb
Host smart-f4ae91d0-5dc9-4878-bc81-606e39abeb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34780
74986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3478074986
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.4285445547
Short name T434
Test name
Test status
Simulation time 2143241304 ps
CPU time 51.7 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:35:38 PM PDT 24
Peak memory 257188 kb
Host smart-ecca70c5-a724-455a-8b66-05c4305cea6f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285445547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.4285445547
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1273499040
Short name T598
Test name
Test status
Simulation time 15626517927 ps
CPU time 455.48 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:42:22 PM PDT 24
Peak memory 273676 kb
Host smart-c751efc1-acb1-4410-b11f-282e577e7d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273499040 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1273499040
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2253980087
Short name T18
Test name
Test status
Simulation time 35700532 ps
CPU time 3.47 seconds
Started Aug 12 04:34:05 PM PDT 24
Finished Aug 12 04:34:08 PM PDT 24
Peak memory 249168 kb
Host smart-aa5a8e22-9657-442d-aa0b-14c6e6b2845f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2253980087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2253980087
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.273438634
Short name T450
Test name
Test status
Simulation time 28307469922 ps
CPU time 2000.26 seconds
Started Aug 12 04:33:58 PM PDT 24
Finished Aug 12 05:07:19 PM PDT 24
Peak memory 283700 kb
Host smart-8894f8ee-ef5b-44b9-836f-d831be139287
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273438634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.273438634
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1001634888
Short name T427
Test name
Test status
Simulation time 929288052 ps
CPU time 13.2 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:34:01 PM PDT 24
Peak memory 249080 kb
Host smart-ad31c2d0-e0af-44c4-9fd3-6f6a09e1db4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1001634888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1001634888
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3017640600
Short name T370
Test name
Test status
Simulation time 7797825213 ps
CPU time 167.18 seconds
Started Aug 12 04:34:06 PM PDT 24
Finished Aug 12 04:36:54 PM PDT 24
Peak memory 256632 kb
Host smart-a7dc3f30-9d8f-4711-ae4c-d522a439f94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30176
40600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3017640600
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.38276893
Short name T670
Test name
Test status
Simulation time 476096435 ps
CPU time 12.16 seconds
Started Aug 12 04:33:55 PM PDT 24
Finished Aug 12 04:34:07 PM PDT 24
Peak memory 257244 kb
Host smart-86678eb9-a009-41ad-84ab-95f2b6951abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38276
893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.38276893
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2436009450
Short name T2
Test name
Test status
Simulation time 95927016181 ps
CPU time 1542.18 seconds
Started Aug 12 04:33:51 PM PDT 24
Finished Aug 12 04:59:33 PM PDT 24
Peak memory 273348 kb
Host smart-40f0ddf1-9611-48cb-9944-a9997d318908
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436009450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2436009450
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.54486958
Short name T375
Test name
Test status
Simulation time 79678109506 ps
CPU time 2516.03 seconds
Started Aug 12 04:33:59 PM PDT 24
Finished Aug 12 05:15:56 PM PDT 24
Peak memory 289984 kb
Host smart-ef132476-9182-4c31-8553-7aca921c01fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54486958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.54486958
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.317930987
Short name T532
Test name
Test status
Simulation time 15373115303 ps
CPU time 360.49 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:39:58 PM PDT 24
Peak memory 248900 kb
Host smart-59be62df-d976-406d-80c8-8fda296fd74e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317930987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.317930987
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.83802386
Short name T414
Test name
Test status
Simulation time 2318772416 ps
CPU time 61.97 seconds
Started Aug 12 04:33:56 PM PDT 24
Finished Aug 12 04:34:58 PM PDT 24
Peak memory 256344 kb
Host smart-f0d86d55-3964-4412-a2bb-b425ab02dc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83802
386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.83802386
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.225991755
Short name T685
Test name
Test status
Simulation time 1657319982 ps
CPU time 39.34 seconds
Started Aug 12 04:33:47 PM PDT 24
Finished Aug 12 04:34:26 PM PDT 24
Peak memory 250308 kb
Host smart-25fda9bc-6497-4ab8-8c6a-7b4ae93b8071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22599
1755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.225991755
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.684532723
Short name T7
Test name
Test status
Simulation time 965324248 ps
CPU time 13.78 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:34:31 PM PDT 24
Peak memory 276972 kb
Host smart-5c2970c9-bdab-4abb-895c-d86957e26f89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=684532723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.684532723
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.724295006
Short name T12
Test name
Test status
Simulation time 2713562512 ps
CPU time 47.9 seconds
Started Aug 12 04:33:45 PM PDT 24
Finished Aug 12 04:34:33 PM PDT 24
Peak memory 248732 kb
Host smart-aea85150-3b8b-4283-bb94-383942a43492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72429
5006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.724295006
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1512893910
Short name T645
Test name
Test status
Simulation time 365521386 ps
CPU time 25.54 seconds
Started Aug 12 04:33:51 PM PDT 24
Finished Aug 12 04:34:16 PM PDT 24
Peak memory 256628 kb
Host smart-9813ca75-7107-4c3e-9ee5-24cb7688f209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15128
93910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1512893910
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1621964433
Short name T423
Test name
Test status
Simulation time 55730709303 ps
CPU time 3101.4 seconds
Started Aug 12 04:34:05 PM PDT 24
Finished Aug 12 05:25:47 PM PDT 24
Peak memory 289556 kb
Host smart-db07a8e4-bd18-43da-8aea-26197a202a85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621964433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1621964433
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1209611689
Short name T462
Test name
Test status
Simulation time 11503342626 ps
CPU time 223.05 seconds
Started Aug 12 04:34:03 PM PDT 24
Finished Aug 12 04:37:46 PM PDT 24
Peak memory 265928 kb
Host smart-7984c7a2-ec4c-4987-b44f-db769a687f65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209611689 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1209611689
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.133565265
Short name T488
Test name
Test status
Simulation time 51024568441 ps
CPU time 782.68 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:47:43 PM PDT 24
Peak memory 265468 kb
Host smart-24dc7de3-f41a-4e04-b680-d6a2f5d83870
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133565265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.133565265
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2714689826
Short name T44
Test name
Test status
Simulation time 7552737130 ps
CPU time 143.64 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 04:37:01 PM PDT 24
Peak memory 257284 kb
Host smart-f8732e04-cc5e-4ebe-8158-2677bc44c003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27146
89826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2714689826
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1096399652
Short name T66
Test name
Test status
Simulation time 988303313 ps
CPU time 28.88 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:35:03 PM PDT 24
Peak memory 248640 kb
Host smart-16824ab0-34e8-4346-8082-6b3b11dc8c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10963
99652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1096399652
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3309694621
Short name T350
Test name
Test status
Simulation time 206891634718 ps
CPU time 2744.67 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 05:20:26 PM PDT 24
Peak memory 290056 kb
Host smart-cfe13791-a1d4-4cd6-8677-887d8595e486
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309694621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3309694621
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3008337048
Short name T104
Test name
Test status
Simulation time 6412445087 ps
CPU time 269.33 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:39:16 PM PDT 24
Peak memory 249036 kb
Host smart-3d59f353-4fc8-4649-904c-26b6c714e234
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008337048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3008337048
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.251762525
Short name T672
Test name
Test status
Simulation time 146421314 ps
CPU time 9.62 seconds
Started Aug 12 04:34:54 PM PDT 24
Finished Aug 12 04:35:04 PM PDT 24
Peak memory 255408 kb
Host smart-e0d829ae-3468-4719-ab85-339b36fb69f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25176
2525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.251762525
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2766705820
Short name T70
Test name
Test status
Simulation time 2036480769 ps
CPU time 36.52 seconds
Started Aug 12 04:34:39 PM PDT 24
Finished Aug 12 04:35:15 PM PDT 24
Peak memory 249096 kb
Host smart-dc6fbb5f-8f6f-4283-9a62-837641c571a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27667
05820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2766705820
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3150758783
Short name T115
Test name
Test status
Simulation time 791309726 ps
CPU time 56.93 seconds
Started Aug 12 04:34:42 PM PDT 24
Finished Aug 12 04:35:39 PM PDT 24
Peak memory 256540 kb
Host smart-a3d42614-2b71-4f45-9f05-1fa1eb67cb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507
58783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3150758783
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2595200242
Short name T624
Test name
Test status
Simulation time 1435551592 ps
CPU time 27.61 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 04:35:08 PM PDT 24
Peak memory 255992 kb
Host smart-3fbe7e8d-5f4b-454f-ba42-6fd8581c3cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25952
00242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2595200242
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.321742959
Short name T495
Test name
Test status
Simulation time 4042175142 ps
CPU time 224.05 seconds
Started Aug 12 04:34:47 PM PDT 24
Finished Aug 12 04:38:32 PM PDT 24
Peak memory 273712 kb
Host smart-9fc1a438-4bb8-4a95-b3e3-c5523f033bce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321742959 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.321742959
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1903477808
Short name T116
Test name
Test status
Simulation time 74587509927 ps
CPU time 960.79 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 04:50:46 PM PDT 24
Peak memory 286100 kb
Host smart-30c61592-4534-4164-8529-8db4d0bddc8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903477808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1903477808
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1474401916
Short name T585
Test name
Test status
Simulation time 2947202214 ps
CPU time 191.62 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 04:37:52 PM PDT 24
Peak memory 256592 kb
Host smart-29aa7880-3388-49cf-b567-d0377bf34bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
01916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1474401916
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2535211495
Short name T515
Test name
Test status
Simulation time 187324883 ps
CPU time 20.52 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:35:01 PM PDT 24
Peak memory 257256 kb
Host smart-8c241a7c-9835-4b3d-be52-7af80f8d2a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25352
11495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2535211495
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2750747584
Short name T501
Test name
Test status
Simulation time 30373949284 ps
CPU time 541.11 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:43:52 PM PDT 24
Peak memory 265460 kb
Host smart-0b00a19e-a34b-4409-b576-7626ced089c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750747584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2750747584
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2756436976
Short name T526
Test name
Test status
Simulation time 30804057152 ps
CPU time 289.08 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:39:40 PM PDT 24
Peak memory 256016 kb
Host smart-1c3b7c56-64a1-4331-b5e3-f32ade2fe533
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756436976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2756436976
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.4238656803
Short name T531
Test name
Test status
Simulation time 343883170 ps
CPU time 22.72 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 04:35:00 PM PDT 24
Peak memory 248992 kb
Host smart-7638f0a1-021c-454e-b394-7ac4f8a2111e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42386
56803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4238656803
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1865776597
Short name T552
Test name
Test status
Simulation time 1536889861 ps
CPU time 39.7 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:35:16 PM PDT 24
Peak memory 256248 kb
Host smart-92854b00-70f4-4350-84e7-3ae0a70cc4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
76597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1865776597
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1618718338
Short name T406
Test name
Test status
Simulation time 1623701588 ps
CPU time 54.04 seconds
Started Aug 12 04:34:44 PM PDT 24
Finished Aug 12 04:35:38 PM PDT 24
Peak memory 248352 kb
Host smart-34a8e43f-9d47-4b46-91fa-6d14d647b5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16187
18338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1618718338
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2208761890
Short name T529
Test name
Test status
Simulation time 758027804 ps
CPU time 26.57 seconds
Started Aug 12 04:34:47 PM PDT 24
Finished Aug 12 04:35:14 PM PDT 24
Peak memory 256352 kb
Host smart-044f1f61-9816-468e-a91e-cb3e982686b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22087
61890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2208761890
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2650009242
Short name T541
Test name
Test status
Simulation time 21801859861 ps
CPU time 1095.36 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 04:52:57 PM PDT 24
Peak memory 282900 kb
Host smart-2b183d2d-052b-4086-b685-3fe888382634
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650009242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2650009242
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3617620894
Short name T275
Test name
Test status
Simulation time 233047185116 ps
CPU time 3323.59 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 05:30:15 PM PDT 24
Peak memory 290116 kb
Host smart-ed644449-1084-4947-b0c5-e783c8452fbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617620894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3617620894
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.325367247
Short name T37
Test name
Test status
Simulation time 6646913300 ps
CPU time 191.07 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:38:04 PM PDT 24
Peak memory 257184 kb
Host smart-e579fc15-3f6f-4dd5-a833-b8c276533c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32536
7247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.325367247
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1501819567
Short name T643
Test name
Test status
Simulation time 3435353220 ps
CPU time 55.86 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:35:45 PM PDT 24
Peak memory 249272 kb
Host smart-79161600-0e8f-4d08-81a7-d27e042ae492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15018
19567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1501819567
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3806718683
Short name T93
Test name
Test status
Simulation time 18215620307 ps
CPU time 854.17 seconds
Started Aug 12 04:34:47 PM PDT 24
Finished Aug 12 04:49:01 PM PDT 24
Peak memory 272104 kb
Host smart-0ebec77e-a47f-40b9-967b-a511e2787a7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806718683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3806718683
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.652115178
Short name T478
Test name
Test status
Simulation time 54530301252 ps
CPU time 2419.01 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 05:14:56 PM PDT 24
Peak memory 283436 kb
Host smart-cc539d56-8de8-4c61-beae-b5e8c37be37a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652115178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.652115178
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3490508737
Short name T313
Test name
Test status
Simulation time 12632294315 ps
CPU time 451.04 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:42:23 PM PDT 24
Peak memory 248992 kb
Host smart-15328054-4b7d-4f68-8d85-1e3336c996ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490508737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3490508737
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.331258484
Short name T504
Test name
Test status
Simulation time 47270602 ps
CPU time 6.95 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 04:34:52 PM PDT 24
Peak memory 253124 kb
Host smart-5ff7babc-fcac-4d02-a860-2e8849b2ce06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33125
8484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.331258484
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2063233901
Short name T85
Test name
Test status
Simulation time 464821580 ps
CPU time 39.02 seconds
Started Aug 12 04:34:39 PM PDT 24
Finished Aug 12 04:35:18 PM PDT 24
Peak memory 248632 kb
Host smart-03413bae-bd12-48df-a736-937d96adcb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20632
33901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2063233901
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2005105197
Short name T64
Test name
Test status
Simulation time 1011964044 ps
CPU time 35.3 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:35:28 PM PDT 24
Peak memory 249404 kb
Host smart-85274b6f-bafa-43c6-99f5-dfe874f114a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20051
05197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2005105197
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1145599074
Short name T584
Test name
Test status
Simulation time 1124167579 ps
CPU time 29.94 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 04:35:13 PM PDT 24
Peak memory 257116 kb
Host smart-834f5df7-0928-4929-8abe-0d4d8258a16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11455
99074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1145599074
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.209921857
Short name T58
Test name
Test status
Simulation time 11168129933 ps
CPU time 216.89 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 04:38:20 PM PDT 24
Peak memory 265600 kb
Host smart-6f757b52-57eb-4669-874d-68cc95d01775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209921857 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.209921857
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3906451918
Short name T234
Test name
Test status
Simulation time 734100832498 ps
CPU time 2515.69 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 05:16:51 PM PDT 24
Peak memory 287772 kb
Host smart-c293c129-690e-4152-ae00-a1d09094bc70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906451918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3906451918
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.11301933
Short name T440
Test name
Test status
Simulation time 4924326009 ps
CPU time 137.74 seconds
Started Aug 12 04:34:59 PM PDT 24
Finished Aug 12 04:37:17 PM PDT 24
Peak memory 256840 kb
Host smart-3958ceaf-4670-49f6-b550-0bea023259fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11301
933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.11301933
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.392930869
Short name T673
Test name
Test status
Simulation time 395771483 ps
CPU time 8.87 seconds
Started Aug 12 04:34:42 PM PDT 24
Finished Aug 12 04:34:51 PM PDT 24
Peak memory 254916 kb
Host smart-bdf64ca3-c606-48b9-955e-8d1cf155765f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39293
0869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.392930869
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2033893479
Short name T341
Test name
Test status
Simulation time 142507881525 ps
CPU time 1783.27 seconds
Started Aug 12 04:34:41 PM PDT 24
Finished Aug 12 05:04:24 PM PDT 24
Peak memory 272912 kb
Host smart-cebc1d0e-4bc8-448a-abc9-b4d1afbe37f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033893479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2033893479
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.4204001278
Short name T405
Test name
Test status
Simulation time 14835674251 ps
CPU time 1160.63 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:54:12 PM PDT 24
Peak memory 287068 kb
Host smart-51fc3379-7132-4890-bdb7-1e8013cc33ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204001278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4204001278
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1952993145
Short name T117
Test name
Test status
Simulation time 16117010122 ps
CPU time 315.6 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:39:52 PM PDT 24
Peak memory 247924 kb
Host smart-ebe33737-eaa9-429c-b731-6d313135ef5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952993145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1952993145
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1306269254
Short name T71
Test name
Test status
Simulation time 315407312 ps
CPU time 19.83 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:35:11 PM PDT 24
Peak memory 249048 kb
Host smart-24cfd3c2-5360-44b2-8a60-440447827fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13062
69254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1306269254
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3723406907
Short name T676
Test name
Test status
Simulation time 2313202763 ps
CPU time 39.34 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 04:35:24 PM PDT 24
Peak memory 256540 kb
Host smart-5655fcf8-4027-4572-ade1-d1944d150aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37234
06907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3723406907
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2040270755
Short name T90
Test name
Test status
Simulation time 248896844 ps
CPU time 16.07 seconds
Started Aug 12 04:34:37 PM PDT 24
Finished Aug 12 04:34:53 PM PDT 24
Peak memory 248444 kb
Host smart-36fd63e1-59c1-4c4d-a4a1-a8c58045dbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402
70755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2040270755
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.868652498
Short name T507
Test name
Test status
Simulation time 1429325374 ps
CPU time 27.36 seconds
Started Aug 12 04:34:53 PM PDT 24
Finished Aug 12 04:35:20 PM PDT 24
Peak memory 256092 kb
Host smart-fe32352a-ac11-4ec1-a767-a3599418603b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86865
2498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.868652498
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4204946878
Short name T392
Test name
Test status
Simulation time 18364011636 ps
CPU time 1576.01 seconds
Started Aug 12 04:34:38 PM PDT 24
Finished Aug 12 05:00:54 PM PDT 24
Peak memory 289916 kb
Host smart-6ff69f36-7141-4c8a-893c-6b98a9dfae8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204946878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4204946878
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.847880495
Short name T633
Test name
Test status
Simulation time 8139445746 ps
CPU time 629.41 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:45:19 PM PDT 24
Peak memory 272520 kb
Host smart-c3d698e5-600e-4106-8a40-d03872b961ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847880495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.847880495
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2125636320
Short name T690
Test name
Test status
Simulation time 6210120251 ps
CPU time 58.13 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:35:44 PM PDT 24
Peak memory 256852 kb
Host smart-de0c80cd-a8f4-42e7-93e4-cd7a6c45f0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21256
36320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2125636320
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.4100863373
Short name T626
Test name
Test status
Simulation time 1045051915 ps
CPU time 29.61 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 04:35:22 PM PDT 24
Peak memory 248588 kb
Host smart-28d4ba48-c6b2-4ad8-b0c1-64544b1c2f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41008
63373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.4100863373
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1021389025
Short name T555
Test name
Test status
Simulation time 111295568905 ps
CPU time 1424.66 seconds
Started Aug 12 04:35:44 PM PDT 24
Finished Aug 12 04:59:29 PM PDT 24
Peak memory 273296 kb
Host smart-ed8fb591-1c5c-4783-a4d1-459028a2903c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021389025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1021389025
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1828470154
Short name T496
Test name
Test status
Simulation time 35867093898 ps
CPU time 969.21 seconds
Started Aug 12 04:35:43 PM PDT 24
Finished Aug 12 04:51:52 PM PDT 24
Peak memory 289384 kb
Host smart-dae84a92-182f-4002-b93b-5d9704d2946d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828470154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1828470154
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3462142065
Short name T324
Test name
Test status
Simulation time 30227525744 ps
CPU time 214.59 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 04:38:30 PM PDT 24
Peak memory 249072 kb
Host smart-9eb82d76-a377-4a50-80f5-8db225dad12c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462142065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3462142065
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3878364022
Short name T569
Test name
Test status
Simulation time 78143384 ps
CPU time 6.94 seconds
Started Aug 12 04:34:39 PM PDT 24
Finished Aug 12 04:34:46 PM PDT 24
Peak memory 249008 kb
Host smart-6c4a7c0b-6528-4961-abe7-95b56f61cb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38783
64022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3878364022
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.4199686140
Short name T39
Test name
Test status
Simulation time 151513338 ps
CPU time 13.72 seconds
Started Aug 12 04:34:54 PM PDT 24
Finished Aug 12 04:35:08 PM PDT 24
Peak memory 254988 kb
Host smart-12eff735-73f7-426e-8442-81a6eb1db5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41996
86140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.4199686140
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2414735110
Short name T592
Test name
Test status
Simulation time 726478394 ps
CPU time 47.47 seconds
Started Aug 12 04:34:58 PM PDT 24
Finished Aug 12 04:35:45 PM PDT 24
Peak memory 249184 kb
Host smart-1f042b43-8fac-494b-a368-2241a249e9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24147
35110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2414735110
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1614924909
Short name T24
Test name
Test status
Simulation time 52817691779 ps
CPU time 1121.74 seconds
Started Aug 12 04:36:08 PM PDT 24
Finished Aug 12 04:54:50 PM PDT 24
Peak memory 283872 kb
Host smart-6f3d875a-4cec-4114-9f74-2118cdca4aab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614924909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1614924909
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2869418493
Short name T286
Test name
Test status
Simulation time 1473939680 ps
CPU time 133.98 seconds
Started Aug 12 04:35:44 PM PDT 24
Finished Aug 12 04:37:58 PM PDT 24
Peak memory 256564 kb
Host smart-6d41d959-075b-48aa-b55f-46d35bae7d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28694
18493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2869418493
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3418340272
Short name T666
Test name
Test status
Simulation time 88730973 ps
CPU time 4.28 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:35:59 PM PDT 24
Peak memory 238264 kb
Host smart-5f5faf36-104b-4af1-92c1-4b3a15b7b5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34183
40272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3418340272
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.930592477
Short name T321
Test name
Test status
Simulation time 28817822244 ps
CPU time 280.53 seconds
Started Aug 12 04:34:40 PM PDT 24
Finished Aug 12 04:39:21 PM PDT 24
Peak memory 249136 kb
Host smart-fec9ac0a-8f1f-4032-97cc-139b1bfef043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930592477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.930592477
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.122605089
Short name T604
Test name
Test status
Simulation time 800930561 ps
CPU time 44.84 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:35:36 PM PDT 24
Peak memory 248988 kb
Host smart-3d7d45a0-084f-4bd4-82e0-f88c1dfe53ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12260
5089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.122605089
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.407908465
Short name T121
Test name
Test status
Simulation time 318610212 ps
CPU time 25.72 seconds
Started Aug 12 04:34:42 PM PDT 24
Finished Aug 12 04:35:08 PM PDT 24
Peak memory 256700 kb
Host smart-f336e51a-f453-49b0-a96d-d3afcda9f4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40790
8465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.407908465
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2192575288
Short name T55
Test name
Test status
Simulation time 2753337939 ps
CPU time 39.44 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:35:25 PM PDT 24
Peak memory 248928 kb
Host smart-14ae81cb-a7cf-43f2-a229-b35877ae067a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21925
75288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2192575288
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1404490330
Short name T577
Test name
Test status
Simulation time 1525528540 ps
CPU time 21.21 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:36:16 PM PDT 24
Peak memory 255432 kb
Host smart-c5ff784f-1b40-43d1-86e5-14bc15ed2c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14044
90330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1404490330
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1924239722
Short name T652
Test name
Test status
Simulation time 33336773556 ps
CPU time 661.83 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:45:51 PM PDT 24
Peak memory 273544 kb
Host smart-59fcfc85-5af3-4152-af41-209a42d37994
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924239722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1924239722
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3591330736
Short name T380
Test name
Test status
Simulation time 33219645119 ps
CPU time 1757.08 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 05:04:06 PM PDT 24
Peak memory 273708 kb
Host smart-107c6d29-e432-4158-9a70-2deb96b0fe8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591330736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3591330736
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1413902511
Short name T194
Test name
Test status
Simulation time 4143181230 ps
CPU time 70.31 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 04:35:53 PM PDT 24
Peak memory 249864 kb
Host smart-d5b0ac6c-82df-462e-a8be-d880f5bfdb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14139
02511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1413902511
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3112839388
Short name T458
Test name
Test status
Simulation time 1381719523 ps
CPU time 35.99 seconds
Started Aug 12 04:34:42 PM PDT 24
Finished Aug 12 04:35:18 PM PDT 24
Peak memory 248780 kb
Host smart-63d57a29-eedd-4fdb-99b9-181311e0d82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31128
39388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3112839388
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.374278110
Short name T442
Test name
Test status
Simulation time 71123622808 ps
CPU time 1241.6 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:56:36 PM PDT 24
Peak memory 288972 kb
Host smart-2afeeae4-2ffc-4b69-9a0c-ba4b2d6aef65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374278110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.374278110
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3784283386
Short name T617
Test name
Test status
Simulation time 5851865614 ps
CPU time 231.72 seconds
Started Aug 12 04:34:42 PM PDT 24
Finished Aug 12 04:38:34 PM PDT 24
Peak memory 248848 kb
Host smart-5b6f3e77-011f-4902-90e2-c259e8b62850
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784283386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3784283386
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1036982633
Short name T662
Test name
Test status
Simulation time 560322011 ps
CPU time 11.25 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:36:06 PM PDT 24
Peak memory 247128 kb
Host smart-a1162fc7-7388-4f8b-a021-d682de38690b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10369
82633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1036982633
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1209825419
Short name T611
Test name
Test status
Simulation time 195273184 ps
CPU time 7.33 seconds
Started Aug 12 04:34:47 PM PDT 24
Finished Aug 12 04:34:54 PM PDT 24
Peak memory 253200 kb
Host smart-1b5a8b43-9b41-4737-b132-7bb818c01849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12098
25419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1209825419
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.21861872
Short name T661
Test name
Test status
Simulation time 118831478 ps
CPU time 8.3 seconds
Started Aug 12 04:34:58 PM PDT 24
Finished Aug 12 04:35:06 PM PDT 24
Peak memory 251632 kb
Host smart-1fd1cbbe-1475-4a80-998f-d8164fd76e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21861
872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.21861872
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3528064967
Short name T567
Test name
Test status
Simulation time 354687364 ps
CPU time 36.34 seconds
Started Aug 12 04:34:53 PM PDT 24
Finished Aug 12 04:35:30 PM PDT 24
Peak memory 248940 kb
Host smart-bdd4e259-ce65-4d3e-b0eb-f691bdd1a6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280
64967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3528064967
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.493663008
Short name T266
Test name
Test status
Simulation time 37272201397 ps
CPU time 2121.15 seconds
Started Aug 12 04:36:07 PM PDT 24
Finished Aug 12 05:11:28 PM PDT 24
Peak memory 289296 kb
Host smart-a82d26aa-a3ea-492d-a55b-32836eb7f544
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493663008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.493663008
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1353002162
Short name T61
Test name
Test status
Simulation time 35692992681 ps
CPU time 719.33 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 04:46:44 PM PDT 24
Peak memory 272984 kb
Host smart-0c31aaa9-6663-46c5-9af5-56dea37b87c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353002162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1353002162
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.702184498
Short name T572
Test name
Test status
Simulation time 6312240497 ps
CPU time 102.2 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 04:36:26 PM PDT 24
Peak memory 256552 kb
Host smart-f7a63507-0d1f-4648-95e4-249ceb8a5756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70218
4498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.702184498
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1324513783
Short name T83
Test name
Test status
Simulation time 519656839 ps
CPU time 29.48 seconds
Started Aug 12 04:34:57 PM PDT 24
Finished Aug 12 04:35:26 PM PDT 24
Peak memory 248940 kb
Host smart-b4c41b7c-b4fc-401d-9f2f-06c1782a038f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13245
13783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1324513783
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1307597369
Short name T497
Test name
Test status
Simulation time 7855129330 ps
CPU time 776.49 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:48:51 PM PDT 24
Peak memory 272036 kb
Host smart-c11eef78-7e3a-413d-bf1a-b03273e2b036
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307597369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1307597369
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1771517097
Short name T473
Test name
Test status
Simulation time 31257392443 ps
CPU time 929.16 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:51:24 PM PDT 24
Peak memory 281480 kb
Host smart-61527bc5-ce5b-499f-b10a-e1bf1fcd91d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771517097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1771517097
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3913257003
Short name T599
Test name
Test status
Simulation time 45191746584 ps
CPU time 446.03 seconds
Started Aug 12 04:34:57 PM PDT 24
Finished Aug 12 04:42:24 PM PDT 24
Peak memory 249020 kb
Host smart-745676a8-dc74-4d24-9242-c04b00517095
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913257003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3913257003
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1339300480
Short name T578
Test name
Test status
Simulation time 1684049418 ps
CPU time 28.42 seconds
Started Aug 12 04:34:44 PM PDT 24
Finished Aug 12 04:35:12 PM PDT 24
Peak memory 256432 kb
Host smart-00b89059-77a4-4e15-82b3-bf1827f05503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13393
00480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1339300480
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3277376736
Short name T451
Test name
Test status
Simulation time 2542709607 ps
CPU time 17.32 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:35:09 PM PDT 24
Peak memory 256876 kb
Host smart-e5e90e3f-2f9c-49ed-8674-8c71d3c967c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32773
76736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3277376736
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1170955180
Short name T415
Test name
Test status
Simulation time 28725326 ps
CPU time 4.11 seconds
Started Aug 12 04:34:53 PM PDT 24
Finished Aug 12 04:34:57 PM PDT 24
Peak memory 249036 kb
Host smart-d4e3f6a3-6fcc-4d04-bbf7-077a5b36c536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11709
55180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1170955180
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2514300629
Short name T566
Test name
Test status
Simulation time 2830494428 ps
CPU time 49.57 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:35:40 PM PDT 24
Peak memory 257196 kb
Host smart-87c1fe92-76ae-4509-b67a-90f80a894d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25143
00629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2514300629
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1991649451
Short name T249
Test name
Test status
Simulation time 258666193748 ps
CPU time 3867.12 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 05:39:12 PM PDT 24
Peak memory 298128 kb
Host smart-2e75db6c-18b0-42ea-a45b-9bc6f71a9289
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991649451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1991649451
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.518804957
Short name T78
Test name
Test status
Simulation time 23651705996 ps
CPU time 1042.47 seconds
Started Aug 12 04:35:01 PM PDT 24
Finished Aug 12 04:52:24 PM PDT 24
Peak memory 289992 kb
Host smart-45e510df-f7e4-4f73-99a8-4ded2b02a901
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518804957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.518804957
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1771084314
Short name T682
Test name
Test status
Simulation time 854032151 ps
CPU time 44.47 seconds
Started Aug 12 04:34:44 PM PDT 24
Finished Aug 12 04:35:29 PM PDT 24
Peak memory 249980 kb
Host smart-4ccb404f-fe50-4345-b21f-f658efdace4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17710
84314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1771084314
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3490676919
Short name T410
Test name
Test status
Simulation time 3285788512 ps
CPU time 43.72 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 04:35:29 PM PDT 24
Peak memory 249012 kb
Host smart-1d0487d4-e226-431c-9934-c831a5e0695f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34906
76919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3490676919
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.814505607
Short name T69
Test name
Test status
Simulation time 21272383077 ps
CPU time 1699.55 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 05:03:11 PM PDT 24
Peak memory 289708 kb
Host smart-cae29d91-093c-402f-aaf5-1003d6ac8e89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814505607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.814505607
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2783923488
Short name T691
Test name
Test status
Simulation time 34893554234 ps
CPU time 794.51 seconds
Started Aug 12 04:34:47 PM PDT 24
Finished Aug 12 04:48:02 PM PDT 24
Peak memory 266428 kb
Host smart-43788d4f-2a2a-450c-a3b1-c6df945f4c9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783923488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2783923488
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1475472383
Short name T502
Test name
Test status
Simulation time 1676210619 ps
CPU time 27.6 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 04:35:11 PM PDT 24
Peak memory 256364 kb
Host smart-ad5da628-e1a9-46e7-bcae-1b9eaabbc7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14754
72383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1475472383
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2401935100
Short name T590
Test name
Test status
Simulation time 199913628 ps
CPU time 5.29 seconds
Started Aug 12 04:34:44 PM PDT 24
Finished Aug 12 04:34:50 PM PDT 24
Peak memory 240308 kb
Host smart-ed6cc81c-d191-4624-86db-253b1b8c108e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24019
35100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2401935100
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3312693645
Short name T576
Test name
Test status
Simulation time 4081157312 ps
CPU time 50.69 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:35:37 PM PDT 24
Peak memory 256920 kb
Host smart-e849fcf0-81a1-45dc-b1af-3bfc7cb760bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33126
93645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3312693645
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.865956810
Short name T431
Test name
Test status
Simulation time 1180833783 ps
CPU time 22.04 seconds
Started Aug 12 04:34:55 PM PDT 24
Finished Aug 12 04:35:17 PM PDT 24
Peak memory 249200 kb
Host smart-5fa59fdb-3721-458d-b133-b57d065c6f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86595
6810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.865956810
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3026857946
Short name T32
Test name
Test status
Simulation time 21470155604 ps
CPU time 1799.82 seconds
Started Aug 12 04:34:55 PM PDT 24
Finished Aug 12 05:04:55 PM PDT 24
Peak memory 289416 kb
Host smart-03b10c98-6fad-40bd-a435-89356af974be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026857946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3026857946
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.268305554
Short name T105
Test name
Test status
Simulation time 179648926966 ps
CPU time 2495.81 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 05:16:27 PM PDT 24
Peak memory 289064 kb
Host smart-2346cdc0-468a-4993-98b2-27170f36b4bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268305554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.268305554
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2220599353
Short name T430
Test name
Test status
Simulation time 60023183 ps
CPU time 8.89 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:35:00 PM PDT 24
Peak memory 255168 kb
Host smart-23fc13de-3434-4841-9b6b-20f4e523aefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22205
99353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2220599353
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1275743825
Short name T500
Test name
Test status
Simulation time 1051770745 ps
CPU time 64.06 seconds
Started Aug 12 04:34:59 PM PDT 24
Finished Aug 12 04:36:03 PM PDT 24
Peak memory 248964 kb
Host smart-dc343812-de4d-4a7b-9883-9868216a804c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12757
43825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1275743825
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1407815625
Short name T508
Test name
Test status
Simulation time 69588774120 ps
CPU time 1035.92 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 04:52:01 PM PDT 24
Peak memory 265444 kb
Host smart-4e4ff95a-b478-46f4-a9f3-6b2bd666c06e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407815625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1407815625
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1403532976
Short name T608
Test name
Test status
Simulation time 78224890282 ps
CPU time 416.91 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:41:46 PM PDT 24
Peak memory 247956 kb
Host smart-2a67eb01-d895-47f6-8e4b-29e9bd4cccc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403532976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1403532976
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.269365346
Short name T607
Test name
Test status
Simulation time 1386500743 ps
CPU time 19.2 seconds
Started Aug 12 04:34:44 PM PDT 24
Finished Aug 12 04:35:04 PM PDT 24
Peak memory 248952 kb
Host smart-5eb42498-99c2-4351-9587-ec2f7186a80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26936
5346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.269365346
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3505290219
Short name T600
Test name
Test status
Simulation time 796594171 ps
CPU time 47.11 seconds
Started Aug 12 04:35:11 PM PDT 24
Finished Aug 12 04:35:58 PM PDT 24
Peak memory 256900 kb
Host smart-8091b0ff-e96e-48e8-9ae7-83d89c7e07c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35052
90219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3505290219
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.4085209635
Short name T262
Test name
Test status
Simulation time 2049362658 ps
CPU time 27.75 seconds
Started Aug 12 04:34:45 PM PDT 24
Finished Aug 12 04:35:13 PM PDT 24
Peak memory 256356 kb
Host smart-63e66509-0b1e-4c55-b159-c89a8a20f6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40852
09635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.4085209635
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2655660064
Short name T491
Test name
Test status
Simulation time 732178596 ps
CPU time 49.43 seconds
Started Aug 12 04:34:47 PM PDT 24
Finished Aug 12 04:35:37 PM PDT 24
Peak memory 256284 kb
Host smart-a27437a8-a3c8-402e-95a7-e3282459f692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26556
60064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2655660064
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2678397826
Short name T207
Test name
Test status
Simulation time 98600896 ps
CPU time 3.13 seconds
Started Aug 12 04:33:54 PM PDT 24
Finished Aug 12 04:33:57 PM PDT 24
Peak memory 249192 kb
Host smart-b9b9d5df-048a-4b69-842a-945ef87fbf23
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2678397826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2678397826
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2309095537
Short name T372
Test name
Test status
Simulation time 51905184018 ps
CPU time 1710.83 seconds
Started Aug 12 04:34:00 PM PDT 24
Finished Aug 12 05:02:31 PM PDT 24
Peak memory 289172 kb
Host smart-6eb68b77-dd38-4910-8e6c-467c0da2cbe6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309095537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2309095537
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3098660783
Short name T482
Test name
Test status
Simulation time 519396934 ps
CPU time 25.82 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:34:43 PM PDT 24
Peak memory 249016 kb
Host smart-d00aa6a1-efce-4f40-80e2-1a83a2876cdd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3098660783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3098660783
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1527790829
Short name T114
Test name
Test status
Simulation time 3007413583 ps
CPU time 71.48 seconds
Started Aug 12 04:34:19 PM PDT 24
Finished Aug 12 04:35:30 PM PDT 24
Peak memory 256712 kb
Host smart-17315047-5d98-4699-8ee9-0a5ee91f5914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
90829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1527790829
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1810730713
Short name T543
Test name
Test status
Simulation time 447918780 ps
CPU time 3.34 seconds
Started Aug 12 04:33:49 PM PDT 24
Finished Aug 12 04:33:53 PM PDT 24
Peak memory 240220 kb
Host smart-975a2df2-a150-4545-b1ae-d0403e4098de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
30713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1810730713
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3621085619
Short name T353
Test name
Test status
Simulation time 63622553803 ps
CPU time 1485.36 seconds
Started Aug 12 04:34:04 PM PDT 24
Finished Aug 12 04:58:50 PM PDT 24
Peak memory 289156 kb
Host smart-f86cd125-8084-4417-9e2b-2e696760505e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621085619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3621085619
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1957562168
Short name T484
Test name
Test status
Simulation time 68270119182 ps
CPU time 2154.03 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 05:09:51 PM PDT 24
Peak memory 273576 kb
Host smart-b2639158-8b20-4e6a-bdd3-85f3331462e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957562168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1957562168
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2457278371
Short name T224
Test name
Test status
Simulation time 2158881315 ps
CPU time 96.67 seconds
Started Aug 12 04:34:06 PM PDT 24
Finished Aug 12 04:35:43 PM PDT 24
Peak memory 249116 kb
Host smart-bbe83b4c-d45e-405e-b611-14057bc46454
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457278371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2457278371
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.412867932
Short name T111
Test name
Test status
Simulation time 580323430 ps
CPU time 27.56 seconds
Started Aug 12 04:34:00 PM PDT 24
Finished Aug 12 04:34:27 PM PDT 24
Peak memory 256648 kb
Host smart-5c84b9bd-6041-4ad9-b6b0-f53d316544ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41286
7932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.412867932
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.697273311
Short name T657
Test name
Test status
Simulation time 474633617 ps
CPU time 38.62 seconds
Started Aug 12 04:34:15 PM PDT 24
Finished Aug 12 04:34:53 PM PDT 24
Peak memory 250044 kb
Host smart-34075e6c-1910-4ee2-bfeb-fff52d46e652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69727
3311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.697273311
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2198615806
Short name T276
Test name
Test status
Simulation time 1172981052 ps
CPU time 36.55 seconds
Started Aug 12 04:34:10 PM PDT 24
Finished Aug 12 04:34:46 PM PDT 24
Peak memory 256420 kb
Host smart-bc9f5025-1146-41e4-808a-24eb9fad734a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21986
15806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2198615806
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1309719247
Short name T522
Test name
Test status
Simulation time 143411059 ps
CPU time 10.7 seconds
Started Aug 12 04:34:16 PM PDT 24
Finished Aug 12 04:34:27 PM PDT 24
Peak memory 249036 kb
Host smart-0973ad10-49c0-4276-9471-50b0246374d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13097
19247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1309719247
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2786155766
Short name T126
Test name
Test status
Simulation time 284041670 ps
CPU time 25.16 seconds
Started Aug 12 04:34:07 PM PDT 24
Finished Aug 12 04:34:32 PM PDT 24
Peak memory 257096 kb
Host smart-1a6c178d-c459-4884-b462-94ba0b5cb6d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786155766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2786155766
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.134578123
Short name T251
Test name
Test status
Simulation time 4225797431 ps
CPU time 127.04 seconds
Started Aug 12 04:34:54 PM PDT 24
Finished Aug 12 04:37:01 PM PDT 24
Peak memory 256820 kb
Host smart-a836bea3-0857-4840-80ef-b0e26fe23a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13457
8123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.134578123
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2290256471
Short name T307
Test name
Test status
Simulation time 21120930695 ps
CPU time 1526.32 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 05:00:23 PM PDT 24
Peak memory 289668 kb
Host smart-c968c205-0927-4c06-9048-352978d8d28e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290256471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2290256471
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1485465399
Short name T103
Test name
Test status
Simulation time 158794564451 ps
CPU time 2325.55 seconds
Started Aug 12 04:34:52 PM PDT 24
Finished Aug 12 05:13:38 PM PDT 24
Peak memory 289688 kb
Host smart-20f7d96c-d9ed-4437-ad97-3311d13aeb8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485465399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1485465399
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4218954336
Short name T325
Test name
Test status
Simulation time 19597008967 ps
CPU time 206.32 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:38:15 PM PDT 24
Peak memory 249008 kb
Host smart-97062ff4-a787-4e26-9654-1fce54312447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218954336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4218954336
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.77657454
Short name T514
Test name
Test status
Simulation time 1379966172 ps
CPU time 33.23 seconds
Started Aug 12 04:34:43 PM PDT 24
Finished Aug 12 04:35:17 PM PDT 24
Peak memory 248980 kb
Host smart-0d3f2aba-fac8-4535-8ed7-917525f0cdf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77657
454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.77657454
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.483567797
Short name T17
Test name
Test status
Simulation time 732949381 ps
CPU time 19.37 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:35:05 PM PDT 24
Peak memory 256688 kb
Host smart-c2bd22fc-a301-4f39-a838-1dff11b7be11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48356
7797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.483567797
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3930113802
Short name T123
Test name
Test status
Simulation time 844320878 ps
CPU time 26.38 seconds
Started Aug 12 04:35:07 PM PDT 24
Finished Aug 12 04:35:33 PM PDT 24
Peak memory 257224 kb
Host smart-0b0e91ae-c48e-4b53-a68d-3208da701dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
13802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3930113802
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.4021130424
Short name T387
Test name
Test status
Simulation time 656970241 ps
CPU time 11.54 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:34:57 PM PDT 24
Peak memory 254016 kb
Host smart-694d8f32-ae91-4540-9844-7bd700da432a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40211
30424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.4021130424
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2535650726
Short name T489
Test name
Test status
Simulation time 9500767516 ps
CPU time 152.1 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:37:21 PM PDT 24
Peak memory 266952 kb
Host smart-9daa3eb3-7dff-4c78-a3bc-ef2598b0282a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535650726 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2535650726
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.456305072
Short name T399
Test name
Test status
Simulation time 16538299652 ps
CPU time 714.51 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:46:46 PM PDT 24
Peak memory 273540 kb
Host smart-90079d85-8fb0-4f20-8b0c-a522b0b0931b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456305072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.456305072
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3029536019
Short name T667
Test name
Test status
Simulation time 3973582752 ps
CPU time 109.22 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:36:39 PM PDT 24
Peak memory 256772 kb
Host smart-363c9d97-327f-4a23-ab71-783913d90daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30295
36019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3029536019
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1688782985
Short name T79
Test name
Test status
Simulation time 955027512 ps
CPU time 53.39 seconds
Started Aug 12 04:35:03 PM PDT 24
Finished Aug 12 04:35:57 PM PDT 24
Peak memory 257128 kb
Host smart-9f69b202-4eba-462d-a61b-b85f46dba30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16887
82985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1688782985
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3690816608
Short name T665
Test name
Test status
Simulation time 13866953083 ps
CPU time 1412.99 seconds
Started Aug 12 04:34:54 PM PDT 24
Finished Aug 12 04:58:27 PM PDT 24
Peak memory 290124 kb
Host smart-f9677326-27c9-4c9d-9168-a2f62cfd8d6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690816608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3690816608
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2557769129
Short name T378
Test name
Test status
Simulation time 62679351411 ps
CPU time 1938.25 seconds
Started Aug 12 04:35:08 PM PDT 24
Finished Aug 12 05:07:26 PM PDT 24
Peak memory 281916 kb
Host smart-4c73716c-30cd-482e-a162-dabfd897a69d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557769129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2557769129
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3820095761
Short name T14
Test name
Test status
Simulation time 6284869618 ps
CPU time 113.83 seconds
Started Aug 12 04:34:54 PM PDT 24
Finished Aug 12 04:36:48 PM PDT 24
Peak memory 253832 kb
Host smart-93375a0b-7592-44e2-b567-fad14e90e52b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820095761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3820095761
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1308674103
Short name T481
Test name
Test status
Simulation time 1212487802 ps
CPU time 19.32 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 04:35:16 PM PDT 24
Peak memory 248972 kb
Host smart-b9f61f70-03c8-4b74-8778-0bc852c28d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
74103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1308674103
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1083521326
Short name T647
Test name
Test status
Simulation time 204241358 ps
CPU time 17.55 seconds
Started Aug 12 04:34:46 PM PDT 24
Finished Aug 12 04:35:03 PM PDT 24
Peak memory 248364 kb
Host smart-adb978dc-050e-4924-a633-e3db03e4624e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10835
21326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1083521326
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1299851291
Short name T365
Test name
Test status
Simulation time 3346755904 ps
CPU time 21.93 seconds
Started Aug 12 04:35:14 PM PDT 24
Finished Aug 12 04:35:36 PM PDT 24
Peak memory 249404 kb
Host smart-e8fe4b08-f904-47c9-90f0-d46cf0f69744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12998
51291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1299851291
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.976852379
Short name T269
Test name
Test status
Simulation time 37817750327 ps
CPU time 1142.37 seconds
Started Aug 12 04:34:48 PM PDT 24
Finished Aug 12 04:53:56 PM PDT 24
Peak memory 284244 kb
Host smart-aa0bba84-f165-4f3f-9474-0239d8b1fd40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976852379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.976852379
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1243730535
Short name T185
Test name
Test status
Simulation time 8053936140 ps
CPU time 129.68 seconds
Started Aug 12 04:34:49 PM PDT 24
Finished Aug 12 04:36:59 PM PDT 24
Peak memory 266768 kb
Host smart-a4682de0-bdf2-435a-acce-e9b3867610a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243730535 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1243730535
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3844381465
Short name T385
Test name
Test status
Simulation time 132997333473 ps
CPU time 1719.15 seconds
Started Aug 12 04:34:53 PM PDT 24
Finished Aug 12 05:03:33 PM PDT 24
Peak memory 282868 kb
Host smart-a877c9c6-11d0-445a-9651-c7ca603de04f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844381465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3844381465
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.305574990
Short name T48
Test name
Test status
Simulation time 4226859208 ps
CPU time 55.78 seconds
Started Aug 12 04:35:10 PM PDT 24
Finished Aug 12 04:36:06 PM PDT 24
Peak memory 256468 kb
Host smart-ba8af21f-8d9a-4ef2-afa0-378c1e0303c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30557
4990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.305574990
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1789741788
Short name T127
Test name
Test status
Simulation time 1048526105 ps
CPU time 60.05 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 04:35:50 PM PDT 24
Peak memory 248684 kb
Host smart-840e9393-9dec-41f6-a112-71a38fc08208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17897
41788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1789741788
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2573605442
Short name T351
Test name
Test status
Simulation time 92769162119 ps
CPU time 2459.38 seconds
Started Aug 12 04:34:50 PM PDT 24
Finished Aug 12 05:15:51 PM PDT 24
Peak memory 286476 kb
Host smart-9e525051-4a47-4609-bb46-1e4d41d1609c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573605442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2573605442
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.184564501
Short name T493
Test name
Test status
Simulation time 12044225684 ps
CPU time 478.39 seconds
Started Aug 12 04:35:06 PM PDT 24
Finished Aug 12 04:43:05 PM PDT 24
Peak memory 249104 kb
Host smart-6d436422-b62e-42f1-9d0a-1bf75317453a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184564501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.184564501
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1089908410
Short name T601
Test name
Test status
Simulation time 970371035 ps
CPU time 33.26 seconds
Started Aug 12 04:35:10 PM PDT 24
Finished Aug 12 04:35:43 PM PDT 24
Peak memory 256272 kb
Host smart-c2469d16-a10a-44bc-9afd-dbd35f38698f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10899
08410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1089908410
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1015756511
Short name T270
Test name
Test status
Simulation time 1195182806 ps
CPU time 24.54 seconds
Started Aug 12 04:35:05 PM PDT 24
Finished Aug 12 04:35:30 PM PDT 24
Peak memory 256444 kb
Host smart-e147a515-69a3-47b1-a658-69e1cba8548c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157
56511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1015756511
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1408525592
Short name T407
Test name
Test status
Simulation time 1178830612 ps
CPU time 57.37 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:35:49 PM PDT 24
Peak memory 256180 kb
Host smart-14393489-a4d3-402f-8c93-1b4f5d077706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14085
25592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1408525592
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.659116959
Short name T283
Test name
Test status
Simulation time 4358534920 ps
CPU time 392.56 seconds
Started Aug 12 04:35:02 PM PDT 24
Finished Aug 12 04:41:35 PM PDT 24
Peak memory 270968 kb
Host smart-044098e8-9be2-48b2-a389-3cdb8ecaaaad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659116959 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.659116959
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.865677063
Short name T124
Test name
Test status
Simulation time 48508787764 ps
CPU time 1487.23 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 04:59:44 PM PDT 24
Peak memory 268452 kb
Host smart-414735c5-41b8-48cd-a9d4-d13aa1f70915
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865677063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.865677063
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3572930283
Short name T364
Test name
Test status
Simulation time 20555103016 ps
CPU time 291.41 seconds
Started Aug 12 04:34:54 PM PDT 24
Finished Aug 12 04:39:46 PM PDT 24
Peak memory 257196 kb
Host smart-964a0e06-c141-4937-8b06-a4505651cb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35729
30283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3572930283
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2882600845
Short name T581
Test name
Test status
Simulation time 893845236 ps
CPU time 17.22 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 04:35:14 PM PDT 24
Peak memory 256736 kb
Host smart-b2db4aac-d5e4-4569-b926-4737f38e8708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28826
00845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2882600845
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1423477331
Short name T102
Test name
Test status
Simulation time 11910328193 ps
CPU time 750.44 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 04:47:27 PM PDT 24
Peak memory 273344 kb
Host smart-50ecb026-42dc-47d4-a852-6abc987e20d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423477331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1423477331
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.866999325
Short name T475
Test name
Test status
Simulation time 36032547391 ps
CPU time 885.21 seconds
Started Aug 12 04:35:13 PM PDT 24
Finished Aug 12 04:49:58 PM PDT 24
Peak memory 272896 kb
Host smart-e4c332da-8f98-47a5-bac7-879b4724fff4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866999325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.866999325
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3049607303
Short name T398
Test name
Test status
Simulation time 1906227829 ps
CPU time 30.86 seconds
Started Aug 12 04:35:09 PM PDT 24
Finished Aug 12 04:35:40 PM PDT 24
Peak memory 256300 kb
Host smart-07a2b03d-3eaf-4416-b3da-66c79f342c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30496
07303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3049607303
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3059573859
Short name T273
Test name
Test status
Simulation time 795889687 ps
CPU time 13.8 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:35:06 PM PDT 24
Peak memory 249048 kb
Host smart-c73d6b5f-97bf-4ded-86b2-bcf32ed8148a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30595
73859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3059573859
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2912847158
Short name T94
Test name
Test status
Simulation time 80782627 ps
CPU time 9.2 seconds
Started Aug 12 04:35:16 PM PDT 24
Finished Aug 12 04:35:26 PM PDT 24
Peak memory 249100 kb
Host smart-37af544b-15af-491f-9168-413c89bc19fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29128
47158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2912847158
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1145376146
Short name T519
Test name
Test status
Simulation time 35782299362 ps
CPU time 979.87 seconds
Started Aug 12 04:34:55 PM PDT 24
Finished Aug 12 04:51:15 PM PDT 24
Peak memory 272816 kb
Host smart-d056acc3-edeb-414b-ab9f-07413859abe8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145376146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1145376146
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.4136832056
Short name T678
Test name
Test status
Simulation time 2348771177 ps
CPU time 142.53 seconds
Started Aug 12 04:35:14 PM PDT 24
Finished Aug 12 04:37:37 PM PDT 24
Peak memory 256744 kb
Host smart-8b021563-4c44-4279-98ac-183cb0814aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41368
32056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.4136832056
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.449374334
Short name T401
Test name
Test status
Simulation time 544094745 ps
CPU time 24.74 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:35:16 PM PDT 24
Peak memory 257220 kb
Host smart-72530f91-90b1-4c50-8fb9-80033b835e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44937
4334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.449374334
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.455158458
Short name T684
Test name
Test status
Simulation time 93980426325 ps
CPU time 1402.03 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:58:14 PM PDT 24
Peak memory 273664 kb
Host smart-e183dbd3-63c0-4271-b6c2-8bfd9d8501b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455158458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.455158458
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1916736157
Short name T16
Test name
Test status
Simulation time 85504178138 ps
CPU time 1539.5 seconds
Started Aug 12 04:35:05 PM PDT 24
Finished Aug 12 05:00:45 PM PDT 24
Peak memory 273068 kb
Host smart-504daf75-8638-4ddd-af99-73ef6515656e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916736157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1916736157
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3223265497
Short name T606
Test name
Test status
Simulation time 30787357635 ps
CPU time 293.08 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 04:39:49 PM PDT 24
Peak memory 249060 kb
Host smart-e2cd4d61-675d-4676-8336-b7f16c0783a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223265497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3223265497
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.450841219
Short name T471
Test name
Test status
Simulation time 778756791 ps
CPU time 24.97 seconds
Started Aug 12 04:34:59 PM PDT 24
Finished Aug 12 04:35:24 PM PDT 24
Peak memory 255848 kb
Host smart-5218969d-9932-488c-ae63-4f7d0c3a665b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45084
1219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.450841219
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.252022406
Short name T615
Test name
Test status
Simulation time 255921384 ps
CPU time 14.08 seconds
Started Aug 12 04:35:00 PM PDT 24
Finished Aug 12 04:35:14 PM PDT 24
Peak memory 255540 kb
Host smart-e3349ca1-cb51-4fa9-b864-e1e07bda1f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25202
2406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.252022406
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.374755391
Short name T77
Test name
Test status
Simulation time 955204788 ps
CPU time 24.26 seconds
Started Aug 12 04:34:56 PM PDT 24
Finished Aug 12 04:35:20 PM PDT 24
Peak memory 248500 kb
Host smart-3d08b993-52e1-4c10-8601-fbd9bb955816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37475
5391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.374755391
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2315913426
Short name T693
Test name
Test status
Simulation time 119829950 ps
CPU time 8.29 seconds
Started Aug 12 04:35:11 PM PDT 24
Finished Aug 12 04:35:20 PM PDT 24
Peak memory 249008 kb
Host smart-7fee9d3d-16f8-4c52-94d4-3a43e54f38e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23159
13426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2315913426
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4223672370
Short name T53
Test name
Test status
Simulation time 3009758232 ps
CPU time 280.5 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:39:32 PM PDT 24
Peak memory 267608 kb
Host smart-70d28341-2d15-4b18-85f5-b91f7bf8dade
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223672370 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4223672370
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.852836776
Short name T536
Test name
Test status
Simulation time 35794880498 ps
CPU time 2350.46 seconds
Started Aug 12 04:34:58 PM PDT 24
Finished Aug 12 05:14:09 PM PDT 24
Peak memory 289972 kb
Host smart-ba738d9a-159e-4ee2-a595-4463f51d025b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852836776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.852836776
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.423508168
Short name T444
Test name
Test status
Simulation time 3405952638 ps
CPU time 26.5 seconds
Started Aug 12 04:35:00 PM PDT 24
Finished Aug 12 04:35:26 PM PDT 24
Peak memory 256848 kb
Host smart-b6d9df9e-4758-4517-be4d-5ae2f96a0c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42350
8168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.423508168
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3097798798
Short name T395
Test name
Test status
Simulation time 222567099 ps
CPU time 20.94 seconds
Started Aug 12 04:35:17 PM PDT 24
Finished Aug 12 04:35:38 PM PDT 24
Peak memory 256696 kb
Host smart-652c59ed-c237-4dcc-9824-a1f9e0179882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30977
98798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3097798798
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1403482005
Short name T571
Test name
Test status
Simulation time 26124659152 ps
CPU time 1465.96 seconds
Started Aug 12 04:35:04 PM PDT 24
Finished Aug 12 04:59:31 PM PDT 24
Peak memory 265396 kb
Host smart-78467bd4-4b34-4a91-86ff-6a18be0acd56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403482005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1403482005
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3616191508
Short name T499
Test name
Test status
Simulation time 85757886936 ps
CPU time 1212.94 seconds
Started Aug 12 04:35:06 PM PDT 24
Finished Aug 12 04:55:19 PM PDT 24
Peak memory 265448 kb
Host smart-80813da1-5836-42ce-8e12-7c214197752c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616191508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3616191508
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.153587113
Short name T538
Test name
Test status
Simulation time 28774111384 ps
CPU time 308.02 seconds
Started Aug 12 04:35:00 PM PDT 24
Finished Aug 12 04:40:08 PM PDT 24
Peak memory 249016 kb
Host smart-45c4f198-5bd3-49ac-8286-919b4f8783bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153587113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.153587113
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3721949446
Short name T472
Test name
Test status
Simulation time 319484381 ps
CPU time 20.3 seconds
Started Aug 12 04:34:55 PM PDT 24
Finished Aug 12 04:35:16 PM PDT 24
Peak memory 256468 kb
Host smart-a9ccb292-84a0-46d4-baed-57a06dee94cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37219
49446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3721949446
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1602607054
Short name T681
Test name
Test status
Simulation time 1030190167 ps
CPU time 63.23 seconds
Started Aug 12 04:34:51 PM PDT 24
Finished Aug 12 04:35:55 PM PDT 24
Peak memory 248580 kb
Host smart-fc4c4623-97a9-486c-bd2a-1b108e79fe3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16026
07054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1602607054
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.62828526
Short name T43
Test name
Test status
Simulation time 1342299334 ps
CPU time 47.66 seconds
Started Aug 12 04:35:06 PM PDT 24
Finished Aug 12 04:35:53 PM PDT 24
Peak memory 257224 kb
Host smart-9f28c66a-2cf1-432a-9caa-771d9323c8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62828
526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.62828526
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.742345187
Short name T583
Test name
Test status
Simulation time 10695021140 ps
CPU time 514.89 seconds
Started Aug 12 04:35:07 PM PDT 24
Finished Aug 12 04:43:42 PM PDT 24
Peak memory 257228 kb
Host smart-56bf20b7-ab9a-48d5-98db-847e0a673ce1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742345187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.742345187
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1993988022
Short name T238
Test name
Test status
Simulation time 1375018037 ps
CPU time 50.64 seconds
Started Aug 12 04:35:00 PM PDT 24
Finished Aug 12 04:35:51 PM PDT 24
Peak memory 266532 kb
Host smart-fc92273c-fd97-4ee3-840d-928bbea27b04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993988022 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1993988022
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3228922941
Short name T75
Test name
Test status
Simulation time 340122191826 ps
CPU time 1769.47 seconds
Started Aug 12 04:35:09 PM PDT 24
Finished Aug 12 05:04:39 PM PDT 24
Peak memory 272996 kb
Host smart-0019ae87-4342-40bb-bb36-57bca6f30168
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228922941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3228922941
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3020350100
Short name T616
Test name
Test status
Simulation time 4143422390 ps
CPU time 109.72 seconds
Started Aug 12 04:34:59 PM PDT 24
Finished Aug 12 04:36:48 PM PDT 24
Peak memory 257564 kb
Host smart-595d867c-07ba-4b87-9fff-8a120a857921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30203
50100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3020350100
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.966385867
Short name T112
Test name
Test status
Simulation time 349328438 ps
CPU time 7.96 seconds
Started Aug 12 04:35:04 PM PDT 24
Finished Aug 12 04:35:12 PM PDT 24
Peak memory 253288 kb
Host smart-bed3aaf8-d487-4b0d-8c0c-284f58137cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96638
5867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.966385867
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1204763184
Short name T697
Test name
Test status
Simulation time 14632376229 ps
CPU time 609.2 seconds
Started Aug 12 04:35:03 PM PDT 24
Finished Aug 12 04:45:13 PM PDT 24
Peak memory 249064 kb
Host smart-cc4b9cda-e1b4-476b-aebf-25ecd946451d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204763184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1204763184
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3716807708
Short name T54
Test name
Test status
Simulation time 926794394 ps
CPU time 27.19 seconds
Started Aug 12 04:35:08 PM PDT 24
Finished Aug 12 04:35:36 PM PDT 24
Peak memory 255976 kb
Host smart-cb407ba1-2612-4962-806b-8283aa64c110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37168
07708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3716807708
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3161654932
Short name T449
Test name
Test status
Simulation time 1858520755 ps
CPU time 33.14 seconds
Started Aug 12 04:35:19 PM PDT 24
Finished Aug 12 04:35:53 PM PDT 24
Peak memory 248528 kb
Host smart-c31c4b25-a6d3-4694-a852-3a99065f3e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31616
54932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3161654932
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2775442673
Short name T271
Test name
Test status
Simulation time 270970981 ps
CPU time 47.75 seconds
Started Aug 12 04:35:01 PM PDT 24
Finished Aug 12 04:35:49 PM PDT 24
Peak memory 249040 kb
Host smart-94173db9-6d0d-4d4d-8571-39d5dea2a3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27754
42673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2775442673
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3149775934
Short name T470
Test name
Test status
Simulation time 946344171 ps
CPU time 25.26 seconds
Started Aug 12 04:35:07 PM PDT 24
Finished Aug 12 04:35:32 PM PDT 24
Peak memory 256720 kb
Host smart-4b97876e-873f-4c8a-8ee5-d98e568600ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31497
75934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3149775934
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2392705092
Short name T246
Test name
Test status
Simulation time 34213794177 ps
CPU time 1933.51 seconds
Started Aug 12 04:35:03 PM PDT 24
Finished Aug 12 05:07:17 PM PDT 24
Peak memory 289748 kb
Host smart-ecf7ea25-16fb-4a05-a232-c43b7bbf7865
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392705092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2392705092
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1300608590
Short name T527
Test name
Test status
Simulation time 11463580911 ps
CPU time 1292.9 seconds
Started Aug 12 04:35:07 PM PDT 24
Finished Aug 12 04:56:40 PM PDT 24
Peak memory 287532 kb
Host smart-3e6e1bf4-43c3-44b5-b2cf-2b898652d63c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300608590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1300608590
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1338942799
Short name T426
Test name
Test status
Simulation time 7598425939 ps
CPU time 189.78 seconds
Started Aug 12 04:35:11 PM PDT 24
Finished Aug 12 04:38:20 PM PDT 24
Peak memory 257348 kb
Host smart-b8d6011e-2350-4998-9b64-bbd33bb4fada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13389
42799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1338942799
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.130428852
Short name T477
Test name
Test status
Simulation time 732941153 ps
CPU time 47.41 seconds
Started Aug 12 04:35:13 PM PDT 24
Finished Aug 12 04:36:00 PM PDT 24
Peak memory 248988 kb
Host smart-7270ce56-b437-4dd4-aa51-a293370adeff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13042
8852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.130428852
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2544698898
Short name T340
Test name
Test status
Simulation time 101310787355 ps
CPU time 1303.81 seconds
Started Aug 12 04:35:21 PM PDT 24
Finished Aug 12 04:57:05 PM PDT 24
Peak memory 289872 kb
Host smart-63dad6ac-5c3c-4c6f-b733-f15a12d592da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544698898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2544698898
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.899242679
Short name T421
Test name
Test status
Simulation time 23044537456 ps
CPU time 1175.22 seconds
Started Aug 12 04:35:23 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 289188 kb
Host smart-bf3e0b67-5108-4fc9-aa44-350ea1a0479e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899242679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.899242679
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.99490587
Short name T376
Test name
Test status
Simulation time 479367068 ps
CPU time 11.88 seconds
Started Aug 12 04:35:06 PM PDT 24
Finished Aug 12 04:35:18 PM PDT 24
Peak memory 249052 kb
Host smart-0a6faf36-c04e-4f0e-b624-4ddaa05bf74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99490
587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.99490587
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2002747263
Short name T306
Test name
Test status
Simulation time 355284574 ps
CPU time 23.69 seconds
Started Aug 12 04:35:16 PM PDT 24
Finished Aug 12 04:35:40 PM PDT 24
Peak memory 256396 kb
Host smart-f064434d-9d9e-4909-bf9e-5b5a4c568416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20027
47263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2002747263
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1351195097
Short name T556
Test name
Test status
Simulation time 2308666911 ps
CPU time 47.31 seconds
Started Aug 12 04:35:12 PM PDT 24
Finished Aug 12 04:35:59 PM PDT 24
Peak memory 249096 kb
Host smart-d8528744-16e0-42ab-9364-ea583c549c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13511
95097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1351195097
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2748425418
Short name T403
Test name
Test status
Simulation time 2256726172 ps
CPU time 36.26 seconds
Started Aug 12 04:35:07 PM PDT 24
Finished Aug 12 04:35:44 PM PDT 24
Peak memory 256228 kb
Host smart-5d4f601d-bf64-4b1e-ad9f-e1b0eb94f6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27484
25418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2748425418
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1853728859
Short name T302
Test name
Test status
Simulation time 67510034889 ps
CPU time 2142.95 seconds
Started Aug 12 04:35:13 PM PDT 24
Finished Aug 12 05:10:56 PM PDT 24
Peak memory 288236 kb
Host smart-cb63811e-4d43-41f3-b26e-0e8dba518861
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853728859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1853728859
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3956788711
Short name T119
Test name
Test status
Simulation time 7650082341 ps
CPU time 365.84 seconds
Started Aug 12 04:35:06 PM PDT 24
Finished Aug 12 04:41:12 PM PDT 24
Peak memory 273812 kb
Host smart-10f2243c-2c18-4075-8557-5460b2738044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956788711 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3956788711
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1087449605
Short name T588
Test name
Test status
Simulation time 54160376638 ps
CPU time 1899.17 seconds
Started Aug 12 04:35:11 PM PDT 24
Finished Aug 12 05:06:51 PM PDT 24
Peak memory 273592 kb
Host smart-4e226bdc-2aca-4a75-880c-2b9a95dc7efd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087449605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1087449605
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3266597534
Short name T659
Test name
Test status
Simulation time 3856281611 ps
CPU time 161.93 seconds
Started Aug 12 04:35:11 PM PDT 24
Finished Aug 12 04:37:53 PM PDT 24
Peak memory 256844 kb
Host smart-842ad481-3cd9-47d7-adfb-950d614c8258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32665
97534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3266597534
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2266418428
Short name T573
Test name
Test status
Simulation time 343358277 ps
CPU time 30.07 seconds
Started Aug 12 04:35:22 PM PDT 24
Finished Aug 12 04:35:52 PM PDT 24
Peak memory 248948 kb
Host smart-8909aac5-aa26-48fe-a1e7-0f6a4a3bc81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22664
18428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2266418428
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3942248338
Short name T347
Test name
Test status
Simulation time 74913683720 ps
CPU time 1463.91 seconds
Started Aug 12 04:35:20 PM PDT 24
Finished Aug 12 04:59:44 PM PDT 24
Peak memory 289852 kb
Host smart-3604d740-51df-4698-b2aa-d9235c94152c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942248338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3942248338
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.940109789
Short name T539
Test name
Test status
Simulation time 66373681623 ps
CPU time 2111.02 seconds
Started Aug 12 04:35:06 PM PDT 24
Finished Aug 12 05:10:18 PM PDT 24
Peak memory 287540 kb
Host smart-27453fd5-8e63-4bfc-a61a-e1688d8d4825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940109789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.940109789
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3427145545
Short name T428
Test name
Test status
Simulation time 1063558856 ps
CPU time 37.32 seconds
Started Aug 12 04:35:23 PM PDT 24
Finished Aug 12 04:36:00 PM PDT 24
Peak memory 256552 kb
Host smart-84462776-f3df-4448-93a1-53512d3f0494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34271
45545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3427145545
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.257506570
Short name T76
Test name
Test status
Simulation time 3330937945 ps
CPU time 54.9 seconds
Started Aug 12 04:35:18 PM PDT 24
Finished Aug 12 04:36:13 PM PDT 24
Peak memory 249072 kb
Host smart-c6ec23f6-9f2e-47d7-a44a-7317428af037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25750
6570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.257506570
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2080779139
Short name T261
Test name
Test status
Simulation time 242621518 ps
CPU time 31.34 seconds
Started Aug 12 04:35:23 PM PDT 24
Finished Aug 12 04:35:54 PM PDT 24
Peak memory 256356 kb
Host smart-28ef84d4-a4ca-47eb-a446-f539ced048ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20807
79139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2080779139
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3082640386
Short name T628
Test name
Test status
Simulation time 231352527 ps
CPU time 19.25 seconds
Started Aug 12 04:35:23 PM PDT 24
Finished Aug 12 04:35:42 PM PDT 24
Peak memory 249000 kb
Host smart-c1771dcb-ec0d-4d9c-897b-4eef97b6ccf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30826
40386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3082640386
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.375785726
Short name T122
Test name
Test status
Simulation time 9104149783 ps
CPU time 163.7 seconds
Started Aug 12 04:35:19 PM PDT 24
Finished Aug 12 04:38:03 PM PDT 24
Peak memory 257264 kb
Host smart-b7aa88f5-0aee-4403-8dd2-9a200f50a0b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375785726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.375785726
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.18945380
Short name T453
Test name
Test status
Simulation time 2468673239 ps
CPU time 276.07 seconds
Started Aug 12 04:35:17 PM PDT 24
Finished Aug 12 04:39:53 PM PDT 24
Peak memory 267488 kb
Host smart-76d61df4-ad77-40c6-879b-5455a7bfc57e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18945380 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.18945380
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3150189829
Short name T74
Test name
Test status
Simulation time 41344971010 ps
CPU time 2622.02 seconds
Started Aug 12 04:35:21 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 289728 kb
Host smart-80b04773-3f1a-4df2-a1e3-815870f58e1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150189829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3150189829
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3651476733
Short name T67
Test name
Test status
Simulation time 13841979328 ps
CPU time 213.17 seconds
Started Aug 12 04:35:23 PM PDT 24
Finished Aug 12 04:38:56 PM PDT 24
Peak memory 257184 kb
Host smart-15cc9f8e-7d6a-4414-8bcd-d80751014ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36514
76733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3651476733
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1641646425
Short name T369
Test name
Test status
Simulation time 687518723 ps
CPU time 11.05 seconds
Started Aug 12 04:35:22 PM PDT 24
Finished Aug 12 04:35:33 PM PDT 24
Peak memory 248608 kb
Host smart-3f040161-de18-4b26-9130-44a3a67114db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16416
46425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1641646425
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4214389954
Short name T348
Test name
Test status
Simulation time 78889860601 ps
CPU time 2341.54 seconds
Started Aug 12 04:35:24 PM PDT 24
Finished Aug 12 05:14:25 PM PDT 24
Peak memory 273572 kb
Host smart-6120df19-4e63-4b48-9345-ea53ff96afd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214389954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4214389954
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3259747192
Short name T91
Test name
Test status
Simulation time 69556982494 ps
CPU time 2086.11 seconds
Started Aug 12 04:35:22 PM PDT 24
Finished Aug 12 05:10:08 PM PDT 24
Peak memory 284596 kb
Host smart-c30860e9-4fa4-43e5-98ec-a967e3b9d2ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259747192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3259747192
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1607252539
Short name T312
Test name
Test status
Simulation time 120252945205 ps
CPU time 304.42 seconds
Started Aug 12 04:35:16 PM PDT 24
Finished Aug 12 04:40:20 PM PDT 24
Peak memory 249056 kb
Host smart-e48cd7f8-8b08-4d15-8e8c-6e9bb8fe3c9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607252539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1607252539
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2245534776
Short name T409
Test name
Test status
Simulation time 474147810 ps
CPU time 26.24 seconds
Started Aug 12 04:35:17 PM PDT 24
Finished Aug 12 04:35:43 PM PDT 24
Peak memory 257196 kb
Host smart-ff340cd8-72f6-4211-8f8f-84dbdfcc36cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22455
34776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2245534776
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1733246150
Short name T15
Test name
Test status
Simulation time 193394228 ps
CPU time 28.14 seconds
Started Aug 12 04:35:14 PM PDT 24
Finished Aug 12 04:35:42 PM PDT 24
Peak memory 256864 kb
Host smart-e66f4e6a-1135-4b72-aa73-72a519f5d95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17332
46150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1733246150
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1362730601
Short name T46
Test name
Test status
Simulation time 1969711415 ps
CPU time 18.99 seconds
Started Aug 12 04:35:16 PM PDT 24
Finished Aug 12 04:35:36 PM PDT 24
Peak memory 255828 kb
Host smart-f249130f-e808-4569-8b0b-1079c4fa7453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13627
30601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1362730601
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.611059691
Short name T594
Test name
Test status
Simulation time 1368927480 ps
CPU time 21.26 seconds
Started Aug 12 04:35:11 PM PDT 24
Finished Aug 12 04:35:32 PM PDT 24
Peak memory 256068 kb
Host smart-7577500d-e603-4bf4-a00c-e77838e08533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61105
9691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.611059691
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1487979760
Short name T535
Test name
Test status
Simulation time 3897267407 ps
CPU time 87.87 seconds
Started Aug 12 04:35:21 PM PDT 24
Finished Aug 12 04:36:49 PM PDT 24
Peak memory 257244 kb
Host smart-0fdfa854-3c76-48b5-b606-263fdd357cb8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487979760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1487979760
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2247746906
Short name T210
Test name
Test status
Simulation time 27443381 ps
CPU time 2.44 seconds
Started Aug 12 04:34:14 PM PDT 24
Finished Aug 12 04:34:17 PM PDT 24
Peak memory 249228 kb
Host smart-06bfc09c-b0c1-4f12-9742-1fb54c524516
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2247746906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2247746906
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3220046383
Short name T72
Test name
Test status
Simulation time 24412207539 ps
CPU time 1031.9 seconds
Started Aug 12 04:34:04 PM PDT 24
Finished Aug 12 04:51:17 PM PDT 24
Peak memory 273080 kb
Host smart-13e3d312-13ce-4575-a827-7f65c1bba5dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220046383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3220046383
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1676157469
Short name T377
Test name
Test status
Simulation time 1161320202 ps
CPU time 50.08 seconds
Started Aug 12 04:34:09 PM PDT 24
Finished Aug 12 04:34:59 PM PDT 24
Peak memory 248976 kb
Host smart-e914415f-c000-4072-a372-529e9ace30d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1676157469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1676157469
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.4284616989
Short name T452
Test name
Test status
Simulation time 2108090687 ps
CPU time 40.1 seconds
Started Aug 12 04:34:02 PM PDT 24
Finished Aug 12 04:34:42 PM PDT 24
Peak memory 256256 kb
Host smart-41cc2435-303b-4901-94a2-a143415c53c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42846
16989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4284616989
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3926062829
Short name T677
Test name
Test status
Simulation time 213922212 ps
CPU time 11.55 seconds
Started Aug 12 04:34:15 PM PDT 24
Finished Aug 12 04:34:27 PM PDT 24
Peak memory 248616 kb
Host smart-5883c6af-a136-41e6-9ad4-cdff28795a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39260
62829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3926062829
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3347961009
Short name T343
Test name
Test status
Simulation time 65267600929 ps
CPU time 1093.98 seconds
Started Aug 12 04:34:00 PM PDT 24
Finished Aug 12 04:52:14 PM PDT 24
Peak memory 281580 kb
Host smart-a6e12d75-39cc-4ac0-b3fd-4e25e2ec5530
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347961009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3347961009
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3676196961
Short name T663
Test name
Test status
Simulation time 775528277764 ps
CPU time 2653.65 seconds
Started Aug 12 04:33:56 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 289596 kb
Host smart-b69d7036-6174-42dc-ae27-726ef71030d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676196961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3676196961
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.655901106
Short name T331
Test name
Test status
Simulation time 12373137096 ps
CPU time 548.49 seconds
Started Aug 12 04:34:09 PM PDT 24
Finished Aug 12 04:43:17 PM PDT 24
Peak memory 249124 kb
Host smart-be181afa-2c7e-4219-a8de-c3540f29ae0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655901106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.655901106
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1870335726
Short name T389
Test name
Test status
Simulation time 483937366 ps
CPU time 8.64 seconds
Started Aug 12 04:34:23 PM PDT 24
Finished Aug 12 04:34:31 PM PDT 24
Peak memory 249000 kb
Host smart-01e557d5-2663-4f84-b59b-1686f614366c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18703
35726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1870335726
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2957241650
Short name T641
Test name
Test status
Simulation time 108346004 ps
CPU time 4.92 seconds
Started Aug 12 04:34:15 PM PDT 24
Finished Aug 12 04:34:20 PM PDT 24
Peak memory 248436 kb
Host smart-f6ec1752-0289-428d-860f-834021fb012a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29572
41650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2957241650
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.292365318
Short name T35
Test name
Test status
Simulation time 1729374364 ps
CPU time 24.22 seconds
Started Aug 12 04:34:13 PM PDT 24
Finished Aug 12 04:34:38 PM PDT 24
Peak memory 277836 kb
Host smart-13bc4d66-e765-4abd-bf82-40376e00e85b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=292365318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.292365318
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3311809071
Short name T640
Test name
Test status
Simulation time 385076659 ps
CPU time 31.97 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:34:29 PM PDT 24
Peak memory 248956 kb
Host smart-abe39cc4-0404-431a-8920-11cc6000e68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33118
09071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3311809071
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2246420461
Short name T561
Test name
Test status
Simulation time 1120256591 ps
CPU time 27.54 seconds
Started Aug 12 04:34:11 PM PDT 24
Finished Aug 12 04:34:39 PM PDT 24
Peak memory 257176 kb
Host smart-d043cbf4-64c5-49bd-9306-8b0723d1ed64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22464
20461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2246420461
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.665201721
Short name T639
Test name
Test status
Simulation time 232098237736 ps
CPU time 3206.66 seconds
Started Aug 12 04:35:16 PM PDT 24
Finished Aug 12 05:28:44 PM PDT 24
Peak memory 289696 kb
Host smart-34db0b32-a8e1-47b6-990b-f9f4259a598d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665201721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.665201721
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3612970926
Short name T223
Test name
Test status
Simulation time 3470749560 ps
CPU time 194.73 seconds
Started Aug 12 04:35:25 PM PDT 24
Finished Aug 12 04:38:39 PM PDT 24
Peak memory 256868 kb
Host smart-27357f8d-d5d0-41f5-9329-413f4b1a815c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36129
70926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3612970926
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.146327935
Short name T658
Test name
Test status
Simulation time 3775048033 ps
CPU time 45.04 seconds
Started Aug 12 04:35:23 PM PDT 24
Finished Aug 12 04:36:09 PM PDT 24
Peak memory 257280 kb
Host smart-af13d682-b875-457c-92ae-d7eeba9e3459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14632
7935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.146327935
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.585346008
Short name T344
Test name
Test status
Simulation time 40258282456 ps
CPU time 1059.19 seconds
Started Aug 12 04:35:15 PM PDT 24
Finished Aug 12 04:52:55 PM PDT 24
Peak memory 265112 kb
Host smart-51729202-3db8-49a1-b9b1-1f9ddf79316e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585346008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.585346008
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1752928780
Short name T463
Test name
Test status
Simulation time 35217617910 ps
CPU time 2023.37 seconds
Started Aug 12 04:35:20 PM PDT 24
Finished Aug 12 05:09:04 PM PDT 24
Peak memory 284504 kb
Host smart-b0714cbf-f06c-4912-b61d-4a1fa07be6c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752928780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1752928780
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.58637966
Short name T322
Test name
Test status
Simulation time 8626339384 ps
CPU time 172.87 seconds
Started Aug 12 04:35:25 PM PDT 24
Finished Aug 12 04:38:18 PM PDT 24
Peak memory 249216 kb
Host smart-87018404-b2d6-40d5-9240-561f5b766349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58637966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.58637966
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1686854744
Short name T195
Test name
Test status
Simulation time 80609912 ps
CPU time 5.65 seconds
Started Aug 12 04:35:20 PM PDT 24
Finished Aug 12 04:35:25 PM PDT 24
Peak memory 249024 kb
Host smart-d6a673d9-647f-49d7-9c35-035c7d172ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16868
54744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1686854744
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1413922015
Short name T101
Test name
Test status
Simulation time 592928343 ps
CPU time 19.78 seconds
Started Aug 12 04:35:17 PM PDT 24
Finished Aug 12 04:35:37 PM PDT 24
Peak memory 248568 kb
Host smart-2ecf397c-dbf9-4dbe-9cbd-7e616b116461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14139
22015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1413922015
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.4127230866
Short name T280
Test name
Test status
Simulation time 3101937140 ps
CPU time 47 seconds
Started Aug 12 04:35:22 PM PDT 24
Finished Aug 12 04:36:09 PM PDT 24
Peak memory 256372 kb
Host smart-04370d48-855f-4574-9ae4-118a019af64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41272
30866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.4127230866
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3694167036
Short name T446
Test name
Test status
Simulation time 4196490149 ps
CPU time 59.15 seconds
Started Aug 12 04:35:20 PM PDT 24
Finished Aug 12 04:36:19 PM PDT 24
Peak memory 249304 kb
Host smart-64b05773-6d0d-412d-821d-8e8b6a6b212d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36941
67036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3694167036
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.464414614
Short name T680
Test name
Test status
Simulation time 83346277530 ps
CPU time 2751.42 seconds
Started Aug 12 04:35:19 PM PDT 24
Finished Aug 12 05:21:11 PM PDT 24
Peak memory 289768 kb
Host smart-1f442423-339f-4a2a-8fde-e65f87df8d42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464414614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.464414614
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.4092052345
Short name T51
Test name
Test status
Simulation time 21509535344 ps
CPU time 1487.55 seconds
Started Aug 12 04:35:37 PM PDT 24
Finished Aug 12 05:00:24 PM PDT 24
Peak memory 269496 kb
Host smart-96db0386-1487-43ec-a666-fe2f090f8b9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092052345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.4092052345
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3181183795
Short name T253
Test name
Test status
Simulation time 6291080644 ps
CPU time 148.54 seconds
Started Aug 12 04:35:37 PM PDT 24
Finished Aug 12 04:38:06 PM PDT 24
Peak memory 257380 kb
Host smart-6a75a9ca-23b3-401b-bb21-82552c0e2c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31811
83795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3181183795
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1917539763
Short name T248
Test name
Test status
Simulation time 417986507 ps
CPU time 34.12 seconds
Started Aug 12 04:35:38 PM PDT 24
Finished Aug 12 04:36:12 PM PDT 24
Peak memory 257240 kb
Host smart-26ab45bc-ef82-4d38-9d6a-1efd0339aaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19175
39763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1917539763
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3966051273
Short name T597
Test name
Test status
Simulation time 8622157839 ps
CPU time 674.18 seconds
Started Aug 12 04:35:35 PM PDT 24
Finished Aug 12 04:46:50 PM PDT 24
Peak memory 273068 kb
Host smart-b29e4092-c471-44a5-abda-f4bef9132ded
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966051273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3966051273
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3639941000
Short name T625
Test name
Test status
Simulation time 5852380288 ps
CPU time 127.12 seconds
Started Aug 12 04:35:35 PM PDT 24
Finished Aug 12 04:37:43 PM PDT 24
Peak memory 249164 kb
Host smart-a29b4b9d-8092-4fb0-b846-db5410b7f8e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639941000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3639941000
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2214034082
Short name T480
Test name
Test status
Simulation time 4105043333 ps
CPU time 59.55 seconds
Started Aug 12 04:35:38 PM PDT 24
Finished Aug 12 04:36:37 PM PDT 24
Peak memory 257252 kb
Host smart-e4028435-7035-436b-97cb-4cfe2f149a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22140
34082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2214034082
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1826774228
Short name T100
Test name
Test status
Simulation time 738916106 ps
CPU time 21.16 seconds
Started Aug 12 04:35:35 PM PDT 24
Finished Aug 12 04:35:56 PM PDT 24
Peak memory 248288 kb
Host smart-e48ebb05-4013-48a0-b894-80fcf6c825bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18267
74228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1826774228
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2862555744
Short name T84
Test name
Test status
Simulation time 3141506598 ps
CPU time 33.22 seconds
Started Aug 12 04:35:36 PM PDT 24
Finished Aug 12 04:36:09 PM PDT 24
Peak memory 256552 kb
Host smart-cd385aac-1b44-4621-b56f-da362fd7fe76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28625
55744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2862555744
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3689382043
Short name T635
Test name
Test status
Simulation time 3966876060 ps
CPU time 29.68 seconds
Started Aug 12 04:35:36 PM PDT 24
Finished Aug 12 04:36:06 PM PDT 24
Peak memory 257324 kb
Host smart-bf975d98-f76c-4a1c-bfd2-648ad63c06f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36893
82043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3689382043
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3307001155
Short name T98
Test name
Test status
Simulation time 11739918104 ps
CPU time 489.06 seconds
Started Aug 12 04:35:35 PM PDT 24
Finished Aug 12 04:43:44 PM PDT 24
Peak memory 272800 kb
Host smart-39884a84-7e49-4e8f-9fb7-4859eb9097be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307001155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3307001155
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.480521420
Short name T674
Test name
Test status
Simulation time 740786101 ps
CPU time 33.68 seconds
Started Aug 12 04:35:38 PM PDT 24
Finished Aug 12 04:36:11 PM PDT 24
Peak memory 256524 kb
Host smart-b62344df-5feb-40b8-a65b-39f861b006c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48052
1420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.480521420
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3371323912
Short name T547
Test name
Test status
Simulation time 349476539 ps
CPU time 21.92 seconds
Started Aug 12 04:35:37 PM PDT 24
Finished Aug 12 04:35:59 PM PDT 24
Peak memory 248996 kb
Host smart-be7fc394-1d42-444e-a164-2b1f7096aedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
23912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3371323912
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.841379122
Short name T346
Test name
Test status
Simulation time 39718840789 ps
CPU time 1493.26 seconds
Started Aug 12 04:35:37 PM PDT 24
Finished Aug 12 05:00:30 PM PDT 24
Peak memory 287408 kb
Host smart-2653e441-9de5-4118-8a2f-88d21b8aba5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841379122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.841379122
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3200131148
Short name T89
Test name
Test status
Simulation time 222113083301 ps
CPU time 1961.32 seconds
Started Aug 12 04:35:36 PM PDT 24
Finished Aug 12 05:08:17 PM PDT 24
Peak memory 272992 kb
Host smart-28654800-2ff8-4053-ad92-b66a1d3564a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200131148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3200131148
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3282397343
Short name T327
Test name
Test status
Simulation time 10728057116 ps
CPU time 85.12 seconds
Started Aug 12 04:35:35 PM PDT 24
Finished Aug 12 04:37:00 PM PDT 24
Peak memory 249076 kb
Host smart-0bc48dc0-0e1f-4877-8cd9-69b30c5fb414
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282397343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3282397343
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.666264227
Short name T52
Test name
Test status
Simulation time 525471806 ps
CPU time 34.56 seconds
Started Aug 12 04:35:35 PM PDT 24
Finished Aug 12 04:36:10 PM PDT 24
Peak memory 256208 kb
Host smart-6fd0c8ac-1674-440f-bf16-a1fdc3f66fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66626
4227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.666264227
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2981246323
Short name T99
Test name
Test status
Simulation time 3366272360 ps
CPU time 60.69 seconds
Started Aug 12 04:35:36 PM PDT 24
Finished Aug 12 04:36:36 PM PDT 24
Peak memory 250120 kb
Host smart-15f85f6a-2810-4620-b525-47e8a477a8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29812
46323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2981246323
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3612278173
Short name T593
Test name
Test status
Simulation time 809398260 ps
CPU time 18.28 seconds
Started Aug 12 04:35:39 PM PDT 24
Finished Aug 12 04:35:57 PM PDT 24
Peak memory 256512 kb
Host smart-5baab62c-407a-41d6-a9b1-cad3980323e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36122
78173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3612278173
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3751008315
Short name T540
Test name
Test status
Simulation time 110431175 ps
CPU time 10.66 seconds
Started Aug 12 04:35:38 PM PDT 24
Finished Aug 12 04:35:48 PM PDT 24
Peak memory 255608 kb
Host smart-63de97f3-bc72-44f6-b51b-830b1f90025e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
08315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3751008315
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3944229025
Short name T282
Test name
Test status
Simulation time 1666097766 ps
CPU time 93.83 seconds
Started Aug 12 04:35:36 PM PDT 24
Finished Aug 12 04:37:10 PM PDT 24
Peak memory 257104 kb
Host smart-815d9072-09a7-40c1-9962-01b46c430e13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944229025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3944229025
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.593146880
Short name T580
Test name
Test status
Simulation time 6634003284 ps
CPU time 685.41 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:47:18 PM PDT 24
Peak memory 272464 kb
Host smart-af595ae7-939b-4688-aa16-03188eaf0d59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593146880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.593146880
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1065086439
Short name T305
Test name
Test status
Simulation time 992976073 ps
CPU time 97.08 seconds
Started Aug 12 04:35:39 PM PDT 24
Finished Aug 12 04:37:16 PM PDT 24
Peak memory 256880 kb
Host smart-4c4ea52d-1976-49e3-aa7a-b651ef4c62a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10650
86439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1065086439
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.868215682
Short name T300
Test name
Test status
Simulation time 1958201905 ps
CPU time 39.71 seconds
Started Aug 12 04:35:36 PM PDT 24
Finished Aug 12 04:36:16 PM PDT 24
Peak memory 255992 kb
Host smart-e2d3ff56-5e59-4b5b-a89f-11895f608775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86821
5682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.868215682
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2538043842
Short name T339
Test name
Test status
Simulation time 38704967240 ps
CPU time 690.93 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 04:47:24 PM PDT 24
Peak memory 272872 kb
Host smart-2b8c3cbc-8ce1-417c-87dc-5da80e2b001b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538043842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2538043842
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2591031083
Short name T474
Test name
Test status
Simulation time 72984006042 ps
CPU time 1146.92 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:54:59 PM PDT 24
Peak memory 273572 kb
Host smart-84e7c004-666e-4461-8a79-b7a1f3757d97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591031083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2591031083
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.712389039
Short name T523
Test name
Test status
Simulation time 7340676572 ps
CPU time 157.39 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:38:30 PM PDT 24
Peak memory 249164 kb
Host smart-d6d7d4c8-f608-416b-9e89-1773161c24d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712389039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.712389039
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1106993884
Short name T402
Test name
Test status
Simulation time 859543982 ps
CPU time 60.13 seconds
Started Aug 12 04:35:39 PM PDT 24
Finished Aug 12 04:36:39 PM PDT 24
Peak memory 249084 kb
Host smart-d5678386-7c6f-48f7-9dbf-fdc8c1fc2cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11069
93884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1106993884
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2639073025
Short name T438
Test name
Test status
Simulation time 1541582329 ps
CPU time 36.13 seconds
Started Aug 12 04:35:37 PM PDT 24
Finished Aug 12 04:36:13 PM PDT 24
Peak memory 257276 kb
Host smart-0d17a48a-3ba4-4063-beb9-6fd3ad7f81da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26390
73025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2639073025
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3492065803
Short name T256
Test name
Test status
Simulation time 343357037 ps
CPU time 23.78 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 04:36:17 PM PDT 24
Peak memory 249568 kb
Host smart-3c870201-35fc-4a5f-9a40-58763bd244ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34920
65803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3492065803
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1190858114
Short name T390
Test name
Test status
Simulation time 148286826 ps
CPU time 9.05 seconds
Started Aug 12 04:35:36 PM PDT 24
Finished Aug 12 04:35:45 PM PDT 24
Peak memory 255784 kb
Host smart-217e1588-8e63-466b-be77-a79bee421116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11908
58114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1190858114
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2834711856
Short name T609
Test name
Test status
Simulation time 36393123651 ps
CPU time 1764.43 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 05:05:19 PM PDT 24
Peak memory 289984 kb
Host smart-d906f815-567b-4fba-ba8c-2a127bb94eb4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834711856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2834711856
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3050321969
Short name T109
Test name
Test status
Simulation time 21716833939 ps
CPU time 1508.02 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 05:01:01 PM PDT 24
Peak memory 273456 kb
Host smart-e1289711-0318-40b8-bacc-b1a1b6a08170
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050321969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3050321969
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2201881882
Short name T293
Test name
Test status
Simulation time 6246106714 ps
CPU time 172.96 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:38:45 PM PDT 24
Peak memory 256580 kb
Host smart-5678810e-d67b-4a61-bcf3-42d505e8f578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22018
81882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2201881882
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2235684141
Short name T10
Test name
Test status
Simulation time 251524851 ps
CPU time 27.62 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:36:19 PM PDT 24
Peak memory 248968 kb
Host smart-5f698438-68fa-4ab6-bba1-231471bf5136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22356
84141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2235684141
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2896793360
Short name T317
Test name
Test status
Simulation time 22310421409 ps
CPU time 1650.49 seconds
Started Aug 12 04:35:50 PM PDT 24
Finished Aug 12 05:03:21 PM PDT 24
Peak memory 289456 kb
Host smart-bbb63909-a8fa-46fc-ae39-4188f1e192ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896793360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2896793360
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.950316938
Short name T512
Test name
Test status
Simulation time 51805925705 ps
CPU time 3083.81 seconds
Started Aug 12 04:35:51 PM PDT 24
Finished Aug 12 05:27:15 PM PDT 24
Peak memory 289312 kb
Host smart-05e72fce-c55e-4988-ad99-d0d0e97e2b47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950316938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.950316938
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1938768744
Short name T323
Test name
Test status
Simulation time 9000823402 ps
CPU time 385.38 seconds
Started Aug 12 04:35:51 PM PDT 24
Finished Aug 12 04:42:17 PM PDT 24
Peak memory 248936 kb
Host smart-9bc9be78-133d-4ff9-93bd-ea32fba126f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938768744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1938768744
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3045592248
Short name T503
Test name
Test status
Simulation time 852061883 ps
CPU time 49.55 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:36:43 PM PDT 24
Peak memory 256144 kb
Host smart-9d316b52-ac28-4362-947d-dab970387078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30455
92248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3045592248
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2443260304
Short name T518
Test name
Test status
Simulation time 113864032 ps
CPU time 14.11 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 04:36:11 PM PDT 24
Peak memory 248268 kb
Host smart-c2ea6514-63e1-40ea-a496-5887be6a5eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24432
60304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2443260304
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.88036252
Short name T656
Test name
Test status
Simulation time 1576315089 ps
CPU time 55.1 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:36:48 PM PDT 24
Peak memory 248992 kb
Host smart-61d11e52-9b1a-47f6-8a92-2c8b16a839c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88036
252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.88036252
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3582125268
Short name T42
Test name
Test status
Simulation time 1241727766 ps
CPU time 12.76 seconds
Started Aug 12 04:35:55 PM PDT 24
Finished Aug 12 04:36:08 PM PDT 24
Peak memory 248960 kb
Host smart-bba3a301-4c9d-426c-8fb1-2bd1ce42b35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35821
25268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3582125268
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3575541255
Short name T565
Test name
Test status
Simulation time 54266841323 ps
CPU time 888.35 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 04:50:41 PM PDT 24
Peak memory 273864 kb
Host smart-948cf0b9-5d56-41a9-b79e-7aff9304d8f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575541255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3575541255
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1529147552
Short name T310
Test name
Test status
Simulation time 44909301877 ps
CPU time 2506.25 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 05:17:38 PM PDT 24
Peak memory 288952 kb
Host smart-92c13cd1-bd94-4c60-9aaf-f7402df4f498
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529147552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1529147552
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2720203232
Short name T460
Test name
Test status
Simulation time 7804344095 ps
CPU time 109.06 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 04:37:42 PM PDT 24
Peak memory 257256 kb
Host smart-c683695e-f6db-4cbd-b8bf-5ec82547898c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
03232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2720203232
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3087955631
Short name T627
Test name
Test status
Simulation time 1421205106 ps
CPU time 24.43 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:36:16 PM PDT 24
Peak memory 257156 kb
Host smart-b82ce3a6-b2fe-49be-8a7c-c81b6a944c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879
55631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3087955631
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3439530628
Short name T38
Test name
Test status
Simulation time 12890407413 ps
CPU time 1384.47 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 04:58:58 PM PDT 24
Peak memory 289668 kb
Host smart-ec1d53e8-734f-41cf-b2e2-6efc0beaf2d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439530628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3439530628
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2176462182
Short name T525
Test name
Test status
Simulation time 26377802629 ps
CPU time 1356.78 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 04:58:30 PM PDT 24
Peak memory 273264 kb
Host smart-ced8d2db-92a2-4b59-84e0-1cb82dbb4975
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176462182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2176462182
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3618736751
Short name T196
Test name
Test status
Simulation time 26924443942 ps
CPU time 184.23 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:38:57 PM PDT 24
Peak memory 249076 kb
Host smart-3e89977b-6287-44c4-af5e-8ba766e2e328
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618736751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3618736751
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1773803725
Short name T363
Test name
Test status
Simulation time 243788571 ps
CPU time 4.87 seconds
Started Aug 12 04:35:55 PM PDT 24
Finished Aug 12 04:36:00 PM PDT 24
Peak memory 240780 kb
Host smart-ba0edf1a-9ace-4889-b6c8-ac9d1dbf9560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17738
03725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1773803725
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1044799396
Short name T648
Test name
Test status
Simulation time 76394787 ps
CPU time 8.14 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:36:02 PM PDT 24
Peak memory 248496 kb
Host smart-6634aa58-bf98-4a8d-bcfa-bc5cda2f263a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10447
99396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1044799396
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3369011012
Short name T268
Test name
Test status
Simulation time 2604084097 ps
CPU time 30.91 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 04:36:24 PM PDT 24
Peak memory 256932 kb
Host smart-87752392-da83-46f9-815e-65a57300f475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33690
11012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3369011012
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.235664400
Short name T397
Test name
Test status
Simulation time 615735601 ps
CPU time 16.51 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:36:08 PM PDT 24
Peak memory 249292 kb
Host smart-4ed9f6d5-a295-4082-8104-497d0f5d8364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23566
4400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.235664400
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.4189861091
Short name T509
Test name
Test status
Simulation time 2250812590 ps
CPU time 185.02 seconds
Started Aug 12 04:35:52 PM PDT 24
Finished Aug 12 04:38:58 PM PDT 24
Peak memory 257248 kb
Host smart-1d78f4e1-4082-466d-b946-7ae60506a592
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189861091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.4189861091
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.735452681
Short name T95
Test name
Test status
Simulation time 4652009653 ps
CPU time 248.18 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:40:02 PM PDT 24
Peak memory 268364 kb
Host smart-4fc378d1-3a0f-46f0-95c4-616ce698476e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735452681 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.735452681
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.855102483
Short name T621
Test name
Test status
Simulation time 28785657107 ps
CPU time 1815.41 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 05:06:12 PM PDT 24
Peak memory 273804 kb
Host smart-df46a5d9-668f-42c6-874c-d14f51601253
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855102483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.855102483
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.694072307
Short name T379
Test name
Test status
Simulation time 18292355010 ps
CPU time 265.79 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:40:20 PM PDT 24
Peak memory 256816 kb
Host smart-d953cf1a-9eaa-4b7e-901d-82c1eb8c4b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69407
2307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.694072307
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1989543965
Short name T366
Test name
Test status
Simulation time 1264759889 ps
CPU time 27.32 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:36:22 PM PDT 24
Peak memory 249012 kb
Host smart-5377668f-c516-4095-bb95-d04510fba57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
43965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1989543965
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.4117321679
Short name T646
Test name
Test status
Simulation time 20391566263 ps
CPU time 794.52 seconds
Started Aug 12 04:35:57 PM PDT 24
Finished Aug 12 04:49:12 PM PDT 24
Peak memory 272944 kb
Host smart-9529437e-c76a-41fd-996d-d409a6fab248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117321679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4117321679
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.966836304
Short name T485
Test name
Test status
Simulation time 186765341584 ps
CPU time 1347.91 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:58:22 PM PDT 24
Peak memory 273620 kb
Host smart-05e6b1e2-1328-4799-9668-490e4321a0e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966836304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.966836304
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1206218422
Short name T329
Test name
Test status
Simulation time 10926710773 ps
CPU time 447.98 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 04:43:24 PM PDT 24
Peak memory 249032 kb
Host smart-5e037cb1-9c6a-4346-9d1d-6bcb254809bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206218422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1206218422
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3436365190
Short name T29
Test name
Test status
Simulation time 228501916 ps
CPU time 8.67 seconds
Started Aug 12 04:35:55 PM PDT 24
Finished Aug 12 04:36:03 PM PDT 24
Peak memory 249092 kb
Host smart-706f4e29-c28a-4b84-9c44-33999960340f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34363
65190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3436365190
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2121093412
Short name T520
Test name
Test status
Simulation time 668358224 ps
CPU time 33.23 seconds
Started Aug 12 04:35:55 PM PDT 24
Finished Aug 12 04:36:28 PM PDT 24
Peak memory 249040 kb
Host smart-31375ed6-b7c9-44bd-afa9-4b49fa6b02b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21210
93412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2121093412
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1378467001
Short name T613
Test name
Test status
Simulation time 3249863227 ps
CPU time 41.02 seconds
Started Aug 12 04:35:55 PM PDT 24
Finished Aug 12 04:36:37 PM PDT 24
Peak memory 257352 kb
Host smart-d54e62ca-c47f-4f8b-ad48-0fcf8e4ab8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784
67001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1378467001
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2636308512
Short name T373
Test name
Test status
Simulation time 948260673 ps
CPU time 15.81 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 04:36:09 PM PDT 24
Peak memory 249360 kb
Host smart-270dec62-0c50-4b5d-a9fe-943d6c498e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26363
08512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2636308512
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.12040494
Short name T669
Test name
Test status
Simulation time 30335860882 ps
CPU time 1387.26 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 04:59:04 PM PDT 24
Peak memory 288472 kb
Host smart-a6cd6cf0-162d-411b-9954-60916a69e328
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12040494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.12040494
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.459642485
Short name T636
Test name
Test status
Simulation time 4644187246 ps
CPU time 77.67 seconds
Started Aug 12 04:35:58 PM PDT 24
Finished Aug 12 04:37:16 PM PDT 24
Peak memory 256776 kb
Host smart-ee84cda4-25fa-43dd-88c5-ecab69bdf68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45964
2485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.459642485
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4240165810
Short name T461
Test name
Test status
Simulation time 148310414 ps
CPU time 6.63 seconds
Started Aug 12 04:35:57 PM PDT 24
Finished Aug 12 04:36:04 PM PDT 24
Peak memory 248980 kb
Host smart-8bd910b6-0fd7-40a3-8846-3560401c0ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42401
65810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4240165810
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1442478567
Short name T243
Test name
Test status
Simulation time 220478946759 ps
CPU time 2456.25 seconds
Started Aug 12 04:35:53 PM PDT 24
Finished Aug 12 05:16:49 PM PDT 24
Peak memory 289492 kb
Host smart-c4b0c1a7-578e-4c3d-abca-24a678a94781
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442478567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1442478567
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3130233558
Short name T466
Test name
Test status
Simulation time 250900543040 ps
CPU time 2662.41 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 05:20:19 PM PDT 24
Peak memory 289936 kb
Host smart-c7152058-bdd4-4c6c-86ae-7c1ca20119ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130233558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3130233558
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3872103453
Short name T227
Test name
Test status
Simulation time 374985223 ps
CPU time 16.42 seconds
Started Aug 12 04:35:55 PM PDT 24
Finished Aug 12 04:36:12 PM PDT 24
Peak memory 257192 kb
Host smart-b8241601-436c-44d8-af46-9eae4549e5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38721
03453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3872103453
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.28901679
Short name T294
Test name
Test status
Simulation time 660985513 ps
CPU time 28.13 seconds
Started Aug 12 04:35:55 PM PDT 24
Finished Aug 12 04:36:23 PM PDT 24
Peak memory 256748 kb
Host smart-ee25800b-8516-4a56-96c8-a92226fb7bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.28901679
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3863194556
Short name T513
Test name
Test status
Simulation time 166900553 ps
CPU time 6.74 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 04:36:03 PM PDT 24
Peak memory 249040 kb
Host smart-179a444a-47fd-4e89-a783-f0d322042384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38631
94556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3863194556
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.224846562
Short name T553
Test name
Test status
Simulation time 860888868 ps
CPU time 25.85 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 04:36:22 PM PDT 24
Peak memory 257148 kb
Host smart-e873c3b7-381d-4384-be5c-c39177da44b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22484
6562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.224846562
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.341475896
Short name T439
Test name
Test status
Simulation time 1388446114 ps
CPU time 22.67 seconds
Started Aug 12 04:35:59 PM PDT 24
Finished Aug 12 04:36:22 PM PDT 24
Peak memory 256220 kb
Host smart-fb22bdfc-071f-48e1-9cdd-b9fc4149500f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341475896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.341475896
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1150333235
Short name T534
Test name
Test status
Simulation time 32366968395 ps
CPU time 2022.37 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 05:09:39 PM PDT 24
Peak memory 284644 kb
Host smart-2e9c6204-ffd8-4c20-8971-508cabc928e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150333235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1150333235
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2049534860
Short name T486
Test name
Test status
Simulation time 2824535867 ps
CPU time 137.27 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 04:38:13 PM PDT 24
Peak memory 256688 kb
Host smart-669bdf52-6758-467a-801c-3d3d81716468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20495
34860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2049534860
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1361231159
Short name T388
Test name
Test status
Simulation time 10210325690 ps
CPU time 39.81 seconds
Started Aug 12 04:35:59 PM PDT 24
Finished Aug 12 04:36:39 PM PDT 24
Peak memory 256696 kb
Host smart-672abc5b-d1b1-4dd8-afce-68e2df16cd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13612
31159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1361231159
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1488055701
Short name T349
Test name
Test status
Simulation time 41570987537 ps
CPU time 2406.95 seconds
Started Aug 12 04:36:00 PM PDT 24
Finished Aug 12 05:16:07 PM PDT 24
Peak memory 289344 kb
Host smart-1c386644-4937-498b-ba34-79b427944696
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488055701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1488055701
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1780951568
Short name T40
Test name
Test status
Simulation time 248688261173 ps
CPU time 1390.6 seconds
Started Aug 12 04:35:56 PM PDT 24
Finished Aug 12 04:59:07 PM PDT 24
Peak memory 289712 kb
Host smart-c15b7584-d285-4e5b-8f51-3d5551944325
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780951568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1780951568
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2468665795
Short name T336
Test name
Test status
Simulation time 10507262226 ps
CPU time 404.47 seconds
Started Aug 12 04:35:59 PM PDT 24
Finished Aug 12 04:42:44 PM PDT 24
Peak memory 247940 kb
Host smart-999e6307-caee-4e89-8bf2-98d4f8de5014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468665795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2468665795
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.855841432
Short name T596
Test name
Test status
Simulation time 374014892 ps
CPU time 24.05 seconds
Started Aug 12 04:35:54 PM PDT 24
Finished Aug 12 04:36:19 PM PDT 24
Peak memory 256740 kb
Host smart-970350f6-dc18-45d3-b909-f50e3b2a6902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85584
1432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.855841432
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1038607445
Short name T19
Test name
Test status
Simulation time 1922718355 ps
CPU time 40.37 seconds
Started Aug 12 04:35:55 PM PDT 24
Finished Aug 12 04:36:36 PM PDT 24
Peak memory 249064 kb
Host smart-9be9569d-dd9c-4376-ad5b-b98252f0aaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10386
07445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1038607445
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2650121826
Short name T696
Test name
Test status
Simulation time 2874906580 ps
CPU time 40.24 seconds
Started Aug 12 04:35:57 PM PDT 24
Finished Aug 12 04:36:38 PM PDT 24
Peak memory 257000 kb
Host smart-40fb53a9-a475-4bb1-ab24-95e587b62130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26501
21826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2650121826
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1959434509
Short name T655
Test name
Test status
Simulation time 35727074653 ps
CPU time 2246.38 seconds
Started Aug 12 04:35:59 PM PDT 24
Finished Aug 12 05:13:26 PM PDT 24
Peak memory 289844 kb
Host smart-19ab9ee9-4acc-48c6-9afd-8fa19eb44344
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959434509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1959434509
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3447975148
Short name T106
Test name
Test status
Simulation time 31299065628 ps
CPU time 1748.88 seconds
Started Aug 12 04:36:09 PM PDT 24
Finished Aug 12 05:05:18 PM PDT 24
Peak memory 289348 kb
Host smart-368d8366-f978-41d4-bc85-0c918e9f7b24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447975148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3447975148
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3422853870
Short name T303
Test name
Test status
Simulation time 11990523805 ps
CPU time 223.09 seconds
Started Aug 12 04:36:04 PM PDT 24
Finished Aug 12 04:39:48 PM PDT 24
Peak memory 256856 kb
Host smart-214211b2-0304-4e15-8328-7922b0408879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34228
53870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3422853870
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.780097417
Short name T412
Test name
Test status
Simulation time 579446173 ps
CPU time 26.09 seconds
Started Aug 12 04:36:07 PM PDT 24
Finished Aug 12 04:36:33 PM PDT 24
Peak memory 255424 kb
Host smart-bd8cfbe7-351d-4bc0-a8fd-449adca3c679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78009
7417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.780097417
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3966680275
Short name T362
Test name
Test status
Simulation time 148802736339 ps
CPU time 1426.38 seconds
Started Aug 12 04:36:07 PM PDT 24
Finished Aug 12 04:59:54 PM PDT 24
Peak memory 288860 kb
Host smart-693a8d2c-189c-4a36-9b26-9021ebd87047
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966680275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3966680275
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2168041234
Short name T568
Test name
Test status
Simulation time 7394519268 ps
CPU time 800.81 seconds
Started Aug 12 04:36:07 PM PDT 24
Finished Aug 12 04:49:28 PM PDT 24
Peak memory 273564 kb
Host smart-973070b8-6d36-49e1-856f-ebcfea1ecee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168041234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2168041234
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2573869158
Short name T316
Test name
Test status
Simulation time 18454994973 ps
CPU time 391.45 seconds
Started Aug 12 04:36:08 PM PDT 24
Finished Aug 12 04:42:40 PM PDT 24
Peak memory 249008 kb
Host smart-8389e926-59ac-441f-be32-aa80070ccb50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573869158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2573869158
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.508854839
Short name T528
Test name
Test status
Simulation time 389955330 ps
CPU time 37.19 seconds
Started Aug 12 04:36:08 PM PDT 24
Finished Aug 12 04:36:45 PM PDT 24
Peak memory 257152 kb
Host smart-42210b02-84fc-4724-a2cf-fb98d8426068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50885
4839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.508854839
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.341764510
Short name T579
Test name
Test status
Simulation time 335730137 ps
CPU time 16.76 seconds
Started Aug 12 04:36:04 PM PDT 24
Finished Aug 12 04:36:21 PM PDT 24
Peak memory 249008 kb
Host smart-5e22d8e0-c089-4246-8079-bb741fdf91af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34176
4510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.341764510
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.887043011
Short name T574
Test name
Test status
Simulation time 159390030 ps
CPU time 16.71 seconds
Started Aug 12 04:36:06 PM PDT 24
Finished Aug 12 04:36:23 PM PDT 24
Peak memory 249388 kb
Host smart-fefa0ec5-9249-4bb0-85dd-18f9bc4e081e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88704
3011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.887043011
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3334180775
Short name T396
Test name
Test status
Simulation time 238135749 ps
CPU time 12.94 seconds
Started Aug 12 04:36:07 PM PDT 24
Finished Aug 12 04:36:20 PM PDT 24
Peak memory 249032 kb
Host smart-950802d4-6787-4bcf-b28c-d10c153ed334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33341
80775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3334180775
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2615216061
Short name T384
Test name
Test status
Simulation time 113916390082 ps
CPU time 3287.93 seconds
Started Aug 12 04:36:01 PM PDT 24
Finished Aug 12 05:30:49 PM PDT 24
Peak memory 289960 kb
Host smart-5823adcc-ac61-4678-a2c4-70d8f08a82e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615216061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2615216061
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1592647630
Short name T118
Test name
Test status
Simulation time 2378231850 ps
CPU time 150.77 seconds
Started Aug 12 04:36:05 PM PDT 24
Finished Aug 12 04:38:36 PM PDT 24
Peak memory 265580 kb
Host smart-522eaadc-7eca-4e8e-a014-4a33a0045dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592647630 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1592647630
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1488826762
Short name T206
Test name
Test status
Simulation time 40602414 ps
CPU time 3.46 seconds
Started Aug 12 04:34:21 PM PDT 24
Finished Aug 12 04:34:25 PM PDT 24
Peak memory 249128 kb
Host smart-df7aa829-9bd8-48a6-af4c-df54d15eb247
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1488826762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1488826762
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1452968539
Short name T242
Test name
Test status
Simulation time 180963687119 ps
CPU time 2046.54 seconds
Started Aug 12 04:34:06 PM PDT 24
Finished Aug 12 05:08:12 PM PDT 24
Peak memory 281844 kb
Host smart-b239512b-fa48-48ec-b0ed-6c15136a0ed2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452968539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1452968539
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2935034989
Short name T408
Test name
Test status
Simulation time 1260495843 ps
CPU time 52.12 seconds
Started Aug 12 04:34:10 PM PDT 24
Finished Aug 12 04:35:02 PM PDT 24
Peak memory 248988 kb
Host smart-f7a4e61e-7460-4d15-8dbd-cd1505dd6f74
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2935034989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2935034989
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.224933110
Short name T30
Test name
Test status
Simulation time 1254546566 ps
CPU time 53.88 seconds
Started Aug 12 04:34:21 PM PDT 24
Finished Aug 12 04:35:15 PM PDT 24
Peak memory 256472 kb
Host smart-98d5899a-988c-4454-9bc3-d206ae125ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22493
3110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.224933110
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.122862193
Short name T441
Test name
Test status
Simulation time 7350741944 ps
CPU time 65.81 seconds
Started Aug 12 04:33:49 PM PDT 24
Finished Aug 12 04:34:55 PM PDT 24
Peak memory 249004 kb
Host smart-777f2bb3-93de-4259-995e-86844f22b770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12286
2193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.122862193
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2572896272
Short name T330
Test name
Test status
Simulation time 93920581022 ps
CPU time 2127.73 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 05:09:25 PM PDT 24
Peak memory 282236 kb
Host smart-4f33cfbf-f714-4125-9363-a41a8ad6f8a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572896272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2572896272
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1661663982
Short name T36
Test name
Test status
Simulation time 66578091722 ps
CPU time 998.41 seconds
Started Aug 12 04:33:57 PM PDT 24
Finished Aug 12 04:50:36 PM PDT 24
Peak memory 273176 kb
Host smart-e6fcbb43-6908-4e27-9c29-030923f740fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661663982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1661663982
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.4183217634
Short name T315
Test name
Test status
Simulation time 6574124320 ps
CPU time 276.36 seconds
Started Aug 12 04:34:14 PM PDT 24
Finished Aug 12 04:38:50 PM PDT 24
Peak memory 247940 kb
Host smart-b58436a0-3c6c-4bba-800d-94926131e68a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183217634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.4183217634
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.894499591
Short name T383
Test name
Test status
Simulation time 1508998657 ps
CPU time 23.43 seconds
Started Aug 12 04:33:50 PM PDT 24
Finished Aug 12 04:34:13 PM PDT 24
Peak memory 256284 kb
Host smart-575fd9ac-f4ef-48f7-9a2b-bd8cbe011526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89449
9591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.894499591
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2079901528
Short name T490
Test name
Test status
Simulation time 777748289 ps
CPU time 14.3 seconds
Started Aug 12 04:34:07 PM PDT 24
Finished Aug 12 04:34:21 PM PDT 24
Peak memory 256320 kb
Host smart-17c73375-0509-444b-8c42-64d74c2e438a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20799
01528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2079901528
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2940627618
Short name T586
Test name
Test status
Simulation time 2332637514 ps
CPU time 59.7 seconds
Started Aug 12 04:34:32 PM PDT 24
Finished Aug 12 04:35:32 PM PDT 24
Peak memory 257040 kb
Host smart-f08344d4-0ab0-4d74-af4a-28ed6788b8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29406
27618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2940627618
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.456513741
Short name T193
Test name
Test status
Simulation time 14576415913 ps
CPU time 215.62 seconds
Started Aug 12 04:34:16 PM PDT 24
Finished Aug 12 04:37:52 PM PDT 24
Peak memory 272528 kb
Host smart-c807b672-be85-46d8-acbc-875ccd466772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456513741 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.456513741
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.839458010
Short name T220
Test name
Test status
Simulation time 16661013 ps
CPU time 2.78 seconds
Started Aug 12 04:34:09 PM PDT 24
Finished Aug 12 04:34:12 PM PDT 24
Peak memory 249204 kb
Host smart-49bef95c-b055-453d-bcf7-98980b4a6055
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=839458010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.839458010
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2721817925
Short name T603
Test name
Test status
Simulation time 121716200464 ps
CPU time 1805.21 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 05:04:22 PM PDT 24
Peak memory 273648 kb
Host smart-ea4c7da7-83dd-464b-abe6-ac2290bc1f7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721817925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2721817925
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1100401368
Short name T245
Test name
Test status
Simulation time 1201888295 ps
CPU time 28.75 seconds
Started Aug 12 04:34:15 PM PDT 24
Finished Aug 12 04:34:44 PM PDT 24
Peak memory 248952 kb
Host smart-438e5cc6-f4d9-44b2-8d43-7b7ba455ffb1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1100401368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1100401368
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1386225191
Short name T587
Test name
Test status
Simulation time 5604302306 ps
CPU time 159.66 seconds
Started Aug 12 04:34:00 PM PDT 24
Finished Aug 12 04:36:40 PM PDT 24
Peak memory 257272 kb
Host smart-2dd9a18a-8633-48fb-8356-cfe342a663ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13862
25191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1386225191
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.404345832
Short name T551
Test name
Test status
Simulation time 202462658 ps
CPU time 14.35 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:34:32 PM PDT 24
Peak memory 248952 kb
Host smart-8882f330-c3e5-47f0-9df7-231f5d062055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40434
5832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.404345832
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.446233423
Short name T582
Test name
Test status
Simulation time 19355899555 ps
CPU time 1516.71 seconds
Started Aug 12 04:34:14 PM PDT 24
Finished Aug 12 04:59:31 PM PDT 24
Peak memory 289936 kb
Host smart-74550b4f-74fa-4fe0-8e31-5b99b2187039
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446233423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.446233423
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3200936107
Short name T521
Test name
Test status
Simulation time 17408057761 ps
CPU time 1083.48 seconds
Started Aug 12 04:33:59 PM PDT 24
Finished Aug 12 04:52:03 PM PDT 24
Peak memory 272948 kb
Host smart-77c17cdb-8ee9-4493-b374-2f56860b5fbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200936107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3200936107
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.74922200
Short name T229
Test name
Test status
Simulation time 52174868839 ps
CPU time 559.15 seconds
Started Aug 12 04:34:26 PM PDT 24
Finished Aug 12 04:43:45 PM PDT 24
Peak memory 249076 kb
Host smart-7aa94591-4543-49fd-bfc1-3d141776e8ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74922200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.74922200
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3061187376
Short name T445
Test name
Test status
Simulation time 708518666 ps
CPU time 11.2 seconds
Started Aug 12 04:33:59 PM PDT 24
Finished Aug 12 04:34:11 PM PDT 24
Peak memory 249016 kb
Host smart-96fb4443-ea9d-4e75-8563-ccb48d4dda52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30611
87376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3061187376
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3554339063
Short name T542
Test name
Test status
Simulation time 305111882 ps
CPU time 10.63 seconds
Started Aug 12 04:34:00 PM PDT 24
Finished Aug 12 04:34:11 PM PDT 24
Peak memory 254768 kb
Host smart-fcfaf515-258e-4355-914b-ef7a76b8f6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35543
39063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3554339063
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.623943734
Short name T620
Test name
Test status
Simulation time 509612703 ps
CPU time 31.33 seconds
Started Aug 12 04:33:56 PM PDT 24
Finished Aug 12 04:34:28 PM PDT 24
Peak memory 257236 kb
Host smart-41c1b79e-bebf-4019-845c-fbf49d8664f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62394
3734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.623943734
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1581876405
Short name T679
Test name
Test status
Simulation time 336386713 ps
CPU time 8.29 seconds
Started Aug 12 04:34:10 PM PDT 24
Finished Aug 12 04:34:19 PM PDT 24
Peak memory 248972 kb
Host smart-212100fe-cce7-4e1d-b803-2adfa872f2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15818
76405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1581876405
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1268408352
Short name T125
Test name
Test status
Simulation time 121625796 ps
CPU time 3.1 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:34:21 PM PDT 24
Peak memory 249168 kb
Host smart-5935844d-6c6b-4d72-9817-781b5cfd48ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1268408352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1268408352
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3313089168
Short name T559
Test name
Test status
Simulation time 12817654822 ps
CPU time 1214.05 seconds
Started Aug 12 04:34:19 PM PDT 24
Finished Aug 12 04:54:33 PM PDT 24
Peak memory 288952 kb
Host smart-f62a5a18-9eeb-461f-bc7b-944bb5d28e22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313089168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3313089168
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3779646092
Short name T564
Test name
Test status
Simulation time 562490067 ps
CPU time 25.94 seconds
Started Aug 12 04:34:19 PM PDT 24
Finished Aug 12 04:34:45 PM PDT 24
Peak memory 248980 kb
Host smart-8432cbb3-b2dd-473b-a50c-ce8cf8f4724c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3779646092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3779646092
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.741394399
Short name T557
Test name
Test status
Simulation time 817655990 ps
CPU time 51.99 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:35:09 PM PDT 24
Peak memory 256776 kb
Host smart-dc400c50-37be-45bb-b484-5fecad8584d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74139
4399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.741394399
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.631934977
Short name T382
Test name
Test status
Simulation time 82628146 ps
CPU time 7.37 seconds
Started Aug 12 04:34:34 PM PDT 24
Finished Aug 12 04:34:42 PM PDT 24
Peak memory 248600 kb
Host smart-d00ed54d-223f-4bd1-99e9-d375df3d75d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63193
4977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.631934977
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1515117355
Short name T337
Test name
Test status
Simulation time 32844905995 ps
CPU time 1323.33 seconds
Started Aug 12 04:34:03 PM PDT 24
Finished Aug 12 04:56:07 PM PDT 24
Peak memory 288052 kb
Host smart-bebad408-831e-46f7-9a61-4dc4fb56ad55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515117355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1515117355
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1881276823
Short name T404
Test name
Test status
Simulation time 10913015022 ps
CPU time 1072.19 seconds
Started Aug 12 04:34:29 PM PDT 24
Finished Aug 12 04:52:22 PM PDT 24
Peak memory 289496 kb
Host smart-a787b63f-6706-4b6f-ada5-7bd6e0a47d9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881276823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1881276823
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.539752437
Short name T418
Test name
Test status
Simulation time 504304675 ps
CPU time 11.6 seconds
Started Aug 12 04:34:12 PM PDT 24
Finished Aug 12 04:34:24 PM PDT 24
Peak memory 256600 kb
Host smart-f31a1fe5-6c47-4c14-bd86-3cc768560ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53975
2437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.539752437
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2609725992
Short name T637
Test name
Test status
Simulation time 2040780638 ps
CPU time 26.49 seconds
Started Aug 12 04:34:18 PM PDT 24
Finished Aug 12 04:34:44 PM PDT 24
Peak memory 256448 kb
Host smart-d3af881f-5297-490d-9fe5-275e82ec5fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26097
25992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2609725992
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.826581990
Short name T575
Test name
Test status
Simulation time 1151697058 ps
CPU time 17.81 seconds
Started Aug 12 04:34:15 PM PDT 24
Finished Aug 12 04:34:33 PM PDT 24
Peak memory 256608 kb
Host smart-0bbecf3e-3e11-4ba2-a72c-eca0b1425775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82658
1990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.826581990
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2844645192
Short name T562
Test name
Test status
Simulation time 86846650 ps
CPU time 9.12 seconds
Started Aug 12 04:34:01 PM PDT 24
Finished Aug 12 04:34:10 PM PDT 24
Peak memory 254848 kb
Host smart-3c0e925b-2579-4a22-bea4-01684fda87d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28446
45192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2844645192
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1783005955
Short name T653
Test name
Test status
Simulation time 76494690951 ps
CPU time 1757.44 seconds
Started Aug 12 04:34:06 PM PDT 24
Finished Aug 12 05:03:23 PM PDT 24
Peak memory 305980 kb
Host smart-68065573-8361-4e3b-bd9e-78265cbc911e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783005955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1783005955
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2896554357
Short name T216
Test name
Test status
Simulation time 64834467 ps
CPU time 2.94 seconds
Started Aug 12 04:34:36 PM PDT 24
Finished Aug 12 04:34:39 PM PDT 24
Peak memory 249188 kb
Host smart-67c9d4da-2f33-4dd4-a2fa-232f07ec0148
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2896554357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2896554357
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2241891579
Short name T96
Test name
Test status
Simulation time 45444081695 ps
CPU time 2574.04 seconds
Started Aug 12 04:34:06 PM PDT 24
Finished Aug 12 05:17:00 PM PDT 24
Peak memory 288668 kb
Host smart-56ba401e-bb04-42f9-b10f-32de60bb6ec9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241891579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2241891579
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1010853188
Short name T492
Test name
Test status
Simulation time 385410613 ps
CPU time 11.4 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:34:29 PM PDT 24
Peak memory 249016 kb
Host smart-21fda0c8-d370-44a6-a470-66017c2657a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1010853188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1010853188
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3848841002
Short name T381
Test name
Test status
Simulation time 2221798992 ps
CPU time 18.34 seconds
Started Aug 12 04:34:09 PM PDT 24
Finished Aug 12 04:34:28 PM PDT 24
Peak memory 256356 kb
Host smart-be657790-62be-4935-954c-a1989a0827b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38488
41002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3848841002
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3813599394
Short name T660
Test name
Test status
Simulation time 11538823347 ps
CPU time 56.31 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:35:13 PM PDT 24
Peak memory 256376 kb
Host smart-0afa79c4-6f66-4274-8cd1-bb655c8887c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38135
99394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3813599394
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1925319672
Short name T288
Test name
Test status
Simulation time 9710289885 ps
CPU time 841.83 seconds
Started Aug 12 04:34:32 PM PDT 24
Finished Aug 12 04:48:34 PM PDT 24
Peak memory 273428 kb
Host smart-841baa6e-b414-4f9a-8142-3fe08c30f2d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925319672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1925319672
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3226937317
Short name T311
Test name
Test status
Simulation time 45298867863 ps
CPU time 350.36 seconds
Started Aug 12 04:34:20 PM PDT 24
Finished Aug 12 04:40:11 PM PDT 24
Peak memory 249076 kb
Host smart-da684772-ee36-4951-bde8-5ecf5a0bf0e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226937317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3226937317
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2742401138
Short name T570
Test name
Test status
Simulation time 756318587 ps
CPU time 15.92 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:34:33 PM PDT 24
Peak memory 256440 kb
Host smart-1a0367de-01b2-421c-8b72-de7fc73b120b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27424
01138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2742401138
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.284589391
Short name T505
Test name
Test status
Simulation time 2054937524 ps
CPU time 64.74 seconds
Started Aug 12 04:34:18 PM PDT 24
Finished Aug 12 04:35:23 PM PDT 24
Peak memory 248388 kb
Host smart-0930d768-d6b9-4ac5-bac1-949e54a0486c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28458
9391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.284589391
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3305893117
Short name T533
Test name
Test status
Simulation time 1566789444 ps
CPU time 48.53 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:35:06 PM PDT 24
Peak memory 256108 kb
Host smart-000c1a07-108c-4e5b-b521-af83cc1f3fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33058
93117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3305893117
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2920233082
Short name T295
Test name
Test status
Simulation time 47533170811 ps
CPU time 2709.1 seconds
Started Aug 12 04:34:19 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 289992 kb
Host smart-3d4e1c4a-3366-4597-b099-0b7a0ee6afd0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920233082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2920233082
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3804210761
Short name T208
Test name
Test status
Simulation time 45991216 ps
CPU time 2.49 seconds
Started Aug 12 04:34:17 PM PDT 24
Finished Aug 12 04:34:20 PM PDT 24
Peak memory 249168 kb
Host smart-b836ac11-076c-490c-ad37-8472998ee042
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3804210761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3804210761
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2917272392
Short name T60
Test name
Test status
Simulation time 56968835817 ps
CPU time 1797.12 seconds
Started Aug 12 04:34:15 PM PDT 24
Finished Aug 12 05:04:12 PM PDT 24
Peak memory 273204 kb
Host smart-61e7645b-c1ba-4f40-9138-00d364fd1646
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917272392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2917272392
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3113212684
Short name T233
Test name
Test status
Simulation time 229535946 ps
CPU time 13.44 seconds
Started Aug 12 04:34:35 PM PDT 24
Finished Aug 12 04:34:49 PM PDT 24
Peak memory 248912 kb
Host smart-1f4d5f47-2451-4253-968e-f5a969340827
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3113212684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3113212684
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3646882542
Short name T524
Test name
Test status
Simulation time 16857160913 ps
CPU time 181.02 seconds
Started Aug 12 04:34:22 PM PDT 24
Finished Aug 12 04:37:23 PM PDT 24
Peak memory 251076 kb
Host smart-e71bc48e-9070-4aa2-afca-57514d8b8d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36468
82542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3646882542
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2686326693
Short name T688
Test name
Test status
Simulation time 437645742 ps
CPU time 28.92 seconds
Started Aug 12 04:34:32 PM PDT 24
Finished Aug 12 04:35:01 PM PDT 24
Peak memory 255712 kb
Host smart-36059e2c-af39-4b99-8fa2-afb4de2b6021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863
26693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2686326693
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3977258864
Short name T338
Test name
Test status
Simulation time 53393320020 ps
CPU time 1492.95 seconds
Started Aug 12 04:34:18 PM PDT 24
Finished Aug 12 04:59:11 PM PDT 24
Peak memory 273636 kb
Host smart-23217d29-be02-49f5-b428-d1c1ac86540c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977258864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3977258864
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3259866398
Short name T129
Test name
Test status
Simulation time 135839333664 ps
CPU time 2131.65 seconds
Started Aug 12 04:34:30 PM PDT 24
Finished Aug 12 05:10:02 PM PDT 24
Peak memory 288016 kb
Host smart-43d29e2e-d8d2-4cd2-aa9a-9a0e3622ee63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259866398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3259866398
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1790503060
Short name T618
Test name
Test status
Simulation time 24432310313 ps
CPU time 238.37 seconds
Started Aug 12 04:34:26 PM PDT 24
Finished Aug 12 04:38:24 PM PDT 24
Peak memory 249076 kb
Host smart-493fd64d-bc9d-4281-9157-0a2207b15bef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790503060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1790503060
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2074620877
Short name T447
Test name
Test status
Simulation time 1260695234 ps
CPU time 36.61 seconds
Started Aug 12 04:34:18 PM PDT 24
Finished Aug 12 04:34:55 PM PDT 24
Peak memory 257164 kb
Host smart-15ac942f-c35e-4e37-8579-7385196f7551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
20877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2074620877
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.4058255259
Short name T413
Test name
Test status
Simulation time 2088812775 ps
CPU time 33.01 seconds
Started Aug 12 04:34:20 PM PDT 24
Finished Aug 12 04:34:53 PM PDT 24
Peak memory 256544 kb
Host smart-becbfa48-a034-4921-80a7-f862e216818b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40582
55259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4058255259
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3647696142
Short name T304
Test name
Test status
Simulation time 1715447314 ps
CPU time 54.78 seconds
Started Aug 12 04:34:18 PM PDT 24
Finished Aug 12 04:35:13 PM PDT 24
Peak memory 249244 kb
Host smart-056b23b8-7ca1-4392-bc59-0fd75e7a3b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36476
96142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3647696142
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3030446
Short name T45
Test name
Test status
Simulation time 807569930 ps
CPU time 18.23 seconds
Started Aug 12 04:34:23 PM PDT 24
Finished Aug 12 04:34:41 PM PDT 24
Peak memory 256232 kb
Host smart-9c98f57e-2a2f-405b-a6f5-477fea33796e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30304
46 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3030446
Directory /workspace/9.alert_handler_smoke/latest
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