Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	66633	1			T2	1		T3	1		T7	2383
class_i[0x1]	54871	1			T2	1		T7	3		T46	212
class_i[0x2]	49712	1			T2	2		T3	8		T7	3
class_i[0x3]	61170	1			T2	2		T3	10		T86	914

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	60224	1			T2	3		T3	4		T7	607
alert[0x1]	54973	1			T2	1		T3	10		T7	610
alert[0x2]	55747	1			T3	3		T7	675		T4	156
alert[0x3]	61442	1			T2	2		T3	2		T7	497

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

232107

1

T3

14

T7

2389

T4

213

esc_ping_fail

279

1

T2

6

T3

5

T16

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	60144	1			T3	3		T7	607		T4	18
esc_integrity_fail	alert[0x1]	54896	1			T3	8		T7	610		T4	25
esc_integrity_fail	alert[0x2]	55686	1			T3	2		T7	675		T4	156
esc_integrity_fail	alert[0x3]	61381	1			T3	1		T7	497		T4	14
esc_ping_fail	alert[0x0]	80	1			T2	3		T3	1		T16	2
esc_ping_fail	alert[0x1]	77	1			T2	1		T3	2		T16	3
esc_ping_fail	alert[0x2]	61	1			T3	1		T16	2		T39	3
esc_ping_fail	alert[0x3]	61	1			T2	2		T3	1		T16	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	66573	1			T7	2383		T4	213		T5	442
esc_integrity_fail	class_i[0x1]	54802	1			T7	3		T46	212		T86	26
esc_integrity_fail	class_i[0x2]	49637	1			T3	7		T7	3		T86	12
esc_integrity_fail	class_i[0x3]	61095	1			T3	7		T86	914		T32	2
esc_ping_fail	class_i[0x0]	60	1			T2	1		T3	1		T16	5
esc_ping_fail	class_i[0x1]	69	1			T2	1		T16	2		T229	9
esc_ping_fail	class_i[0x2]	75	1			T2	2		T3	1		T39	7
esc_ping_fail	class_i[0x3]	75	1			T2	2		T3	3		T16	2