Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	170	1			T7	1		T13	3		T5	1
index[0x1]	143	1			T12	1		T4	3		T26	1
index[0x2]	188	1			T2	1		T13	3		T4	1
index[0x3]	176	1			T12	3		T4	1		T5	5

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	236	1			T2	1		T12	4		T13	3
lens_less_than_1000[1]	124	1			T4	1		T15	1		T17	2
lens_less_than_1000[2]	76	1			T69	1		T32	1		T101	2
lens_less_than_1000[3]	68	1			T4	3		T26	1		T49	1
lens_less_than_1000[4]	60	1			T5	6		T20	1		T71	1
lens_less_than_1000[5]	36	1			T7	1		T4	1		T5	1
lens_less_than_1000[6]	33	1			T13	3		T29	1		T75	1
lens_less_than_1000[7]	26	1			T47	1		T70	1		T83	1
lens_less_than_1000[8]	11	1			T20	1		T83	1		T259	1
lens_less_than_1000[9]	3	1			T22	1		T89	1		T112	1
len_2	4	1			T260	1		T252	1		T261	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	62	1			T6	1		T69	1		T101	1
index[0x0]	lens_less_than_1000[1]	31	1			T101	1		T75	2		T76	1
index[0x0]	lens_less_than_1000[2]	23	1			T228	1		T76	1		T31	2
index[0x0]	lens_less_than_1000[3]	16	1			T36	1		T100	1		T262	1
index[0x0]	lens_less_than_1000[4]	10	1			T5	1		T71	1		T76	1
index[0x0]	lens_less_than_1000[5]	6	1			T7	1		T59	2		T263	1
index[0x0]	lens_less_than_1000[6]	12	1			T13	3		T75	1		T264	1
index[0x0]	lens_less_than_1000[7]	8	1			T47	1		T83	1		T265	1
index[0x0]	lens_less_than_1000[8]	1	1			T20	1		-	-		-	-
index[0x0]	len_2	1	1			T252	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	46	1			T12	1		T32	1		T50	1
index[0x1]	lens_less_than_1000[1]	23	1			T266	1		T114	1		T59	2
index[0x1]	lens_less_than_1000[2]	18	1			T50	1		T52	1		T267	1
index[0x1]	lens_less_than_1000[3]	19	1			T4	3		T26	1		T80	1
index[0x1]	lens_less_than_1000[4]	9	1			T87	1		T268	1		T269	1
index[0x1]	lens_less_than_1000[5]	12	1			T5	1		T90	1		T270	1
index[0x1]	lens_less_than_1000[6]	9	1			T58	1		T115	1		T105	1
index[0x1]	lens_less_than_1000[7]	5	1			T25	1		T254	1		T271	2
index[0x1]	lens_less_than_1000[8]	1	1			T272	1		-	-		-	-
index[0x1]	len_2	1	1			T261	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	62	1			T2	1		T13	3		T5	1
index[0x2]	lens_less_than_1000[1]	43	1			T4	1		T15	1		T17	2
index[0x2]	lens_less_than_1000[2]	20	1			T69	1		T222	1		T81	1
index[0x2]	lens_less_than_1000[3]	16	1			T49	1		T90	1		T28	1
index[0x2]	lens_less_than_1000[4]	16	1			T75	1		T31	3		T57	1
index[0x2]	lens_less_than_1000[5]	8	1			T64	1		T36	1		T273	1
index[0x2]	lens_less_than_1000[6]	5	1			T29	1		T274	1		T234	1
index[0x2]	lens_less_than_1000[7]	10	1			T70	1		T275	1		T276	3
index[0x2]	lens_less_than_1000[8]	5	1			T83	1		T259	1		T277	1
index[0x2]	lens_less_than_1000[9]	2	1			T22	1		T89	1		-	-
index[0x2]	len_2	1	1			T260	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	66	1			T12	3		T6	1		T49	1
index[0x3]	lens_less_than_1000[1]	27	1			T77	1		T278	2		T111	1
index[0x3]	lens_less_than_1000[2]	15	1			T32	1		T101	2		T52	1
index[0x3]	lens_less_than_1000[3]	17	1			T68	1		T80	2		T83	1
index[0x3]	lens_less_than_1000[4]	25	1			T5	5		T20	1		T80	1
index[0x3]	lens_less_than_1000[5]	10	1			T4	1		T81	1		T100	1
index[0x3]	lens_less_than_1000[6]	7	1			T59	1		T245	1		T279	1
index[0x3]	lens_less_than_1000[7]	3	1			T280	1		T57	1		T59	1
index[0x3]	lens_less_than_1000[8]	4	1			T95	1		T281	3		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T112	1		-	-		-	-
index[0x3]	len_2	1	1			T282	1		-	-		-	-