Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	70	1			T5	1		T67	1		T50	2
class_index[0x1]	53	1			T23	1		T6	3		T32	2
class_index[0x2]	57	1			T6	2		T32	1		T36	1
class_index[0x3]	45	1			T6	1		T20	1		T36	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	80	1			T23	1		T6	3		T67	1
intr_timeout_cnt[1]	54	1			T6	1		T50	1		T76	1
intr_timeout_cnt[2]	25	1			T6	2		T50	2		T28	1
intr_timeout_cnt[3]	17	1			T20	1		T112	1		T109	1
intr_timeout_cnt[4]	13	1			T36	1		T72	2		T52	1
intr_timeout_cnt[5]	9	1			T80	1		T83	1		T59	3
intr_timeout_cnt[6]	9	1			T5	1		T36	1		T77	1
intr_timeout_cnt[7]	7	1			T32	2		T78	2		T241	1
intr_timeout_cnt[8]	3	1			T242	1		T238	1		T243	1
intr_timeout_cnt[9]	8	1			T32	1		T112	1		T109	2

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	24	1			T67	1		T50	1		T76	1
class_index[0x0]	intr_timeout_cnt[1]	19	1			T79	1		T80	1		T81	1
class_index[0x0]	intr_timeout_cnt[2]	4	1			T50	1		T28	1		T244	1
class_index[0x0]	intr_timeout_cnt[3]	10	1			T109	1		T245	1		T63	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T59	1		T246	1		T247	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T109	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	4	1			T5	1		T93	3		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T78	1		T248	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T63	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	18	1			T23	1		T6	1		T84	1
class_index[0x1]	intr_timeout_cnt[1]	11	1			T80	1		T24	1		T98	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T6	2		T50	1		T81	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T112	1		T249	1		T250	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T251	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	6	1			T80	1		T83	1		T59	3
class_index[0x1]	intr_timeout_cnt[6]	1	1			T63	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T32	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T242	1		T243	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T112	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T6	2		T80	1		T99	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T76	1		T80	1		T52	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T83	1		T252	1		T25	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T63	1		T253	1		T254	1
class_index[0x2]	intr_timeout_cnt[4]	6	1			T36	1		T72	2		T52	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T255	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T77	1		T256	1		T257	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T238	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T32	1		T237	2		-	-
class_index[0x3]	intr_timeout_cnt[0]	17	1			T75	1		T80	1		T81	2
class_index[0x3]	intr_timeout_cnt[1]	10	1			T6	1		T50	1		T80	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T258	2		T246	1		T232	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T20	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T25	1		T257	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T36	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T78	1		T241	1		T84	1
class_index[0x3]	intr_timeout_cnt[9]	3	1			T109	2		T63	1		-	-