Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	294075	1			T1	13		T2	41		T3	25
all_values[1]	294075	1			T1	13		T2	41		T3	25
all_values[2]	294075	1			T1	13		T2	41		T3	25
all_values[3]	294075	1			T1	13		T2	41		T3	25

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

584595

1

T1

22

T11

27

T7

1836

auto[1]

591705

1

T1

30

T2

164

T3

100

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

693364

1

T1

29

T2

144

T3

87

auto[1]

482936

1

T1

23

T2

20

T3

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83582	1			T1	3		T7	219		T12	315
all_values[0]	auto[0]	auto[1]	62079	1			T1	3		T11	2		T7	220
all_values[0]	auto[1]	auto[0]	85854	1			T1	4		T2	40		T3	23
all_values[0]	auto[1]	auto[1]	62560	1			T1	3		T2	1		T3	2
all_values[1]	auto[0]	auto[0]	86337	1			T1	5		T11	1		T7	227
all_values[1]	auto[0]	auto[1]	59798	1			T1	3		T11	9		T7	227
all_values[1]	auto[1]	auto[0]	87640	1			T1	3		T2	38		T3	25
all_values[1]	auto[1]	auto[1]	60300	1			T1	2		T2	3		T11	2
all_values[2]	auto[0]	auto[0]	86177	1			T1	2		T11	2		T7	224
all_values[2]	auto[0]	auto[1]	59960	1			T1	2		T11	5		T7	223
all_values[2]	auto[1]	auto[0]	87708	1			T1	5		T2	37		T3	23
all_values[2]	auto[1]	auto[1]	60230	1			T1	4		T2	4		T3	2
all_values[3]	auto[0]	auto[0]	87556	1			T1	2		T11	1		T7	250
all_values[3]	auto[0]	auto[1]	59106	1			T1	2		T11	7		T7	246
all_values[3]	auto[1]	auto[0]	88510	1			T1	5		T2	29		T3	16
all_values[3]	auto[1]	auto[1]	58903	1			T1	4		T2	12		T3	9