Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	294075	1			T1	13		T2	41		T3	25
all_pins[1]	294075	1			T1	13		T2	41		T3	25
all_pins[2]	294075	1			T1	13		T2	41		T3	25
all_pins[3]	294075	1			T1	13		T2	41		T3	25

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	934307	1			T1	39		T2	144		T3	87
values[0x1]	241993	1			T1	13		T2	20		T3	13
transitions[0x0=>0x1]	158821	1			T1	7		T2	20		T3	12
transitions[0x1=>0x0]	159057	1			T1	7		T2	20		T3	13

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	231515	1			T1	10		T2	40		T3	23
all_pins[0]	values[0x1]	62560	1			T1	3		T2	1		T3	2
all_pins[0]	transitions[0x0=>0x1]	62066	1			T1	3		T2	1		T3	1
all_pins[0]	transitions[0x1=>0x0]	58645	1			T1	4		T2	12		T3	9
all_pins[1]	values[0x0]	233775	1			T1	11		T2	38		T3	25
all_pins[1]	values[0x1]	60300	1			T1	2		T2	3		T11	2
all_pins[1]	transitions[0x0=>0x1]	32415	1			T1	1		T2	3		T7	111
all_pins[1]	transitions[0x1=>0x0]	34675	1			T1	2		T2	1		T3	2
all_pins[2]	values[0x0]	233845	1			T1	9		T2	37		T3	23
all_pins[2]	values[0x1]	60230	1			T1	4		T2	4		T3	2
all_pins[2]	transitions[0x0=>0x1]	32653	1			T1	2		T2	4		T3	2
all_pins[2]	transitions[0x1=>0x0]	32723	1			T2	3		T11	2		T7	94
all_pins[3]	values[0x0]	235172	1			T1	9		T2	29		T3	16
all_pins[3]	values[0x1]	58903	1			T1	4		T2	12		T3	9
all_pins[3]	transitions[0x0=>0x1]	31687	1			T1	1		T2	12		T3	9
all_pins[3]	transitions[0x1=>0x0]	33014	1			T1	1		T2	4		T3	2