Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	82578	1			T7	596		T12	430		T13	965
accum_cnt_1000	173381	1			T7	671		T12	401		T13	1746
accum_cnt_100	17791	1			T7	38		T12	24		T13	95
accum_cnt_50	53021	1			T1	2		T7	34		T12	17
accum_cnt_10	166750	1			T1	22		T2	27		T11	4
accum_cnt_0	342537	1			T1	16		T2	93		T3	80

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	217739	1			T1	10		T2	30		T3	20
class_index[0x1]	217739	1			T1	10		T2	30		T3	20
class_index[0x2]	217739	1			T1	10		T2	30		T3	20
class_index[0x3]	217739	1			T1	10		T2	30		T3	20

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20112	1			T7	232		T13	349		T228	564
class_index[0x0]	accum_cnt_1000	43911	1			T7	223		T13	563		T4	22
class_index[0x0]	accum_cnt_100	4781	1			T7	13		T13	30		T29	11
class_index[0x0]	accum_cnt_50	13634	1			T7	9		T13	22		T15	3
class_index[0x0]	accum_cnt_10	46954	1			T1	10		T11	2		T7	5
class_index[0x0]	accum_cnt_0	78601	1			T2	30		T3	20		T11	19
class_index[0x1]	accum_cnt_2000	20703	1			T7	86		T12	430		T13	225
class_index[0x1]	accum_cnt_1000	41138	1			T7	81		T12	401		T13	660
class_index[0x1]	accum_cnt_100	4216	1			T7	6		T12	24		T13	40
class_index[0x1]	accum_cnt_50	13705	1			T7	7		T12	17		T13	28
class_index[0x1]	accum_cnt_10	32026	1			T1	6		T2	27		T11	2
class_index[0x1]	accum_cnt_0	99498	1			T1	4		T2	3		T3	20
class_index[0x2]	accum_cnt_2000	20659	1			T7	278		T13	391		T20	105
class_index[0x2]	accum_cnt_1000	44206	1			T7	367		T13	523		T17	477
class_index[0x2]	accum_cnt_100	4583	1			T7	19		T13	25		T17	119
class_index[0x2]	accum_cnt_50	11731	1			T1	2		T7	18		T13	26
class_index[0x2]	accum_cnt_10	47869	1			T1	6		T7	3		T13	7
class_index[0x2]	accum_cnt_0	79381	1			T1	2		T2	30		T3	20
class_index[0x3]	accum_cnt_2000	21104	1			T5	157		T65	211		T37	419
class_index[0x3]	accum_cnt_1000	44126	1			T14	944		T5	674		T20	601
class_index[0x3]	accum_cnt_100	4211	1			T14	161		T5	40		T43	9
class_index[0x3]	accum_cnt_50	13951	1			T4	20		T14	127		T26	3
class_index[0x3]	accum_cnt_10	39901	1			T12	890		T13	972		T4	20
class_index[0x3]	accum_cnt_0	85057	1			T1	10		T2	30		T3	20