Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2439	1			T3	1		T16	1		T75	1
alert[0x1]	7376	1			T3	1		T16	1		T72	1
alert[0x2]	2883	1			T16	1		T106	99		T50	95
alert[0x3]	5598	1			T2	1		T16	1		T106	482
alert[0x4]	19377	1			T7	1810		T46	1		T20	3
alert[0x5]	4783	1			T2	1		T3	1		T18	1
alert[0x6]	6554	1			T7	111		T46	3		T229	1
alert[0x7]	4839	1			T5	14		T86	2		T39	1
alert[0x8]	1364	1			T7	73		T75	5		T28	63
alert[0x9]	1606	1			T5	5		T106	53		T50	28
alert[0xa]	4139	1			T66	1		T36	3		T39	1
alert[0xb]	9589	1			T2	1		T4	10		T46	23
alert[0xc]	6270	1			T2	1		T7	201		T75	110
alert[0xd]	4507	1			T39	2		T75	92		T106	198
alert[0xe]	1370	1			T7	153		T20	1		T50	10
alert[0xf]	3016	1			T46	5		T36	1		T75	29
alert[0x10]	5330	1			T3	1		T39	1		T75	342
alert[0x11]	8852	1			T2	1		T32	1		T16	1
alert[0x12]	8323	1			T7	1		T75	4		T106	113
alert[0x13]	6570	1			T37	2		T39	1		T75	130
alert[0x14]	6038	1			T14	1		T5	96		T18	2
alert[0x15]	3178	1			T2	1		T16	1		T39	1
alert[0x16]	7805	1			T7	1346		T75	1		T106	2
alert[0x17]	8515	1			T39	1		T106	11		T286	1
alert[0x18]	10875	1			T3	1		T65	1		T72	29
alert[0x19]	9812	1			T5	42		T75	33		T50	279
alert[0x1a]	3171	1			T7	54		T16	2		T36	3
alert[0x1b]	9523	1			T7	46		T65	1		T75	47
alert[0x1c]	4259	1			T5	3		T39	1		T75	20
alert[0x1d]	8939	1			T7	14		T86	1		T75	6
alert[0x1e]	9481	1			T7	35		T46	1		T39	1
alert[0x1f]	3505	1			T7	153		T39	1		T75	1286
alert[0x20]	4515	1			T286	1		T88	1		T81	17
alert[0x21]	11878	1			T7	313		T50	25		T286	1
alert[0x22]	3417	1			T7	84		T5	25		T86	36
alert[0x23]	7069	1			T86	19		T16	1		T75	26
alert[0x24]	7321	1			T4	1		T16	1		T106	209
alert[0x25]	3356	1			T2	1		T86	2		T16	2
alert[0x26]	3303	1			T7	117		T50	224		T287	1
alert[0x27]	2467	1			T2	1		T7	833		T46	2
alert[0x28]	3134	1			T7	44		T5	213		T88	8
alert[0x29]	1584	1			T5	92		T36	4		T106	111
alert[0x2a]	2551	1			T5	29		T36	3		T72	2
alert[0x2b]	3173	1			T7	498		T39	2		T229	1
alert[0x2c]	5992	1			T2	2		T7	19		T75	94
alert[0x2d]	3590	1			T5	8		T90	204		T28	44
alert[0x2e]	6151	1			T3	1		T5	61		T46	2
alert[0x2f]	3711	1			T7	342		T20	3		T39	2
alert[0x30]	2256	1			T2	1		T90	5		T28	1
alert[0x31]	9193	1			T36	3		T39	1		T72	7
alert[0x32]	4671	1			T75	13		T229	1		T50	670
alert[0x33]	10555	1			T20	20		T72	1		T75	17
alert[0x34]	4742	1			T7	3		T86	13		T106	86
alert[0x35]	3603	1			T7	54		T106	86		T90	6
alert[0x36]	4279	1			T2	1		T7	16		T86	2
alert[0x37]	4788	1			T4	4		T36	1		T39	1
alert[0x38]	5098	1			T7	762		T75	50		T286	1
alert[0x39]	9388	1			T2	1		T7	179		T4	13
alert[0x3a]	4983	1			T2	1		T7	25		T86	4
alert[0x3b]	9656	1			T7	1034		T5	49		T16	1
alert[0x3c]	1259	1			T88	4		T90	2		T222	1
alert[0x3d]	3118	1			T86	1		T16	1		T72	32
alert[0x3e]	4576	1			T3	1		T86	3		T36	1
alert[0x3f]	2642	1			T39	1		T75	53		T90	61
alert[0x40]	8901	1			T72	26		T106	432		T50	3087

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	105474	1			T3	1		T4	13		T14	1
class_i[0x1]	70591	1			T2	2		T7	8320		T4	10
class_i[0x2]	138123	1			T2	2		T20	25		T65	2
class_i[0x3]	52618	1			T2	10		T3	6		T4	5

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

366093

1

T7

8320

T4

28

T5

637

alert_ping_fail

713

1

T2

14

T3

7

T14

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2433	1			T75	1		T76	11		T51	5
alert_integrity_fail	alert[0x1]	7368	1			T72	1		T75	2083		T106	25
alert_integrity_fail	alert[0x2]	2871	1			T106	99		T50	95		T90	25
alert_integrity_fail	alert[0x3]	5587	1			T106	482		T50	453		T51	2
alert_integrity_fail	alert[0x4]	19370	1			T7	1810		T46	1		T20	3
alert_integrity_fail	alert[0x5]	4767	1			T106	9		T50	83		T76	5
alert_integrity_fail	alert[0x6]	6544	1			T7	111		T46	3		T50	197
alert_integrity_fail	alert[0x7]	4826	1			T5	14		T86	2		T75	13
alert_integrity_fail	alert[0x8]	1350	1			T7	73		T75	5		T28	63
alert_integrity_fail	alert[0x9]	1597	1			T5	5		T106	53		T50	28
alert_integrity_fail	alert[0xa]	4125	1			T36	3		T75	14		T106	332
alert_integrity_fail	alert[0xb]	9579	1			T4	10		T46	23		T20	1
alert_integrity_fail	alert[0xc]	6262	1			T7	201		T75	110		T106	3
alert_integrity_fail	alert[0xd]	4498	1			T75	92		T106	198		T78	8
alert_integrity_fail	alert[0xe]	1364	1			T7	153		T20	1		T50	10
alert_integrity_fail	alert[0xf]	3007	1			T46	5		T36	1		T75	29
alert_integrity_fail	alert[0x10]	5318	1			T75	342		T106	20		T90	90
alert_integrity_fail	alert[0x11]	8841	1			T32	1		T75	46		T76	7
alert_integrity_fail	alert[0x12]	8318	1			T7	1		T75	4		T106	113
alert_integrity_fail	alert[0x13]	6558	1			T37	2		T75	130		T106	10
alert_integrity_fail	alert[0x14]	6021	1			T5	96		T75	169		T106	21
alert_integrity_fail	alert[0x15]	3165	1			T75	36		T50	533		T76	2
alert_integrity_fail	alert[0x16]	7790	1			T7	1346		T75	1		T106	2
alert_integrity_fail	alert[0x17]	8507	1			T106	11		T90	43		T78	1
alert_integrity_fail	alert[0x18]	10868	1			T72	29		T75	16		T106	331
alert_integrity_fail	alert[0x19]	9805	1			T5	42		T75	33		T50	279
alert_integrity_fail	alert[0x1a]	3161	1			T7	54		T36	3		T75	6
alert_integrity_fail	alert[0x1b]	9507	1			T7	46		T75	47		T50	94
alert_integrity_fail	alert[0x1c]	4252	1			T5	3		T75	20		T76	3
alert_integrity_fail	alert[0x1d]	8927	1			T7	14		T86	1		T75	6
alert_integrity_fail	alert[0x1e]	9471	1			T7	35		T46	1		T72	1
alert_integrity_fail	alert[0x1f]	3492	1			T7	153		T75	1286		T50	13
alert_integrity_fail	alert[0x20]	4508	1			T88	1		T81	17		T288	8
alert_integrity_fail	alert[0x21]	11873	1			T7	313		T50	25		T51	1
alert_integrity_fail	alert[0x22]	3396	1			T7	84		T5	25		T86	36
alert_integrity_fail	alert[0x23]	7058	1			T86	19		T75	26		T106	25
alert_integrity_fail	alert[0x24]	7309	1			T4	1		T106	209		T50	40
alert_integrity_fail	alert[0x25]	3342	1			T86	2		T106	1892		T50	531
alert_integrity_fail	alert[0x26]	3292	1			T7	117		T50	224		T90	22
alert_integrity_fail	alert[0x27]	2454	1			T7	833		T46	2		T106	37
alert_integrity_fail	alert[0x28]	3124	1			T7	44		T5	213		T88	8
alert_integrity_fail	alert[0x29]	1573	1			T5	92		T36	4		T106	111
alert_integrity_fail	alert[0x2a]	2542	1			T5	29		T36	3		T72	2
alert_integrity_fail	alert[0x2b]	3159	1			T7	498		T50	182		T90	99
alert_integrity_fail	alert[0x2c]	5979	1			T7	19		T75	94		T27	1
alert_integrity_fail	alert[0x2d]	3581	1			T5	8		T90	204		T28	44
alert_integrity_fail	alert[0x2e]	6136	1			T5	61		T46	2		T86	23
alert_integrity_fail	alert[0x2f]	3690	1			T7	342		T20	3		T75	30
alert_integrity_fail	alert[0x30]	2244	1			T90	5		T28	1		T52	28
alert_integrity_fail	alert[0x31]	9180	1			T36	3		T72	7		T75	54
alert_integrity_fail	alert[0x32]	4660	1			T75	13		T50	670		T289	2
alert_integrity_fail	alert[0x33]	10547	1			T20	20		T72	1		T75	17
alert_integrity_fail	alert[0x34]	4732	1			T7	3		T86	13		T106	86
alert_integrity_fail	alert[0x35]	3596	1			T7	54		T106	86		T90	6
alert_integrity_fail	alert[0x36]	4268	1			T7	16		T86	2		T36	11
alert_integrity_fail	alert[0x37]	4775	1			T4	4		T36	1		T75	10
alert_integrity_fail	alert[0x38]	5091	1			T7	762		T75	50		T52	5
alert_integrity_fail	alert[0x39]	9377	1			T7	179		T4	13		T46	3
alert_integrity_fail	alert[0x3a]	4970	1			T7	25		T86	4		T36	1
alert_integrity_fail	alert[0x3b]	9643	1			T7	1034		T5	49		T75	60
alert_integrity_fail	alert[0x3c]	1251	1			T88	4		T90	2		T116	11
alert_integrity_fail	alert[0x3d]	3110	1			T86	1		T72	32		T75	461
alert_integrity_fail	alert[0x3e]	4561	1			T86	3		T36	1		T75	38
alert_integrity_fail	alert[0x3f]	2632	1			T75	53		T90	61		T28	5
alert_integrity_fail	alert[0x40]	8891	1			T72	26		T106	432		T50	3087
alert_ping_fail	alert[0x0]	6	1			T3	1		T16	1		T229	1
alert_ping_fail	alert[0x1]	8	1			T3	1		T16	1		T290	1
alert_ping_fail	alert[0x2]	12	1			T16	1		T30	1		T291	1
alert_ping_fail	alert[0x3]	11	1			T2	1		T16	1		T229	1
alert_ping_fail	alert[0x4]	7	1			T229	1		T292	1		T293	1
alert_ping_fail	alert[0x5]	16	1			T2	1		T3	1		T18	1
alert_ping_fail	alert[0x6]	10	1			T229	1		T221	1		T30	1
alert_ping_fail	alert[0x7]	13	1			T39	1		T221	1		T294	1
alert_ping_fail	alert[0x8]	14	1			T30	1		T284	2		T295	1
alert_ping_fail	alert[0x9]	9	1			T286	1		T221	1		T30	1
alert_ping_fail	alert[0xa]	14	1			T66	1		T39	1		T290	1
alert_ping_fail	alert[0xb]	10	1			T2	1		T229	2		T221	1
alert_ping_fail	alert[0xc]	8	1			T2	1		T30	1		T295	1
alert_ping_fail	alert[0xd]	9	1			T39	2		T291	1		T290	1
alert_ping_fail	alert[0xe]	6	1			T295	1		T296	1		T297	1
alert_ping_fail	alert[0xf]	9	1			T298	2		T100	2		T290	1
alert_ping_fail	alert[0x10]	12	1			T3	1		T39	1		T229	1
alert_ping_fail	alert[0x11]	11	1			T2	1		T16	1		T287	1
alert_ping_fail	alert[0x12]	5	1			T295	1		T290	1		T275	1
alert_ping_fail	alert[0x13]	12	1			T39	1		T298	1		T100	1
alert_ping_fail	alert[0x14]	17	1			T14	1		T18	2		T66	1
alert_ping_fail	alert[0x15]	13	1			T2	1		T16	1		T39	1
alert_ping_fail	alert[0x16]	15	1			T298	1		T299	1		T300	2
alert_ping_fail	alert[0x17]	8	1			T39	1		T286	1		T222	1
alert_ping_fail	alert[0x18]	7	1			T3	1		T65	1		T301	2
alert_ping_fail	alert[0x19]	7	1			T295	1		T293	1		T297	1
alert_ping_fail	alert[0x1a]	10	1			T16	2		T287	1		T100	1
alert_ping_fail	alert[0x1b]	16	1			T65	1		T287	1		T296	2
alert_ping_fail	alert[0x1c]	7	1			T39	1		T292	1		T302	1
alert_ping_fail	alert[0x1d]	12	1			T100	1		T303	1		T300	1
alert_ping_fail	alert[0x1e]	10	1			T39	1		T303	2		T211	1
alert_ping_fail	alert[0x1f]	13	1			T39	1		T304	1		T305	1
alert_ping_fail	alert[0x20]	7	1			T286	1		T30	1		T262	1
alert_ping_fail	alert[0x21]	5	1			T286	1		T306	1		T307	1
alert_ping_fail	alert[0x22]	21	1			T16	1		T229	2		T286	1
alert_ping_fail	alert[0x23]	11	1			T16	1		T30	1		T291	1
alert_ping_fail	alert[0x24]	12	1			T16	1		T298	1		T211	1
alert_ping_fail	alert[0x25]	14	1			T2	1		T16	2		T287	1
alert_ping_fail	alert[0x26]	11	1			T287	1		T298	1		T290	3
alert_ping_fail	alert[0x27]	13	1			T2	1		T286	1		T295	2
alert_ping_fail	alert[0x28]	10	1			T221	1		T300	1		T297	1
alert_ping_fail	alert[0x29]	11	1			T229	1		T300	1		T308	1
alert_ping_fail	alert[0x2a]	9	1			T291	1		T308	2		T275	2
alert_ping_fail	alert[0x2b]	14	1			T39	2		T229	1		T286	1
alert_ping_fail	alert[0x2c]	13	1			T2	2		T286	1		T22	1
alert_ping_fail	alert[0x2d]	9	1			T222	1		T30	1		T309	1
alert_ping_fail	alert[0x2e]	15	1			T3	1		T18	1		T230	2
alert_ping_fail	alert[0x2f]	21	1			T39	2		T40	1		T286	2
alert_ping_fail	alert[0x30]	12	1			T2	1		T30	1		T290	2
alert_ping_fail	alert[0x31]	13	1			T39	1		T229	1		T286	1
alert_ping_fail	alert[0x32]	11	1			T229	1		T221	1		T300	1
alert_ping_fail	alert[0x33]	8	1			T229	1		T222	1		T100	1
alert_ping_fail	alert[0x34]	10	1			T100	2		T300	1		T275	1
alert_ping_fail	alert[0x35]	7	1			T100	1		T300	1		T296	1
alert_ping_fail	alert[0x36]	11	1			T2	1		T16	1		T222	1
alert_ping_fail	alert[0x37]	13	1			T39	1		T229	2		T290	1
alert_ping_fail	alert[0x38]	7	1			T286	1		T292	1		T222	1
alert_ping_fail	alert[0x39]	11	1			T2	1		T229	1		T287	1
alert_ping_fail	alert[0x3a]	13	1			T2	1		T30	1		T262	1
alert_ping_fail	alert[0x3b]	13	1			T16	1		T39	1		T222	1
alert_ping_fail	alert[0x3c]	8	1			T222	1		T303	1		T296	1
alert_ping_fail	alert[0x3d]	8	1			T16	1		T222	1		T100	1
alert_ping_fail	alert[0x3e]	15	1			T3	1		T39	1		T229	1
alert_ping_fail	alert[0x3f]	10	1			T39	1		T30	1		T100	1
alert_ping_fail	alert[0x40]	10	1			T221	2		T30	2		T295	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	105360	1			T4	13		T46	24		T32	1
alert_integrity_fail	class_i[0x1]	70467	1			T7	8320		T4	10		T46	16
alert_integrity_fail	class_i[0x2]	137931	1			T20	25		T36	55		T72	7
alert_integrity_fail	class_i[0x3]	52335	1			T4	5		T5	637		T86	106
alert_ping_fail	class_i[0x0]	114	1			T3	1		T14	1		T18	4
alert_ping_fail	class_i[0x1]	124	1			T2	2		T39	1		T230	2
alert_ping_fail	class_i[0x2]	192	1			T2	2		T65	2		T16	1
alert_ping_fail	class_i[0x3]	283	1			T2	10		T3	6		T66	2