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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 99.99 98.80 97.09 100.00 100.00 99.38 99.56


Total test records in report: 830
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T773 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4051145149 Aug 18 04:27:21 PM PDT 24 Aug 18 04:27:33 PM PDT 24 781053870 ps
T774 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.513297598 Aug 18 04:27:31 PM PDT 24 Aug 18 04:27:41 PM PDT 24 241421689 ps
T775 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3971225484 Aug 18 04:27:17 PM PDT 24 Aug 18 04:35:29 PM PDT 24 17115587892 ps
T135 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3154908645 Aug 18 04:27:21 PM PDT 24 Aug 18 04:28:54 PM PDT 24 1600386787 ps
T776 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3008492648 Aug 18 04:27:19 PM PDT 24 Aug 18 04:27:27 PM PDT 24 1441873976 ps
T777 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2425074190 Aug 18 04:27:29 PM PDT 24 Aug 18 04:27:32 PM PDT 24 34713510 ps
T778 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.901946912 Aug 18 04:27:30 PM PDT 24 Aug 18 04:27:38 PM PDT 24 92401782 ps
T779 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2074573234 Aug 18 04:27:34 PM PDT 24 Aug 18 04:27:36 PM PDT 24 13831321 ps
T147 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.634857297 Aug 18 04:27:19 PM PDT 24 Aug 18 04:32:02 PM PDT 24 24388984344 ps
T780 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.184786124 Aug 18 04:27:33 PM PDT 24 Aug 18 04:27:35 PM PDT 24 6730478 ps
T781 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.664463095 Aug 18 04:27:12 PM PDT 24 Aug 18 04:27:22 PM PDT 24 143117382 ps
T782 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1602492255 Aug 18 04:27:18 PM PDT 24 Aug 18 04:27:24 PM PDT 24 73555122 ps
T783 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2398335224 Aug 18 04:27:19 PM PDT 24 Aug 18 04:27:24 PM PDT 24 61401216 ps
T176 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.4195958524 Aug 18 04:27:17 PM PDT 24 Aug 18 04:28:17 PM PDT 24 3549850181 ps
T784 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3079868773 Aug 18 04:27:49 PM PDT 24 Aug 18 04:27:58 PM PDT 24 252110317 ps
T177 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.105310921 Aug 18 04:27:29 PM PDT 24 Aug 18 04:28:00 PM PDT 24 1841438392 ps
T785 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2039015480 Aug 18 04:27:12 PM PDT 24 Aug 18 04:27:34 PM PDT 24 1696241548 ps
T786 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4188898272 Aug 18 04:27:34 PM PDT 24 Aug 18 04:27:35 PM PDT 24 6158959 ps
T787 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2362939900 Aug 18 04:27:33 PM PDT 24 Aug 18 04:27:35 PM PDT 24 7351101 ps
T141 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.312141656 Aug 18 04:27:14 PM PDT 24 Aug 18 04:32:30 PM PDT 24 4038269538 ps
T788 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1159284379 Aug 18 04:27:14 PM PDT 24 Aug 18 04:35:17 PM PDT 24 35625344530 ps
T151 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1115154097 Aug 18 04:27:51 PM PDT 24 Aug 18 04:35:41 PM PDT 24 7890523041 ps
T789 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2670501402 Aug 18 04:27:37 PM PDT 24 Aug 18 04:27:39 PM PDT 24 7916977 ps
T790 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1776015578 Aug 18 04:27:56 PM PDT 24 Aug 18 04:28:20 PM PDT 24 1473061393 ps
T154 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3222986488 Aug 18 04:27:31 PM PDT 24 Aug 18 04:38:14 PM PDT 24 17502102092 ps
T791 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.362299935 Aug 18 04:27:13 PM PDT 24 Aug 18 04:31:02 PM PDT 24 6543214254 ps
T164 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2434501860 Aug 18 04:27:32 PM PDT 24 Aug 18 04:27:36 PM PDT 24 210476708 ps
T792 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2947008722 Aug 18 04:27:59 PM PDT 24 Aug 18 04:28:01 PM PDT 24 7620840 ps
T793 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1202839788 Aug 18 04:27:28 PM PDT 24 Aug 18 04:27:50 PM PDT 24 1400222791 ps
T794 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2772735022 Aug 18 04:27:24 PM PDT 24 Aug 18 04:27:34 PM PDT 24 584704101 ps
T795 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1792678876 Aug 18 04:27:31 PM PDT 24 Aug 18 04:27:32 PM PDT 24 9543233 ps
T796 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2749831595 Aug 18 04:27:30 PM PDT 24 Aug 18 04:27:32 PM PDT 24 15013502 ps
T797 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1046353388 Aug 18 04:27:32 PM PDT 24 Aug 18 04:27:43 PM PDT 24 603234518 ps
T798 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2389294748 Aug 18 04:27:44 PM PDT 24 Aug 18 04:27:46 PM PDT 24 10164319 ps
T799 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1848331245 Aug 18 04:27:54 PM PDT 24 Aug 18 04:28:21 PM PDT 24 382325435 ps
T800 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2785592545 Aug 18 04:27:50 PM PDT 24 Aug 18 04:27:53 PM PDT 24 75488904 ps
T801 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.845168453 Aug 18 04:27:58 PM PDT 24 Aug 18 04:28:00 PM PDT 24 8064061 ps
T802 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.481352588 Aug 18 04:27:33 PM PDT 24 Aug 18 04:27:35 PM PDT 24 18843514 ps
T144 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1824439798 Aug 18 04:27:51 PM PDT 24 Aug 18 04:38:13 PM PDT 24 4615066722 ps
T803 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.450791123 Aug 18 04:27:30 PM PDT 24 Aug 18 04:27:42 PM PDT 24 107507085 ps
T804 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3169280336 Aug 18 04:27:20 PM PDT 24 Aug 18 04:29:42 PM PDT 24 9263069542 ps
T805 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1289874331 Aug 18 04:27:42 PM PDT 24 Aug 18 04:27:51 PM PDT 24 63925366 ps
T806 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.212684550 Aug 18 04:27:17 PM PDT 24 Aug 18 04:28:02 PM PDT 24 719252579 ps
T181 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2816303190 Aug 18 04:27:19 PM PDT 24 Aug 18 04:27:22 PM PDT 24 35399430 ps
T807 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1750655198 Aug 18 04:27:30 PM PDT 24 Aug 18 04:27:31 PM PDT 24 9767870 ps
T808 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.660227433 Aug 18 04:27:15 PM PDT 24 Aug 18 04:29:51 PM PDT 24 4091998705 ps
T156 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.564763943 Aug 18 04:27:16 PM PDT 24 Aug 18 04:32:40 PM PDT 24 5253039192 ps
T809 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1049877627 Aug 18 04:27:18 PM PDT 24 Aug 18 04:27:31 PM PDT 24 392620290 ps
T810 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.436599285 Aug 18 04:27:16 PM PDT 24 Aug 18 04:27:21 PM PDT 24 44065157 ps
T811 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3464713754 Aug 18 04:27:33 PM PDT 24 Aug 18 04:27:35 PM PDT 24 12064061 ps
T153 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1876307519 Aug 18 04:27:15 PM PDT 24 Aug 18 04:36:49 PM PDT 24 7991139713 ps
T173 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2914468140 Aug 18 04:27:29 PM PDT 24 Aug 18 04:27:34 PM PDT 24 55866346 ps
T163 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1064555643 Aug 18 04:27:47 PM PDT 24 Aug 18 04:28:22 PM PDT 24 304992566 ps
T812 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4140171016 Aug 18 04:27:32 PM PDT 24 Aug 18 04:27:54 PM PDT 24 179502598 ps
T169 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3282534190 Aug 18 04:27:14 PM PDT 24 Aug 18 04:27:16 PM PDT 24 23284920 ps
T150 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3123509347 Aug 18 04:27:30 PM PDT 24 Aug 18 04:38:36 PM PDT 24 8675346657 ps
T813 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2543461583 Aug 18 04:27:32 PM PDT 24 Aug 18 04:27:38 PM PDT 24 324457403 ps
T155 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3590766584 Aug 18 04:27:27 PM PDT 24 Aug 18 04:32:33 PM PDT 24 4270882718 ps
T814 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1602470789 Aug 18 04:27:27 PM PDT 24 Aug 18 04:27:35 PM PDT 24 104076096 ps
T174 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1825729710 Aug 18 04:27:16 PM PDT 24 Aug 18 04:27:37 PM PDT 24 2425821220 ps
T335 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2754097617 Aug 18 04:27:19 PM PDT 24 Aug 18 04:47:09 PM PDT 24 65855862190 ps
T815 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3495977317 Aug 18 04:27:17 PM PDT 24 Aug 18 04:33:34 PM PDT 24 22813666572 ps
T816 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4085240047 Aug 18 04:27:29 PM PDT 24 Aug 18 04:27:36 PM PDT 24 99013457 ps
T817 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3721291240 Aug 18 04:27:19 PM PDT 24 Aug 18 04:27:21 PM PDT 24 11127431 ps
T818 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.731119023 Aug 18 04:27:28 PM PDT 24 Aug 18 04:27:33 PM PDT 24 32618501 ps
T819 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1701439962 Aug 18 04:27:30 PM PDT 24 Aug 18 04:28:06 PM PDT 24 523797382 ps
T820 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2292046210 Aug 18 04:27:15 PM PDT 24 Aug 18 04:27:26 PM PDT 24 114391209 ps
T821 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2878681218 Aug 18 04:27:22 PM PDT 24 Aug 18 04:27:23 PM PDT 24 8097629 ps
T168 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2524115873 Aug 18 04:27:44 PM PDT 24 Aug 18 04:28:29 PM PDT 24 404269254 ps
T822 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1417406088 Aug 18 04:27:32 PM PDT 24 Aug 18 04:28:07 PM PDT 24 3862132904 ps
T823 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3293437681 Aug 18 04:27:30 PM PDT 24 Aug 18 04:27:52 PM PDT 24 659255132 ps
T824 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3086334556 Aug 18 04:27:28 PM PDT 24 Aug 18 04:27:34 PM PDT 24 70098344 ps
T825 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3055505014 Aug 18 04:27:55 PM PDT 24 Aug 18 04:28:03 PM PDT 24 463833244 ps
T826 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.695467183 Aug 18 04:27:19 PM PDT 24 Aug 18 04:27:31 PM PDT 24 1552002206 ps
T143 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3634483879 Aug 18 04:27:30 PM PDT 24 Aug 18 04:29:10 PM PDT 24 4727179650 ps
T827 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2586174851 Aug 18 04:27:33 PM PDT 24 Aug 18 04:27:35 PM PDT 24 8205913 ps
T828 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.378315444 Aug 18 04:27:16 PM PDT 24 Aug 18 04:27:17 PM PDT 24 7315371 ps
T829 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1531601882 Aug 18 04:27:51 PM PDT 24 Aug 18 04:27:57 PM PDT 24 36103788 ps
T830 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4203502275 Aug 18 04:27:12 PM PDT 24 Aug 18 04:27:13 PM PDT 24 26812290 ps
T152 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2534239132 Aug 18 04:27:18 PM PDT 24 Aug 18 04:29:07 PM PDT 24 14263260758 ps

Test location /workspace/coverage/default/35.alert_handler_entropy.2057508536
Short name T7
Test name
Test status
Simulation time 15645443126 ps
CPU time 669.37 seconds
Started Aug 18 04:30:52 PM PDT 24
Finished Aug 18 04:42:01 PM PDT 24
Peak memory 265364 kb
Host smart-5bcb314d-2e96-4640-ab43-1da1b10f1f76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057508536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2057508536
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2129490850
Short name T6
Test name
Test status
Simulation time 10778140978 ps
CPU time 187.33 seconds
Started Aug 18 04:29:55 PM PDT 24
Finished Aug 18 04:33:03 PM PDT 24
Peak memory 265372 kb
Host smart-d4243cf0-97fd-4356-9138-3b7375ab1012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129490850 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2129490850
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3674833518
Short name T8
Test name
Test status
Simulation time 482785212 ps
CPU time 25.92 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:30:25 PM PDT 24
Peak memory 271008 kb
Host smart-15a213d0-ff5b-48d5-bad2-9b67cfa1df37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3674833518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3674833518
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2174216063
Short name T20
Test name
Test status
Simulation time 64121286785 ps
CPU time 2085.66 seconds
Started Aug 18 04:30:30 PM PDT 24
Finished Aug 18 05:05:16 PM PDT 24
Peak memory 273304 kb
Host smart-07a1c8d1-e5fd-4708-9747-e52f79f18a9c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174216063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2174216063
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4056488976
Short name T157
Test name
Test status
Simulation time 295757951 ps
CPU time 43.35 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:28:15 PM PDT 24
Peak memory 240496 kb
Host smart-9594ced2-8fa3-4dd4-b8b6-243a06f7ba50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4056488976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4056488976
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.957129872
Short name T14
Test name
Test status
Simulation time 127237378482 ps
CPU time 1366.61 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 04:53:55 PM PDT 24
Peak memory 289312 kb
Host smart-21c81dc2-7f87-47ae-9195-bdf5004b04bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957129872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.957129872
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1102029112
Short name T75
Test name
Test status
Simulation time 156151321074 ps
CPU time 2673.24 seconds
Started Aug 18 04:30:55 PM PDT 24
Finished Aug 18 05:15:29 PM PDT 24
Peak memory 288712 kb
Host smart-cd54e15f-1c4c-4ec9-a366-22f512f88eeb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102029112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1102029112
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1704924341
Short name T5
Test name
Test status
Simulation time 12504594758 ps
CPU time 1136.31 seconds
Started Aug 18 04:30:13 PM PDT 24
Finished Aug 18 04:49:09 PM PDT 24
Peak memory 289192 kb
Host smart-052005f9-6b8d-4fc7-b151-473c119c9067
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704924341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1704924341
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3283675670
Short name T89
Test name
Test status
Simulation time 15572455036 ps
CPU time 1248.31 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:51:04 PM PDT 24
Peak memory 285912 kb
Host smart-3d88283a-0145-4c60-b2dd-b8244bbae756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283675670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3283675670
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.414042791
Short name T184
Test name
Test status
Simulation time 335928387 ps
CPU time 26.45 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 04:31:35 PM PDT 24
Peak memory 270772 kb
Host smart-cd75716a-7029-4ce3-bedf-c605cf40aec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414042791 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.414042791
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2346359493
Short name T133
Test name
Test status
Simulation time 1962831876 ps
CPU time 210.73 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:30:44 PM PDT 24
Peak memory 265508 kb
Host smart-d709209d-1d57-4cf3-81e7-55fcc756a4b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2346359493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2346359493
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3483764397
Short name T93
Test name
Test status
Simulation time 174622623982 ps
CPU time 1234.52 seconds
Started Aug 18 04:30:33 PM PDT 24
Finished Aug 18 04:51:08 PM PDT 24
Peak memory 265172 kb
Host smart-07c0e65c-4633-4042-87da-d42bb2d06d40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483764397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3483764397
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3827964813
Short name T140
Test name
Test status
Simulation time 4620031946 ps
CPU time 674.51 seconds
Started Aug 18 04:27:28 PM PDT 24
Finished Aug 18 04:38:43 PM PDT 24
Peak memory 265516 kb
Host smart-87f23be6-0894-4e76-bd31-102da04f66a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827964813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3827964813
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1660226873
Short name T226
Test name
Test status
Simulation time 1540317845 ps
CPU time 52.98 seconds
Started Aug 18 04:30:01 PM PDT 24
Finished Aug 18 04:30:54 PM PDT 24
Peak memory 248808 kb
Host smart-580df47f-039f-44cd-b2a6-08473e68ccdd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1660226873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1660226873
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3878107164
Short name T4
Test name
Test status
Simulation time 450501789 ps
CPU time 59.62 seconds
Started Aug 18 04:30:35 PM PDT 24
Finished Aug 18 04:31:35 PM PDT 24
Peak memory 256824 kb
Host smart-703b3393-8c68-4b8d-a51d-28c420ef3ef7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878107164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3878107164
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1950497081
Short name T129
Test name
Test status
Simulation time 4327686512 ps
CPU time 271.92 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:31:49 PM PDT 24
Peak memory 265604 kb
Host smart-9f1d0891-86b4-4076-8a34-f570091b56e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1950497081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1950497081
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1129857534
Short name T136
Test name
Test status
Simulation time 2123281459 ps
CPU time 253.53 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:31:28 PM PDT 24
Peak memory 269720 kb
Host smart-4286742e-6476-4144-94d2-9ae3098a02c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129857534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1129857534
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.576506541
Short name T40
Test name
Test status
Simulation time 28667606516 ps
CPU time 1542.81 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:56:21 PM PDT 24
Peak memory 273292 kb
Host smart-9a63f29e-d57c-495a-884c-f8e000260c97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576506541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.576506541
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3830195844
Short name T2
Test name
Test status
Simulation time 36675577212 ps
CPU time 377.51 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 04:36:20 PM PDT 24
Peak memory 248764 kb
Host smart-d3e2567d-50f3-4363-8257-f81c67b510de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830195844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3830195844
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1891788496
Short name T161
Test name
Test status
Simulation time 7961121 ps
CPU time 1.27 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 236756 kb
Host smart-be0fbbce-c112-4d40-8941-3fc1e48a80a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1891788496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1891788496
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.353069004
Short name T123
Test name
Test status
Simulation time 17568744933 ps
CPU time 661.74 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:38:34 PM PDT 24
Peak memory 265456 kb
Host smart-7139787e-e2ea-430e-80c3-eb1e79dc5b63
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353069004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.353069004
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3860093628
Short name T284
Test name
Test status
Simulation time 70512547545 ps
CPU time 2094.76 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 05:05:41 PM PDT 24
Peak memory 284352 kb
Host smart-01f570e4-de0a-41ff-bf8a-3b77ff44e35f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860093628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3860093628
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3674391710
Short name T39
Test name
Test status
Simulation time 12471143261 ps
CPU time 504.4 seconds
Started Aug 18 04:30:10 PM PDT 24
Finished Aug 18 04:38:34 PM PDT 24
Peak memory 248740 kb
Host smart-9584fee1-a662-4e38-8587-1fbf4d066e73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674391710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3674391710
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.399770387
Short name T120
Test name
Test status
Simulation time 24800863750 ps
CPU time 960.63 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:43:34 PM PDT 24
Peak memory 273528 kb
Host smart-3ece5165-1500-4ad7-a47b-f495e6551a0a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399770387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.399770387
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1817658903
Short name T139
Test name
Test status
Simulation time 6845984928 ps
CPU time 217.35 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:30:55 PM PDT 24
Peak memory 273008 kb
Host smart-b1a001c8-7dfa-4c53-8722-91ab8cc7384f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1817658903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1817658903
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1753079439
Short name T318
Test name
Test status
Simulation time 45209260396 ps
CPU time 2488.66 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 05:12:15 PM PDT 24
Peak memory 288920 kb
Host smart-ae5665f4-9457-4dc5-8d67-2f1d2d9d9c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753079439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1753079439
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2647842805
Short name T59
Test name
Test status
Simulation time 40756631724 ps
CPU time 947.01 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:46:53 PM PDT 24
Peak memory 283156 kb
Host smart-581c7ee4-edf7-410a-84ef-6f1254f1426e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647842805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2647842805
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1711457451
Short name T306
Test name
Test status
Simulation time 26802619078 ps
CPU time 576.19 seconds
Started Aug 18 04:30:28 PM PDT 24
Finished Aug 18 04:40:05 PM PDT 24
Peak memory 255368 kb
Host smart-a4b8b29f-b31e-456d-834f-60355ca23a0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711457451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1711457451
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.930817005
Short name T125
Test name
Test status
Simulation time 4269572544 ps
CPU time 292.99 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:32:07 PM PDT 24
Peak memory 265468 kb
Host smart-b621bcb8-9629-4ff7-921b-451ca2ae45d6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930817005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.930817005
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1786312128
Short name T50
Test name
Test status
Simulation time 211214275149 ps
CPU time 2566.53 seconds
Started Aug 18 04:30:48 PM PDT 24
Finished Aug 18 05:13:35 PM PDT 24
Peak memory 289120 kb
Host smart-118aa967-798b-47d2-b823-b949ac727212
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786312128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1786312128
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2754097617
Short name T335
Test name
Test status
Simulation time 65855862190 ps
CPU time 1184.97 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:47:09 PM PDT 24
Peak memory 273436 kb
Host smart-7336d48c-8115-46c5-ae32-9c0304880488
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754097617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2754097617
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1061038661
Short name T322
Test name
Test status
Simulation time 214816720161 ps
CPU time 1904.33 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 05:02:02 PM PDT 24
Peak memory 273372 kb
Host smart-785bce19-72b8-4645-a057-5b1bac13e2f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061038661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1061038661
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.927814656
Short name T109
Test name
Test status
Simulation time 212278587150 ps
CPU time 3088.87 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 05:21:41 PM PDT 24
Peak memory 289676 kb
Host smart-10d1eee3-88e6-46e7-9e4e-7557aff2850a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927814656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.927814656
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2717467222
Short name T532
Test name
Test status
Simulation time 48488115181 ps
CPU time 455.68 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:38:15 PM PDT 24
Peak memory 248744 kb
Host smart-ce048e93-4e9e-457f-8383-c2f566f29c53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717467222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2717467222
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3518830891
Short name T124
Test name
Test status
Simulation time 1455377512 ps
CPU time 160.84 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:30:13 PM PDT 24
Peak memory 271028 kb
Host smart-670c1cf7-3171-4dbe-9763-35b47053426f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3518830891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3518830891
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2797594004
Short name T22
Test name
Test status
Simulation time 465454360576 ps
CPU time 2307.33 seconds
Started Aug 18 04:30:09 PM PDT 24
Finished Aug 18 05:08:37 PM PDT 24
Peak memory 285616 kb
Host smart-dcc01334-8e86-49a7-8b42-ae0c57cf0961
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797594004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2797594004
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2673287641
Short name T332
Test name
Test status
Simulation time 22734539 ps
CPU time 1.35 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 236712 kb
Host smart-11df5bbc-931b-41a4-a786-66acf697ff73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2673287641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2673287641
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3913375969
Short name T275
Test name
Test status
Simulation time 26090669986 ps
CPU time 552.96 seconds
Started Aug 18 04:31:09 PM PDT 24
Finished Aug 18 04:40:22 PM PDT 24
Peak memory 248840 kb
Host smart-1f123968-9f6e-4d36-a66a-46c1dd7b327b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913375969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3913375969
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.4065271591
Short name T663
Test name
Test status
Simulation time 51524233781 ps
CPU time 509.25 seconds
Started Aug 18 04:30:06 PM PDT 24
Finished Aug 18 04:38:35 PM PDT 24
Peak memory 247564 kb
Host smart-0318ee28-e5d0-4336-ad35-6a8587bfec9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065271591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.4065271591
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2938594195
Short name T257
Test name
Test status
Simulation time 1001358329 ps
CPU time 38.62 seconds
Started Aug 18 04:30:20 PM PDT 24
Finished Aug 18 04:30:58 PM PDT 24
Peak memory 248688 kb
Host smart-6957f611-1ff6-44ab-944d-5769f6de5983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29385
94195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2938594195
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3154898619
Short name T149
Test name
Test status
Simulation time 4278197851 ps
CPU time 339.71 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:32:53 PM PDT 24
Peak memory 265464 kb
Host smart-da55a580-f93c-4224-8a73-02963309d156
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154898619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3154898619
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1682349964
Short name T32
Test name
Test status
Simulation time 1882951839 ps
CPU time 17.36 seconds
Started Aug 18 04:31:31 PM PDT 24
Finished Aug 18 04:31:49 PM PDT 24
Peak memory 254376 kb
Host smart-ed88a1c6-ecc5-4280-a746-956ddea81e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16823
49964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1682349964
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2721007237
Short name T166
Test name
Test status
Simulation time 39503645 ps
CPU time 2.72 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:18 PM PDT 24
Peak memory 237944 kb
Host smart-0c394a3e-4b22-43d7-8d85-4dcf53d7e811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2721007237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2721007237
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2779830005
Short name T252
Test name
Test status
Simulation time 2954260496 ps
CPU time 208.5 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:33:46 PM PDT 24
Peak memory 270432 kb
Host smart-8dfb91c6-a237-406c-a1a6-899374ad898e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779830005 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2779830005
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.634857297
Short name T147
Test name
Test status
Simulation time 24388984344 ps
CPU time 282.67 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:32:02 PM PDT 24
Peak memory 265432 kb
Host smart-4c8e65ab-762a-402b-9bea-9cdb18a4d8d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=634857297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.634857297
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.4249072110
Short name T254
Test name
Test status
Simulation time 198023593814 ps
CPU time 2585.99 seconds
Started Aug 18 04:30:29 PM PDT 24
Finished Aug 18 05:13:35 PM PDT 24
Peak memory 299376 kb
Host smart-bbdf9c8d-ffa0-4d28-aac7-1dc3ae72aa6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249072110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.4249072110
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3637264775
Short name T312
Test name
Test status
Simulation time 11969411724 ps
CPU time 735.76 seconds
Started Aug 18 04:29:57 PM PDT 24
Finished Aug 18 04:42:15 PM PDT 24
Peak memory 272284 kb
Host smart-00904ac6-1b79-4ef4-9149-6aea4d2a0349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637264775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3637264775
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.366525988
Short name T293
Test name
Test status
Simulation time 13490236047 ps
CPU time 296.82 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:35:37 PM PDT 24
Peak memory 255660 kb
Host smart-a7449b42-af7a-47e1-b9d6-08c8eca234a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366525988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.366525988
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.334063220
Short name T115
Test name
Test status
Simulation time 72942323592 ps
CPU time 1586.62 seconds
Started Aug 18 04:31:22 PM PDT 24
Finished Aug 18 04:57:49 PM PDT 24
Peak memory 273232 kb
Host smart-c39f9891-61e3-41fd-a31b-73533e522e16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334063220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.334063220
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3969286682
Short name T112
Test name
Test status
Simulation time 905477996 ps
CPU time 21.9 seconds
Started Aug 18 04:29:53 PM PDT 24
Finished Aug 18 04:30:15 PM PDT 24
Peak memory 255620 kb
Host smart-b307036b-dff7-4aaf-b445-535d6dbe5b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39692
86682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3969286682
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3222986488
Short name T154
Test name
Test status
Simulation time 17502102092 ps
CPU time 642.78 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:38:14 PM PDT 24
Peak memory 265424 kb
Host smart-b0d38b98-1ebf-4b83-8c44-178f90f295b8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222986488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3222986488
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1685970586
Short name T201
Test name
Test status
Simulation time 82316105 ps
CPU time 3.45 seconds
Started Aug 18 04:29:57 PM PDT 24
Finished Aug 18 04:30:01 PM PDT 24
Peak memory 248712 kb
Host smart-bf955be8-64ae-4c7d-bd15-f17d8d9086ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1685970586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1685970586
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.136112919
Short name T209
Test name
Test status
Simulation time 12719750 ps
CPU time 2.21 seconds
Started Aug 18 04:29:40 PM PDT 24
Finished Aug 18 04:29:42 PM PDT 24
Peak memory 248888 kb
Host smart-287a6fa5-6b53-43f8-a39f-c0fb643eb56b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=136112919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.136112919
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.212189277
Short name T200
Test name
Test status
Simulation time 17785049 ps
CPU time 2.75 seconds
Started Aug 18 04:30:07 PM PDT 24
Finished Aug 18 04:30:10 PM PDT 24
Peak memory 249004 kb
Host smart-95f17489-d27c-426a-8f83-07b9853f1a17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=212189277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.212189277
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3034454959
Short name T206
Test name
Test status
Simulation time 73723275 ps
CPU time 3.46 seconds
Started Aug 18 04:30:01 PM PDT 24
Finished Aug 18 04:30:04 PM PDT 24
Peak memory 248896 kb
Host smart-80dde4dd-5b53-4a8f-8bae-030230131c3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3034454959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3034454959
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1399126944
Short name T134
Test name
Test status
Simulation time 4343520076 ps
CPU time 732.77 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:39:26 PM PDT 24
Peak memory 265472 kb
Host smart-3c5a7d3a-5bea-440f-ba5b-7dd57e87c720
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399126944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1399126944
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2362806599
Short name T682
Test name
Test status
Simulation time 80391201308 ps
CPU time 389.6 seconds
Started Aug 18 04:29:52 PM PDT 24
Finished Aug 18 04:36:22 PM PDT 24
Peak memory 247068 kb
Host smart-d968be24-eff0-4a73-9e49-c65ab2b0b5dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362806599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2362806599
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1400489198
Short name T238
Test name
Test status
Simulation time 11788307697 ps
CPU time 207.4 seconds
Started Aug 18 04:30:06 PM PDT 24
Finished Aug 18 04:33:34 PM PDT 24
Peak memory 265228 kb
Host smart-baf92b01-8421-4d46-95c4-93739e3a7932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400489198 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1400489198
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.17966899
Short name T232
Test name
Test status
Simulation time 5511192765 ps
CPU time 85.49 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 04:32:02 PM PDT 24
Peak memory 266492 kb
Host smart-8b13ef2e-709e-4594-81ea-a38c86aa20f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17966899 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.17966899
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.550277027
Short name T78
Test name
Test status
Simulation time 4289464399 ps
CPU time 47.63 seconds
Started Aug 18 04:30:33 PM PDT 24
Finished Aug 18 04:31:21 PM PDT 24
Peak memory 248536 kb
Host smart-e5d00ad7-878a-4c33-a0fa-a3f2dfbf0c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55027
7027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.550277027
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3024983236
Short name T13
Test name
Test status
Simulation time 22510119331 ps
CPU time 1070.64 seconds
Started Aug 18 04:30:23 PM PDT 24
Finished Aug 18 04:48:14 PM PDT 24
Peak memory 272956 kb
Host smart-15c9be1e-6e1c-4445-8519-9f120bf16059
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024983236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3024983236
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3051525883
Short name T494
Test name
Test status
Simulation time 102619890202 ps
CPU time 1019.2 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 04:47:57 PM PDT 24
Peak memory 273164 kb
Host smart-1ded84e5-386e-47e0-a4e1-438ae70d3306
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051525883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3051525883
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1161707010
Short name T63
Test name
Test status
Simulation time 9002376794 ps
CPU time 577.19 seconds
Started Aug 18 04:31:26 PM PDT 24
Finished Aug 18 04:41:04 PM PDT 24
Peak memory 265116 kb
Host smart-da6a3f14-a10a-4419-a738-1243ef63e328
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161707010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1161707010
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2624531940
Short name T327
Test name
Test status
Simulation time 23524778993 ps
CPU time 1454.52 seconds
Started Aug 18 04:31:35 PM PDT 24
Finished Aug 18 04:55:50 PM PDT 24
Peak memory 273256 kb
Host smart-124d714f-6d4c-4dbd-a04d-96cb2fbcf9f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624531940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2624531940
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1906725223
Short name T94
Test name
Test status
Simulation time 14176124585 ps
CPU time 1218.29 seconds
Started Aug 18 04:30:08 PM PDT 24
Finished Aug 18 04:50:26 PM PDT 24
Peak memory 281480 kb
Host smart-c56d5b49-6395-4995-968d-65705332387e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906725223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1906725223
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.105310921
Short name T177
Test name
Test status
Simulation time 1841438392 ps
CPU time 30.59 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:28:00 PM PDT 24
Peak memory 240500 kb
Host smart-f58d590b-b42b-4e45-870b-c0844bcb862d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=105310921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.105310921
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1973968055
Short name T127
Test name
Test status
Simulation time 6389654619 ps
CPU time 188.22 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:30:40 PM PDT 24
Peak memory 273460 kb
Host smart-9c83297e-57dc-4ef9-a531-68791122ccaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1973968055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1973968055
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3684777556
Short name T146
Test name
Test status
Simulation time 9214662823 ps
CPU time 341.25 seconds
Started Aug 18 04:27:20 PM PDT 24
Finished Aug 18 04:33:01 PM PDT 24
Peak memory 265480 kb
Host smart-67b36b75-daf1-42f3-80e5-9b898baf5022
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684777556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3684777556
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2070675038
Short name T426
Test name
Test status
Simulation time 4881706694 ps
CPU time 244.82 seconds
Started Aug 18 04:29:51 PM PDT 24
Finished Aug 18 04:33:56 PM PDT 24
Peak memory 256956 kb
Host smart-3f4d0a32-1a99-4fc8-a474-6fd2e771f8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20706
75038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2070675038
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.4224879240
Short name T281
Test name
Test status
Simulation time 279188789620 ps
CPU time 4233.64 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 05:41:10 PM PDT 24
Peak memory 303792 kb
Host smart-13551e3d-a387-46f1-8e02-97cc517184fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224879240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.4224879240
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.599369819
Short name T277
Test name
Test status
Simulation time 154707979175 ps
CPU time 2419.54 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 05:10:32 PM PDT 24
Peak memory 273492 kb
Host smart-1332a6e4-d1f8-4b6a-b88b-158ce2084a65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599369819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.599369819
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1928970681
Short name T272
Test name
Test status
Simulation time 42453297859 ps
CPU time 1008.27 seconds
Started Aug 18 04:30:32 PM PDT 24
Finished Aug 18 04:47:21 PM PDT 24
Peak memory 273288 kb
Host smart-8c98b684-7174-4b38-930c-22eccd50e40e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928970681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1928970681
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2346716059
Short name T251
Test name
Test status
Simulation time 916864084 ps
CPU time 27.44 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 04:30:49 PM PDT 24
Peak memory 248100 kb
Host smart-bf3c477c-0280-4175-b683-99677f1bfb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23467
16059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2346716059
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.635119158
Short name T261
Test name
Test status
Simulation time 95666307035 ps
CPU time 2677.34 seconds
Started Aug 18 04:30:19 PM PDT 24
Finished Aug 18 05:14:57 PM PDT 24
Peak memory 289736 kb
Host smart-8b4c7b93-739f-4657-acaa-84474023ea58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635119158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.635119158
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2933261475
Short name T242
Test name
Test status
Simulation time 421376066 ps
CPU time 8.25 seconds
Started Aug 18 04:30:49 PM PDT 24
Finished Aug 18 04:30:58 PM PDT 24
Peak memory 249384 kb
Host smart-45ce38b4-2340-47a4-9e6b-16b254b4978c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29332
61475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2933261475
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3983573456
Short name T282
Test name
Test status
Simulation time 2777797572 ps
CPU time 46.25 seconds
Started Aug 18 04:30:59 PM PDT 24
Finished Aug 18 04:31:46 PM PDT 24
Peak memory 256432 kb
Host smart-b1024281-54ec-428c-8791-098a20d868cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39835
73456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3983573456
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.413290522
Short name T36
Test name
Test status
Simulation time 5078182660 ps
CPU time 180.05 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:34:07 PM PDT 24
Peak memory 266224 kb
Host smart-bc56cc91-efb9-4d0c-b3f3-7f87b3b51807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413290522 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.413290522
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2104169712
Short name T260
Test name
Test status
Simulation time 320069943 ps
CPU time 9.51 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:31:17 PM PDT 24
Peak memory 248148 kb
Host smart-fa5af0cb-b958-404b-84fa-01d6c34ba1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21041
69712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2104169712
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.4264711842
Short name T255
Test name
Test status
Simulation time 36403771208 ps
CPU time 1182.6 seconds
Started Aug 18 04:31:14 PM PDT 24
Finished Aug 18 04:50:57 PM PDT 24
Peak memory 287608 kb
Host smart-ea74ca7f-4d40-44c6-a3a8-ea31bbf90682
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264711842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.4264711842
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1064555643
Short name T163
Test name
Test status
Simulation time 304992566 ps
CPU time 34.99 seconds
Started Aug 18 04:27:47 PM PDT 24
Finished Aug 18 04:28:22 PM PDT 24
Peak memory 245852 kb
Host smart-dbc0fc16-f669-4eef-a0c8-3c91072bfb6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1064555643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1064555643
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1693240909
Short name T667
Test name
Test status
Simulation time 217451347873 ps
CPU time 1721.27 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 306164 kb
Host smart-56005c0c-9ee2-4ce1-911f-625d8007aef5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693240909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1693240909
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2524115873
Short name T168
Test name
Test status
Simulation time 404269254 ps
CPU time 44.72 seconds
Started Aug 18 04:27:44 PM PDT 24
Finished Aug 18 04:28:29 PM PDT 24
Peak memory 237704 kb
Host smart-e57910d2-4514-4e6c-9b31-a23911565bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2524115873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2524115873
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2434501860
Short name T164
Test name
Test status
Simulation time 210476708 ps
CPU time 3.5 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:27:36 PM PDT 24
Peak memory 238144 kb
Host smart-070d573d-bd67-4dd8-8bad-2492f1e62fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2434501860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2434501860
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3282534190
Short name T169
Test name
Test status
Simulation time 23284920 ps
CPU time 2.51 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:27:16 PM PDT 24
Peak memory 237808 kb
Host smart-3d8b2c13-266c-4e1e-a616-c3fcdb549580
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3282534190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3282534190
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.312141656
Short name T141
Test name
Test status
Simulation time 4038269538 ps
CPU time 316.03 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:32:30 PM PDT 24
Peak memory 265564 kb
Host smart-4592baef-cbd1-427f-8331-d3965fe70f73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=312141656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.312141656
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1876307519
Short name T153
Test name
Test status
Simulation time 7991139713 ps
CPU time 574.36 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:36:49 PM PDT 24
Peak memory 265524 kb
Host smart-e399c89f-69b7-4f81-91d9-7453be0910e5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876307519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1876307519
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3372633850
Short name T167
Test name
Test status
Simulation time 61281218 ps
CPU time 4.12 seconds
Started Aug 18 04:27:50 PM PDT 24
Finished Aug 18 04:27:54 PM PDT 24
Peak memory 237632 kb
Host smart-92960b31-45f0-4e99-b3eb-ef5220325218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3372633850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3372633850
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1866721718
Short name T159
Test name
Test status
Simulation time 1228526378 ps
CPU time 74.28 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:28:34 PM PDT 24
Peak memory 246472 kb
Host smart-0611d7b0-85d5-4218-8838-bf48cd754002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1866721718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1866721718
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.747619717
Short name T171
Test name
Test status
Simulation time 62162505 ps
CPU time 2.22 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:27:34 PM PDT 24
Peak memory 237852 kb
Host smart-8330b405-85ad-4b04-ad6b-7d21245f5b13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=747619717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.747619717
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3646462676
Short name T165
Test name
Test status
Simulation time 36583339 ps
CPU time 2.22 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:20 PM PDT 24
Peak memory 237936 kb
Host smart-56224ff4-23f6-4bbd-adc3-e86b7c4ce882
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3646462676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3646462676
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3033618766
Short name T172
Test name
Test status
Simulation time 269080220 ps
CPU time 2.53 seconds
Started Aug 18 04:27:20 PM PDT 24
Finished Aug 18 04:27:22 PM PDT 24
Peak memory 237404 kb
Host smart-e363bb35-0fb0-4d68-87e6-f5a3897f691a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3033618766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3033618766
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2816303190
Short name T181
Test name
Test status
Simulation time 35399430 ps
CPU time 2.86 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:22 PM PDT 24
Peak memory 237828 kb
Host smart-6e5be035-017f-429e-9288-fc84d15ebddc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2816303190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2816303190
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.247077690
Short name T170
Test name
Test status
Simulation time 607886723 ps
CPU time 19.77 seconds
Started Aug 18 04:28:01 PM PDT 24
Finished Aug 18 04:28:21 PM PDT 24
Peak memory 237868 kb
Host smart-302031fb-7b6e-4a5f-bd0a-b6696a5ce8cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=247077690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.247077690
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1807828062
Short name T182
Test name
Test status
Simulation time 2231681596 ps
CPU time 67.54 seconds
Started Aug 18 04:27:11 PM PDT 24
Finished Aug 18 04:28:19 PM PDT 24
Peak memory 240500 kb
Host smart-240eff08-f42c-4e00-92f2-2614b2ab874f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1807828062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1807828062
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.4195958524
Short name T176
Test name
Test status
Simulation time 3549850181 ps
CPU time 60 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:28:17 PM PDT 24
Peak memory 240572 kb
Host smart-d4a60f53-bdf8-4815-bd5d-de71a7db3713
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4195958524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.4195958524
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2914468140
Short name T173
Test name
Test status
Simulation time 55866346 ps
CPU time 3.83 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:27:34 PM PDT 24
Peak memory 237568 kb
Host smart-3aa7f080-deca-4490-a00f-148dad8e9d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2914468140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2914468140
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1881280082
Short name T24
Test name
Test status
Simulation time 1449536230 ps
CPU time 195.63 seconds
Started Aug 18 04:31:31 PM PDT 24
Finished Aug 18 04:34:47 PM PDT 24
Peak memory 267484 kb
Host smart-e3694185-49c6-44cb-ab47-1557cf63e4d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881280082 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1881280082
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3149470432
Short name T25
Test name
Test status
Simulation time 28137970885 ps
CPU time 1669.64 seconds
Started Aug 18 04:30:02 PM PDT 24
Finished Aug 18 04:57:51 PM PDT 24
Peak memory 283248 kb
Host smart-8407bbd5-ca56-4d60-b11c-f83b26a6f747
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149470432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3149470432
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.195443184
Short name T759
Test name
Test status
Simulation time 1150225458 ps
CPU time 136.86 seconds
Started Aug 18 04:27:27 PM PDT 24
Finished Aug 18 04:29:44 PM PDT 24
Peak memory 240520 kb
Host smart-5a6ac5a1-ed58-4ca8-821b-4a8b161e86ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=195443184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.195443184
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1159284379
Short name T788
Test name
Test status
Simulation time 35625344530 ps
CPU time 482.3 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:35:17 PM PDT 24
Peak memory 237652 kb
Host smart-5e036d5f-1633-42e8-b933-d822fa16dcd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1159284379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1159284379
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.436599285
Short name T810
Test name
Test status
Simulation time 44065157 ps
CPU time 4.62 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:27:21 PM PDT 24
Peak memory 248724 kb
Host smart-11247777-3491-4f54-8fe6-a55c5d938292
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=436599285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.436599285
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3710072467
Short name T717
Test name
Test status
Simulation time 118432568 ps
CPU time 8.58 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:24 PM PDT 24
Peak memory 252000 kb
Host smart-6b800b94-68a0-4df4-b214-a38e62381f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710072467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3710072467
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2944238887
Short name T768
Test name
Test status
Simulation time 33941800 ps
CPU time 5.35 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:27:19 PM PDT 24
Peak memory 240544 kb
Host smart-1c68fbf3-52af-47b7-81e9-ab51d88603a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2944238887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2944238887
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3793816868
Short name T331
Test name
Test status
Simulation time 7546021 ps
CPU time 1.39 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:27:14 PM PDT 24
Peak memory 235604 kb
Host smart-f3e772d9-d7f9-4278-8ca7-6eea714064c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3793816868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3793816868
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2292046210
Short name T820
Test name
Test status
Simulation time 114391209 ps
CPU time 9.9 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:26 PM PDT 24
Peak memory 240496 kb
Host smart-7cb3ce0d-3d38-4973-8437-45c8e5f07ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2292046210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2292046210
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1046353388
Short name T797
Test name
Test status
Simulation time 603234518 ps
CPU time 10.55 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:27:43 PM PDT 24
Peak memory 254836 kb
Host smart-2e9445b3-fa62-46e0-911b-ed731aac1b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1046353388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1046353388
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.362299935
Short name T791
Test name
Test status
Simulation time 6543214254 ps
CPU time 228.61 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:31:02 PM PDT 24
Peak memory 241888 kb
Host smart-c3cf68ae-6ff1-4cfe-bcdc-a1a0e837f6a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=362299935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.362299935
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3495977317
Short name T815
Test name
Test status
Simulation time 22813666572 ps
CPU time 376.98 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:33:34 PM PDT 24
Peak memory 237652 kb
Host smart-448ba053-7ca4-4018-ab90-c2e8dc0547a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3495977317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3495977317
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2398335224
Short name T783
Test name
Test status
Simulation time 61401216 ps
CPU time 5.02 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:24 PM PDT 24
Peak memory 240476 kb
Host smart-f267ac67-3587-46e0-97d6-4e0d06d0b0ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2398335224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2398335224
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1602492255
Short name T782
Test name
Test status
Simulation time 73555122 ps
CPU time 5.62 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:24 PM PDT 24
Peak memory 240000 kb
Host smart-5b91843f-fb48-45b9-8206-558ce5fe5888
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602492255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1602492255
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3103945190
Short name T186
Test name
Test status
Simulation time 94417199 ps
CPU time 7.84 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:20 PM PDT 24
Peak memory 237576 kb
Host smart-8cc92234-1dd2-4bde-9f68-7355537795d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3103945190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3103945190
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4203502275
Short name T830
Test name
Test status
Simulation time 26812290 ps
CPU time 1.27 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:13 PM PDT 24
Peak memory 236628 kb
Host smart-2c5f2763-51ed-40fc-9e4e-8ee6dc77893b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4203502275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.4203502275
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.212684550
Short name T806
Test name
Test status
Simulation time 719252579 ps
CPU time 45.14 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:28:02 PM PDT 24
Peak memory 245808 kb
Host smart-5ec8a61b-d6f5-4df5-8d07-fe56c83391da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=212684550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.212684550
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1653938364
Short name T719
Test name
Test status
Simulation time 123595559 ps
CPU time 4.44 seconds
Started Aug 18 04:27:09 PM PDT 24
Finished Aug 18 04:27:13 PM PDT 24
Peak memory 249808 kb
Host smart-d57aec40-2b59-424b-b394-193a2405a8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1653938364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1653938364
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1825729710
Short name T174
Test name
Test status
Simulation time 2425821220 ps
CPU time 20.64 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:27:37 PM PDT 24
Peak memory 240608 kb
Host smart-facda9a6-b7e1-40dc-ac21-f48368475d31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1825729710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1825729710
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3662434306
Short name T749
Test name
Test status
Simulation time 63170903 ps
CPU time 4.89 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:27:37 PM PDT 24
Peak memory 240640 kb
Host smart-886efeab-2fa0-4d0e-aeed-e722f18af380
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662434306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3662434306
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2543461583
Short name T813
Test name
Test status
Simulation time 324457403 ps
CPU time 5.06 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:27:38 PM PDT 24
Peak memory 237636 kb
Host smart-afc62239-f491-4781-9487-5bed63622148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2543461583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2543461583
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1792678876
Short name T795
Test name
Test status
Simulation time 9543233 ps
CPU time 1.24 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:27:32 PM PDT 24
Peak memory 235756 kb
Host smart-2a2802d4-46c4-470c-a670-534c7df182b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1792678876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1792678876
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3372768166
Short name T189
Test name
Test status
Simulation time 324630667 ps
CPU time 21.02 seconds
Started Aug 18 04:27:49 PM PDT 24
Finished Aug 18 04:28:10 PM PDT 24
Peak memory 248884 kb
Host smart-718b2275-578e-4cdb-8846-ad2d2ea0b27e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3372768166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3372768166
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3154908645
Short name T135
Test name
Test status
Simulation time 1600386787 ps
CPU time 92.88 seconds
Started Aug 18 04:27:21 PM PDT 24
Finished Aug 18 04:28:54 PM PDT 24
Peak memory 265932 kb
Host smart-b37b90c3-2077-47ec-b7e9-c8979a201b02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3154908645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3154908645
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1388801424
Short name T761
Test name
Test status
Simulation time 261416025 ps
CPU time 17.6 seconds
Started Aug 18 04:27:27 PM PDT 24
Finished Aug 18 04:27:45 PM PDT 24
Peak memory 248776 kb
Host smart-dc9d9642-f0fc-40c6-8162-461e10b7a9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1388801424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1388801424
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.695467183
Short name T826
Test name
Test status
Simulation time 1552002206 ps
CPU time 11.71 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:31 PM PDT 24
Peak memory 252524 kb
Host smart-6a60a2ba-ec2b-493e-95d6-832574f6fb60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695467183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.695467183
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1468995280
Short name T178
Test name
Test status
Simulation time 129239101 ps
CPU time 9.21 seconds
Started Aug 18 04:27:27 PM PDT 24
Finished Aug 18 04:27:36 PM PDT 24
Peak memory 237520 kb
Host smart-43c9919a-3883-4104-89b0-4ab5fdcf3dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1468995280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1468995280
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2290179417
Short name T758
Test name
Test status
Simulation time 10231994 ps
CPU time 1.32 seconds
Started Aug 18 04:27:21 PM PDT 24
Finished Aug 18 04:27:23 PM PDT 24
Peak memory 237764 kb
Host smart-09f1736c-4880-4e3b-bdfa-742f968620b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2290179417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2290179417
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3984403393
Short name T753
Test name
Test status
Simulation time 1260166761 ps
CPU time 34.86 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:27:51 PM PDT 24
Peak memory 245796 kb
Host smart-f218a328-6103-4fed-a334-251062d21d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3984403393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3984403393
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.645782617
Short name T137
Test name
Test status
Simulation time 3944558821 ps
CPU time 162.72 seconds
Started Aug 18 04:27:35 PM PDT 24
Finished Aug 18 04:30:18 PM PDT 24
Peak memory 266512 kb
Host smart-a4d320e3-5377-4aab-ad37-5a1be98702e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=645782617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.645782617
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1049877627
Short name T809
Test name
Test status
Simulation time 392620290 ps
CPU time 12.82 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:31 PM PDT 24
Peak memory 248804 kb
Host smart-c81da79f-90f2-4e69-8624-5af8023a27d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1049877627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1049877627
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2369621045
Short name T158
Test name
Test status
Simulation time 650969008 ps
CPU time 37.18 seconds
Started Aug 18 04:27:22 PM PDT 24
Finished Aug 18 04:28:00 PM PDT 24
Peak memory 237624 kb
Host smart-29ca11ea-9114-46c9-acff-63f40ad9098c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2369621045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2369621045
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.901946912
Short name T778
Test name
Test status
Simulation time 92401782 ps
CPU time 7.42 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:38 PM PDT 24
Peak memory 240316 kb
Host smart-3aa9a827-d8bf-44bd-a810-3d60db9d1a13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901946912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.901946912
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2969111727
Short name T755
Test name
Test status
Simulation time 118607979 ps
CPU time 3.98 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:37 PM PDT 24
Peak memory 236724 kb
Host smart-4c42d71c-e06b-48dd-831a-73270a25801c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2969111727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2969111727
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1723660826
Short name T160
Test name
Test status
Simulation time 8833279 ps
CPU time 1.47 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:32 PM PDT 24
Peak memory 237608 kb
Host smart-b7c46e10-c7d2-4ab3-9371-bc2dca7d4b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1723660826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1723660826
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1202839788
Short name T793
Test name
Test status
Simulation time 1400222791 ps
CPU time 21.98 seconds
Started Aug 18 04:27:28 PM PDT 24
Finished Aug 18 04:27:50 PM PDT 24
Peak memory 248740 kb
Host smart-de66d808-7a0b-4496-a1b7-9dfbe83a3e9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1202839788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1202839788
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.35935918
Short name T765
Test name
Test status
Simulation time 396214541 ps
CPU time 24.77 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:44 PM PDT 24
Peak memory 247156 kb
Host smart-65b156ba-29ee-40e7-896d-2a6ea8b5beb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=35935918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.35935918
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3115389087
Short name T723
Test name
Test status
Simulation time 95800763 ps
CPU time 6.02 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:27:37 PM PDT 24
Peak memory 248852 kb
Host smart-997c946f-e1e1-420a-8a50-0812ca84f20a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115389087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3115389087
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.338392577
Short name T763
Test name
Test status
Simulation time 246449528 ps
CPU time 5.49 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:24 PM PDT 24
Peak memory 240448 kb
Host smart-4e406bcc-11f2-46b1-aa7e-b29f4721fe3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=338392577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.338392577
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2586174851
Short name T827
Test name
Test status
Simulation time 8205913 ps
CPU time 1.42 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 237636 kb
Host smart-d458f687-8918-40c4-87fb-5e4e8c28b608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2586174851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2586174851
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4140171016
Short name T812
Test name
Test status
Simulation time 179502598 ps
CPU time 21.75 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:27:54 PM PDT 24
Peak memory 245784 kb
Host smart-67444e19-17e2-4bb1-831b-d3568d8729ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4140171016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4140171016
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.564763943
Short name T156
Test name
Test status
Simulation time 5253039192 ps
CPU time 323.09 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:32:40 PM PDT 24
Peak memory 265496 kb
Host smart-e1a48c4e-9662-4b2c-a335-405bed9f7e4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=564763943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.564763943
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.4176028772
Short name T730
Test name
Test status
Simulation time 168617122 ps
CPU time 10.02 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:41 PM PDT 24
Peak memory 248004 kb
Host smart-e3daa34b-1302-4d74-a04b-997f4426117e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4176028772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.4176028772
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2813179873
Short name T175
Test name
Test status
Simulation time 69408798 ps
CPU time 4.34 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 237852 kb
Host smart-1a1edf72-ba1a-49be-865e-78d7e662cf20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2813179873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2813179873
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1602470789
Short name T814
Test name
Test status
Simulation time 104076096 ps
CPU time 7.22 seconds
Started Aug 18 04:27:27 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 240216 kb
Host smart-c3898791-3b23-4245-b212-d2a854867578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602470789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1602470789
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2425074190
Short name T777
Test name
Test status
Simulation time 34713510 ps
CPU time 3.23 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:27:32 PM PDT 24
Peak memory 237540 kb
Host smart-eabfb809-7fab-4898-8b88-f686a2ac7631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2425074190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2425074190
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.213447971
Short name T720
Test name
Test status
Simulation time 17786478 ps
CPU time 1.33 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:27:30 PM PDT 24
Peak memory 237596 kb
Host smart-7ca26f93-58ce-4a6b-841c-9bbf51cbd6bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=213447971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.213447971
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.229885052
Short name T191
Test name
Test status
Simulation time 673387378 ps
CPU time 38.79 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:28:08 PM PDT 24
Peak memory 248740 kb
Host smart-b3b9a0a5-f6a5-4efc-a44d-ac27312a01d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=229885052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.229885052
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1684514744
Short name T709
Test name
Test status
Simulation time 65574316 ps
CPU time 7.94 seconds
Started Aug 18 04:27:25 PM PDT 24
Finished Aug 18 04:27:33 PM PDT 24
Peak memory 248784 kb
Host smart-b314f7f1-4310-4ed0-ab65-8106ce97c418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1684514744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1684514744
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4085240047
Short name T816
Test name
Test status
Simulation time 99013457 ps
CPU time 7.07 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:27:36 PM PDT 24
Peak memory 253224 kb
Host smart-f90ed5e8-d2f1-46f8-bc84-e2f1289afb8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085240047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.4085240047
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1531601882
Short name T829
Test name
Test status
Simulation time 36103788 ps
CPU time 5.4 seconds
Started Aug 18 04:27:51 PM PDT 24
Finished Aug 18 04:27:57 PM PDT 24
Peak memory 237588 kb
Host smart-a9c5a821-f16f-442f-93b3-5bdb525aea82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1531601882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1531601882
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1566700929
Short name T752
Test name
Test status
Simulation time 9600809 ps
CPU time 1.33 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:17 PM PDT 24
Peak memory 235716 kb
Host smart-05a4674a-3eb4-4636-aad4-af6cb3577889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1566700929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1566700929
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.450791123
Short name T803
Test name
Test status
Simulation time 107507085 ps
CPU time 12.04 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:42 PM PDT 24
Peak memory 245748 kb
Host smart-b589484a-0ae9-4bba-bd32-2365f3a120d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=450791123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.450791123
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2776746082
Short name T118
Test name
Test status
Simulation time 1821470193 ps
CPU time 208.96 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:30:48 PM PDT 24
Peak memory 272684 kb
Host smart-a7d94869-7eac-4535-8dd8-663e1b4fbcc4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2776746082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2776746082
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3123509347
Short name T150
Test name
Test status
Simulation time 8675346657 ps
CPU time 665.19 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:38:36 PM PDT 24
Peak memory 273052 kb
Host smart-cfb78702-f540-40f0-9da2-efda3b53186e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123509347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3123509347
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.829178520
Short name T732
Test name
Test status
Simulation time 399531857 ps
CPU time 7.17 seconds
Started Aug 18 04:27:21 PM PDT 24
Finished Aug 18 04:27:29 PM PDT 24
Peak memory 249036 kb
Host smart-845ed2e9-2563-4989-ad88-6544121f9127
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=829178520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.829178520
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.37020510
Short name T766
Test name
Test status
Simulation time 581331042 ps
CPU time 13.94 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:27:31 PM PDT 24
Peak memory 252596 kb
Host smart-243899a2-b128-47fd-9446-a5cfa59da9bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37020510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.alert_handler_csr_mem_rw_with_rand_reset.37020510
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1443691383
Short name T731
Test name
Test status
Simulation time 92704454 ps
CPU time 4.34 seconds
Started Aug 18 04:27:21 PM PDT 24
Finished Aug 18 04:27:26 PM PDT 24
Peak memory 240500 kb
Host smart-4fed9e1d-5c92-4c9a-9aae-c768ac958916
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1443691383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1443691383
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3942142788
Short name T333
Test name
Test status
Simulation time 10784913 ps
CPU time 1.33 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:31 PM PDT 24
Peak memory 236592 kb
Host smart-421f2a71-ef7a-4c9b-b700-2532a7d02bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3942142788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3942142788
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3293437681
Short name T823
Test name
Test status
Simulation time 659255132 ps
CPU time 22.49 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:52 PM PDT 24
Peak memory 245776 kb
Host smart-0407509d-15d0-467a-8ede-d025d5041019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3293437681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3293437681
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1839877600
Short name T132
Test name
Test status
Simulation time 804259247 ps
CPU time 89.75 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:29:00 PM PDT 24
Peak memory 268836 kb
Host smart-a473d6d2-c3e4-4908-9942-09dc9a0e5ae3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1839877600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1839877600
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4127323443
Short name T145
Test name
Test status
Simulation time 10987223745 ps
CPU time 480.66 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:35:30 PM PDT 24
Peak memory 265504 kb
Host smart-8b13aa49-a30c-4fe1-b64b-0c05c2d8e94e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127323443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4127323443
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2232575140
Short name T712
Test name
Test status
Simulation time 106736091 ps
CPU time 6.88 seconds
Started Aug 18 04:27:28 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 251880 kb
Host smart-97363b8a-018b-4f74-8afe-01a6dcd4e028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2232575140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2232575140
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2614689319
Short name T726
Test name
Test status
Simulation time 223501914 ps
CPU time 8.73 seconds
Started Aug 18 04:27:49 PM PDT 24
Finished Aug 18 04:27:58 PM PDT 24
Peak memory 256576 kb
Host smart-91ae5c76-c756-4232-aaf3-9f1bd3c1f302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614689319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2614689319
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1191115750
Short name T740
Test name
Test status
Simulation time 128078506 ps
CPU time 4.99 seconds
Started Aug 18 04:27:44 PM PDT 24
Finished Aug 18 04:27:49 PM PDT 24
Peak memory 236704 kb
Host smart-7c31bf20-1ee7-4d5d-9da6-0063fca706e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1191115750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1191115750
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2389294748
Short name T798
Test name
Test status
Simulation time 10164319 ps
CPU time 1.53 seconds
Started Aug 18 04:27:44 PM PDT 24
Finished Aug 18 04:27:46 PM PDT 24
Peak memory 237644 kb
Host smart-b98f7c6c-3839-4b2d-b0b9-db787590b503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2389294748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2389294748
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1943474877
Short name T772
Test name
Test status
Simulation time 272178499 ps
CPU time 16.51 seconds
Started Aug 18 04:27:57 PM PDT 24
Finished Aug 18 04:28:13 PM PDT 24
Peak memory 244932 kb
Host smart-5b4ae479-59c6-45ed-9b11-02035d4fa5dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1943474877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1943474877
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3440518989
Short name T142
Test name
Test status
Simulation time 3183991062 ps
CPU time 96.15 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:28:55 PM PDT 24
Peak memory 265508 kb
Host smart-60fc5a64-2aa0-46c4-8822-c11e95e2dd7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3440518989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3440518989
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2028828344
Short name T122
Test name
Test status
Simulation time 9047717103 ps
CPU time 300.2 seconds
Started Aug 18 04:27:23 PM PDT 24
Finished Aug 18 04:32:24 PM PDT 24
Peak memory 265452 kb
Host smart-25f19e44-7705-4ac1-bfa7-bf525cb4cb70
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028828344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2028828344
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.710792393
Short name T708
Test name
Test status
Simulation time 321860837 ps
CPU time 11.04 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:27:42 PM PDT 24
Peak memory 248548 kb
Host smart-6a3a44a2-c4ec-4866-8336-d0a769283f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=710792393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.710792393
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3079868773
Short name T784
Test name
Test status
Simulation time 252110317 ps
CPU time 8.7 seconds
Started Aug 18 04:27:49 PM PDT 24
Finished Aug 18 04:27:58 PM PDT 24
Peak memory 239788 kb
Host smart-13de0173-4cbf-4653-bc4c-46ede53946d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079868773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3079868773
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2785592545
Short name T800
Test name
Test status
Simulation time 75488904 ps
CPU time 2.98 seconds
Started Aug 18 04:27:50 PM PDT 24
Finished Aug 18 04:27:53 PM PDT 24
Peak memory 236752 kb
Host smart-786454c4-0f76-4bba-88d2-af3d68d35a40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2785592545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2785592545
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2947008722
Short name T792
Test name
Test status
Simulation time 7620840 ps
CPU time 1.26 seconds
Started Aug 18 04:27:59 PM PDT 24
Finished Aug 18 04:28:01 PM PDT 24
Peak memory 236740 kb
Host smart-723aaa9e-93a5-4aa2-b0e1-065b8c7b593a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2947008722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2947008722
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1776015578
Short name T790
Test name
Test status
Simulation time 1473061393 ps
CPU time 23.8 seconds
Started Aug 18 04:27:56 PM PDT 24
Finished Aug 18 04:28:20 PM PDT 24
Peak memory 245876 kb
Host smart-0ed92b54-0870-4c41-816b-5f41161f4c57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1776015578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1776015578
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2633561083
Short name T131
Test name
Test status
Simulation time 5556965182 ps
CPU time 183.4 seconds
Started Aug 18 04:27:25 PM PDT 24
Finished Aug 18 04:30:34 PM PDT 24
Peak memory 271560 kb
Host smart-630b5192-6759-45b2-8414-e0a0b83a6ba7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2633561083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2633561083
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1115154097
Short name T151
Test name
Test status
Simulation time 7890523041 ps
CPU time 469.56 seconds
Started Aug 18 04:27:51 PM PDT 24
Finished Aug 18 04:35:41 PM PDT 24
Peak memory 265616 kb
Host smart-498dda3e-d833-4f36-a7a6-00104c22d5e3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115154097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1115154097
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3212045804
Short name T725
Test name
Test status
Simulation time 155623704 ps
CPU time 4.58 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:27:37 PM PDT 24
Peak memory 248652 kb
Host smart-59063659-0665-46b0-8f97-91feff78ddb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3212045804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3212045804
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2521657859
Short name T736
Test name
Test status
Simulation time 58749994 ps
CPU time 5.17 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:27:36 PM PDT 24
Peak memory 252500 kb
Host smart-d9114968-beaf-4db6-ac74-ce691d72bfc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521657859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2521657859
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1992970546
Short name T187
Test name
Test status
Simulation time 25183817 ps
CPU time 3.23 seconds
Started Aug 18 04:28:05 PM PDT 24
Finished Aug 18 04:28:08 PM PDT 24
Peak memory 237672 kb
Host smart-b5303fa8-179c-4678-940e-bb33ae0719fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1992970546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1992970546
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3428131707
Short name T714
Test name
Test status
Simulation time 10558671 ps
CPU time 1.55 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:36 PM PDT 24
Peak memory 235648 kb
Host smart-627ef8f5-7743-4461-aa52-ba8791b1537c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3428131707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3428131707
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1848331245
Short name T799
Test name
Test status
Simulation time 382325435 ps
CPU time 26.5 seconds
Started Aug 18 04:27:54 PM PDT 24
Finished Aug 18 04:28:21 PM PDT 24
Peak memory 245944 kb
Host smart-62fba0a9-a021-4ece-b286-75e612f50dc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1848331245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1848331245
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1388189301
Short name T128
Test name
Test status
Simulation time 1570712913 ps
CPU time 84.77 seconds
Started Aug 18 04:28:03 PM PDT 24
Finished Aug 18 04:29:28 PM PDT 24
Peak memory 257040 kb
Host smart-e69e8281-0b03-48f3-a246-4e82df3162e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1388189301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1388189301
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2982897530
Short name T121
Test name
Test status
Simulation time 23926779957 ps
CPU time 599.92 seconds
Started Aug 18 04:27:45 PM PDT 24
Finished Aug 18 04:37:45 PM PDT 24
Peak memory 265544 kb
Host smart-19597445-8a7c-4f84-88ea-bcbe89b75efa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982897530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2982897530
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3055505014
Short name T825
Test name
Test status
Simulation time 463833244 ps
CPU time 8.62 seconds
Started Aug 18 04:27:55 PM PDT 24
Finished Aug 18 04:28:03 PM PDT 24
Peak memory 251940 kb
Host smart-adc08568-5250-49f7-8043-735203628323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3055505014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3055505014
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3169280336
Short name T804
Test name
Test status
Simulation time 9263069542 ps
CPU time 141.81 seconds
Started Aug 18 04:27:20 PM PDT 24
Finished Aug 18 04:29:42 PM PDT 24
Peak memory 237660 kb
Host smart-68c38395-028d-4f95-8aa1-86a599d889ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3169280336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3169280336
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3971225484
Short name T775
Test name
Test status
Simulation time 17115587892 ps
CPU time 491.08 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 237652 kb
Host smart-d615fd8c-74d5-47d9-9c2e-737afcbaa48a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3971225484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3971225484
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3162652684
Short name T185
Test name
Test status
Simulation time 109595187 ps
CPU time 9.52 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:27:25 PM PDT 24
Peak memory 249068 kb
Host smart-6c6a8a28-c749-4ca1-b923-d780d748750b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3162652684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3162652684
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1652217918
Short name T750
Test name
Test status
Simulation time 47279414 ps
CPU time 5.72 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:24 PM PDT 24
Peak memory 240372 kb
Host smart-817d8b09-0d00-4828-8c2f-e7ce3c7ccea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652217918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1652217918
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3751057271
Short name T190
Test name
Test status
Simulation time 305218225 ps
CPU time 7.2 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:27 PM PDT 24
Peak memory 240488 kb
Host smart-4ce81d09-ea24-4e61-bd1e-381f06996707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3751057271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3751057271
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2878681218
Short name T821
Test name
Test status
Simulation time 8097629 ps
CPU time 1.39 seconds
Started Aug 18 04:27:22 PM PDT 24
Finished Aug 18 04:27:23 PM PDT 24
Peak memory 237608 kb
Host smart-02a974e6-6ee0-4a23-a376-216787f91b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2878681218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2878681218
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2039015480
Short name T785
Test name
Test status
Simulation time 1696241548 ps
CPU time 21.47 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:34 PM PDT 24
Peak memory 245768 kb
Host smart-a8148213-08d5-41a2-9f0f-78dd27f8d524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2039015480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2039015480
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3121661375
Short name T737
Test name
Test status
Simulation time 435950283 ps
CPU time 26.43 seconds
Started Aug 18 04:27:22 PM PDT 24
Finished Aug 18 04:27:49 PM PDT 24
Peak memory 248040 kb
Host smart-20416560-176d-4f9d-8fc5-c5af429ec321
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3121661375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3121661375
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3464713754
Short name T811
Test name
Test status
Simulation time 12064061 ps
CPU time 1.3 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 236752 kb
Host smart-e5da4ccc-2df9-4125-8f8a-5de020ac4c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3464713754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3464713754
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1011306443
Short name T724
Test name
Test status
Simulation time 9401561 ps
CPU time 1.53 seconds
Started Aug 18 04:27:54 PM PDT 24
Finished Aug 18 04:27:56 PM PDT 24
Peak memory 237664 kb
Host smart-174dfa50-d144-4ac2-8470-7856a43d425f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1011306443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1011306443
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3367771084
Short name T711
Test name
Test status
Simulation time 14298368 ps
CPU time 1.51 seconds
Started Aug 18 04:27:34 PM PDT 24
Finished Aug 18 04:27:36 PM PDT 24
Peak memory 236652 kb
Host smart-e42ac29e-dc81-468b-be66-e379a7f7524c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3367771084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3367771084
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3737126681
Short name T733
Test name
Test status
Simulation time 14319973 ps
CPU time 1.26 seconds
Started Aug 18 04:28:00 PM PDT 24
Finished Aug 18 04:28:01 PM PDT 24
Peak memory 237520 kb
Host smart-c080efe9-cc32-4020-ae12-e836de5a42bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3737126681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3737126681
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.481352588
Short name T802
Test name
Test status
Simulation time 18843514 ps
CPU time 1.4 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 237584 kb
Host smart-44b98dbf-6332-4762-9641-b9dc28b18401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=481352588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.481352588
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.777161195
Short name T329
Test name
Test status
Simulation time 8847339 ps
CPU time 1.47 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:21 PM PDT 24
Peak memory 236736 kb
Host smart-0ae9dd34-d954-41c1-a80c-bbfd9b31d917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=777161195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.777161195
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1579440963
Short name T713
Test name
Test status
Simulation time 8911842 ps
CPU time 1.25 seconds
Started Aug 18 04:27:22 PM PDT 24
Finished Aug 18 04:27:24 PM PDT 24
Peak memory 236724 kb
Host smart-987b2645-f82e-4c8f-bdf0-66cc4dbc44e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1579440963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1579440963
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.561783443
Short name T330
Test name
Test status
Simulation time 12526467 ps
CPU time 1.41 seconds
Started Aug 18 04:27:48 PM PDT 24
Finished Aug 18 04:27:50 PM PDT 24
Peak memory 237760 kb
Host smart-ff81f4b0-cb98-436c-ab23-83a64c2443c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=561783443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.561783443
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3630805939
Short name T745
Test name
Test status
Simulation time 25220109 ps
CPU time 1.33 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 236776 kb
Host smart-a6664b9e-35fb-425d-afaf-3ab0cac2f889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3630805939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3630805939
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.660227433
Short name T808
Test name
Test status
Simulation time 4091998705 ps
CPU time 155.93 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:29:51 PM PDT 24
Peak memory 241868 kb
Host smart-ed1e6770-3fa3-426a-9c59-90e883aedf14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=660227433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.660227433
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.77789346
Short name T334
Test name
Test status
Simulation time 5710344001 ps
CPU time 378.46 seconds
Started Aug 18 04:27:25 PM PDT 24
Finished Aug 18 04:33:44 PM PDT 24
Peak memory 237560 kb
Host smart-c64c3d9c-6971-45d3-8540-adacacde5e01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=77789346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.77789346
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2624299892
Short name T718
Test name
Test status
Simulation time 23201084 ps
CPU time 3.39 seconds
Started Aug 18 04:27:26 PM PDT 24
Finished Aug 18 04:27:30 PM PDT 24
Peak memory 248756 kb
Host smart-793efabf-a83e-40c2-a017-8caa73b88e2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2624299892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2624299892
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2911198692
Short name T179
Test name
Test status
Simulation time 147036382 ps
CPU time 13.49 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:29 PM PDT 24
Peak memory 252012 kb
Host smart-5a4a98ff-109e-4ceb-8cfe-5ef9de7c4953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911198692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2911198692
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1408117485
Short name T727
Test name
Test status
Simulation time 122766369 ps
CPU time 4.8 seconds
Started Aug 18 04:27:08 PM PDT 24
Finished Aug 18 04:27:13 PM PDT 24
Peak memory 237544 kb
Host smart-d252e94b-0c55-4861-a972-e3f7e30b9382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1408117485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1408117485
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.378315444
Short name T828
Test name
Test status
Simulation time 7315371 ps
CPU time 1.31 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:27:17 PM PDT 24
Peak memory 237600 kb
Host smart-27d5a0f0-4b67-4ebb-83c2-3ca05609e031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=378315444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.378315444
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2482047156
Short name T757
Test name
Test status
Simulation time 372933125 ps
CPU time 11.46 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:27:41 PM PDT 24
Peak memory 244888 kb
Host smart-e6759ae9-d34f-4dcb-bc70-90f03e691f03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2482047156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2482047156
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1824439798
Short name T144
Test name
Test status
Simulation time 4615066722 ps
CPU time 621.77 seconds
Started Aug 18 04:27:51 PM PDT 24
Finished Aug 18 04:38:13 PM PDT 24
Peak memory 265468 kb
Host smart-dc8b1961-b29e-4f47-b574-b23607fb225b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824439798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1824439798
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2409380770
Short name T734
Test name
Test status
Simulation time 348827091 ps
CPU time 21.91 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:40 PM PDT 24
Peak memory 254656 kb
Host smart-f4283567-9c0a-429a-ba16-74259fa53c0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2409380770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2409380770
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.184786124
Short name T780
Test name
Test status
Simulation time 6730478 ps
CPU time 1.45 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 237620 kb
Host smart-624a5437-8a01-4bf1-93a1-e79fd502f003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=184786124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.184786124
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.126017944
Short name T722
Test name
Test status
Simulation time 8704953 ps
CPU time 1.33 seconds
Started Aug 18 04:27:52 PM PDT 24
Finished Aug 18 04:27:53 PM PDT 24
Peak memory 236704 kb
Host smart-aa53634c-5348-4ee6-9bde-b4212208cd97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126017944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.126017944
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4244516648
Short name T760
Test name
Test status
Simulation time 13112343 ps
CPU time 1.6 seconds
Started Aug 18 04:27:42 PM PDT 24
Finished Aug 18 04:27:43 PM PDT 24
Peak memory 235676 kb
Host smart-87d9ff63-b1e7-43fa-99ac-dc038af89cb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4244516648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4244516648
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4188898272
Short name T786
Test name
Test status
Simulation time 6158959 ps
CPU time 1.34 seconds
Started Aug 18 04:27:34 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 237636 kb
Host smart-521a322f-136d-46ac-87f9-1ab7d86689a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4188898272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4188898272
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2074573234
Short name T779
Test name
Test status
Simulation time 13831321 ps
CPU time 1.64 seconds
Started Aug 18 04:27:34 PM PDT 24
Finished Aug 18 04:27:36 PM PDT 24
Peak memory 237648 kb
Host smart-f6cf3691-6ce8-42e6-8717-25e8b0e5dfac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2074573234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2074573234
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.845168453
Short name T801
Test name
Test status
Simulation time 8064061 ps
CPU time 1.51 seconds
Started Aug 18 04:27:58 PM PDT 24
Finished Aug 18 04:28:00 PM PDT 24
Peak memory 237640 kb
Host smart-17967661-d90a-4f3e-b3c5-e78370d32575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=845168453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.845168453
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.633344071
Short name T162
Test name
Test status
Simulation time 8846880 ps
CPU time 1.46 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 235672 kb
Host smart-7a646e9f-554f-44e4-9d00-cf127e5baaa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=633344071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.633344071
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3287965112
Short name T764
Test name
Test status
Simulation time 20505690 ps
CPU time 1.98 seconds
Started Aug 18 04:27:50 PM PDT 24
Finished Aug 18 04:27:52 PM PDT 24
Peak memory 237664 kb
Host smart-d76e7bf2-0749-4440-9005-aa056c063dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3287965112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3287965112
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.8790535
Short name T751
Test name
Test status
Simulation time 8900461 ps
CPU time 1.56 seconds
Started Aug 18 04:28:03 PM PDT 24
Finished Aug 18 04:28:05 PM PDT 24
Peak memory 237680 kb
Host smart-3e1d1ab3-1211-41d2-af3b-2dab7d9b364a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=8790535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.8790535
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3827504377
Short name T729
Test name
Test status
Simulation time 7940091 ps
CPU time 1.49 seconds
Started Aug 18 04:27:53 PM PDT 24
Finished Aug 18 04:27:54 PM PDT 24
Peak memory 237648 kb
Host smart-82263c8b-d510-4745-8b3b-74fdf9315a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3827504377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3827504377
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1346676032
Short name T742
Test name
Test status
Simulation time 1709297534 ps
CPU time 110.25 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:29:09 PM PDT 24
Peak memory 240540 kb
Host smart-cef9c408-83b8-4f93-829c-d32657e8a19e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1346676032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1346676032
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2710507778
Short name T754
Test name
Test status
Simulation time 5723820939 ps
CPU time 184.05 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:30:34 PM PDT 24
Peak memory 240556 kb
Host smart-1d6a65ff-e5f8-4874-8bb4-1b09fdc3f540
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2710507778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2710507778
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2772735022
Short name T794
Test name
Test status
Simulation time 584704101 ps
CPU time 10.01 seconds
Started Aug 18 04:27:24 PM PDT 24
Finished Aug 18 04:27:34 PM PDT 24
Peak memory 249080 kb
Host smart-46ee1f37-24e1-4842-908f-2f28eec0be4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2772735022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2772735022
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2018386665
Short name T192
Test name
Test status
Simulation time 589189928 ps
CPU time 11.89 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:42 PM PDT 24
Peak memory 243404 kb
Host smart-47ed47b6-b246-42fe-bb29-8a537b9a1bb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018386665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2018386665
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1952246992
Short name T188
Test name
Test status
Simulation time 23263455 ps
CPU time 3.49 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:27 PM PDT 24
Peak memory 240544 kb
Host smart-470457a7-4102-467f-808a-e7a569fc4fc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1952246992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1952246992
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.955304030
Short name T738
Test name
Test status
Simulation time 14444422 ps
CPU time 1.28 seconds
Started Aug 18 04:27:09 PM PDT 24
Finished Aug 18 04:27:11 PM PDT 24
Peak memory 237544 kb
Host smart-ab36aae8-df36-4086-adea-6e32e2524bc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=955304030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.955304030
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1501495388
Short name T739
Test name
Test status
Simulation time 87225177 ps
CPU time 11.9 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:30 PM PDT 24
Peak memory 245736 kb
Host smart-b30c0202-a447-4d5b-9f21-4ad3d6ec1e19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1501495388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1501495388
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3588883619
Short name T138
Test name
Test status
Simulation time 1723175862 ps
CPU time 99.88 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:28:58 PM PDT 24
Peak memory 265436 kb
Host smart-aa4b30d0-0af3-47ea-9817-2d5127bc325e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3588883619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3588883619
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.469953876
Short name T741
Test name
Test status
Simulation time 152759063 ps
CPU time 9.92 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:27:24 PM PDT 24
Peak memory 248672 kb
Host smart-6ad4e4a6-fb9a-4922-9eca-c7b0692294f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=469953876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.469953876
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3777246697
Short name T747
Test name
Test status
Simulation time 9104523 ps
CPU time 1.49 seconds
Started Aug 18 04:27:54 PM PDT 24
Finished Aug 18 04:27:56 PM PDT 24
Peak memory 237644 kb
Host smart-ac9642c7-6603-44b1-bae2-ec8fe767702e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3777246697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3777246697
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3270426548
Short name T744
Test name
Test status
Simulation time 10941600 ps
CPU time 1.3 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:27:34 PM PDT 24
Peak memory 236708 kb
Host smart-3192fdab-e259-435e-a2c0-aa494abf1ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3270426548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3270426548
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.72048120
Short name T767
Test name
Test status
Simulation time 30217338 ps
CPU time 1.38 seconds
Started Aug 18 04:27:38 PM PDT 24
Finished Aug 18 04:27:40 PM PDT 24
Peak memory 236656 kb
Host smart-367f99c0-2751-42ff-be55-7a1ef403e19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=72048120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.72048120
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2749831595
Short name T796
Test name
Test status
Simulation time 15013502 ps
CPU time 1.27 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:32 PM PDT 24
Peak memory 237604 kb
Host smart-ff2e8259-b04d-48f8-a54e-1ea4c3323a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2749831595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2749831595
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.487646664
Short name T771
Test name
Test status
Simulation time 16347576 ps
CPU time 1.23 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 236624 kb
Host smart-3c958a4d-4694-4422-9a6c-0f9995822114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=487646664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.487646664
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2878276265
Short name T328
Test name
Test status
Simulation time 9440363 ps
CPU time 1.45 seconds
Started Aug 18 04:27:53 PM PDT 24
Finished Aug 18 04:27:54 PM PDT 24
Peak memory 235656 kb
Host smart-4f01676b-1df5-4a10-8c1c-5805be628081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2878276265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2878276265
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1323438169
Short name T225
Test name
Test status
Simulation time 10278238 ps
CPU time 1.52 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:27:43 PM PDT 24
Peak memory 236672 kb
Host smart-81cbfc15-cc53-47d0-b0b0-045da3bbc9b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1323438169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1323438169
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2678515044
Short name T710
Test name
Test status
Simulation time 11958690 ps
CPU time 1.43 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:27:33 PM PDT 24
Peak memory 237552 kb
Host smart-1e9c8a4b-9137-45f4-be86-a43394de2be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2678515044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2678515044
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2362939900
Short name T787
Test name
Test status
Simulation time 7351101 ps
CPU time 1.43 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 235700 kb
Host smart-8c474105-0f93-4ca6-9ea0-76db4cb3e27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2362939900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2362939900
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2201929013
Short name T716
Test name
Test status
Simulation time 681660983 ps
CPU time 11.25 seconds
Started Aug 18 04:27:34 PM PDT 24
Finished Aug 18 04:27:45 PM PDT 24
Peak memory 252756 kb
Host smart-36af32d8-1b72-4dd9-b8b6-1c4610e36217
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201929013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2201929013
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3537817418
Short name T769
Test name
Test status
Simulation time 62354820 ps
CPU time 4.51 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:27:21 PM PDT 24
Peak memory 236704 kb
Host smart-35f5ec4c-6548-47c8-a9e7-9373d3642620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3537817418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3537817418
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3164800748
Short name T743
Test name
Test status
Simulation time 9164755 ps
CPU time 1.51 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:17 PM PDT 24
Peak memory 237740 kb
Host smart-3d2463b8-6c1c-4ac0-8e8f-e6a6be352f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3164800748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3164800748
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1993211189
Short name T748
Test name
Test status
Simulation time 87694277 ps
CPU time 10.98 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:27:27 PM PDT 24
Peak memory 245916 kb
Host smart-7b06e520-96fc-459b-88aa-01cafca607b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1993211189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1993211189
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2534239132
Short name T152
Test name
Test status
Simulation time 14263260758 ps
CPU time 108.77 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:29:07 PM PDT 24
Peak memory 265628 kb
Host smart-43b8d2a6-9442-4c74-8ebb-e6e3eb8776b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2534239132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2534239132
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.4147369017
Short name T148
Test name
Test status
Simulation time 8579318663 ps
CPU time 529.16 seconds
Started Aug 18 04:27:22 PM PDT 24
Finished Aug 18 04:36:11 PM PDT 24
Peak memory 265488 kb
Host smart-2a750878-4be1-4612-a14f-f915c0933af8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147369017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.4147369017
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.664463095
Short name T781
Test name
Test status
Simulation time 143117382 ps
CPU time 9.58 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:22 PM PDT 24
Peak memory 255928 kb
Host smart-ab9c559f-ac2e-4085-b860-f7c70a875c15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=664463095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.664463095
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1289874331
Short name T805
Test name
Test status
Simulation time 63925366 ps
CPU time 9.49 seconds
Started Aug 18 04:27:42 PM PDT 24
Finished Aug 18 04:27:51 PM PDT 24
Peak memory 254836 kb
Host smart-ff8d05a8-6696-4445-8798-2165f2e68862
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289874331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1289874331
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.731119023
Short name T818
Test name
Test status
Simulation time 32618501 ps
CPU time 4.9 seconds
Started Aug 18 04:27:28 PM PDT 24
Finished Aug 18 04:27:33 PM PDT 24
Peak memory 237552 kb
Host smart-8d53f391-5ce0-4801-9693-880021cb5871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=731119023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.731119023
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3721291240
Short name T817
Test name
Test status
Simulation time 11127431 ps
CPU time 1.42 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:21 PM PDT 24
Peak memory 237528 kb
Host smart-086ac35d-cfd0-42ee-9e06-1493e69418c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3721291240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3721291240
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1701439962
Short name T819
Test name
Test status
Simulation time 523797382 ps
CPU time 35.82 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:28:06 PM PDT 24
Peak memory 244888 kb
Host smart-f264fe01-777e-48b2-8062-9c1a0a33dec8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1701439962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1701439962
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3730059528
Short name T126
Test name
Test status
Simulation time 25628822841 ps
CPU time 352.37 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:33:08 PM PDT 24
Peak memory 271496 kb
Host smart-37f5b38b-5be1-4349-bcc1-7704112bbea3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730059528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3730059528
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.505088656
Short name T735
Test name
Test status
Simulation time 568537549 ps
CPU time 17.43 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:27:47 PM PDT 24
Peak memory 248688 kb
Host smart-1682de85-1ec2-45ed-975f-34c9febdef5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=505088656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.505088656
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.263322213
Short name T721
Test name
Test status
Simulation time 151370163 ps
CPU time 11.42 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:27:41 PM PDT 24
Peak memory 251788 kb
Host smart-6afbfde6-11d8-4e2a-9fdc-a3f674a0d434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263322213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.263322213
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2273644436
Short name T180
Test name
Test status
Simulation time 371717826 ps
CPU time 7.71 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:27:37 PM PDT 24
Peak memory 237548 kb
Host smart-e2d88eab-0708-41d0-8315-4867fef621a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2273644436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2273644436
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1750655198
Short name T807
Test name
Test status
Simulation time 9767870 ps
CPU time 1.2 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:27:31 PM PDT 24
Peak memory 236684 kb
Host smart-45fec1b5-76ca-41ac-9512-27a80a6d165e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1750655198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1750655198
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4051145149
Short name T773
Test name
Test status
Simulation time 781053870 ps
CPU time 11.37 seconds
Started Aug 18 04:27:21 PM PDT 24
Finished Aug 18 04:27:33 PM PDT 24
Peak memory 240664 kb
Host smart-5723ce6c-cd24-4a2f-8e08-e6aa56fc55f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4051145149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.4051145149
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2823028961
Short name T130
Test name
Test status
Simulation time 2275093446 ps
CPU time 170.11 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:30:20 PM PDT 24
Peak memory 265652 kb
Host smart-0dbcdbcb-55f7-4aa8-a520-61c70024141c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2823028961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2823028961
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2674660373
Short name T770
Test name
Test status
Simulation time 170469594 ps
CPU time 10.89 seconds
Started Aug 18 04:27:22 PM PDT 24
Finished Aug 18 04:27:33 PM PDT 24
Peak memory 254672 kb
Host smart-c8e0fa1c-752d-4a51-949d-1ddd9024d84f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2674660373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2674660373
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.513297598
Short name T774
Test name
Test status
Simulation time 241421689 ps
CPU time 9.95 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:27:41 PM PDT 24
Peak memory 244236 kb
Host smart-90874801-8e57-42ed-9529-352d2f5f0a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513297598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.513297598
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3008492648
Short name T776
Test name
Test status
Simulation time 1441873976 ps
CPU time 7.54 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:27 PM PDT 24
Peak memory 237480 kb
Host smart-a9167ea1-7316-45f7-80cb-a63018982b31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3008492648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3008492648
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2227828150
Short name T762
Test name
Test status
Simulation time 11472162 ps
CPU time 1.64 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:27:34 PM PDT 24
Peak memory 237636 kb
Host smart-4a1083ce-1585-4654-a562-4bb8483792ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2227828150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2227828150
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2359539094
Short name T746
Test name
Test status
Simulation time 511768320 ps
CPU time 34.4 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:28:06 PM PDT 24
Peak memory 245840 kb
Host smart-2410bb2f-1004-4892-8deb-7f60570ad92a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2359539094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2359539094
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3634483879
Short name T143
Test name
Test status
Simulation time 4727179650 ps
CPU time 99.28 seconds
Started Aug 18 04:27:30 PM PDT 24
Finished Aug 18 04:29:10 PM PDT 24
Peak memory 264960 kb
Host smart-8ef9f7b0-ac5b-490d-a725-50ddd5cc2813
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3634483879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3634483879
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4236848583
Short name T715
Test name
Test status
Simulation time 1012583204 ps
CPU time 13.71 seconds
Started Aug 18 04:27:28 PM PDT 24
Finished Aug 18 04:27:42 PM PDT 24
Peak memory 248636 kb
Host smart-de7b5acc-2f5c-44ae-b13a-8a165cafb10b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4236848583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4236848583
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.171248271
Short name T728
Test name
Test status
Simulation time 201618765 ps
CPU time 4.66 seconds
Started Aug 18 04:27:33 PM PDT 24
Finished Aug 18 04:27:39 PM PDT 24
Peak memory 239816 kb
Host smart-3cc4f285-d60d-452f-914f-ac56c54859ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171248271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.171248271
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3086334556
Short name T824
Test name
Test status
Simulation time 70098344 ps
CPU time 5.2 seconds
Started Aug 18 04:27:28 PM PDT 24
Finished Aug 18 04:27:34 PM PDT 24
Peak memory 240460 kb
Host smart-d4eb1f9e-89e4-4b1b-a54b-d19c6d4beb9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3086334556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3086334556
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2670501402
Short name T789
Test name
Test status
Simulation time 7916977 ps
CPU time 1.46 seconds
Started Aug 18 04:27:37 PM PDT 24
Finished Aug 18 04:27:39 PM PDT 24
Peak memory 237736 kb
Host smart-4fff4ef7-b64f-4131-984c-a1c7aaf7731e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2670501402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2670501402
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1417406088
Short name T822
Test name
Test status
Simulation time 3862132904 ps
CPU time 34.24 seconds
Started Aug 18 04:27:32 PM PDT 24
Finished Aug 18 04:28:07 PM PDT 24
Peak memory 245820 kb
Host smart-4bca946f-5603-4e8d-986e-6d88b7d6a3de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1417406088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1417406088
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3109992578
Short name T119
Test name
Test status
Simulation time 2701289563 ps
CPU time 173.52 seconds
Started Aug 18 04:27:29 PM PDT 24
Finished Aug 18 04:30:23 PM PDT 24
Peak memory 265444 kb
Host smart-9d85ce6a-548e-4fe0-b41f-70c43dcda484
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3109992578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3109992578
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3590766584
Short name T155
Test name
Test status
Simulation time 4270882718 ps
CPU time 306.38 seconds
Started Aug 18 04:27:27 PM PDT 24
Finished Aug 18 04:32:33 PM PDT 24
Peak memory 265496 kb
Host smart-6444e6a0-12d2-4bc5-b35e-b9d5c73e26d4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590766584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3590766584
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3677193319
Short name T756
Test name
Test status
Simulation time 40635333 ps
CPU time 5.23 seconds
Started Aug 18 04:27:31 PM PDT 24
Finished Aug 18 04:27:36 PM PDT 24
Peak memory 248000 kb
Host smart-70782ef5-585e-4c98-b5d1-ae254389a9bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3677193319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3677193319
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.287568829
Short name T96
Test name
Test status
Simulation time 66175357709 ps
CPU time 1271.76 seconds
Started Aug 18 04:29:32 PM PDT 24
Finished Aug 18 04:50:44 PM PDT 24
Peak memory 289100 kb
Host smart-05c8a902-c3d5-4b50-b994-0aac32195b14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287568829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.287568829
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.405642653
Short name T526
Test name
Test status
Simulation time 101875829 ps
CPU time 6.92 seconds
Started Aug 18 04:29:51 PM PDT 24
Finished Aug 18 04:29:58 PM PDT 24
Peak memory 247424 kb
Host smart-67827fe6-6a45-4661-8569-584a5f094850
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=405642653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.405642653
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3710444714
Short name T38
Test name
Test status
Simulation time 926176470 ps
CPU time 19.92 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:30:19 PM PDT 24
Peak memory 256984 kb
Host smart-921890eb-6dc6-4b7c-99c3-8d701b34772b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37104
44714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3710444714
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2440516227
Short name T476
Test name
Test status
Simulation time 23834296839 ps
CPU time 667.31 seconds
Started Aug 18 04:29:35 PM PDT 24
Finished Aug 18 04:40:42 PM PDT 24
Peak memory 272368 kb
Host smart-b52a4c89-4d09-4a9c-8d93-b5b7458bf6f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440516227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2440516227
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.815869491
Short name T383
Test name
Test status
Simulation time 28859217849 ps
CPU time 1837.95 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 05:00:37 PM PDT 24
Peak memory 273128 kb
Host smart-589c8a35-8143-40eb-a204-751947ab4c05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815869491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.815869491
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3298365452
Short name T507
Test name
Test status
Simulation time 190012969 ps
CPU time 17 seconds
Started Aug 18 04:29:38 PM PDT 24
Finished Aug 18 04:29:55 PM PDT 24
Peak memory 248708 kb
Host smart-0bc2e2e9-29fc-40b9-ae52-803b4b672092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32983
65452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3298365452
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3577939854
Short name T477
Test name
Test status
Simulation time 594786376 ps
CPU time 33.85 seconds
Started Aug 18 04:29:54 PM PDT 24
Finished Aug 18 04:30:28 PM PDT 24
Peak memory 255612 kb
Host smart-912a85ee-2891-4bbf-a506-0017e7163430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35779
39854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3577939854
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3639775927
Short name T10
Test name
Test status
Simulation time 1834699872 ps
CPU time 19.05 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:30:18 PM PDT 24
Peak memory 278332 kb
Host smart-cde28d95-d3c9-4ac4-8f08-7a58a035f0c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3639775927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3639775927
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2303726544
Short name T512
Test name
Test status
Simulation time 954071696 ps
CPU time 15.32 seconds
Started Aug 18 04:29:54 PM PDT 24
Finished Aug 18 04:30:10 PM PDT 24
Peak memory 248192 kb
Host smart-9c411780-0c4f-4fbe-9e10-66a0e558a6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23037
26544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2303726544
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1304624766
Short name T405
Test name
Test status
Simulation time 598553569 ps
CPU time 33.12 seconds
Started Aug 18 04:29:52 PM PDT 24
Finished Aug 18 04:30:25 PM PDT 24
Peak memory 255848 kb
Host smart-64c78cb7-af36-49dd-9f7a-23c299afc972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13046
24766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1304624766
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2728488149
Short name T70
Test name
Test status
Simulation time 13518400941 ps
CPU time 477.89 seconds
Started Aug 18 04:29:35 PM PDT 24
Finished Aug 18 04:37:33 PM PDT 24
Peak memory 256896 kb
Host smart-1a5ab432-3795-4c38-9587-10eb5b586b65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728488149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2728488149
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3570517643
Short name T234
Test name
Test status
Simulation time 10912601897 ps
CPU time 171.59 seconds
Started Aug 18 04:29:54 PM PDT 24
Finished Aug 18 04:32:46 PM PDT 24
Peak memory 265300 kb
Host smart-9d8ca820-f0b9-4460-b547-1369ec06a5af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570517643 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3570517643
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2134884583
Short name T474
Test name
Test status
Simulation time 7502205940 ps
CPU time 917.89 seconds
Started Aug 18 04:29:56 PM PDT 24
Finished Aug 18 04:45:14 PM PDT 24
Peak memory 284252 kb
Host smart-0ac22cec-b3df-4cb7-9333-25e6b9f705bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134884583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2134884583
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.354908080
Short name T219
Test name
Test status
Simulation time 198422202 ps
CPU time 11.11 seconds
Started Aug 18 04:29:55 PM PDT 24
Finished Aug 18 04:30:06 PM PDT 24
Peak memory 248780 kb
Host smart-2810825d-5c21-4984-ae0f-9734ec1d83d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=354908080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.354908080
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2516961861
Short name T610
Test name
Test status
Simulation time 414397387 ps
CPU time 8.87 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:30:07 PM PDT 24
Peak memory 256800 kb
Host smart-3f81f038-d4a8-4bed-92ed-5c91ed393df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25169
61861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2516961861
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.386850830
Short name T436
Test name
Test status
Simulation time 301828347 ps
CPU time 13.35 seconds
Started Aug 18 04:29:55 PM PDT 24
Finished Aug 18 04:30:09 PM PDT 24
Peak memory 255480 kb
Host smart-8c28c7fd-e146-4882-90db-f851880a5f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38685
0830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.386850830
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2060350725
Short name T285
Test name
Test status
Simulation time 29423756212 ps
CPU time 1711.89 seconds
Started Aug 18 04:29:53 PM PDT 24
Finished Aug 18 04:58:25 PM PDT 24
Peak memory 273236 kb
Host smart-0cb1b985-3415-46cb-b206-0f59df1cf5bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060350725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2060350725
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1262553471
Short name T228
Test name
Test status
Simulation time 115811373688 ps
CPU time 2083.03 seconds
Started Aug 18 04:29:53 PM PDT 24
Finished Aug 18 05:04:36 PM PDT 24
Peak memory 286440 kb
Host smart-3c846b34-0a7e-4dcc-98d5-716290e91678
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262553471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1262553471
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3762038115
Short name T675
Test name
Test status
Simulation time 46130715482 ps
CPU time 529.95 seconds
Started Aug 18 04:29:55 PM PDT 24
Finished Aug 18 04:38:45 PM PDT 24
Peak memory 247772 kb
Host smart-6f55c722-2106-4a5c-b4be-dd9152dd99f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762038115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3762038115
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.695574670
Short name T371
Test name
Test status
Simulation time 1121291617 ps
CPU time 20.28 seconds
Started Aug 18 04:29:57 PM PDT 24
Finished Aug 18 04:30:17 PM PDT 24
Peak memory 256472 kb
Host smart-5796cc1d-1e07-4f36-8e42-f1dadac49c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69557
4670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.695574670
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1653413563
Short name T690
Test name
Test status
Simulation time 3563470516 ps
CPU time 29.22 seconds
Started Aug 18 04:29:55 PM PDT 24
Finished Aug 18 04:30:25 PM PDT 24
Peak memory 248708 kb
Host smart-e5621aef-b49c-4863-9390-7ea9dccf6f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16534
13563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1653413563
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.860009295
Short name T33
Test name
Test status
Simulation time 1648756097 ps
CPU time 61.66 seconds
Started Aug 18 04:29:55 PM PDT 24
Finished Aug 18 04:30:57 PM PDT 24
Peak memory 266792 kb
Host smart-2802b5af-8da8-4893-b764-d98a2773e9ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=860009295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.860009295
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3625762825
Short name T501
Test name
Test status
Simulation time 613705094 ps
CPU time 19 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:30:17 PM PDT 24
Peak memory 256412 kb
Host smart-bf91c69e-13a1-49ef-a042-e867ddf4d9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36257
62825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3625762825
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2682150103
Short name T340
Test name
Test status
Simulation time 131599359 ps
CPU time 14.53 seconds
Started Aug 18 04:29:50 PM PDT 24
Finished Aug 18 04:30:05 PM PDT 24
Peak memory 248640 kb
Host smart-f514b272-41de-4e22-bb4a-fc0cbd8199af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26821
50103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2682150103
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2441925257
Short name T57
Test name
Test status
Simulation time 23335804895 ps
CPU time 278.33 seconds
Started Aug 18 04:29:50 PM PDT 24
Finished Aug 18 04:34:29 PM PDT 24
Peak memory 256868 kb
Host smart-4c2852ed-6d56-4bf8-8d52-d001c0cdc09a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441925257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2441925257
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1629781921
Short name T517
Test name
Test status
Simulation time 1510758090 ps
CPU time 164.62 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:32:43 PM PDT 24
Peak memory 265340 kb
Host smart-1e251ecd-b6bb-4afb-bb9e-0dcb0642d2ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629781921 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1629781921
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3017610432
Short name T524
Test name
Test status
Simulation time 499395035 ps
CPU time 19.15 seconds
Started Aug 18 04:30:06 PM PDT 24
Finished Aug 18 04:30:25 PM PDT 24
Peak memory 248780 kb
Host smart-8e25297f-790f-47a6-9351-087ee5199ce7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3017610432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3017610432
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4053318044
Short name T428
Test name
Test status
Simulation time 25763043803 ps
CPU time 199.44 seconds
Started Aug 18 04:30:08 PM PDT 24
Finished Aug 18 04:33:27 PM PDT 24
Peak memory 257096 kb
Host smart-e16ec789-4f05-40d9-995b-10c1da130640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40533
18044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4053318044
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2695799836
Short name T369
Test name
Test status
Simulation time 762328056 ps
CPU time 50.24 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 04:30:59 PM PDT 24
Peak memory 248232 kb
Host smart-b3ef0ab1-e71d-473f-804f-44a48816ab2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26957
99836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2695799836
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2820593840
Short name T630
Test name
Test status
Simulation time 43143802103 ps
CPU time 2359.23 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 05:09:24 PM PDT 24
Peak memory 284604 kb
Host smart-9c6bac4a-6214-44bf-8fa5-699c68c5ba69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820593840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2820593840
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.460662209
Short name T689
Test name
Test status
Simulation time 9333197704 ps
CPU time 882.9 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 273332 kb
Host smart-7cc5f538-8761-486c-836a-ebe7c9b443ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460662209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.460662209
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.608511585
Short name T468
Test name
Test status
Simulation time 391910104 ps
CPU time 26.27 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 04:30:37 PM PDT 24
Peak memory 256044 kb
Host smart-edd2d2fd-3058-46b0-a1b1-2396e5e86907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60851
1585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.608511585
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4056201433
Short name T684
Test name
Test status
Simulation time 642653600 ps
CPU time 19.05 seconds
Started Aug 18 04:30:07 PM PDT 24
Finished Aug 18 04:30:26 PM PDT 24
Peak memory 254904 kb
Host smart-be69c124-a2bb-4602-bef5-8ed27f964c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40562
01433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4056201433
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4285421916
Short name T522
Test name
Test status
Simulation time 296702485 ps
CPU time 18.04 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:30:33 PM PDT 24
Peak memory 248328 kb
Host smart-0122929d-0507-4bc1-befb-4e597eb0d71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42854
21916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4285421916
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.901162340
Short name T595
Test name
Test status
Simulation time 511676305 ps
CPU time 32.97 seconds
Started Aug 18 04:30:10 PM PDT 24
Finished Aug 18 04:30:43 PM PDT 24
Peak memory 256824 kb
Host smart-cdc9ca75-59d1-4b83-b499-cffe5fb2c62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90116
2340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.901162340
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2595725754
Short name T510
Test name
Test status
Simulation time 55271480606 ps
CPU time 300.77 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:35:19 PM PDT 24
Peak memory 269708 kb
Host smart-722c60e1-cf89-4abc-8647-5bd6c5aa18c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595725754 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2595725754
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3474399262
Short name T193
Test name
Test status
Simulation time 419545663 ps
CPU time 3.8 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 04:30:15 PM PDT 24
Peak memory 248724 kb
Host smart-57ec3fea-bba7-4d0b-84b3-69eec9af5bbc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3474399262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3474399262
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1204855773
Short name T622
Test name
Test status
Simulation time 46094670905 ps
CPU time 859.34 seconds
Started Aug 18 04:30:02 PM PDT 24
Finished Aug 18 04:44:22 PM PDT 24
Peak memory 280972 kb
Host smart-b9560c2a-686f-4d4f-8753-90881b77a36e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204855773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1204855773
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1665606080
Short name T687
Test name
Test status
Simulation time 171763044 ps
CPU time 8.99 seconds
Started Aug 18 04:30:07 PM PDT 24
Finished Aug 18 04:30:16 PM PDT 24
Peak memory 248588 kb
Host smart-09512295-9261-40f0-8c76-ee2a51cf493f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1665606080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1665606080
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2032452447
Short name T451
Test name
Test status
Simulation time 23222049120 ps
CPU time 312.42 seconds
Started Aug 18 04:30:09 PM PDT 24
Finished Aug 18 04:35:21 PM PDT 24
Peak memory 256136 kb
Host smart-f975cceb-6654-4297-be74-b04e38b0445e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20324
52447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2032452447
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1607705629
Short name T642
Test name
Test status
Simulation time 71373073 ps
CPU time 7.76 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 04:30:44 PM PDT 24
Peak memory 248300 kb
Host smart-b649facd-763a-4d44-bbbc-11b67d146906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16077
05629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1607705629
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2589960910
Short name T569
Test name
Test status
Simulation time 13729745917 ps
CPU time 1218.62 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 04:50:22 PM PDT 24
Peak memory 289428 kb
Host smart-826d7f9b-a538-48e2-b6ff-d34b9c3f467a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589960910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2589960910
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3144796517
Short name T220
Test name
Test status
Simulation time 180303866454 ps
CPU time 2765 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 05:16:14 PM PDT 24
Peak memory 285428 kb
Host smart-c0e47a4e-a394-4674-9271-7fba97c57e68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144796517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3144796517
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4104768143
Short name T660
Test name
Test status
Simulation time 500171091 ps
CPU time 35.03 seconds
Started Aug 18 04:30:01 PM PDT 24
Finished Aug 18 04:30:36 PM PDT 24
Peak memory 256220 kb
Host smart-fe242c6e-8afc-4352-bf5e-ec02f7223ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41047
68143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4104768143
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3350521272
Short name T482
Test name
Test status
Simulation time 319079199 ps
CPU time 12.68 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:30:12 PM PDT 24
Peak memory 256320 kb
Host smart-1a9b98bc-ee4b-4000-b955-fbd8d36ed096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33505
21272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3350521272
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.111191548
Short name T274
Test name
Test status
Simulation time 218696384 ps
CPU time 21.35 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:30:39 PM PDT 24
Peak memory 249236 kb
Host smart-349d63f8-2544-4c79-b9dc-c5a84013b949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11119
1548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.111191548
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2121037799
Short name T354
Test name
Test status
Simulation time 1250883749 ps
CPU time 22.22 seconds
Started Aug 18 04:30:07 PM PDT 24
Finished Aug 18 04:30:30 PM PDT 24
Peak memory 256560 kb
Host smart-ff381bef-1a9f-4cc0-9201-063d85fc3981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21210
37799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2121037799
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3180806320
Short name T203
Test name
Test status
Simulation time 26193642 ps
CPU time 2.46 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:30:00 PM PDT 24
Peak memory 248856 kb
Host smart-60640f89-e082-490d-a70b-e3d9e5d1b32e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3180806320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3180806320
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1807663791
Short name T539
Test name
Test status
Simulation time 119719197297 ps
CPU time 1918.68 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 05:02:20 PM PDT 24
Peak memory 280924 kb
Host smart-2604f460-23cd-41d5-a63e-b618625d546d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807663791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1807663791
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3523104773
Short name T639
Test name
Test status
Simulation time 508954415 ps
CPU time 23.19 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 04:30:28 PM PDT 24
Peak memory 248668 kb
Host smart-d8df3036-ffbc-441c-a3aa-abad74fa90a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3523104773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3523104773
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.4274560563
Short name T101
Test name
Test status
Simulation time 9198974273 ps
CPU time 299.91 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 04:35:34 PM PDT 24
Peak memory 256456 kb
Host smart-8e3cdf38-89f2-4155-b52e-e930de5a4050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42745
60563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4274560563
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2885119989
Short name T646
Test name
Test status
Simulation time 828503938 ps
CPU time 46.86 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:31:05 PM PDT 24
Peak memory 255480 kb
Host smart-0ea43cdf-c9ae-4afc-b0ac-912688d8e569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28851
19989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2885119989
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3752948084
Short name T486
Test name
Test status
Simulation time 81629111160 ps
CPU time 774.73 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:43:34 PM PDT 24
Peak memory 273136 kb
Host smart-2468da16-5d44-4fde-9547-93a701298b08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752948084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3752948084
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1034384350
Short name T213
Test name
Test status
Simulation time 70688394812 ps
CPU time 1983.76 seconds
Started Aug 18 04:30:06 PM PDT 24
Finished Aug 18 05:03:10 PM PDT 24
Peak memory 273280 kb
Host smart-ac060d0e-62a3-4c5f-924a-f7624a3eaf19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034384350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1034384350
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2351195450
Short name T699
Test name
Test status
Simulation time 13884822264 ps
CPU time 268.36 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 04:34:41 PM PDT 24
Peak memory 247568 kb
Host smart-660a81b0-cdc2-4eef-a1d7-c47b6724a1c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351195450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2351195450
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1788752309
Short name T117
Test name
Test status
Simulation time 389540403 ps
CPU time 25.76 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 04:30:47 PM PDT 24
Peak memory 254312 kb
Host smart-43910d4f-5afc-429a-931e-4317e556ee08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17887
52309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1788752309
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1081859622
Short name T107
Test name
Test status
Simulation time 112150852 ps
CPU time 12.14 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 04:30:23 PM PDT 24
Peak memory 248028 kb
Host smart-3b4b7cc3-253d-408a-ad91-5818905c838f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10818
59622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1081859622
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3497598966
Short name T248
Test name
Test status
Simulation time 583999499 ps
CPU time 36.24 seconds
Started Aug 18 04:30:08 PM PDT 24
Finished Aug 18 04:30:44 PM PDT 24
Peak memory 248020 kb
Host smart-41bed847-35dd-4f04-b62e-09a9ca882db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34975
98966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3497598966
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2499061371
Short name T694
Test name
Test status
Simulation time 534714412 ps
CPU time 18.14 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 04:30:22 PM PDT 24
Peak memory 256204 kb
Host smart-6cb61b07-8b7e-4b5b-9f62-eb7995915197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24990
61371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2499061371
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2201552388
Short name T202
Test name
Test status
Simulation time 48494747 ps
CPU time 3.75 seconds
Started Aug 18 04:30:14 PM PDT 24
Finished Aug 18 04:30:18 PM PDT 24
Peak memory 248892 kb
Host smart-0809189a-dc1f-4175-87d3-f6fa15de74cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2201552388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2201552388
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2991527443
Short name T618
Test name
Test status
Simulation time 306420161 ps
CPU time 6.29 seconds
Started Aug 18 04:30:22 PM PDT 24
Finished Aug 18 04:30:28 PM PDT 24
Peak memory 248712 kb
Host smart-4bc59b72-d626-4864-8cde-b9ac88f79f52
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2991527443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2991527443
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.838657579
Short name T552
Test name
Test status
Simulation time 1254144105 ps
CPU time 66.1 seconds
Started Aug 18 04:30:02 PM PDT 24
Finished Aug 18 04:31:09 PM PDT 24
Peak memory 256408 kb
Host smart-acdc03bf-4bd7-41f6-812e-36da2835a9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83865
7579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.838657579
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1399888940
Short name T657
Test name
Test status
Simulation time 1160428931 ps
CPU time 34.13 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 04:30:38 PM PDT 24
Peak memory 248640 kb
Host smart-01231230-3128-4e00-a57a-2abd559976eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13998
88940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1399888940
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3036098803
Short name T302
Test name
Test status
Simulation time 43661989919 ps
CPU time 1068.8 seconds
Started Aug 18 04:30:02 PM PDT 24
Finished Aug 18 04:47:51 PM PDT 24
Peak memory 289820 kb
Host smart-50df4902-dcce-482a-bc79-639b84d42df3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036098803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3036098803
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3915784106
Short name T420
Test name
Test status
Simulation time 22905870294 ps
CPU time 669.55 seconds
Started Aug 18 04:30:13 PM PDT 24
Finished Aug 18 04:41:23 PM PDT 24
Peak memory 265148 kb
Host smart-4f0968d6-bc14-44e0-8a83-18f1d440fdea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915784106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3915784106
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2763059070
Short name T221
Test name
Test status
Simulation time 15022943330 ps
CPU time 317.03 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 04:35:30 PM PDT 24
Peak memory 248704 kb
Host smart-d4e329e9-cbc0-47d6-bcc0-05e0f44b0ee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763059070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2763059070
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2347340212
Short name T446
Test name
Test status
Simulation time 3245927739 ps
CPU time 51.45 seconds
Started Aug 18 04:30:24 PM PDT 24
Finished Aug 18 04:31:16 PM PDT 24
Peak memory 256040 kb
Host smart-228ae487-f42a-43db-900b-0da504f02bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23473
40212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2347340212
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2040982957
Short name T655
Test name
Test status
Simulation time 466756779 ps
CPU time 31.77 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 04:30:44 PM PDT 24
Peak memory 248764 kb
Host smart-63a0cd33-fa9a-480e-a695-89b9d1d4019d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20409
82957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2040982957
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2240456921
Short name T84
Test name
Test status
Simulation time 1306364897 ps
CPU time 40.99 seconds
Started Aug 18 04:30:13 PM PDT 24
Finished Aug 18 04:30:55 PM PDT 24
Peak memory 248812 kb
Host smart-9c3a4b12-d8ef-431d-bae6-6c0fddd0c005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22404
56921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2240456921
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2882065485
Short name T337
Test name
Test status
Simulation time 2988760768 ps
CPU time 42.98 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 04:31:18 PM PDT 24
Peak memory 255812 kb
Host smart-1c3d9d12-2f22-4f2f-a4e4-666817cddd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28820
65485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2882065485
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.4004541335
Short name T244
Test name
Test status
Simulation time 4132088301 ps
CPU time 495.4 seconds
Started Aug 18 04:30:19 PM PDT 24
Finished Aug 18 04:38:34 PM PDT 24
Peak memory 270900 kb
Host smart-8705908b-32ca-4df4-bd42-08ac56badf37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004541335 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.4004541335
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1056621534
Short name T51
Test name
Test status
Simulation time 9058250090 ps
CPU time 1030.18 seconds
Started Aug 18 04:30:35 PM PDT 24
Finished Aug 18 04:47:45 PM PDT 24
Peak memory 289532 kb
Host smart-3c1fecb1-bf71-4ca8-9eea-fef220138388
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056621534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1056621534
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3546321409
Short name T387
Test name
Test status
Simulation time 212661424 ps
CPU time 10.6 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 04:30:22 PM PDT 24
Peak memory 248636 kb
Host smart-e0efad29-1657-439e-8524-6d3c2968f43a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3546321409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3546321409
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2995308980
Short name T678
Test name
Test status
Simulation time 2567611443 ps
CPU time 54.22 seconds
Started Aug 18 04:30:05 PM PDT 24
Finished Aug 18 04:31:00 PM PDT 24
Peak memory 256492 kb
Host smart-035f77b3-0760-4543-831d-9e07f2a7bb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29953
08980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2995308980
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1461602297
Short name T400
Test name
Test status
Simulation time 4104341203 ps
CPU time 59.07 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:31:15 PM PDT 24
Peak memory 248660 kb
Host smart-c8b330ea-cc44-49ad-b1be-f2f9b965171a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14616
02297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1461602297
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3095069296
Short name T17
Test name
Test status
Simulation time 8657596320 ps
CPU time 803.14 seconds
Started Aug 18 04:30:14 PM PDT 24
Finished Aug 18 04:43:38 PM PDT 24
Peak memory 273136 kb
Host smart-f0b8572f-892f-4551-83bd-adfc2bbca868
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095069296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3095069296
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1183323575
Short name T487
Test name
Test status
Simulation time 284190916376 ps
CPU time 2435.56 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 05:10:48 PM PDT 24
Peak memory 281476 kb
Host smart-86d68e47-aefe-491a-b406-8745c7140a93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183323575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1183323575
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.806679264
Short name T626
Test name
Test status
Simulation time 14630091615 ps
CPU time 162.95 seconds
Started Aug 18 04:30:05 PM PDT 24
Finished Aug 18 04:32:48 PM PDT 24
Peak memory 248700 kb
Host smart-ce3962d0-76de-4857-987c-a7c5fc5a32cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806679264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.806679264
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.756178896
Short name T615
Test name
Test status
Simulation time 313900295 ps
CPU time 30.47 seconds
Started Aug 18 04:30:00 PM PDT 24
Finished Aug 18 04:30:31 PM PDT 24
Peak memory 256832 kb
Host smart-370ccb1a-9d01-4b8c-a897-fe3fd26d6583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75617
8896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.756178896
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2434769160
Short name T459
Test name
Test status
Simulation time 2686230540 ps
CPU time 37.52 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:55 PM PDT 24
Peak memory 256312 kb
Host smart-eefcf15c-1883-4240-b7b4-33c437e0c253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24347
69160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2434769160
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4278544390
Short name T253
Test name
Test status
Simulation time 3093167963 ps
CPU time 44.52 seconds
Started Aug 18 04:30:20 PM PDT 24
Finished Aug 18 04:31:05 PM PDT 24
Peak memory 248604 kb
Host smart-a276afca-d0c0-44b8-904d-b1c3dce0fc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42785
44390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4278544390
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2249215611
Short name T412
Test name
Test status
Simulation time 1860463209 ps
CPU time 22.78 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:31:01 PM PDT 24
Peak memory 256804 kb
Host smart-2222c65d-2573-4750-a8cc-ef76a70b969d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22492
15611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2249215611
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3571527162
Short name T52
Test name
Test status
Simulation time 64963638481 ps
CPU time 3536.84 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 05:29:13 PM PDT 24
Peak memory 289432 kb
Host smart-9768fafa-ca35-4c12-9734-a7b3c972c075
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571527162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3571527162
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2720978114
Short name T44
Test name
Test status
Simulation time 123153237 ps
CPU time 3.45 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:22 PM PDT 24
Peak memory 248888 kb
Host smart-e115fad5-0fd4-4c27-9000-4abb1ac24c63
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2720978114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2720978114
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1574959524
Short name T464
Test name
Test status
Simulation time 119897965852 ps
CPU time 1498.95 seconds
Started Aug 18 04:30:19 PM PDT 24
Finished Aug 18 04:55:18 PM PDT 24
Peak memory 273216 kb
Host smart-09bed553-ed24-4fa3-978e-8650304b157a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574959524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1574959524
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3799792085
Short name T434
Test name
Test status
Simulation time 240142909 ps
CPU time 11.93 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:31 PM PDT 24
Peak memory 248704 kb
Host smart-a00d7313-9f65-4a01-a0d4-18e9566aebcd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3799792085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3799792085
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2214186587
Short name T43
Test name
Test status
Simulation time 5559804126 ps
CPU time 95.62 seconds
Started Aug 18 04:30:05 PM PDT 24
Finished Aug 18 04:31:40 PM PDT 24
Peak memory 249804 kb
Host smart-e7dbc24c-1be7-4679-be79-fc00878b2bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22141
86587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2214186587
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1200573736
Short name T580
Test name
Test status
Simulation time 847819043 ps
CPU time 50.36 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:31:09 PM PDT 24
Peak memory 248396 kb
Host smart-17e71516-dcb1-46b5-b6af-bc7ca15a75b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005
73736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1200573736
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.612377140
Short name T653
Test name
Test status
Simulation time 88101633980 ps
CPU time 1439.48 seconds
Started Aug 18 04:30:35 PM PDT 24
Finished Aug 18 04:54:35 PM PDT 24
Peak memory 273280 kb
Host smart-61f4c175-a389-4b4c-8e43-8a74911605ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612377140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.612377140
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.653793072
Short name T553
Test name
Test status
Simulation time 35222960635 ps
CPU time 1409.92 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:54:09 PM PDT 24
Peak memory 288848 kb
Host smart-dc65a212-bf1e-4fb4-b255-81648a03eacd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653793072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.653793072
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1099751928
Short name T222
Test name
Test status
Simulation time 19280931746 ps
CPU time 316.21 seconds
Started Aug 18 04:30:16 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 247636 kb
Host smart-8a4c7730-9c11-4450-9bc2-66cbd569d2c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099751928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1099751928
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3994867625
Short name T455
Test name
Test status
Simulation time 426028236 ps
CPU time 18.59 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:37 PM PDT 24
Peak memory 256192 kb
Host smart-84d302fc-0abb-4d7c-9eb5-ce09609f7b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39948
67625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3994867625
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1262355569
Short name T502
Test name
Test status
Simulation time 516806341 ps
CPU time 15.68 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 04:30:26 PM PDT 24
Peak memory 254808 kb
Host smart-58ffb8fe-c4bf-4b4c-aa89-198343ded20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
55569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1262355569
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3052244546
Short name T401
Test name
Test status
Simulation time 342047377 ps
CPU time 11.57 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:30 PM PDT 24
Peak memory 248656 kb
Host smart-a21d7593-81b2-404c-9ed9-e00cc1e5eeef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522
44546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3052244546
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3266905385
Short name T197
Test name
Test status
Simulation time 57678478 ps
CPU time 4.54 seconds
Started Aug 18 04:30:16 PM PDT 24
Finished Aug 18 04:30:21 PM PDT 24
Peak memory 249032 kb
Host smart-2caf96f2-7294-4496-879d-d28fe829b2ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3266905385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3266905385
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.872953642
Short name T614
Test name
Test status
Simulation time 8350218687 ps
CPU time 1022.02 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 04:47:06 PM PDT 24
Peak memory 284488 kb
Host smart-cde636b9-996c-4864-8d90-15ea2f843de2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872953642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.872953642
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2633632956
Short name T406
Test name
Test status
Simulation time 212879076 ps
CPU time 8.25 seconds
Started Aug 18 04:30:30 PM PDT 24
Finished Aug 18 04:30:39 PM PDT 24
Peak memory 248628 kb
Host smart-696ae285-e638-4e90-813f-2779fbb6b2de
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2633632956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2633632956
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2524925821
Short name T453
Test name
Test status
Simulation time 1571040226 ps
CPU time 51.68 seconds
Started Aug 18 04:30:06 PM PDT 24
Finished Aug 18 04:30:58 PM PDT 24
Peak memory 256832 kb
Host smart-e501f672-1e0f-4668-bf7d-65c2c81fe45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25249
25821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2524925821
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.496230369
Short name T270
Test name
Test status
Simulation time 604020250 ps
CPU time 30.15 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 04:30:41 PM PDT 24
Peak memory 248676 kb
Host smart-6bf93862-b7a8-44d3-8490-9f03360bae3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49623
0369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.496230369
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.865543666
Short name T376
Test name
Test status
Simulation time 28843171268 ps
CPU time 1683.06 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 04:58:24 PM PDT 24
Peak memory 288620 kb
Host smart-78f7ad8f-cd85-4194-8164-2da1d220723e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865543666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.865543666
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2448334788
Short name T557
Test name
Test status
Simulation time 16265163966 ps
CPU time 672.42 seconds
Started Aug 18 04:30:06 PM PDT 24
Finished Aug 18 04:41:19 PM PDT 24
Peak memory 255848 kb
Host smart-1d42df43-a3e3-47d6-aff1-990904b5ed33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448334788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2448334788
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1334954771
Short name T603
Test name
Test status
Simulation time 676839527 ps
CPU time 27.99 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:46 PM PDT 24
Peak memory 248812 kb
Host smart-8d2751dd-db0a-4a54-a2e0-e5432e824149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13349
54771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1334954771
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.283203594
Short name T479
Test name
Test status
Simulation time 839728992 ps
CPU time 48.25 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 04:31:25 PM PDT 24
Peak memory 248728 kb
Host smart-ec910220-9be4-41a0-ad98-89439643dcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28320
3594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.283203594
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1740009198
Short name T247
Test name
Test status
Simulation time 1311327428 ps
CPU time 41.6 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:30:59 PM PDT 24
Peak memory 248660 kb
Host smart-25812595-5798-4c3f-8a00-dead76e341d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17400
09198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1740009198
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1511251008
Short name T374
Test name
Test status
Simulation time 1881414549 ps
CPU time 28.18 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:47 PM PDT 24
Peak memory 256432 kb
Host smart-8bd848d0-8c22-4de9-bd09-3b8996dd3dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15112
51008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1511251008
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.871295820
Short name T207
Test name
Test status
Simulation time 105244244 ps
CPU time 2.86 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:21 PM PDT 24
Peak memory 248892 kb
Host smart-6904b04b-c2bc-4556-962d-b5f7d6a216b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=871295820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.871295820
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1724970280
Short name T458
Test name
Test status
Simulation time 48351094856 ps
CPU time 2918.96 seconds
Started Aug 18 04:30:13 PM PDT 24
Finished Aug 18 05:18:53 PM PDT 24
Peak memory 281528 kb
Host smart-f2b92622-cda6-4586-97b2-33ab6acb96b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724970280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1724970280
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1778017465
Short name T413
Test name
Test status
Simulation time 563514601 ps
CPU time 10.15 seconds
Started Aug 18 04:30:16 PM PDT 24
Finished Aug 18 04:30:27 PM PDT 24
Peak memory 248672 kb
Host smart-11937dbf-6695-4339-8133-73a63e8db0ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1778017465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1778017465
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.944049686
Short name T384
Test name
Test status
Simulation time 816370366 ps
CPU time 50.4 seconds
Started Aug 18 04:30:20 PM PDT 24
Finished Aug 18 04:31:11 PM PDT 24
Peak memory 256360 kb
Host smart-048fdf0a-68cb-4f94-84b0-a6686a50409b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94404
9686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.944049686
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2697826725
Short name T606
Test name
Test status
Simulation time 795937084 ps
CPU time 18.16 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:30:35 PM PDT 24
Peak memory 248724 kb
Host smart-d0bf0690-32ba-461e-a6a4-97acfa303ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26978
26725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2697826725
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.320422353
Short name T320
Test name
Test status
Simulation time 110496449276 ps
CPU time 3254.36 seconds
Started Aug 18 04:30:19 PM PDT 24
Finished Aug 18 05:24:34 PM PDT 24
Peak memory 289304 kb
Host smart-59b1a2b0-8b8a-45b8-acc5-bb169b28e388
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320422353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.320422353
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.4117181111
Short name T497
Test name
Test status
Simulation time 70918739111 ps
CPU time 2058.61 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 05:04:22 PM PDT 24
Peak memory 289460 kb
Host smart-62922a05-0cee-413f-bbd2-5cb5dbe1522b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117181111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.4117181111
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1245276035
Short name T594
Test name
Test status
Simulation time 12840704665 ps
CPU time 147.02 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 04:32:38 PM PDT 24
Peak memory 248736 kb
Host smart-047d9e1e-30e3-49dc-a273-ae35176d6d6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245276035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1245276035
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1329432143
Short name T587
Test name
Test status
Simulation time 2151624364 ps
CPU time 37.67 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:56 PM PDT 24
Peak memory 256844 kb
Host smart-d9f0e0aa-be68-40aa-b38b-55108d4bc15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13294
32143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1329432143
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.141906510
Short name T61
Test name
Test status
Simulation time 36398264 ps
CPU time 5.31 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:30:22 PM PDT 24
Peak memory 248080 kb
Host smart-f6c7b71b-b464-448b-bd8c-d65193c77376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14190
6510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.141906510
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3659912182
Short name T648
Test name
Test status
Simulation time 399027130 ps
CPU time 25.62 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:30:43 PM PDT 24
Peak memory 256808 kb
Host smart-c56ff327-b3e1-4c66-be63-9ae390e53f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36599
12182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3659912182
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4111801310
Short name T338
Test name
Test status
Simulation time 1316514915 ps
CPU time 45.78 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 04:30:49 PM PDT 24
Peak memory 256884 kb
Host smart-e0348fe9-f0b7-4d61-a22a-9d9e8e606d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41118
01310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4111801310
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.511481423
Short name T236
Test name
Test status
Simulation time 13422524162 ps
CPU time 310.43 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 267612 kb
Host smart-fff605e4-9420-44a2-a477-6ad9f957165a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511481423 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.511481423
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2092816890
Short name T196
Test name
Test status
Simulation time 365049638 ps
CPU time 2.73 seconds
Started Aug 18 04:30:14 PM PDT 24
Finished Aug 18 04:30:17 PM PDT 24
Peak memory 248852 kb
Host smart-88b0e476-c2dd-4a08-a09f-bcff46a8afcb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2092816890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2092816890
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1963603513
Short name T368
Test name
Test status
Simulation time 81036905430 ps
CPU time 1819.48 seconds
Started Aug 18 04:30:35 PM PDT 24
Finished Aug 18 05:00:55 PM PDT 24
Peak memory 272992 kb
Host smart-6890ffb5-419c-4f56-87a2-d26031540f17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963603513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1963603513
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.178867746
Short name T484
Test name
Test status
Simulation time 298398422 ps
CPU time 14.41 seconds
Started Aug 18 04:30:05 PM PDT 24
Finished Aug 18 04:30:20 PM PDT 24
Peak memory 248628 kb
Host smart-74a4010f-3b22-45f4-bffc-898b5f300059
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=178867746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.178867746
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.842596992
Short name T214
Test name
Test status
Simulation time 481002514 ps
CPU time 13.36 seconds
Started Aug 18 04:30:20 PM PDT 24
Finished Aug 18 04:30:33 PM PDT 24
Peak memory 256280 kb
Host smart-16edaa26-7237-42c5-8337-a1a3e2073a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84259
6992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.842596992
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3323872769
Short name T417
Test name
Test status
Simulation time 657930263 ps
CPU time 31.27 seconds
Started Aug 18 04:30:19 PM PDT 24
Finished Aug 18 04:30:50 PM PDT 24
Peak memory 248740 kb
Host smart-dbddfa3f-cb98-404a-9677-b0fd3bf80c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33238
72769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3323872769
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4288404294
Short name T283
Test name
Test status
Simulation time 9682827579 ps
CPU time 853.83 seconds
Started Aug 18 04:30:33 PM PDT 24
Finished Aug 18 04:44:47 PM PDT 24
Peak memory 273444 kb
Host smart-a8b69b26-80fe-412c-8b99-02737f34114a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288404294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4288404294
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3622560874
Short name T294
Test name
Test status
Simulation time 8382243708 ps
CPU time 172.81 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:33:11 PM PDT 24
Peak memory 248580 kb
Host smart-58ea24ad-4682-4750-a21c-2b2bc59b21ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622560874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3622560874
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3948075173
Short name T475
Test name
Test status
Simulation time 2874333885 ps
CPU time 42 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 04:30:53 PM PDT 24
Peak memory 256724 kb
Host smart-049f6b84-50d1-4708-941c-3dfc88c94e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39480
75173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3948075173
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1039881421
Short name T49
Test name
Test status
Simulation time 747159001 ps
CPU time 38.33 seconds
Started Aug 18 04:30:05 PM PDT 24
Finished Aug 18 04:30:44 PM PDT 24
Peak memory 256984 kb
Host smart-0ce31df6-69ae-4751-9308-8ec0398e08dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
81421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1039881421
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2110271725
Short name T432
Test name
Test status
Simulation time 181508616 ps
CPU time 19.4 seconds
Started Aug 18 04:30:23 PM PDT 24
Finished Aug 18 04:30:43 PM PDT 24
Peak memory 256076 kb
Host smart-847e3280-e914-4fa9-8fda-57839fe8a5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21102
71725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2110271725
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.916898624
Short name T367
Test name
Test status
Simulation time 1988861158 ps
CPU time 10.71 seconds
Started Aug 18 04:30:28 PM PDT 24
Finished Aug 18 04:30:39 PM PDT 24
Peak memory 248696 kb
Host smart-0488b1da-892d-4270-984a-ab49b7f6e2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91689
8624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.916898624
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.4088024337
Short name T58
Test name
Test status
Simulation time 230745847756 ps
CPU time 1325.17 seconds
Started Aug 18 04:30:16 PM PDT 24
Finished Aug 18 04:52:21 PM PDT 24
Peak memory 289184 kb
Host smart-1eb8fade-382a-4b79-80a6-93a1eeadf9ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088024337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.4088024337
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2147354552
Short name T45
Test name
Test status
Simulation time 40664238 ps
CPU time 3.35 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:30:21 PM PDT 24
Peak memory 248892 kb
Host smart-868e98a1-1c0a-4ec8-b3b5-2131ff15594e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2147354552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2147354552
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2425362645
Short name T591
Test name
Test status
Simulation time 74782141758 ps
CPU time 1235.82 seconds
Started Aug 18 04:30:35 PM PDT 24
Finished Aug 18 04:51:11 PM PDT 24
Peak memory 273372 kb
Host smart-e3710d07-6583-44ac-b4bf-e532cdfc9117
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425362645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2425362645
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.686631615
Short name T385
Test name
Test status
Simulation time 739385318 ps
CPU time 24.95 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:44 PM PDT 24
Peak memory 248676 kb
Host smart-ab3ffca4-58e5-4083-8e15-0b422fec9921
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=686631615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.686631615
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2551990518
Short name T348
Test name
Test status
Simulation time 5384396297 ps
CPU time 318.63 seconds
Started Aug 18 04:30:28 PM PDT 24
Finished Aug 18 04:35:47 PM PDT 24
Peak memory 256288 kb
Host smart-389fb40b-050a-4de7-a1c7-112daef9af8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25519
90518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2551990518
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2155980158
Short name T685
Test name
Test status
Simulation time 3889073233 ps
CPU time 38.19 seconds
Started Aug 18 04:30:22 PM PDT 24
Finished Aug 18 04:31:01 PM PDT 24
Peak memory 248348 kb
Host smart-75dc13d8-1fd6-4ac5-8102-17ecb60b9795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21559
80158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2155980158
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3792176741
Short name T375
Test name
Test status
Simulation time 92658735245 ps
CPU time 2604.93 seconds
Started Aug 18 04:30:32 PM PDT 24
Finished Aug 18 05:13:57 PM PDT 24
Peak memory 288780 kb
Host smart-26ed6160-f137-459e-995e-1277aef744b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792176741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3792176741
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1389075519
Short name T621
Test name
Test status
Simulation time 8246505527 ps
CPU time 324.47 seconds
Started Aug 18 04:30:08 PM PDT 24
Finished Aug 18 04:35:32 PM PDT 24
Peak memory 255040 kb
Host smart-607f6e6e-cb1d-431c-b213-fa8153d2b32b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389075519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1389075519
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2394047093
Short name T67
Test name
Test status
Simulation time 661257503 ps
CPU time 25.48 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 04:30:37 PM PDT 24
Peak memory 256120 kb
Host smart-45a39a5f-d899-49b3-98b3-d011c95360ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23940
47093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2394047093
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.437617850
Short name T527
Test name
Test status
Simulation time 1456529672 ps
CPU time 47.58 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 04:31:08 PM PDT 24
Peak memory 248632 kb
Host smart-439158ab-65bb-4c33-86d4-e1663b7335e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43761
7850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.437617850
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1600467852
Short name T351
Test name
Test status
Simulation time 860665326 ps
CPU time 22.32 seconds
Started Aug 18 04:30:13 PM PDT 24
Finished Aug 18 04:30:36 PM PDT 24
Peak memory 247968 kb
Host smart-5c30011c-6d23-47c8-8a1d-a4f07e2ae173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16004
67852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1600467852
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.518009401
Short name T629
Test name
Test status
Simulation time 96082576 ps
CPU time 4.27 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:30:19 PM PDT 24
Peak memory 250964 kb
Host smart-b8de3c95-afb7-498d-bfdc-a76be5a44c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51800
9401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.518009401
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.896973434
Short name T246
Test name
Test status
Simulation time 14814692977 ps
CPU time 163.32 seconds
Started Aug 18 04:30:13 PM PDT 24
Finished Aug 18 04:32:56 PM PDT 24
Peak memory 265220 kb
Host smart-ebc1aeb9-f6b5-4a0e-abc1-22298863e11c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896973434 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.896973434
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2143361679
Short name T205
Test name
Test status
Simulation time 39215585 ps
CPU time 3.1 seconds
Started Aug 18 04:29:51 PM PDT 24
Finished Aug 18 04:29:55 PM PDT 24
Peak memory 248852 kb
Host smart-ea83b083-2b05-4470-a919-2a038a57814f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2143361679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2143361679
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2696015654
Short name T681
Test name
Test status
Simulation time 30996414427 ps
CPU time 755.76 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:42:34 PM PDT 24
Peak memory 272648 kb
Host smart-954aa7fc-0adb-488c-b883-c941dbe72f69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696015654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2696015654
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1601018431
Short name T427
Test name
Test status
Simulation time 1137010999 ps
CPU time 24 seconds
Started Aug 18 04:29:54 PM PDT 24
Finished Aug 18 04:30:18 PM PDT 24
Peak memory 248684 kb
Host smart-361a1cab-27be-42e1-aeaa-054c726517c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1601018431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1601018431
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3086590200
Short name T480
Test name
Test status
Simulation time 3131178172 ps
CPU time 171.47 seconds
Started Aug 18 04:29:56 PM PDT 24
Finished Aug 18 04:32:47 PM PDT 24
Peak memory 256520 kb
Host smart-25fd1aa8-b677-4a01-b1df-9659149570aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30865
90200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3086590200
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3379192800
Short name T421
Test name
Test status
Simulation time 5446582175 ps
CPU time 62.06 seconds
Started Aug 18 04:29:53 PM PDT 24
Finished Aug 18 04:30:55 PM PDT 24
Peak memory 256324 kb
Host smart-a976cfc9-a38d-4221-aba6-18b3d3d45d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33791
92800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3379192800
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.898735954
Short name T466
Test name
Test status
Simulation time 60492244964 ps
CPU time 1959.68 seconds
Started Aug 18 04:29:54 PM PDT 24
Finished Aug 18 05:02:34 PM PDT 24
Peak memory 284376 kb
Host smart-69b76486-f313-4347-9eda-205e4d133639
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898735954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.898735954
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.230379537
Short name T505
Test name
Test status
Simulation time 106318606093 ps
CPU time 533.5 seconds
Started Aug 18 04:30:00 PM PDT 24
Finished Aug 18 04:38:53 PM PDT 24
Peak memory 254868 kb
Host smart-29225151-041f-45bc-8017-420d6077ed87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230379537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.230379537
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.351929842
Short name T500
Test name
Test status
Simulation time 270946351 ps
CPU time 18.29 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:30:17 PM PDT 24
Peak memory 256148 kb
Host smart-9fa79471-53fe-408c-acdf-4fc068632c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35192
9842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.351929842
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4140652263
Short name T397
Test name
Test status
Simulation time 221600382 ps
CPU time 15.22 seconds
Started Aug 18 04:30:01 PM PDT 24
Finished Aug 18 04:30:17 PM PDT 24
Peak memory 248252 kb
Host smart-b155131a-69ea-4ecb-8ca1-b9fd8caa2f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41406
52263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4140652263
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4112886717
Short name T34
Test name
Test status
Simulation time 470539691 ps
CPU time 25.17 seconds
Started Aug 18 04:29:54 PM PDT 24
Finished Aug 18 04:30:20 PM PDT 24
Peak memory 275872 kb
Host smart-5f0110ca-f15b-4a2b-b28b-fe6fcca44df7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4112886717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4112886717
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.4106578484
Short name T683
Test name
Test status
Simulation time 738539731 ps
CPU time 20.21 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:30:19 PM PDT 24
Peak memory 255764 kb
Host smart-86dec93f-e56a-4fe0-a899-1d56c1c0df95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41065
78484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.4106578484
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1229746281
Short name T395
Test name
Test status
Simulation time 11656372116 ps
CPU time 44.77 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:30:43 PM PDT 24
Peak memory 256064 kb
Host smart-1646b62e-6320-4ede-8880-d00bb854bc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12297
46281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1229746281
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2406269164
Short name T452
Test name
Test status
Simulation time 10357868604 ps
CPU time 948.87 seconds
Started Aug 18 04:29:57 PM PDT 24
Finished Aug 18 04:45:46 PM PDT 24
Peak memory 273464 kb
Host smart-9c99b4c2-0b93-403a-8e97-7adb2b45bbaa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406269164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2406269164
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.796837303
Short name T377
Test name
Test status
Simulation time 435346751 ps
CPU time 11.38 seconds
Started Aug 18 04:30:31 PM PDT 24
Finished Aug 18 04:30:42 PM PDT 24
Peak memory 248268 kb
Host smart-3f4bc376-a163-4268-b3ed-bd8e1d227950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79683
7303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.796837303
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1852485210
Short name T357
Test name
Test status
Simulation time 951615150 ps
CPU time 56.97 seconds
Started Aug 18 04:30:07 PM PDT 24
Finished Aug 18 04:31:04 PM PDT 24
Peak memory 256892 kb
Host smart-fe620b5e-ae18-4c03-85be-73bdd2599249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18524
85210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1852485210
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3076745023
Short name T321
Test name
Test status
Simulation time 83016471111 ps
CPU time 1136.89 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 04:49:18 PM PDT 24
Peak memory 273304 kb
Host smart-cae59f08-f125-4af9-b837-9584a1a1f90e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076745023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3076745023
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2196447155
Short name T227
Test name
Test status
Simulation time 57656195473 ps
CPU time 3132.32 seconds
Started Aug 18 04:30:32 PM PDT 24
Finished Aug 18 05:22:45 PM PDT 24
Peak memory 289392 kb
Host smart-5c851ad5-0d9c-4d45-b7d0-706828e7b3f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196447155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2196447155
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3897606823
Short name T287
Test name
Test status
Simulation time 25668291436 ps
CPU time 252.11 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 04:34:33 PM PDT 24
Peak memory 248704 kb
Host smart-c5eed982-bae1-4a2a-a95d-7387c6ec6a0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897606823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3897606823
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3649936675
Short name T407
Test name
Test status
Simulation time 1222459786 ps
CPU time 76.32 seconds
Started Aug 18 04:30:27 PM PDT 24
Finished Aug 18 04:31:43 PM PDT 24
Peak memory 256884 kb
Host smart-96bc1aa0-484c-46e1-ac66-0432cec8656b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36499
36675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3649936675
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1984266100
Short name T108
Test name
Test status
Simulation time 5094174281 ps
CPU time 34.96 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 04:30:39 PM PDT 24
Peak memory 256312 kb
Host smart-312deabf-211c-483b-8957-928293e70bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19842
66100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1984266100
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3444471068
Short name T411
Test name
Test status
Simulation time 1312683335 ps
CPU time 28.6 seconds
Started Aug 18 04:30:30 PM PDT 24
Finished Aug 18 04:30:58 PM PDT 24
Peak memory 256828 kb
Host smart-7bc52425-ee1b-4414-aeec-1c8f3a72075c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34444
71068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3444471068
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1776862521
Short name T460
Test name
Test status
Simulation time 178875112299 ps
CPU time 2868.8 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 05:18:24 PM PDT 24
Peak memory 289376 kb
Host smart-816d5bc6-3467-49eb-80c1-e282d29b5adb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776862521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1776862521
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.473997973
Short name T240
Test name
Test status
Simulation time 11973854114 ps
CPU time 194.06 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 04:33:35 PM PDT 24
Peak memory 265296 kb
Host smart-d9b8c178-b5fa-43ad-bbb5-568c0be968bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473997973 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.473997973
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.71204814
Short name T102
Test name
Test status
Simulation time 37906633166 ps
CPU time 742.22 seconds
Started Aug 18 04:30:30 PM PDT 24
Finished Aug 18 04:42:53 PM PDT 24
Peak memory 273376 kb
Host smart-b6531d42-741d-4408-8201-75234ef1e444
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71204814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.71204814
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.83631873
Short name T339
Test name
Test status
Simulation time 2618661375 ps
CPU time 165.29 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:33:03 PM PDT 24
Peak memory 256044 kb
Host smart-327c9434-b244-4ee4-a381-3e8fbad3abaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83631
873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.83631873
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1197635982
Short name T99
Test name
Test status
Simulation time 5142038533 ps
CPU time 79.77 seconds
Started Aug 18 04:30:16 PM PDT 24
Finished Aug 18 04:31:36 PM PDT 24
Peak memory 256804 kb
Host smart-eec8eca0-63b9-4b0a-9451-d342737acfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11976
35982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1197635982
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1386828051
Short name T313
Test name
Test status
Simulation time 85182142842 ps
CPU time 1369.39 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 272616 kb
Host smart-af47c55d-2a99-4b39-a755-13ec041c5afc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386828051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1386828051
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.360233760
Short name T443
Test name
Test status
Simulation time 28488152317 ps
CPU time 1160.36 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:49:35 PM PDT 24
Peak memory 283580 kb
Host smart-15127263-8561-4884-bbb5-1c9dd16e220d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360233760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.360233760
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.270527247
Short name T292
Test name
Test status
Simulation time 33098611591 ps
CPU time 113.98 seconds
Started Aug 18 04:30:19 PM PDT 24
Finished Aug 18 04:32:14 PM PDT 24
Peak memory 255336 kb
Host smart-e988fbde-af74-4b25-a261-e427ca956352
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270527247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.270527247
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.827770785
Short name T343
Test name
Test status
Simulation time 4287215121 ps
CPU time 60.09 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:31:17 PM PDT 24
Peak memory 248768 kb
Host smart-826563d5-3e1f-4c3c-a654-4283886a8af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82777
0785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.827770785
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1360619950
Short name T513
Test name
Test status
Simulation time 820868701 ps
CPU time 45.89 seconds
Started Aug 18 04:30:35 PM PDT 24
Finished Aug 18 04:31:21 PM PDT 24
Peak memory 256792 kb
Host smart-19995d89-322a-4c2c-8b15-21831f35744a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13606
19950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1360619950
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1016478203
Short name T388
Test name
Test status
Simulation time 1934833254 ps
CPU time 43.5 seconds
Started Aug 18 04:30:35 PM PDT 24
Finished Aug 18 04:31:19 PM PDT 24
Peak memory 256072 kb
Host smart-0e92531a-94ed-42b3-a51b-902b33b28990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
78203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1016478203
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.4121859937
Short name T349
Test name
Test status
Simulation time 1016193232 ps
CPU time 53.11 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 04:31:28 PM PDT 24
Peak memory 255792 kb
Host smart-2d8ae142-22e3-4757-939f-05c7a6698dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41218
59937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.4121859937
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3045580290
Short name T686
Test name
Test status
Simulation time 83086538615 ps
CPU time 2518 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 05:12:14 PM PDT 24
Peak memory 289008 kb
Host smart-f7de9627-10bb-46ea-8910-661b06225cc3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045580290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3045580290
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.325905574
Short name T237
Test name
Test status
Simulation time 3030028730 ps
CPU time 176.48 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 04:33:30 PM PDT 24
Peak memory 265184 kb
Host smart-93512128-b46e-4374-9545-0b57902f4769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325905574 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.325905574
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1656954517
Short name T370
Test name
Test status
Simulation time 44847351974 ps
CPU time 950.95 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 04:46:26 PM PDT 24
Peak memory 272932 kb
Host smart-8ba51320-fec6-4b76-bd73-1b092df8e408
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656954517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1656954517
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2726931525
Short name T585
Test name
Test status
Simulation time 1090313127 ps
CPU time 63.17 seconds
Started Aug 18 04:30:24 PM PDT 24
Finished Aug 18 04:31:27 PM PDT 24
Peak memory 256892 kb
Host smart-d9e61026-32a2-4484-bc7b-37193bb5cf59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27269
31525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2726931525
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2344022236
Short name T82
Test name
Test status
Simulation time 538584444 ps
CPU time 30.26 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:30:45 PM PDT 24
Peak memory 255288 kb
Host smart-edad063e-35e4-4925-b2cd-50b92e06e20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23440
22236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2344022236
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1975854921
Short name T548
Test name
Test status
Simulation time 33471695379 ps
CPU time 686.44 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:41:44 PM PDT 24
Peak memory 273276 kb
Host smart-b757b73c-856a-407d-bee7-85bdfb6ebcbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975854921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1975854921
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3253184933
Short name T463
Test name
Test status
Simulation time 77045946571 ps
CPU time 2299.71 seconds
Started Aug 18 04:30:14 PM PDT 24
Finished Aug 18 05:08:34 PM PDT 24
Peak memory 289168 kb
Host smart-549eca62-72a1-470e-8474-22f49c254243
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253184933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3253184933
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.24267189
Short name T543
Test name
Test status
Simulation time 111019701 ps
CPU time 5.64 seconds
Started Aug 18 04:30:05 PM PDT 24
Finished Aug 18 04:30:11 PM PDT 24
Peak memory 254592 kb
Host smart-61e8c91d-e112-4cdf-a61a-6b04a3531135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24267
189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.24267189
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1041905072
Short name T471
Test name
Test status
Simulation time 2925940677 ps
CPU time 37.56 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 04:30:41 PM PDT 24
Peak memory 256508 kb
Host smart-56887a28-4515-4353-885e-adfd3159407e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10419
05072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1041905072
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3469755341
Short name T600
Test name
Test status
Simulation time 982127777 ps
CPU time 21.39 seconds
Started Aug 18 04:30:31 PM PDT 24
Finished Aug 18 04:30:52 PM PDT 24
Peak memory 255964 kb
Host smart-8fd2eec9-69b7-4127-b649-19cdf65c35d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34697
55341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3469755341
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1661736807
Short name T55
Test name
Test status
Simulation time 206604527223 ps
CPU time 2861.93 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 05:18:01 PM PDT 24
Peak memory 289352 kb
Host smart-bd376202-163b-45fe-aebc-52ca8c4dba72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661736807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1661736807
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1969496965
Short name T659
Test name
Test status
Simulation time 50955150286 ps
CPU time 2895.16 seconds
Started Aug 18 04:30:28 PM PDT 24
Finished Aug 18 05:18:43 PM PDT 24
Peak memory 288960 kb
Host smart-50f557fa-cf20-4187-aa4e-16041dbdf7c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969496965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1969496965
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1217021002
Short name T345
Test name
Test status
Simulation time 1446323870 ps
CPU time 111.14 seconds
Started Aug 18 04:30:14 PM PDT 24
Finished Aug 18 04:32:05 PM PDT 24
Peak memory 256788 kb
Host smart-c2de199d-c09e-46ec-96ca-619454c2f286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12170
21002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1217021002
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3850500735
Short name T668
Test name
Test status
Simulation time 250514123 ps
CPU time 29.1 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 04:30:42 PM PDT 24
Peak memory 256800 kb
Host smart-8a708a92-66b8-4dbd-8da8-2877be48df6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38505
00735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3850500735
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1666160278
Short name T268
Test name
Test status
Simulation time 27159645264 ps
CPU time 1100.03 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 04:48:55 PM PDT 24
Peak memory 284796 kb
Host smart-4f7e4739-7e5e-4111-8c1a-1159ac77f2e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666160278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1666160278
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.4004167362
Short name T519
Test name
Test status
Simulation time 10582431415 ps
CPU time 1256.02 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 04:51:32 PM PDT 24
Peak memory 289428 kb
Host smart-119b715b-5a25-49c9-ac8a-d0af1317eaf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004167362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4004167362
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2242614105
Short name T30
Test name
Test status
Simulation time 40689926098 ps
CPU time 425.05 seconds
Started Aug 18 04:30:22 PM PDT 24
Finished Aug 18 04:37:27 PM PDT 24
Peak memory 248684 kb
Host smart-c253fb6f-edd9-48c7-9921-5f84cf0abd12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242614105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2242614105
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2902043325
Short name T672
Test name
Test status
Simulation time 1302393028 ps
CPU time 29.17 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:30:44 PM PDT 24
Peak memory 248688 kb
Host smart-e3200575-2f19-4910-8934-6ec29ccab7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29020
43325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2902043325
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.445420212
Short name T680
Test name
Test status
Simulation time 2407522294 ps
CPU time 27.93 seconds
Started Aug 18 04:30:29 PM PDT 24
Finished Aug 18 04:30:57 PM PDT 24
Peak memory 248192 kb
Host smart-bca918eb-9a4c-4e1d-8211-dde4afabd8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44542
0212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.445420212
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.421176488
Short name T449
Test name
Test status
Simulation time 682700206 ps
CPU time 50.34 seconds
Started Aug 18 04:30:22 PM PDT 24
Finished Aug 18 04:31:13 PM PDT 24
Peak memory 256116 kb
Host smart-f7ba6264-047b-4248-87d0-5a2651270241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42117
6488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.421176488
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.792481425
Short name T392
Test name
Test status
Simulation time 356703577 ps
CPU time 21.03 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:30:36 PM PDT 24
Peak memory 256824 kb
Host smart-8146fcde-1421-4a13-afb3-508ac48dcaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79248
1425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.792481425
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1709678964
Short name T518
Test name
Test status
Simulation time 14566684358 ps
CPU time 1495.95 seconds
Started Aug 18 04:30:22 PM PDT 24
Finished Aug 18 04:55:19 PM PDT 24
Peak memory 289700 kb
Host smart-b90dd3d5-f737-4959-8172-af9907e2e531
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709678964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1709678964
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.767254926
Short name T542
Test name
Test status
Simulation time 7251538985 ps
CPU time 387.97 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:37:06 PM PDT 24
Peak memory 268228 kb
Host smart-532e4c54-4b14-4856-8c74-8d305642c421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767254926 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.767254926
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.93632508
Short name T111
Test name
Test status
Simulation time 228401098609 ps
CPU time 2966.11 seconds
Started Aug 18 04:30:19 PM PDT 24
Finished Aug 18 05:19:46 PM PDT 24
Peak memory 289436 kb
Host smart-1122b65a-625d-4238-bb14-aa3075b8c3dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93632508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.93632508
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.467872938
Short name T664
Test name
Test status
Simulation time 1755520313 ps
CPU time 107.83 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:32:27 PM PDT 24
Peak memory 256684 kb
Host smart-55f62df8-c6d6-441b-b032-acddf81c4d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46787
2938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.467872938
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1200243175
Short name T488
Test name
Test status
Simulation time 787085712 ps
CPU time 22.11 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 04:30:58 PM PDT 24
Peak memory 256076 kb
Host smart-8ff80ff9-49ab-4ceb-988f-2a810b08823a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12002
43175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1200243175
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.4187916467
Short name T311
Test name
Test status
Simulation time 31800249995 ps
CPU time 1300.47 seconds
Started Aug 18 04:30:19 PM PDT 24
Finished Aug 18 04:52:00 PM PDT 24
Peak memory 284080 kb
Host smart-9fcb1172-5ac5-480e-a83e-f038f111001b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187916467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.4187916467
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.498349414
Short name T592
Test name
Test status
Simulation time 58991643417 ps
CPU time 823.51 seconds
Started Aug 18 04:30:23 PM PDT 24
Finished Aug 18 04:44:07 PM PDT 24
Peak memory 272568 kb
Host smart-e68604a8-6c62-497b-9785-5f4c050932ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498349414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.498349414
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3141816321
Short name T303
Test name
Test status
Simulation time 25290113195 ps
CPU time 231.12 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 04:34:27 PM PDT 24
Peak memory 248720 kb
Host smart-2c5bebbc-4f72-4cd0-b155-fed60213175f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141816321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3141816321
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.213730768
Short name T654
Test name
Test status
Simulation time 116495307 ps
CPU time 7.67 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:30:46 PM PDT 24
Peak memory 248800 kb
Host smart-c0235c1e-7fcb-4344-9e2b-99277d2e36fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21373
0768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.213730768
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1989549619
Short name T85
Test name
Test status
Simulation time 294913735 ps
CPU time 25.55 seconds
Started Aug 18 04:30:32 PM PDT 24
Finished Aug 18 04:30:58 PM PDT 24
Peak memory 256748 kb
Host smart-16a99f61-e799-41f2-b329-c9a86067557a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
49619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1989549619
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1881438000
Short name T380
Test name
Test status
Simulation time 474033845 ps
CPU time 9.43 seconds
Started Aug 18 04:30:31 PM PDT 24
Finished Aug 18 04:30:40 PM PDT 24
Peak memory 253848 kb
Host smart-6c1a68f9-107e-45e4-99a1-a6ef6b249a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18814
38000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1881438000
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3184264467
Short name T693
Test name
Test status
Simulation time 309702744 ps
CPU time 26.87 seconds
Started Aug 18 04:30:35 PM PDT 24
Finished Aug 18 04:31:02 PM PDT 24
Peak memory 256908 kb
Host smart-5910ade9-8fad-48f4-a9be-8ec9602cb2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31842
64467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3184264467
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3593261184
Short name T106
Test name
Test status
Simulation time 28948604553 ps
CPU time 1777.94 seconds
Started Aug 18 04:30:37 PM PDT 24
Finished Aug 18 05:00:15 PM PDT 24
Peak memory 273352 kb
Host smart-d7b0748b-b329-48da-b3b4-1866db8f7cf3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593261184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3593261184
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2464903481
Short name T607
Test name
Test status
Simulation time 2218674151 ps
CPU time 71.99 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:31:50 PM PDT 24
Peak memory 256572 kb
Host smart-4efdd6fc-64a3-4eb6-9ceb-389fbb0ee0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24649
03481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2464903481
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2525258364
Short name T564
Test name
Test status
Simulation time 1430133037 ps
CPU time 33.87 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 04:31:08 PM PDT 24
Peak memory 248236 kb
Host smart-2bd93e07-c504-4633-a3cd-c5f411fd6ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25252
58364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2525258364
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1947331116
Short name T704
Test name
Test status
Simulation time 394375113568 ps
CPU time 2244.96 seconds
Started Aug 18 04:30:19 PM PDT 24
Finished Aug 18 05:07:44 PM PDT 24
Peak memory 289116 kb
Host smart-7afdd277-ca6d-444a-95b2-2fa1787a03b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947331116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1947331116
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1576602530
Short name T506
Test name
Test status
Simulation time 31864572135 ps
CPU time 823.68 seconds
Started Aug 18 04:30:40 PM PDT 24
Finished Aug 18 04:44:24 PM PDT 24
Peak memory 288920 kb
Host smart-4900b62d-35eb-4517-aef7-6b488328b441
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576602530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1576602530
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1371787858
Short name T444
Test name
Test status
Simulation time 401111986 ps
CPU time 3.61 seconds
Started Aug 18 04:30:20 PM PDT 24
Finished Aug 18 04:30:29 PM PDT 24
Peak memory 240460 kb
Host smart-3b2b4627-d2aa-4b9f-b19d-3b0eab27e7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717
87858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1371787858
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1740638192
Short name T602
Test name
Test status
Simulation time 554391934 ps
CPU time 40.96 seconds
Started Aug 18 04:30:31 PM PDT 24
Finished Aug 18 04:31:12 PM PDT 24
Peak memory 248240 kb
Host smart-ea4658a5-d2ac-4ff1-8335-86d2589b2551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17406
38192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1740638192
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1097580920
Short name T536
Test name
Test status
Simulation time 670195253 ps
CPU time 13.68 seconds
Started Aug 18 04:30:37 PM PDT 24
Finished Aug 18 04:30:51 PM PDT 24
Peak memory 247848 kb
Host smart-ba6441fd-c20d-4d43-9781-b4ffca95983d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10975
80920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1097580920
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3598732814
Short name T612
Test name
Test status
Simulation time 355265460 ps
CPU time 23.68 seconds
Started Aug 18 04:30:30 PM PDT 24
Finished Aug 18 04:30:54 PM PDT 24
Peak memory 248648 kb
Host smart-83f552e6-99df-49a4-ae25-c77a6acdaa7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35987
32814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3598732814
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3461739560
Short name T408
Test name
Test status
Simulation time 195569724867 ps
CPU time 2969.8 seconds
Started Aug 18 04:30:22 PM PDT 24
Finished Aug 18 05:19:52 PM PDT 24
Peak memory 305836 kb
Host smart-fcebff2e-749e-4e8a-ade8-a81159d8fc2d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461739560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3461739560
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2992459541
Short name T674
Test name
Test status
Simulation time 1626786646 ps
CPU time 192.71 seconds
Started Aug 18 04:30:29 PM PDT 24
Finished Aug 18 04:33:42 PM PDT 24
Peak memory 265272 kb
Host smart-785047c8-ee27-4eb0-934a-b74d75e6e094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992459541 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2992459541
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.48193423
Short name T661
Test name
Test status
Simulation time 111863019860 ps
CPU time 1706.59 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:58:44 PM PDT 24
Peak memory 289216 kb
Host smart-9b8803de-b31d-40de-8224-dfb17c96184d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48193423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.48193423
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1355825895
Short name T703
Test name
Test status
Simulation time 67248758614 ps
CPU time 300.15 seconds
Started Aug 18 04:30:35 PM PDT 24
Finished Aug 18 04:35:35 PM PDT 24
Peak memory 256368 kb
Host smart-5efcbddc-cb3e-41b0-9a66-23bbd6a4ec82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13558
25895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1355825895
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3755180477
Short name T352
Test name
Test status
Simulation time 925432838 ps
CPU time 9.53 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 04:30:44 PM PDT 24
Peak memory 248276 kb
Host smart-ffa84618-91c8-4860-992d-b0c584d5623b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551
80477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3755180477
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3668282637
Short name T324
Test name
Test status
Simulation time 28503970213 ps
CPU time 1794.32 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 05:00:29 PM PDT 24
Peak memory 282548 kb
Host smart-636abc2b-26c6-44ac-981d-c36e20a6efe6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668282637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3668282637
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2758705246
Short name T521
Test name
Test status
Simulation time 58221609720 ps
CPU time 338.32 seconds
Started Aug 18 04:30:40 PM PDT 24
Finished Aug 18 04:36:19 PM PDT 24
Peak memory 248704 kb
Host smart-5b0a4ce6-217a-4695-b465-608a5f453452
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758705246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2758705246
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3353557409
Short name T533
Test name
Test status
Simulation time 1335700458 ps
CPU time 30.1 seconds
Started Aug 18 04:30:18 PM PDT 24
Finished Aug 18 04:30:49 PM PDT 24
Peak memory 248664 kb
Host smart-a0575b9a-64a9-4797-b387-1d0234702115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33535
57409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3353557409
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2616122576
Short name T71
Test name
Test status
Simulation time 251040938 ps
CPU time 24.33 seconds
Started Aug 18 04:30:23 PM PDT 24
Finished Aug 18 04:30:47 PM PDT 24
Peak memory 256392 kb
Host smart-00217ac6-ff63-41b0-96b4-d824380b04ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26161
22576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2616122576
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2217582939
Short name T691
Test name
Test status
Simulation time 1882228512 ps
CPU time 51.13 seconds
Started Aug 18 04:30:37 PM PDT 24
Finished Aug 18 04:31:28 PM PDT 24
Peak memory 248656 kb
Host smart-4f2b27bf-d685-4f13-9e04-2a5b7c6fdc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22175
82939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2217582939
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4162564286
Short name T465
Test name
Test status
Simulation time 264540664 ps
CPU time 22.39 seconds
Started Aug 18 04:30:33 PM PDT 24
Finished Aug 18 04:30:56 PM PDT 24
Peak memory 256868 kb
Host smart-ef3f302c-f5a2-4cd7-9808-dd2a7fa3b056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41625
64286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4162564286
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1727099458
Short name T403
Test name
Test status
Simulation time 71433737247 ps
CPU time 3877.54 seconds
Started Aug 18 04:30:27 PM PDT 24
Finished Aug 18 05:35:05 PM PDT 24
Peak memory 301072 kb
Host smart-42de8d94-f7f0-4cdf-b819-e360d6af793a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727099458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1727099458
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.561469746
Short name T105
Test name
Test status
Simulation time 12294339504 ps
CPU time 1276.13 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 04:51:53 PM PDT 24
Peak memory 289500 kb
Host smart-a728f9ad-4c93-47b2-b074-5d157e7c2b4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561469746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.561469746
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1361409612
Short name T355
Test name
Test status
Simulation time 1406190590 ps
CPU time 91.08 seconds
Started Aug 18 04:30:21 PM PDT 24
Finished Aug 18 04:31:53 PM PDT 24
Peak memory 256232 kb
Host smart-af7afb51-1e02-436e-9ded-062ab4d0a78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13614
09612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1361409612
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.878364156
Short name T35
Test name
Test status
Simulation time 321708793 ps
CPU time 19.22 seconds
Started Aug 18 04:30:20 PM PDT 24
Finished Aug 18 04:30:40 PM PDT 24
Peak memory 248628 kb
Host smart-1a90c7ef-846a-480d-86df-28f85c3015eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87836
4156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.878364156
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3299639810
Short name T299
Test name
Test status
Simulation time 483146363992 ps
CPU time 2191.72 seconds
Started Aug 18 04:30:41 PM PDT 24
Finished Aug 18 05:07:13 PM PDT 24
Peak memory 283568 kb
Host smart-2c09d370-492e-4402-a3d8-cbb8e7664df2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299639810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3299639810
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1383481288
Short name T393
Test name
Test status
Simulation time 29577329176 ps
CPU time 1883.59 seconds
Started Aug 18 04:30:42 PM PDT 24
Finished Aug 18 05:02:06 PM PDT 24
Peak memory 286196 kb
Host smart-cc6832d1-bcf3-46c2-adf4-4d686a6daf86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383481288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1383481288
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1826547481
Short name T549
Test name
Test status
Simulation time 5827402299 ps
CPU time 63.55 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:31:42 PM PDT 24
Peak memory 256116 kb
Host smart-69cf735f-c71a-49aa-a503-7f527e7bf9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18265
47481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1826547481
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2942548095
Short name T456
Test name
Test status
Simulation time 713300178 ps
CPU time 20.82 seconds
Started Aug 18 04:30:34 PM PDT 24
Finished Aug 18 04:30:55 PM PDT 24
Peak memory 256888 kb
Host smart-535fa335-5649-4460-8bc7-be24176d8743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29425
48095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2942548095
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2165588807
Short name T394
Test name
Test status
Simulation time 414553253 ps
CPU time 13.46 seconds
Started Aug 18 04:30:41 PM PDT 24
Finished Aug 18 04:30:55 PM PDT 24
Peak memory 255496 kb
Host smart-14dc293a-78c1-4a68-bdc4-f931c311ccf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
88807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2165588807
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2215120414
Short name T441
Test name
Test status
Simulation time 2771444578 ps
CPU time 40.47 seconds
Started Aug 18 04:30:23 PM PDT 24
Finished Aug 18 04:31:04 PM PDT 24
Peak memory 256552 kb
Host smart-6a9e3ee6-fed6-44f7-ae9b-4a961696f984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22151
20414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2215120414
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.637992363
Short name T656
Test name
Test status
Simulation time 5445734715 ps
CPU time 146.44 seconds
Started Aug 18 04:30:31 PM PDT 24
Finished Aug 18 04:32:57 PM PDT 24
Peak memory 273016 kb
Host smart-3788f3ba-d72e-4a32-9757-eab9ecb84eb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637992363 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.637992363
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1402347974
Short name T637
Test name
Test status
Simulation time 72054047127 ps
CPU time 1657.44 seconds
Started Aug 18 04:30:32 PM PDT 24
Finished Aug 18 04:58:09 PM PDT 24
Peak memory 289436 kb
Host smart-4441e2b8-1be7-42ee-85da-9b5eb7897055
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402347974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1402347974
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2177592773
Short name T381
Test name
Test status
Simulation time 2927714802 ps
CPU time 180.42 seconds
Started Aug 18 04:30:41 PM PDT 24
Finished Aug 18 04:33:41 PM PDT 24
Peak memory 256904 kb
Host smart-d8f9771c-ed12-43a1-b129-ad2490e25453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21775
92773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2177592773
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3617330393
Short name T416
Test name
Test status
Simulation time 235611633 ps
CPU time 20.36 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 04:30:57 PM PDT 24
Peak memory 248292 kb
Host smart-d570a741-3365-41df-9b7e-c61e1395645b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36173
30393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3617330393
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1820695791
Short name T628
Test name
Test status
Simulation time 330246444323 ps
CPU time 1690.28 seconds
Started Aug 18 04:30:40 PM PDT 24
Finished Aug 18 04:58:50 PM PDT 24
Peak memory 272732 kb
Host smart-68567946-f57c-4dac-9824-cfd914e3e47a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820695791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1820695791
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.962246413
Short name T623
Test name
Test status
Simulation time 11398721454 ps
CPU time 928.77 seconds
Started Aug 18 04:30:43 PM PDT 24
Finished Aug 18 04:46:12 PM PDT 24
Peak memory 273328 kb
Host smart-aa30e228-6c81-4d27-91ba-307aa52c959b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962246413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.962246413
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1200938395
Short name T620
Test name
Test status
Simulation time 14245622672 ps
CPU time 284.25 seconds
Started Aug 18 04:30:45 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 248744 kb
Host smart-b80e47f9-9bf2-4dca-a841-bde17b1f37f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200938395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1200938395
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.615907498
Short name T457
Test name
Test status
Simulation time 332321715 ps
CPU time 19.75 seconds
Started Aug 18 04:30:41 PM PDT 24
Finished Aug 18 04:31:01 PM PDT 24
Peak memory 255212 kb
Host smart-a24a3784-ae85-4242-9214-c11ed7a17aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61590
7498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.615907498
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2476518232
Short name T640
Test name
Test status
Simulation time 1588296204 ps
CPU time 25.55 seconds
Started Aug 18 04:30:37 PM PDT 24
Finished Aug 18 04:31:02 PM PDT 24
Peak memory 256720 kb
Host smart-05853d81-c2ad-4df3-8f59-5a1e7b3cda62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24765
18232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2476518232
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.579153205
Short name T289
Test name
Test status
Simulation time 458037142 ps
CPU time 26.39 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 04:31:12 PM PDT 24
Peak memory 248124 kb
Host smart-0fed9871-7359-4bc8-b84f-5d7ca1c828c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57915
3205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.579153205
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3583922198
Short name T364
Test name
Test status
Simulation time 2619584264 ps
CPU time 44.17 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 04:31:31 PM PDT 24
Peak memory 256952 kb
Host smart-47511875-4f1c-4957-bf5d-a858f4c61256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35839
22198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3583922198
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1398142302
Short name T431
Test name
Test status
Simulation time 2153541206 ps
CPU time 165.61 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 04:33:32 PM PDT 24
Peak memory 256960 kb
Host smart-64806295-93e8-4389-aeb7-50376ae388de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398142302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1398142302
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3883482372
Short name T611
Test name
Test status
Simulation time 1480732313 ps
CPU time 102.04 seconds
Started Aug 18 04:30:30 PM PDT 24
Finished Aug 18 04:32:12 PM PDT 24
Peak memory 265508 kb
Host smart-19f20e45-0ed2-439f-870a-b85ee4105218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883482372 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3883482372
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.29051483
Short name T267
Test name
Test status
Simulation time 51980845058 ps
CPU time 2832.73 seconds
Started Aug 18 04:30:44 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 289328 kb
Host smart-47278d8b-dae5-4691-b6c8-7aaa49f4e4a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29051483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.29051483
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.710874720
Short name T41
Test name
Test status
Simulation time 9163039464 ps
CPU time 142.88 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 04:33:09 PM PDT 24
Peak memory 256524 kb
Host smart-b11713ce-86e6-47e9-bd27-f3a5615fedc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71087
4720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.710874720
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2375715401
Short name T422
Test name
Test status
Simulation time 2934429773 ps
CPU time 42.46 seconds
Started Aug 18 04:30:37 PM PDT 24
Finished Aug 18 04:31:20 PM PDT 24
Peak memory 256972 kb
Host smart-d5b29c07-3040-4575-a78d-f136a9e614d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23757
15401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2375715401
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1795165574
Short name T319
Test name
Test status
Simulation time 42300365273 ps
CPU time 2030.16 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 05:04:29 PM PDT 24
Peak memory 289588 kb
Host smart-841323ba-1c5b-4e2d-b06f-95a8da9440b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795165574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1795165574
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.351010524
Short name T68
Test name
Test status
Simulation time 47460374494 ps
CPU time 880.22 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 04:45:27 PM PDT 24
Peak memory 273088 kb
Host smart-3a916419-19d9-4e15-87ea-84ac68209de2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351010524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.351010524
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3677246121
Short name T582
Test name
Test status
Simulation time 9857675617 ps
CPU time 393.56 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 04:37:20 PM PDT 24
Peak memory 247604 kb
Host smart-a655a8c3-edc3-4f98-9b17-7cfecd2bae9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677246121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3677246121
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1891610757
Short name T372
Test name
Test status
Simulation time 114052002 ps
CPU time 11.28 seconds
Started Aug 18 04:30:37 PM PDT 24
Finished Aug 18 04:30:48 PM PDT 24
Peak memory 256208 kb
Host smart-3f18f138-b67b-44ec-9ca3-fc32e21e61e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
10757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1891610757
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2737670143
Short name T662
Test name
Test status
Simulation time 29359846 ps
CPU time 3.08 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:30:41 PM PDT 24
Peak memory 239680 kb
Host smart-01acebe5-c58a-4721-9fe1-894564a73954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27376
70143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2737670143
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2127559135
Short name T46
Test name
Test status
Simulation time 509142486 ps
CPU time 29.25 seconds
Started Aug 18 04:30:33 PM PDT 24
Finished Aug 18 04:31:03 PM PDT 24
Peak memory 256440 kb
Host smart-b7a84e34-0c01-42fa-8c3b-54ade0446742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21275
59135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2127559135
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1149142392
Short name T263
Test name
Test status
Simulation time 1271042740 ps
CPU time 21.39 seconds
Started Aug 18 04:30:40 PM PDT 24
Finished Aug 18 04:31:02 PM PDT 24
Peak memory 256576 kb
Host smart-4228d450-1223-4dc6-9dae-78eba71e7678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11491
42392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1149142392
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1067985536
Short name T540
Test name
Test status
Simulation time 7647695129 ps
CPU time 139.25 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:32:58 PM PDT 24
Peak memory 266820 kb
Host smart-2c6e663a-36c9-407f-85f1-78f7e0cce967
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067985536 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1067985536
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.304907082
Short name T208
Test name
Test status
Simulation time 36176174 ps
CPU time 2.32 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:30:07 PM PDT 24
Peak memory 248816 kb
Host smart-d3805516-f457-4ef8-83f4-16035eabe81c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=304907082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.304907082
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.494104152
Short name T534
Test name
Test status
Simulation time 68091777672 ps
CPU time 2387.95 seconds
Started Aug 18 04:29:57 PM PDT 24
Finished Aug 18 05:09:45 PM PDT 24
Peak memory 289024 kb
Host smart-4421c57c-6ebf-4aa1-b91b-475da7ca447f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494104152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.494104152
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.470605430
Short name T575
Test name
Test status
Simulation time 2317054112 ps
CPU time 10.33 seconds
Started Aug 18 04:29:57 PM PDT 24
Finished Aug 18 04:30:07 PM PDT 24
Peak memory 248736 kb
Host smart-c7badd8a-f00c-47b3-91ca-83df831dd9b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=470605430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.470605430
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1576366753
Short name T410
Test name
Test status
Simulation time 742646090 ps
CPU time 48.86 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:30:48 PM PDT 24
Peak memory 256788 kb
Host smart-00a51c79-12c8-43de-a7ea-c41dbc001773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15763
66753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1576366753
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1659691974
Short name T437
Test name
Test status
Simulation time 1935732844 ps
CPU time 27.42 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:30:25 PM PDT 24
Peak memory 248580 kb
Host smart-2299adcb-138a-4a12-ae48-5af65ea08a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16596
91974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1659691974
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2393078031
Short name T304
Test name
Test status
Simulation time 208159535866 ps
CPU time 1696.93 seconds
Started Aug 18 04:29:56 PM PDT 24
Finished Aug 18 04:58:13 PM PDT 24
Peak memory 271500 kb
Host smart-b92d6d70-7544-48da-ba95-c55c9aa811a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393078031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2393078031
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1099735025
Short name T670
Test name
Test status
Simulation time 81289082271 ps
CPU time 1748.78 seconds
Started Aug 18 04:29:54 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 272920 kb
Host smart-657a3982-a574-441b-84bf-b2e4b3eeafd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099735025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1099735025
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2734983875
Short name T286
Test name
Test status
Simulation time 11667754104 ps
CPU time 484.66 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:38:04 PM PDT 24
Peak memory 248748 kb
Host smart-c1809da6-acab-4e30-9bac-58124b1bc8bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734983875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2734983875
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1782268077
Short name T562
Test name
Test status
Simulation time 1656770526 ps
CPU time 24.96 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 04:30:28 PM PDT 24
Peak memory 255644 kb
Host smart-ffcda515-e147-421b-8243-efe0ac2c7f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17822
68077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1782268077
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.621915509
Short name T647
Test name
Test status
Simulation time 2488788831 ps
CPU time 64.38 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:31:03 PM PDT 24
Peak memory 256428 kb
Host smart-0dd101e0-97fb-48ca-832b-56e963ebc6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62191
5509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.621915509
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1095916269
Short name T9
Test name
Test status
Simulation time 652023114 ps
CPU time 9.61 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:30:08 PM PDT 24
Peak memory 270716 kb
Host smart-bafbcc57-3708-42f6-8ff8-cda69383789b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1095916269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1095916269
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1036010166
Short name T79
Test name
Test status
Simulation time 232851610 ps
CPU time 21.91 seconds
Started Aug 18 04:29:51 PM PDT 24
Finished Aug 18 04:30:13 PM PDT 24
Peak memory 248644 kb
Host smart-41fb5527-9ee8-4429-afe9-f05c062bc5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10360
10166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1036010166
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3571944485
Short name T454
Test name
Test status
Simulation time 11712086771 ps
CPU time 65.77 seconds
Started Aug 18 04:29:53 PM PDT 24
Finished Aug 18 04:30:59 PM PDT 24
Peak memory 256716 kb
Host smart-6d7a2a1a-e0a4-4930-bd9c-7d76624606d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35719
44485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3571944485
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3359167056
Short name T91
Test name
Test status
Simulation time 27033077948 ps
CPU time 1592.5 seconds
Started Aug 18 04:30:00 PM PDT 24
Finished Aug 18 04:56:33 PM PDT 24
Peak memory 273252 kb
Host smart-04825a45-b24a-4a04-b5a5-9fc0f1b99c21
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359167056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3359167056
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.728501065
Short name T104
Test name
Test status
Simulation time 4919486095 ps
CPU time 344.58 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 04:35:56 PM PDT 24
Peak memory 265740 kb
Host smart-5f58a031-8442-4eb8-99b3-0945545338d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728501065 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.728501065
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3741830667
Short name T415
Test name
Test status
Simulation time 63647242695 ps
CPU time 2612.65 seconds
Started Aug 18 04:30:40 PM PDT 24
Finished Aug 18 05:14:13 PM PDT 24
Peak memory 289244 kb
Host smart-d52a3267-7dd0-456b-9c5d-3cf25f1d24ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741830667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3741830667
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2559714814
Short name T358
Test name
Test status
Simulation time 6811928425 ps
CPU time 202.99 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:34:02 PM PDT 24
Peak memory 256496 kb
Host smart-5fafdf5e-c637-4082-8706-eea19fe21d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25597
14814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2559714814
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.4103734434
Short name T584
Test name
Test status
Simulation time 229047198 ps
CPU time 3.57 seconds
Started Aug 18 04:30:37 PM PDT 24
Finished Aug 18 04:30:41 PM PDT 24
Peak memory 240412 kb
Host smart-b861d6fd-4558-4f0c-8dce-ead1848e8b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41037
34434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.4103734434
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1905852127
Short name T325
Test name
Test status
Simulation time 52158960202 ps
CPU time 1401.62 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:54:01 PM PDT 24
Peak memory 272684 kb
Host smart-bbdbb990-1508-4b61-8b06-c97a039bc0b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905852127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1905852127
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2418656253
Short name T269
Test name
Test status
Simulation time 220252390325 ps
CPU time 2945.52 seconds
Started Aug 18 04:30:36 PM PDT 24
Finished Aug 18 05:19:42 PM PDT 24
Peak memory 288864 kb
Host smart-6b364d7a-fa71-4499-80a5-7b4d6a2fd1c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418656253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2418656253
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4191205433
Short name T419
Test name
Test status
Simulation time 140169510 ps
CPU time 5.29 seconds
Started Aug 18 04:30:45 PM PDT 24
Finished Aug 18 04:30:51 PM PDT 24
Peak memory 248680 kb
Host smart-0d8e95d2-9d7c-43cc-9235-44f283e62105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41912
05433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4191205433
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.668647388
Short name T62
Test name
Test status
Simulation time 580003163 ps
CPU time 25.01 seconds
Started Aug 18 04:30:40 PM PDT 24
Finished Aug 18 04:31:05 PM PDT 24
Peak memory 248020 kb
Host smart-cea4d97a-e80d-4d13-9058-1313eaba2874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66864
7388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.668647388
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.601305016
Short name T577
Test name
Test status
Simulation time 154743606 ps
CPU time 6.64 seconds
Started Aug 18 04:30:41 PM PDT 24
Finished Aug 18 04:30:48 PM PDT 24
Peak memory 248980 kb
Host smart-2835168a-4f66-45ba-9899-fe03aa80168d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60130
5016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.601305016
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2113573781
Short name T280
Test name
Test status
Simulation time 520469532 ps
CPU time 36.17 seconds
Started Aug 18 04:30:30 PM PDT 24
Finished Aug 18 04:31:07 PM PDT 24
Peak memory 256840 kb
Host smart-0e5592c7-f425-46e3-81c1-a9623cbe2f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21135
73781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2113573781
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1865697780
Short name T567
Test name
Test status
Simulation time 179868819776 ps
CPU time 2652.39 seconds
Started Aug 18 04:30:41 PM PDT 24
Finished Aug 18 05:14:54 PM PDT 24
Peak memory 297960 kb
Host smart-5cfc0a9e-2db8-4666-b750-56c95a3bfab5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865697780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1865697780
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.4237707613
Short name T95
Test name
Test status
Simulation time 18931832832 ps
CPU time 1186.47 seconds
Started Aug 18 04:30:45 PM PDT 24
Finished Aug 18 04:50:31 PM PDT 24
Peak memory 283592 kb
Host smart-6188c79b-86c8-4598-87e9-62f6a696adea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237707613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.4237707613
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2515409198
Short name T705
Test name
Test status
Simulation time 4132373388 ps
CPU time 158.09 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:33:17 PM PDT 24
Peak memory 256500 kb
Host smart-b2e766d5-26f6-4be3-9b60-e4e219401876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25154
09198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2515409198
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.312040802
Short name T530
Test name
Test status
Simulation time 4662366478 ps
CPU time 28.31 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:31:07 PM PDT 24
Peak memory 256276 kb
Host smart-8bd0692f-c436-4e33-a31f-336d1fa7fdf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31204
0802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.312040802
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1449796815
Short name T316
Test name
Test status
Simulation time 63028640653 ps
CPU time 1263.3 seconds
Started Aug 18 04:30:45 PM PDT 24
Finished Aug 18 04:51:49 PM PDT 24
Peak memory 281464 kb
Host smart-e6c46d23-ee23-40dd-9cec-7275ad8e1de0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449796815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1449796815
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.948448589
Short name T698
Test name
Test status
Simulation time 174162100477 ps
CPU time 2760.98 seconds
Started Aug 18 04:30:48 PM PDT 24
Finished Aug 18 05:16:50 PM PDT 24
Peak memory 285052 kb
Host smart-55f49682-5a89-4b8d-962f-d0c7a00413c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948448589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.948448589
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3662578523
Short name T295
Test name
Test status
Simulation time 10901926815 ps
CPU time 437.16 seconds
Started Aug 18 04:30:37 PM PDT 24
Finished Aug 18 04:37:55 PM PDT 24
Peak memory 248828 kb
Host smart-9cbc4816-cd8c-48b3-9ab5-088831d5eddc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662578523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3662578523
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3103520378
Short name T574
Test name
Test status
Simulation time 1369957909 ps
CPU time 17.99 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:30:56 PM PDT 24
Peak memory 248716 kb
Host smart-90845930-5af3-4c4d-b2d5-8ea55f6b0380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31035
20378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3103520378
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1338010771
Short name T113
Test name
Test status
Simulation time 434481700 ps
CPU time 29.28 seconds
Started Aug 18 04:30:44 PM PDT 24
Finished Aug 18 04:31:14 PM PDT 24
Peak memory 248384 kb
Host smart-c86fc511-7c66-453c-a977-ffbf733416a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13380
10771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1338010771
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3626784169
Short name T250
Test name
Test status
Simulation time 275172054 ps
CPU time 15.25 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:30:53 PM PDT 24
Peak memory 249228 kb
Host smart-7ce4442e-578c-4cb0-b719-ecae6d374919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36267
84169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3626784169
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1799396846
Short name T645
Test name
Test status
Simulation time 3528116247 ps
CPU time 54.37 seconds
Started Aug 18 04:30:33 PM PDT 24
Finished Aug 18 04:31:27 PM PDT 24
Peak memory 256008 kb
Host smart-5c9efb59-dde2-4cd6-b4ba-ee35397f9253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17993
96846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1799396846
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1534639052
Short name T88
Test name
Test status
Simulation time 103183534917 ps
CPU time 1768.88 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 05:00:15 PM PDT 24
Peak memory 284164 kb
Host smart-a31a0b5e-0261-4cdf-8e54-d3e074cd7ce4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534639052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1534639052
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3996983415
Short name T90
Test name
Test status
Simulation time 68285651530 ps
CPU time 1461.06 seconds
Started Aug 18 04:30:45 PM PDT 24
Finished Aug 18 04:55:06 PM PDT 24
Peak memory 289464 kb
Host smart-7ec29a66-be50-43c2-9ea5-051ef01f2d0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996983415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3996983415
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.97301888
Short name T224
Test name
Test status
Simulation time 5165238888 ps
CPU time 126.46 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:32:45 PM PDT 24
Peak memory 256432 kb
Host smart-4e125fa4-ad67-4cf9-bd66-6e989a415963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97301
888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.97301888
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.48748271
Short name T578
Test name
Test status
Simulation time 31949315 ps
CPU time 2.92 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:30:42 PM PDT 24
Peak memory 240516 kb
Host smart-8f49ac21-2873-424b-bfe1-917a7f2ca564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48748
271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.48748271
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3664237630
Short name T305
Test name
Test status
Simulation time 75623949015 ps
CPU time 2748.22 seconds
Started Aug 18 04:30:47 PM PDT 24
Finished Aug 18 05:16:36 PM PDT 24
Peak memory 285000 kb
Host smart-43be9bc8-7748-4e42-a728-4e013f53b000
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664237630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3664237630
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.912712986
Short name T508
Test name
Test status
Simulation time 30355338665 ps
CPU time 671.3 seconds
Started Aug 18 04:30:43 PM PDT 24
Finished Aug 18 04:41:54 PM PDT 24
Peak memory 273408 kb
Host smart-f823b8f5-45a0-4c61-9f7a-7e94038c3f6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912712986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.912712986
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1585552490
Short name T3
Test name
Test status
Simulation time 4224841816 ps
CPU time 167.92 seconds
Started Aug 18 04:30:45 PM PDT 24
Finished Aug 18 04:33:33 PM PDT 24
Peak memory 248736 kb
Host smart-d00ab747-699d-4744-a2c0-f90fbed2d45a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585552490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1585552490
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1890518686
Short name T556
Test name
Test status
Simulation time 4528765290 ps
CPU time 64.73 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:31:44 PM PDT 24
Peak memory 256108 kb
Host smart-985180a0-bc9d-4361-9f40-e68d809a852a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18905
18686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1890518686
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.660425724
Short name T448
Test name
Test status
Simulation time 951589218 ps
CPU time 59.1 seconds
Started Aug 18 04:30:41 PM PDT 24
Finished Aug 18 04:31:41 PM PDT 24
Peak memory 249808 kb
Host smart-e7d3759e-1fa5-4ece-90a3-84a0189f831a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66042
5724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.660425724
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4091640770
Short name T288
Test name
Test status
Simulation time 1369053340 ps
CPU time 48.95 seconds
Started Aug 18 04:30:38 PM PDT 24
Finished Aug 18 04:31:27 PM PDT 24
Peak memory 255900 kb
Host smart-c359aa1f-29dd-4a91-8041-c2cf66775f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40916
40770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4091640770
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1399074777
Short name T418
Test name
Test status
Simulation time 266459762 ps
CPU time 8.18 seconds
Started Aug 18 04:30:39 PM PDT 24
Finished Aug 18 04:30:47 PM PDT 24
Peak memory 248808 kb
Host smart-7b82a560-31e2-464a-85a3-ff8bf8bdab98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990
74777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1399074777
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1398370917
Short name T233
Test name
Test status
Simulation time 3813190969 ps
CPU time 127.01 seconds
Started Aug 18 04:30:47 PM PDT 24
Finished Aug 18 04:32:54 PM PDT 24
Peak memory 265416 kb
Host smart-32d90768-4924-403b-aebd-1ef72c0664ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398370917 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1398370917
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3087432781
Short name T701
Test name
Test status
Simulation time 43518470237 ps
CPU time 1152.19 seconds
Started Aug 18 04:30:50 PM PDT 24
Finished Aug 18 04:50:03 PM PDT 24
Peak memory 289792 kb
Host smart-c708e50d-703c-4a76-aa89-1e494faa3e81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087432781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3087432781
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.337155559
Short name T389
Test name
Test status
Simulation time 46259167867 ps
CPU time 314.09 seconds
Started Aug 18 04:30:45 PM PDT 24
Finished Aug 18 04:36:00 PM PDT 24
Peak memory 256936 kb
Host smart-6bed1a37-62e3-464e-bd4e-cd8ee7fb706f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33715
5559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.337155559
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.540760623
Short name T643
Test name
Test status
Simulation time 129300487 ps
CPU time 14.82 seconds
Started Aug 18 04:30:45 PM PDT 24
Finished Aug 18 04:31:00 PM PDT 24
Peak memory 248640 kb
Host smart-cfa68eed-ad14-422b-bfd5-10047bdda30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54076
0623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.540760623
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1976258976
Short name T423
Test name
Test status
Simulation time 172722976495 ps
CPU time 2290.53 seconds
Started Aug 18 04:30:48 PM PDT 24
Finished Aug 18 05:08:59 PM PDT 24
Peak memory 288852 kb
Host smart-8b6452d8-3cf2-4a5b-8329-46a2eb82626a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976258976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1976258976
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1709489507
Short name T291
Test name
Test status
Simulation time 18417339745 ps
CPU time 162.32 seconds
Started Aug 18 04:30:41 PM PDT 24
Finished Aug 18 04:33:24 PM PDT 24
Peak memory 248732 kb
Host smart-25f967f3-c9f6-4c6f-a504-2864c0630db4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709489507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1709489507
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1702397825
Short name T707
Test name
Test status
Simulation time 5011077264 ps
CPU time 30.41 seconds
Started Aug 18 04:30:50 PM PDT 24
Finished Aug 18 04:31:21 PM PDT 24
Peak memory 256012 kb
Host smart-8893e7c4-2fe3-4fb5-b41a-aec389e36df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17023
97825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1702397825
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3158789947
Short name T429
Test name
Test status
Simulation time 57049764 ps
CPU time 4.39 seconds
Started Aug 18 04:30:37 PM PDT 24
Finished Aug 18 04:30:42 PM PDT 24
Peak memory 240460 kb
Host smart-d06149f6-ae03-4b75-b5b6-218ad823e8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31587
89947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3158789947
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2940952687
Short name T706
Test name
Test status
Simulation time 273760309 ps
CPU time 7.84 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 04:30:54 PM PDT 24
Peak memory 247964 kb
Host smart-d021b955-561d-4617-8c9e-98c83111fcb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29409
52687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2940952687
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4208288409
Short name T541
Test name
Test status
Simulation time 2413131479 ps
CPU time 42.18 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 04:31:28 PM PDT 24
Peak memory 256916 kb
Host smart-020c26ed-2c3b-463f-981d-8aed5a2872bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42082
88409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4208288409
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2148172688
Short name T183
Test name
Test status
Simulation time 5004706297 ps
CPU time 89.88 seconds
Started Aug 18 04:30:45 PM PDT 24
Finished Aug 18 04:32:15 PM PDT 24
Peak memory 265292 kb
Host smart-43f96aa9-d2f8-462e-950a-59b7fb1152bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148172688 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2148172688
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.758447716
Short name T470
Test name
Test status
Simulation time 63619117707 ps
CPU time 1536 seconds
Started Aug 18 04:30:46 PM PDT 24
Finished Aug 18 04:56:22 PM PDT 24
Peak memory 289336 kb
Host smart-3a911e26-18bf-4a9d-93fb-d17178b911db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758447716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.758447716
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1064208996
Short name T266
Test name
Test status
Simulation time 3456799778 ps
CPU time 96.87 seconds
Started Aug 18 04:30:48 PM PDT 24
Finished Aug 18 04:32:25 PM PDT 24
Peak memory 256548 kb
Host smart-86506a76-bfa8-4924-8c69-7a957fac10a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
08996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1064208996
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.776880921
Short name T609
Test name
Test status
Simulation time 177888878 ps
CPU time 16.61 seconds
Started Aug 18 04:30:53 PM PDT 24
Finished Aug 18 04:31:10 PM PDT 24
Peak memory 256368 kb
Host smart-157cd968-ed4f-41fc-b37b-963f0875e819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77688
0921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.776880921
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1101983922
Short name T382
Test name
Test status
Simulation time 48301511696 ps
CPU time 2922.65 seconds
Started Aug 18 04:30:50 PM PDT 24
Finished Aug 18 05:19:33 PM PDT 24
Peak memory 289468 kb
Host smart-56f242dd-23dc-4619-8076-52d5eeaaa234
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101983922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1101983922
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3753940154
Short name T547
Test name
Test status
Simulation time 53418308454 ps
CPU time 250.06 seconds
Started Aug 18 04:30:51 PM PDT 24
Finished Aug 18 04:35:02 PM PDT 24
Peak memory 248348 kb
Host smart-72ad0dac-cbe9-43e1-ae2f-f609c2849983
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753940154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3753940154
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3507434558
Short name T391
Test name
Test status
Simulation time 614353849 ps
CPU time 39.83 seconds
Started Aug 18 04:30:50 PM PDT 24
Finished Aug 18 04:31:30 PM PDT 24
Peak memory 256852 kb
Host smart-288b5dcc-8d81-4bfd-b485-74c146010327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35074
34558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3507434558
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.438826897
Short name T531
Test name
Test status
Simulation time 3756192973 ps
CPU time 54.6 seconds
Started Aug 18 04:30:47 PM PDT 24
Finished Aug 18 04:31:41 PM PDT 24
Peak memory 248728 kb
Host smart-8a9a8896-cd58-4bee-a538-2618aa89048e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43882
6897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.438826897
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.419783461
Short name T110
Test name
Test status
Simulation time 793640508 ps
CPU time 46.06 seconds
Started Aug 18 04:30:52 PM PDT 24
Finished Aug 18 04:31:38 PM PDT 24
Peak memory 248604 kb
Host smart-5c336e87-3ca0-44b3-9665-a4c926ddff38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41978
3461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.419783461
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.335960119
Short name T336
Test name
Test status
Simulation time 306998866 ps
CPU time 12.62 seconds
Started Aug 18 04:30:50 PM PDT 24
Finished Aug 18 04:31:03 PM PDT 24
Peak memory 248852 kb
Host smart-4aee527a-0999-446f-9f5a-0006ca37e4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33596
0119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.335960119
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1711948832
Short name T76
Test name
Test status
Simulation time 168892078827 ps
CPU time 2331.23 seconds
Started Aug 18 04:30:56 PM PDT 24
Finished Aug 18 05:09:47 PM PDT 24
Peak memory 286332 kb
Host smart-a91bc8a2-394c-4ad3-8839-db92af19f163
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711948832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1711948832
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1080077101
Short name T608
Test name
Test status
Simulation time 14281856041 ps
CPU time 297.45 seconds
Started Aug 18 04:30:53 PM PDT 24
Finished Aug 18 04:35:51 PM PDT 24
Peak memory 256492 kb
Host smart-bfbb869b-c588-454d-97d5-a713ddbb4bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10800
77101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1080077101
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.4189471918
Short name T396
Test name
Test status
Simulation time 1215082136 ps
CPU time 36.79 seconds
Started Aug 18 04:30:50 PM PDT 24
Finished Aug 18 04:31:27 PM PDT 24
Peak memory 256924 kb
Host smart-d00a0f88-d4ef-48a2-89db-fb203c6c5be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41894
71918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.4189471918
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2595041674
Short name T589
Test name
Test status
Simulation time 35792411556 ps
CPU time 1577.16 seconds
Started Aug 18 04:30:54 PM PDT 24
Finished Aug 18 04:57:11 PM PDT 24
Peak memory 289252 kb
Host smart-24796fc0-ed1e-4ed8-bd13-9e8bb91f9c41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595041674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2595041674
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2199277778
Short name T264
Test name
Test status
Simulation time 8859087058 ps
CPU time 882.63 seconds
Started Aug 18 04:30:50 PM PDT 24
Finished Aug 18 04:45:32 PM PDT 24
Peak memory 273288 kb
Host smart-af882bcd-1458-4e39-95cf-a1c6a27bc5dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199277778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2199277778
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3645983126
Short name T300
Test name
Test status
Simulation time 31251525051 ps
CPU time 448.24 seconds
Started Aug 18 04:30:53 PM PDT 24
Finished Aug 18 04:38:22 PM PDT 24
Peak memory 248692 kb
Host smart-01bf694e-8b13-48f8-95fe-2ff6fa57ce84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645983126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3645983126
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1489110618
Short name T511
Test name
Test status
Simulation time 185838180 ps
CPU time 16.85 seconds
Started Aug 18 04:30:55 PM PDT 24
Finished Aug 18 04:31:12 PM PDT 24
Peak memory 248732 kb
Host smart-7c6fb31a-0515-48a4-b29a-f0cea509ad7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14891
10618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1489110618
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3571890252
Short name T619
Test name
Test status
Simulation time 15661976373 ps
CPU time 54.46 seconds
Started Aug 18 04:30:47 PM PDT 24
Finished Aug 18 04:31:42 PM PDT 24
Peak memory 256500 kb
Host smart-98ea343f-a394-4c29-862a-5af071557bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35718
90252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3571890252
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2308729470
Short name T516
Test name
Test status
Simulation time 3255597196 ps
CPU time 24.03 seconds
Started Aug 18 04:30:53 PM PDT 24
Finished Aug 18 04:31:17 PM PDT 24
Peak memory 256132 kb
Host smart-a3256966-0380-4dab-8f5e-67a3025db866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23087
29470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2308729470
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3505518807
Short name T472
Test name
Test status
Simulation time 154922127 ps
CPU time 13.5 seconds
Started Aug 18 04:30:50 PM PDT 24
Finished Aug 18 04:31:03 PM PDT 24
Peak memory 256904 kb
Host smart-6a635704-381e-418b-90ef-60e5fd547b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35055
18807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3505518807
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.189738225
Short name T559
Test name
Test status
Simulation time 78356623468 ps
CPU time 1965.74 seconds
Started Aug 18 04:30:47 PM PDT 24
Finished Aug 18 05:03:33 PM PDT 24
Peak memory 282556 kb
Host smart-9e313499-c84a-4575-b338-f45c2149b46d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189738225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.189738225
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3257940900
Short name T103
Test name
Test status
Simulation time 5655679523 ps
CPU time 699.56 seconds
Started Aug 18 04:30:53 PM PDT 24
Finished Aug 18 04:42:33 PM PDT 24
Peak memory 273144 kb
Host smart-53907fe4-efa2-47a7-8ebb-5a73197a5951
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257940900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3257940900
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3005281593
Short name T605
Test name
Test status
Simulation time 2566791886 ps
CPU time 50.82 seconds
Started Aug 18 04:30:49 PM PDT 24
Finished Aug 18 04:31:40 PM PDT 24
Peak memory 256504 kb
Host smart-b0b4192d-4a88-4ac5-bfec-82e2f1281de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30052
81593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3005281593
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1785414324
Short name T551
Test name
Test status
Simulation time 197799627 ps
CPU time 22 seconds
Started Aug 18 04:30:49 PM PDT 24
Finished Aug 18 04:31:11 PM PDT 24
Peak memory 256372 kb
Host smart-f569e627-920b-4c5a-a0ad-3a891f6d969e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17854
14324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1785414324
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.615404760
Short name T498
Test name
Test status
Simulation time 40985223082 ps
CPU time 626.75 seconds
Started Aug 18 04:30:54 PM PDT 24
Finished Aug 18 04:41:21 PM PDT 24
Peak memory 265044 kb
Host smart-fbd88b6b-ebc8-4431-b5fd-012e6e40c6dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615404760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.615404760
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3825340658
Short name T520
Test name
Test status
Simulation time 66941122311 ps
CPU time 1204.45 seconds
Started Aug 18 04:30:52 PM PDT 24
Finished Aug 18 04:50:56 PM PDT 24
Peak memory 273264 kb
Host smart-05a1af03-8d7b-4663-b322-5cbc0285b1d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825340658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3825340658
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2754226615
Short name T296
Test name
Test status
Simulation time 18781333915 ps
CPU time 378.5 seconds
Started Aug 18 04:30:55 PM PDT 24
Finished Aug 18 04:37:14 PM PDT 24
Peak memory 248736 kb
Host smart-5fe6c55f-5a2d-484e-844b-f3e16755d8cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754226615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2754226615
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.994817969
Short name T353
Test name
Test status
Simulation time 1210786413 ps
CPU time 19.15 seconds
Started Aug 18 04:30:49 PM PDT 24
Finished Aug 18 04:31:09 PM PDT 24
Peak memory 255020 kb
Host smart-047812fe-f87f-4535-99d2-98b9c44bdfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99481
7969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.994817969
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4053947008
Short name T69
Test name
Test status
Simulation time 492961101 ps
CPU time 28.69 seconds
Started Aug 18 04:30:53 PM PDT 24
Finished Aug 18 04:31:22 PM PDT 24
Peak memory 248248 kb
Host smart-612be756-efa9-4b1b-b1d9-c968e1f0407a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40539
47008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4053947008
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.432581586
Short name T598
Test name
Test status
Simulation time 131061644 ps
CPU time 10.94 seconds
Started Aug 18 04:30:52 PM PDT 24
Finished Aug 18 04:31:03 PM PDT 24
Peak memory 248684 kb
Host smart-683bd169-afdd-410e-9785-750a29cdd44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43258
1586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.432581586
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1156424508
Short name T259
Test name
Test status
Simulation time 18678951242 ps
CPU time 1440.84 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 04:54:58 PM PDT 24
Peak memory 289692 kb
Host smart-79032aaa-bb01-4088-9e3e-3aec15bc14c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156424508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1156424508
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2871571818
Short name T243
Test name
Test status
Simulation time 1700433281 ps
CPU time 198.36 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 04:34:16 PM PDT 24
Peak memory 266896 kb
Host smart-24956e6b-60d5-479d-aa05-5da0a676fbb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871571818 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2871571818
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2681070492
Short name T469
Test name
Test status
Simulation time 36198819525 ps
CPU time 1937.79 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 05:03:16 PM PDT 24
Peak memory 282748 kb
Host smart-1b124986-b0a7-4b09-9175-3df3aed2abff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681070492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2681070492
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2601310218
Short name T435
Test name
Test status
Simulation time 208560935 ps
CPU time 4.35 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 04:31:02 PM PDT 24
Peak memory 240044 kb
Host smart-b05d4131-3d4c-4de2-b0dd-011510735ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26013
10218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2601310218
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.29988371
Short name T700
Test name
Test status
Simulation time 818239636 ps
CPU time 46.73 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 04:31:45 PM PDT 24
Peak memory 248120 kb
Host smart-bc587f54-e5cc-4873-a38b-b411e8411ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.29988371
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3332360413
Short name T217
Test name
Test status
Simulation time 135218985567 ps
CPU time 2075.03 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 05:05:33 PM PDT 24
Peak memory 289256 kb
Host smart-613fcb34-4fc8-49e0-ba90-41a4d56ca990
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332360413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3332360413
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.827256593
Short name T16
Test name
Test status
Simulation time 80924911707 ps
CPU time 419.17 seconds
Started Aug 18 04:30:59 PM PDT 24
Finished Aug 18 04:37:58 PM PDT 24
Peak memory 255588 kb
Host smart-4e3d5aa7-d6ea-40ea-9dcc-b863c2324860
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827256593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.827256593
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2252292753
Short name T483
Test name
Test status
Simulation time 856639267 ps
CPU time 47.45 seconds
Started Aug 18 04:31:00 PM PDT 24
Finished Aug 18 04:31:48 PM PDT 24
Peak memory 256252 kb
Host smart-5f22bf66-a1da-455d-8d3f-980280a3bc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22522
92753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2252292753
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.4263064911
Short name T631
Test name
Test status
Simulation time 7139370233 ps
CPU time 43.62 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 04:31:42 PM PDT 24
Peak memory 256216 kb
Host smart-e4ce3c9f-0ea3-427f-b985-f7c4017b5176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42630
64911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4263064911
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.18710307
Short name T601
Test name
Test status
Simulation time 3774778497 ps
CPU time 49.35 seconds
Started Aug 18 04:31:00 PM PDT 24
Finished Aug 18 04:31:50 PM PDT 24
Peak memory 256888 kb
Host smart-e6fc94a3-0637-4e1e-bf13-c1763ed0d89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18710
307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.18710307
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2266915029
Short name T276
Test name
Test status
Simulation time 22203008810 ps
CPU time 1310.84 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 04:52:49 PM PDT 24
Peak memory 289664 kb
Host smart-e80cfc73-cbf5-4ddd-ad9a-6e687ff5e968
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266915029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2266915029
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.377043864
Short name T28
Test name
Test status
Simulation time 2770477290 ps
CPU time 192.64 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 04:34:11 PM PDT 24
Peak memory 265436 kb
Host smart-e75d3b1e-9dcd-4e95-b837-e94255392a17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377043864 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.377043864
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.229228036
Short name T632
Test name
Test status
Simulation time 20410267088 ps
CPU time 1035.32 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 04:48:13 PM PDT 24
Peak memory 281604 kb
Host smart-4506030a-e70b-4e96-8e02-79373dc4a50d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229228036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.229228036
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3891323189
Short name T679
Test name
Test status
Simulation time 2125182851 ps
CPU time 128.65 seconds
Started Aug 18 04:30:59 PM PDT 24
Finished Aug 18 04:33:08 PM PDT 24
Peak memory 256816 kb
Host smart-0634af8d-f90b-4618-959d-7727bb9700c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38913
23189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3891323189
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.4002588278
Short name T74
Test name
Test status
Simulation time 92024382 ps
CPU time 4.28 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 04:31:03 PM PDT 24
Peak memory 240592 kb
Host smart-29f43fb0-90a6-44b4-a666-4da8c25c17a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40025
88278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.4002588278
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1830559016
Short name T373
Test name
Test status
Simulation time 66663360052 ps
CPU time 1286.19 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 04:52:24 PM PDT 24
Peak memory 265064 kb
Host smart-572942d2-844a-44c7-a09e-6238bbb527c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830559016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1830559016
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1669462213
Short name T229
Test name
Test status
Simulation time 9722532300 ps
CPU time 382.04 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 04:37:20 PM PDT 24
Peak memory 248716 kb
Host smart-bc1dc9f4-0648-4771-ab28-c1f8ab475699
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669462213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1669462213
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.420409640
Short name T29
Test name
Test status
Simulation time 331127394 ps
CPU time 30.44 seconds
Started Aug 18 04:31:00 PM PDT 24
Finished Aug 18 04:31:31 PM PDT 24
Peak memory 256288 kb
Host smart-b308133c-5598-4b76-b684-d031a3a7f1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42040
9640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.420409640
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.542741336
Short name T402
Test name
Test status
Simulation time 36539372 ps
CPU time 7.18 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 04:31:04 PM PDT 24
Peak memory 240484 kb
Host smart-dcf77fa9-8e41-465e-8860-eb418b7e5ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54274
1336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.542741336
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.74438964
Short name T588
Test name
Test status
Simulation time 220446768 ps
CPU time 26.91 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 04:31:25 PM PDT 24
Peak memory 248276 kb
Host smart-b0daf8d2-3c3a-45f9-8263-04b4c63f181c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74438
964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.74438964
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3476486769
Short name T561
Test name
Test status
Simulation time 974871168 ps
CPU time 17.57 seconds
Started Aug 18 04:31:01 PM PDT 24
Finished Aug 18 04:31:19 PM PDT 24
Peak memory 256720 kb
Host smart-0b8d7a0d-135c-434e-bee6-c342315dd621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34764
86769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3476486769
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2539384145
Short name T279
Test name
Test status
Simulation time 285777372865 ps
CPU time 2639.26 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 05:14:57 PM PDT 24
Peak memory 289468 kb
Host smart-3362c1c3-9a28-4e92-8124-ecfb6c960232
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539384145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2539384145
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3911673949
Short name T27
Test name
Test status
Simulation time 14814197132 ps
CPU time 167.09 seconds
Started Aug 18 04:30:59 PM PDT 24
Finished Aug 18 04:33:46 PM PDT 24
Peak memory 273376 kb
Host smart-2d3f401c-754b-40a0-aae7-50b374195484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911673949 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3911673949
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2068590250
Short name T430
Test name
Test status
Simulation time 35623184338 ps
CPU time 2436.39 seconds
Started Aug 18 04:30:57 PM PDT 24
Finished Aug 18 05:11:33 PM PDT 24
Peak memory 289312 kb
Host smart-897dea20-ad73-42e4-a980-35e9a1b458a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068590250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2068590250
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1442506729
Short name T440
Test name
Test status
Simulation time 4039059611 ps
CPU time 141.05 seconds
Started Aug 18 04:30:56 PM PDT 24
Finished Aug 18 04:33:17 PM PDT 24
Peak memory 256944 kb
Host smart-9d3265f9-f702-4a02-9b87-fd5166aae3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14425
06729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1442506729
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1069638123
Short name T538
Test name
Test status
Simulation time 79303122 ps
CPU time 3.18 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 04:31:01 PM PDT 24
Peak memory 240172 kb
Host smart-149f6c60-fbdd-42ac-a461-14927becdf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10696
38123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1069638123
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1196069920
Short name T314
Test name
Test status
Simulation time 133506367725 ps
CPU time 1936.42 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 05:03:23 PM PDT 24
Peak memory 283552 kb
Host smart-21a75e80-1644-4fbc-87d8-a7c0700bbf27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196069920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1196069920
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3206628085
Short name T695
Test name
Test status
Simulation time 17646532630 ps
CPU time 1459.54 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:55:26 PM PDT 24
Peak memory 289400 kb
Host smart-7b049ee0-82fe-4e13-b1f8-4c87070bc073
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206628085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3206628085
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2314732676
Short name T356
Test name
Test status
Simulation time 940186931 ps
CPU time 22.63 seconds
Started Aug 18 04:30:58 PM PDT 24
Finished Aug 18 04:31:20 PM PDT 24
Peak memory 256092 kb
Host smart-c7298680-f822-451a-9bbc-34fd8f01815b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23147
32676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2314732676
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.139503200
Short name T60
Test name
Test status
Simulation time 1257751261 ps
CPU time 75.06 seconds
Started Aug 18 04:31:00 PM PDT 24
Finished Aug 18 04:32:15 PM PDT 24
Peak memory 248196 kb
Host smart-4d573e0e-e68e-4f1f-bc37-4780adeb7c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13950
3200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.139503200
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2747657554
Short name T366
Test name
Test status
Simulation time 225628282 ps
CPU time 12.8 seconds
Started Aug 18 04:30:59 PM PDT 24
Finished Aug 18 04:31:12 PM PDT 24
Peak memory 254120 kb
Host smart-cbb9b6a8-2bbe-4715-9378-df0618280e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27476
57554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2747657554
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3822739886
Short name T21
Test name
Test status
Simulation time 1488459491 ps
CPU time 34.46 seconds
Started Aug 18 04:31:00 PM PDT 24
Finished Aug 18 04:31:35 PM PDT 24
Peak memory 256976 kb
Host smart-db202037-5f06-4f34-a9f0-e6c2f4d5491e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
39886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3822739886
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1108631656
Short name T195
Test name
Test status
Simulation time 294084600 ps
CPU time 3.49 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:30:19 PM PDT 24
Peak memory 248800 kb
Host smart-0177de48-349f-4425-b139-c30a2756ad2a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1108631656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1108631656
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3313598199
Short name T361
Test name
Test status
Simulation time 39524293981 ps
CPU time 2091.71 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 05:04:50 PM PDT 24
Peak memory 288964 kb
Host smart-c8f1c6a3-ebbd-462a-8480-7cd4573ae133
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313598199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3313598199
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4083988112
Short name T590
Test name
Test status
Simulation time 707454970 ps
CPU time 9.93 seconds
Started Aug 18 04:30:00 PM PDT 24
Finished Aug 18 04:30:10 PM PDT 24
Peak memory 248600 kb
Host smart-fa7d9d09-669f-4ef3-88df-abc5468f13c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4083988112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4083988112
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3076902111
Short name T433
Test name
Test status
Simulation time 5043168607 ps
CPU time 75.31 seconds
Started Aug 18 04:30:10 PM PDT 24
Finished Aug 18 04:31:25 PM PDT 24
Peak memory 249708 kb
Host smart-7267d4b7-ba98-4386-9409-554b009b979e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30769
02111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3076902111
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2575496855
Short name T597
Test name
Test status
Simulation time 354665833 ps
CPU time 17.25 seconds
Started Aug 18 04:30:06 PM PDT 24
Finished Aug 18 04:30:23 PM PDT 24
Peak memory 248260 kb
Host smart-c9eaa415-df8b-4f6d-999d-c9a357f80d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25754
96855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2575496855
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2788867200
Short name T627
Test name
Test status
Simulation time 21840985095 ps
CPU time 1340.89 seconds
Started Aug 18 04:30:02 PM PDT 24
Finished Aug 18 04:52:23 PM PDT 24
Peak memory 272516 kb
Host smart-cb6c7189-be73-4da1-af37-216108210f62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788867200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2788867200
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.448163223
Short name T568
Test name
Test status
Simulation time 8249467610 ps
CPU time 767.88 seconds
Started Aug 18 04:30:02 PM PDT 24
Finished Aug 18 04:42:51 PM PDT 24
Peak memory 265172 kb
Host smart-2a21dd00-0469-47a3-9a50-f2191c8fbe82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448163223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.448163223
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3472728382
Short name T697
Test name
Test status
Simulation time 19268998177 ps
CPU time 359 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:35:57 PM PDT 24
Peak memory 255472 kb
Host smart-ab3453dd-7481-4461-8531-dd203bc24663
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472728382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3472728382
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1216564730
Short name T613
Test name
Test status
Simulation time 2299771998 ps
CPU time 34.61 seconds
Started Aug 18 04:29:55 PM PDT 24
Finished Aug 18 04:30:30 PM PDT 24
Peak memory 256764 kb
Host smart-24d7ff99-136e-482e-8da3-9faa45da3a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12165
64730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1216564730
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3419252309
Short name T633
Test name
Test status
Simulation time 1218570374 ps
CPU time 8.97 seconds
Started Aug 18 04:30:01 PM PDT 24
Finished Aug 18 04:30:10 PM PDT 24
Peak memory 252316 kb
Host smart-7cd0fe98-cd18-44b5-9fb5-9cce8f62d3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34192
52309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3419252309
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3608735977
Short name T241
Test name
Test status
Simulation time 3287817102 ps
CPU time 48.68 seconds
Started Aug 18 04:30:00 PM PDT 24
Finished Aug 18 04:30:49 PM PDT 24
Peak memory 248296 kb
Host smart-23962f01-0c92-4000-b5a6-42665fc5e179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36087
35977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3608735977
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2710416401
Short name T576
Test name
Test status
Simulation time 1260523034 ps
CPU time 64.97 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:31:04 PM PDT 24
Peak memory 248608 kb
Host smart-f79f42c8-a7ca-4fa9-b005-39977fd5e41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27104
16401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2710416401
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2474281759
Short name T81
Test name
Test status
Simulation time 175481363830 ps
CPU time 2268.63 seconds
Started Aug 18 04:30:00 PM PDT 24
Finished Aug 18 05:07:49 PM PDT 24
Peak memory 285428 kb
Host smart-bc544662-63d4-485a-a92b-5449bb24e5c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474281759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2474281759
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.334784853
Short name T83
Test name
Test status
Simulation time 12592727779 ps
CPU time 330.59 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:35:29 PM PDT 24
Peak memory 266912 kb
Host smart-6603e8a0-d940-48cc-920e-94ea2114a026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334784853 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.334784853
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2214215989
Short name T650
Test name
Test status
Simulation time 61392429565 ps
CPU time 3438.2 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 05:28:24 PM PDT 24
Peak memory 289596 kb
Host smart-c9fc7d29-d668-497b-9d25-a37e87c88f52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214215989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2214215989
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2596005840
Short name T702
Test name
Test status
Simulation time 19583887178 ps
CPU time 161.69 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:33:48 PM PDT 24
Peak memory 256992 kb
Host smart-334275db-ef2e-4c84-a498-6d08180656be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25960
05840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2596005840
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2031025190
Short name T649
Test name
Test status
Simulation time 715801508 ps
CPU time 34.81 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 04:31:43 PM PDT 24
Peak memory 248616 kb
Host smart-c43167a0-0ee4-479e-913a-638a5ae438b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20310
25190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2031025190
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.622024240
Short name T573
Test name
Test status
Simulation time 22508474377 ps
CPU time 1309.2 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:52:55 PM PDT 24
Peak memory 289428 kb
Host smart-21f94494-8d41-4af1-85be-b1940c241a69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622024240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.622024240
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.189343939
Short name T688
Test name
Test status
Simulation time 10276626776 ps
CPU time 439.87 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:38:26 PM PDT 24
Peak memory 248460 kb
Host smart-ad535b4c-0653-4f2a-8571-b2236dd9ca32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189343939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.189343939
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.750262899
Short name T31
Test name
Test status
Simulation time 2351269776 ps
CPU time 38.68 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:31:46 PM PDT 24
Peak memory 256924 kb
Host smart-e950821b-d921-4456-b6d4-dbf26252f3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75026
2899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.750262899
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3927226496
Short name T447
Test name
Test status
Simulation time 1174403875 ps
CPU time 30.02 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:31:36 PM PDT 24
Peak memory 256428 kb
Host smart-4f338406-d013-482e-acf0-391d1f58ae02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39272
26496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3927226496
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2473119582
Short name T490
Test name
Test status
Simulation time 66072219 ps
CPU time 8.26 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:31:15 PM PDT 24
Peak memory 254820 kb
Host smart-a7606049-5f83-4131-89f8-712b45815514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24731
19582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2473119582
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1804558620
Short name T593
Test name
Test status
Simulation time 172494721 ps
CPU time 14.51 seconds
Started Aug 18 04:31:05 PM PDT 24
Finished Aug 18 04:31:20 PM PDT 24
Peak memory 256820 kb
Host smart-e761c682-3c8a-4b4e-9998-67e0f388b457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18045
58620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1804558620
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.328136433
Short name T56
Test name
Test status
Simulation time 1939393602 ps
CPU time 157.2 seconds
Started Aug 18 04:31:05 PM PDT 24
Finished Aug 18 04:33:43 PM PDT 24
Peak memory 256932 kb
Host smart-a440b9c4-f609-46e5-82d5-36cd3e6169fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328136433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.328136433
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.897433483
Short name T37
Test name
Test status
Simulation time 25145244265 ps
CPU time 1154.53 seconds
Started Aug 18 04:31:05 PM PDT 24
Finished Aug 18 04:50:20 PM PDT 24
Peak memory 272360 kb
Host smart-049a74c8-5412-4491-8dea-7c7c9cdf810d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897433483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.897433483
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.55223645
Short name T503
Test name
Test status
Simulation time 6767913754 ps
CPU time 217.6 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:34:45 PM PDT 24
Peak memory 256956 kb
Host smart-0e8c9120-7b9b-410f-9153-6e814a394533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55223
645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.55223645
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3738786692
Short name T439
Test name
Test status
Simulation time 929964855 ps
CPU time 22.03 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:31:28 PM PDT 24
Peak memory 255948 kb
Host smart-730a2e4a-a88c-4595-a90a-2478e010527b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37387
86692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3738786692
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3296801760
Short name T504
Test name
Test status
Simulation time 40956620489 ps
CPU time 715.72 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:43:02 PM PDT 24
Peak memory 273220 kb
Host smart-5a3edd07-3a4e-4f93-9d5b-e946d95676d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296801760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3296801760
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3811091759
Short name T528
Test name
Test status
Simulation time 9761218053 ps
CPU time 870.31 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:45:37 PM PDT 24
Peak memory 273244 kb
Host smart-b1276f14-05db-45a6-96c9-92bf59008c6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811091759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3811091759
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.4289066612
Short name T262
Test name
Test status
Simulation time 3190890093 ps
CPU time 130.38 seconds
Started Aug 18 04:31:10 PM PDT 24
Finished Aug 18 04:33:21 PM PDT 24
Peak memory 254244 kb
Host smart-28b2185f-a444-480e-b31c-9307f37fe5b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289066612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.4289066612
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.613373527
Short name T560
Test name
Test status
Simulation time 263118462 ps
CPU time 26.41 seconds
Started Aug 18 04:31:05 PM PDT 24
Finished Aug 18 04:31:32 PM PDT 24
Peak memory 256820 kb
Host smart-a8418639-108c-4ae2-82a6-3f0539cf7dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61337
3527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.613373527
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2636260406
Short name T223
Test name
Test status
Simulation time 1379069048 ps
CPU time 26.42 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 04:31:35 PM PDT 24
Peak memory 256248 kb
Host smart-7e1d3087-5222-492b-82a1-4d8c30f05c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26362
60406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2636260406
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1310722755
Short name T258
Test name
Test status
Simulation time 495579785 ps
CPU time 15.35 seconds
Started Aug 18 04:31:10 PM PDT 24
Finished Aug 18 04:31:26 PM PDT 24
Peak memory 256848 kb
Host smart-1654e37c-3bce-4962-a37b-5ed9bb9ee964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13107
22755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1310722755
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.564903182
Short name T473
Test name
Test status
Simulation time 543795723 ps
CPU time 16.54 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 04:31:24 PM PDT 24
Peak memory 256544 kb
Host smart-954434c9-a202-483c-9d9a-195525ffa319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56490
3182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.564903182
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2147248438
Short name T80
Test name
Test status
Simulation time 2831056876 ps
CPU time 161.04 seconds
Started Aug 18 04:31:05 PM PDT 24
Finished Aug 18 04:33:46 PM PDT 24
Peak memory 256964 kb
Host smart-b8cbc21f-b7db-4e17-9371-42c83929844c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147248438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2147248438
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4246483894
Short name T550
Test name
Test status
Simulation time 12572336741 ps
CPU time 1034.1 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:48:20 PM PDT 24
Peak memory 287028 kb
Host smart-836d1bb1-11a6-4058-aa7d-4024949c183a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246483894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4246483894
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1580927209
Short name T696
Test name
Test status
Simulation time 3595050338 ps
CPU time 123.59 seconds
Started Aug 18 04:31:10 PM PDT 24
Finished Aug 18 04:33:14 PM PDT 24
Peak memory 256600 kb
Host smart-b7d65835-70d6-4d4b-89bd-0dab967c8f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15809
27209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1580927209
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2918111203
Short name T625
Test name
Test status
Simulation time 834434313 ps
CPU time 57.3 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:32:04 PM PDT 24
Peak memory 248248 kb
Host smart-000b4f2f-c488-42ce-9e16-a2d6e68a5932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29181
11203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2918111203
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3931555901
Short name T572
Test name
Test status
Simulation time 107720192456 ps
CPU time 2547.79 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 05:13:36 PM PDT 24
Peak memory 285092 kb
Host smart-9e4e5522-b54f-4b7c-8c12-027913d7c2bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931555901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3931555901
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2641372985
Short name T359
Test name
Test status
Simulation time 193791925793 ps
CPU time 2649.05 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 05:15:17 PM PDT 24
Peak memory 289020 kb
Host smart-828a0a97-60f2-4765-ba08-2fb4337b7dc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641372985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2641372985
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3039920162
Short name T298
Test name
Test status
Simulation time 6296160635 ps
CPU time 245.57 seconds
Started Aug 18 04:31:10 PM PDT 24
Finished Aug 18 04:35:16 PM PDT 24
Peak memory 248532 kb
Host smart-240501ce-4da9-4163-89a1-feffd883ddc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039920162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3039920162
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1236184077
Short name T644
Test name
Test status
Simulation time 771717323 ps
CPU time 4.15 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 04:31:12 PM PDT 24
Peak memory 240516 kb
Host smart-69bcbd7f-435e-46e5-85c1-a6004fcfd085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12361
84077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1236184077
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.213401026
Short name T563
Test name
Test status
Simulation time 435255404 ps
CPU time 24.98 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:31:31 PM PDT 24
Peak memory 248304 kb
Host smart-e051de93-caa2-4720-bab5-e3128485762d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21340
1026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.213401026
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3437724287
Short name T350
Test name
Test status
Simulation time 8011270345 ps
CPU time 67.83 seconds
Started Aug 18 04:31:11 PM PDT 24
Finished Aug 18 04:32:19 PM PDT 24
Peak memory 248732 kb
Host smart-62898316-cacc-4d18-8337-5dad68966bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34377
24287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3437724287
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.4013899153
Short name T271
Test name
Test status
Simulation time 223427700098 ps
CPU time 1123.28 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:49:50 PM PDT 24
Peak memory 286912 kb
Host smart-03a2c957-c25c-4e58-b28f-9d4a0bc1bbbb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013899153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.4013899153
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2938663261
Short name T265
Test name
Test status
Simulation time 27393812976 ps
CPU time 1567.52 seconds
Started Aug 18 04:31:13 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 273316 kb
Host smart-684735f4-1871-44ad-9fb4-22072effe009
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938663261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2938663261
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.811721703
Short name T398
Test name
Test status
Simulation time 1220085116 ps
CPU time 68.33 seconds
Started Aug 18 04:31:14 PM PDT 24
Finished Aug 18 04:32:22 PM PDT 24
Peak memory 256888 kb
Host smart-a61c90bc-517a-457e-a499-0a7993067d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81172
1703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.811721703
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.111290379
Short name T535
Test name
Test status
Simulation time 2071720794 ps
CPU time 38.83 seconds
Started Aug 18 04:31:12 PM PDT 24
Finished Aug 18 04:31:51 PM PDT 24
Peak memory 256388 kb
Host smart-651e3573-6459-4a66-b0de-6ec24b7fe9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11129
0379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.111290379
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.289947761
Short name T315
Test name
Test status
Simulation time 13759344839 ps
CPU time 1456.77 seconds
Started Aug 18 04:31:16 PM PDT 24
Finished Aug 18 04:55:33 PM PDT 24
Peak memory 289736 kb
Host smart-e4aee8b6-5825-4bab-bbca-9777be1734c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289947761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.289947761
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1198663572
Short name T673
Test name
Test status
Simulation time 56463099784 ps
CPU time 927.15 seconds
Started Aug 18 04:31:17 PM PDT 24
Finished Aug 18 04:46:44 PM PDT 24
Peak memory 270640 kb
Host smart-0e2e877a-8125-4f5a-ae1e-a780aee4e162
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198663572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1198663572
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1476147116
Short name T290
Test name
Test status
Simulation time 69803685152 ps
CPU time 682.1 seconds
Started Aug 18 04:31:16 PM PDT 24
Finished Aug 18 04:42:38 PM PDT 24
Peak memory 247616 kb
Host smart-e8080030-e40c-4ca3-b7e4-435156c2b496
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476147116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1476147116
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.49593829
Short name T467
Test name
Test status
Simulation time 425508999 ps
CPU time 5.17 seconds
Started Aug 18 04:31:17 PM PDT 24
Finished Aug 18 04:31:22 PM PDT 24
Peak memory 248680 kb
Host smart-6521b365-7319-46da-a574-41c7477fbab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49593
829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.49593829
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3465229139
Short name T599
Test name
Test status
Simulation time 539260964 ps
CPU time 32.23 seconds
Started Aug 18 04:31:16 PM PDT 24
Finished Aug 18 04:31:48 PM PDT 24
Peak memory 248716 kb
Host smart-c21d63bc-1ee1-488c-bc66-c1dcc0968ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34652
29139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3465229139
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3607395303
Short name T77
Test name
Test status
Simulation time 5787905757 ps
CPU time 58.37 seconds
Started Aug 18 04:31:14 PM PDT 24
Finished Aug 18 04:32:13 PM PDT 24
Peak memory 248748 kb
Host smart-3e54125b-c655-462d-8ab3-66127dabd219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36073
95303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3607395303
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.281893707
Short name T442
Test name
Test status
Simulation time 1678867062 ps
CPU time 48.69 seconds
Started Aug 18 04:31:10 PM PDT 24
Finished Aug 18 04:31:58 PM PDT 24
Peak memory 256568 kb
Host smart-52484b67-a4d1-451b-9e10-3558aeea7c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28189
3707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.281893707
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3882454770
Short name T231
Test name
Test status
Simulation time 5479279339 ps
CPU time 196.04 seconds
Started Aug 18 04:31:14 PM PDT 24
Finished Aug 18 04:34:30 PM PDT 24
Peak memory 265596 kb
Host smart-13c089dc-9cb2-4c75-b7b1-6810ae2dd132
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882454770 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3882454770
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1658718660
Short name T481
Test name
Test status
Simulation time 46736274564 ps
CPU time 1353.84 seconds
Started Aug 18 04:31:17 PM PDT 24
Finished Aug 18 04:53:51 PM PDT 24
Peak memory 272932 kb
Host smart-9535dbff-7999-4a86-b7c7-4d8558110f6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658718660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1658718660
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.243129778
Short name T47
Test name
Test status
Simulation time 5037714277 ps
CPU time 109.09 seconds
Started Aug 18 04:31:17 PM PDT 24
Finished Aug 18 04:33:06 PM PDT 24
Peak memory 256952 kb
Host smart-8bab060d-887b-4271-a116-899a96fb69c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24312
9778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.243129778
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.605983972
Short name T73
Test name
Test status
Simulation time 804668673 ps
CPU time 9.76 seconds
Started Aug 18 04:31:16 PM PDT 24
Finished Aug 18 04:31:26 PM PDT 24
Peak memory 247984 kb
Host smart-a22f94e1-8a80-4bb8-8b4e-b79852a9047d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60598
3972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.605983972
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.785035146
Short name T317
Test name
Test status
Simulation time 147635835273 ps
CPU time 2665.41 seconds
Started Aug 18 04:31:15 PM PDT 24
Finished Aug 18 05:15:41 PM PDT 24
Peak memory 289556 kb
Host smart-b7863c58-e99f-4364-abf8-ecb03d9aed32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785035146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.785035146
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.411485403
Short name T491
Test name
Test status
Simulation time 27033422064 ps
CPU time 1620.5 seconds
Started Aug 18 04:31:13 PM PDT 24
Finished Aug 18 04:58:14 PM PDT 24
Peak memory 272952 kb
Host smart-3fca11b5-a234-427d-b7cd-c68053c61590
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411485403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.411485403
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3172704695
Short name T307
Test name
Test status
Simulation time 17030327756 ps
CPU time 345.89 seconds
Started Aug 18 04:31:15 PM PDT 24
Finished Aug 18 04:37:01 PM PDT 24
Peak memory 255628 kb
Host smart-c91d3148-5956-4767-8a08-b1e8554f2d9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172704695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3172704695
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.350631317
Short name T347
Test name
Test status
Simulation time 2266351223 ps
CPU time 25.54 seconds
Started Aug 18 04:31:16 PM PDT 24
Finished Aug 18 04:31:42 PM PDT 24
Peak memory 255952 kb
Host smart-07000294-e31f-4c4e-bc0a-57bb5f097316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35063
1317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.350631317
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3094914899
Short name T26
Test name
Test status
Simulation time 1046721221 ps
CPU time 34.54 seconds
Started Aug 18 04:31:13 PM PDT 24
Finished Aug 18 04:31:48 PM PDT 24
Peak memory 248460 kb
Host smart-83f26c9e-9f8d-4e8a-a115-5fd3455c1110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30949
14899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3094914899
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.128235790
Short name T11
Test name
Test status
Simulation time 2160181834 ps
CPU time 49.38 seconds
Started Aug 18 04:31:12 PM PDT 24
Finished Aug 18 04:32:02 PM PDT 24
Peak memory 256132 kb
Host smart-05c5e0db-2a77-4784-8536-db7702b6d734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12823
5790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.128235790
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2962414739
Short name T342
Test name
Test status
Simulation time 614035683 ps
CPU time 24.05 seconds
Started Aug 18 04:31:14 PM PDT 24
Finished Aug 18 04:31:38 PM PDT 24
Peak memory 256792 kb
Host smart-c7b38268-03c3-4da2-ac24-04f5625473e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29624
14739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2962414739
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.288055644
Short name T638
Test name
Test status
Simulation time 2221562277 ps
CPU time 144.31 seconds
Started Aug 18 04:31:14 PM PDT 24
Finished Aug 18 04:33:38 PM PDT 24
Peak memory 256912 kb
Host smart-c253659e-f1f2-4120-9f42-fec7ec2a7370
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288055644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.288055644
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2676653209
Short name T92
Test name
Test status
Simulation time 4962653393 ps
CPU time 460.83 seconds
Started Aug 18 04:31:15 PM PDT 24
Finished Aug 18 04:38:56 PM PDT 24
Peak memory 273504 kb
Host smart-0ca7c391-a2ec-46be-b130-0362b7a47bc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676653209 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2676653209
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.4182039913
Short name T424
Test name
Test status
Simulation time 17223163380 ps
CPU time 1426.73 seconds
Started Aug 18 04:31:28 PM PDT 24
Finished Aug 18 04:55:15 PM PDT 24
Peak memory 289380 kb
Host smart-b2c6d900-c40e-4d26-8aed-db03a476c1c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182039913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4182039913
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3112127886
Short name T671
Test name
Test status
Simulation time 6424285719 ps
CPU time 90.7 seconds
Started Aug 18 04:31:24 PM PDT 24
Finished Aug 18 04:32:55 PM PDT 24
Peak memory 249888 kb
Host smart-d503de7a-70b1-4fe2-b124-5fe2c73947b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31121
27886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3112127886
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1307479515
Short name T514
Test name
Test status
Simulation time 895304666 ps
CPU time 65.56 seconds
Started Aug 18 04:31:21 PM PDT 24
Finished Aug 18 04:32:27 PM PDT 24
Peak memory 248644 kb
Host smart-fa825a9e-613d-47dc-a973-c99892bc6df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13074
79515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1307479515
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.501220745
Short name T18
Test name
Test status
Simulation time 38988969971 ps
CPU time 2113.55 seconds
Started Aug 18 04:31:25 PM PDT 24
Finished Aug 18 05:06:39 PM PDT 24
Peak memory 273400 kb
Host smart-d44b1986-5f7c-4c24-8991-5137898cde67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501220745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.501220745
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2962264956
Short name T669
Test name
Test status
Simulation time 38930046852 ps
CPU time 2268.29 seconds
Started Aug 18 04:31:24 PM PDT 24
Finished Aug 18 05:09:13 PM PDT 24
Peak memory 287176 kb
Host smart-84855ba3-28a9-44c7-b3fb-e6a246faf439
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962264956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2962264956
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.71930709
Short name T554
Test name
Test status
Simulation time 18083062154 ps
CPU time 377.96 seconds
Started Aug 18 04:31:22 PM PDT 24
Finished Aug 18 04:37:40 PM PDT 24
Peak memory 248604 kb
Host smart-41466315-f728-4670-9753-bf590fb705ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71930709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.71930709
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1550904499
Short name T515
Test name
Test status
Simulation time 531721413 ps
CPU time 27.86 seconds
Started Aug 18 04:31:25 PM PDT 24
Finished Aug 18 04:31:53 PM PDT 24
Peak memory 255884 kb
Host smart-1aa46a17-e417-4ee9-bc85-2703cdc3a1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15509
04499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1550904499
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.4164023124
Short name T478
Test name
Test status
Simulation time 777672297 ps
CPU time 48.66 seconds
Started Aug 18 04:31:21 PM PDT 24
Finished Aug 18 04:32:09 PM PDT 24
Peak memory 248352 kb
Host smart-8ca2fdd8-8358-4af2-b8ce-34b60bacc095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41640
23124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.4164023124
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.753600316
Short name T256
Test name
Test status
Simulation time 795894123 ps
CPU time 20.9 seconds
Started Aug 18 04:31:21 PM PDT 24
Finished Aug 18 04:31:42 PM PDT 24
Peak memory 256164 kb
Host smart-cc8b6e6d-3210-4ec6-8164-d91c2b9c25f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75360
0316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.753600316
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2145866888
Short name T525
Test name
Test status
Simulation time 53836332 ps
CPU time 3.97 seconds
Started Aug 18 04:31:21 PM PDT 24
Finished Aug 18 04:31:25 PM PDT 24
Peak memory 250980 kb
Host smart-0eed624e-f2ae-4a5d-93ca-e33478005099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21458
66888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2145866888
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1598672390
Short name T624
Test name
Test status
Simulation time 6987300860 ps
CPU time 138.77 seconds
Started Aug 18 04:31:24 PM PDT 24
Finished Aug 18 04:33:43 PM PDT 24
Peak memory 265308 kb
Host smart-889fa7e4-aa2f-41c5-9431-c30e70978067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598672390 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1598672390
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.348036190
Short name T493
Test name
Test status
Simulation time 1499480768 ps
CPU time 38.55 seconds
Started Aug 18 04:31:22 PM PDT 24
Finished Aug 18 04:32:00 PM PDT 24
Peak memory 256412 kb
Host smart-9f177b06-7d7c-49c2-b18f-ac16716d3888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34803
6190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.348036190
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1364687840
Short name T665
Test name
Test status
Simulation time 112971952 ps
CPU time 8.05 seconds
Started Aug 18 04:31:24 PM PDT 24
Finished Aug 18 04:31:32 PM PDT 24
Peak memory 248096 kb
Host smart-f67bc50f-a1e1-47c0-a699-9018d8df157a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13646
87840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1364687840
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3084286956
Short name T323
Test name
Test status
Simulation time 174624559962 ps
CPU time 2637.53 seconds
Started Aug 18 04:31:24 PM PDT 24
Finished Aug 18 05:15:22 PM PDT 24
Peak memory 289676 kb
Host smart-392de303-7b6f-4ea2-8d6a-7ef4d224f1ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084286956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3084286956
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2556224615
Short name T360
Test name
Test status
Simulation time 37805644921 ps
CPU time 932.47 seconds
Started Aug 18 04:31:28 PM PDT 24
Finished Aug 18 04:47:01 PM PDT 24
Peak memory 284328 kb
Host smart-8cf145d1-82a9-4370-8f82-236ff0555861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556224615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2556224615
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3424167640
Short name T211
Test name
Test status
Simulation time 13846173674 ps
CPU time 302.05 seconds
Started Aug 18 04:31:23 PM PDT 24
Finished Aug 18 04:36:25 PM PDT 24
Peak memory 248684 kb
Host smart-f090bf17-0dc4-494e-93aa-0367b0e9dad6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424167640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3424167640
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2231195272
Short name T365
Test name
Test status
Simulation time 356612573 ps
CPU time 27.06 seconds
Started Aug 18 04:31:21 PM PDT 24
Finished Aug 18 04:31:48 PM PDT 24
Peak memory 256048 kb
Host smart-6e52a933-a9ed-4e3b-bbec-0c7ab096e916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22311
95272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2231195272
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.957091629
Short name T445
Test name
Test status
Simulation time 633708595 ps
CPU time 14.62 seconds
Started Aug 18 04:31:20 PM PDT 24
Finished Aug 18 04:31:35 PM PDT 24
Peak memory 256492 kb
Host smart-403f8231-e175-4958-b21a-f73c5472ac1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95709
1629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.957091629
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3973678556
Short name T249
Test name
Test status
Simulation time 207497945 ps
CPU time 14.68 seconds
Started Aug 18 04:31:25 PM PDT 24
Finished Aug 18 04:31:40 PM PDT 24
Peak memory 248364 kb
Host smart-ef20ce4b-4378-4715-bb03-f13b72f54dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39736
78556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3973678556
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.167828324
Short name T346
Test name
Test status
Simulation time 2462958992 ps
CPU time 40.23 seconds
Started Aug 18 04:31:23 PM PDT 24
Finished Aug 18 04:32:04 PM PDT 24
Peak memory 256904 kb
Host smart-4e4a45a9-0aa2-4a38-b37c-111292682eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782
8324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.167828324
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2010531630
Short name T98
Test name
Test status
Simulation time 60043581111 ps
CPU time 1871.84 seconds
Started Aug 18 04:31:25 PM PDT 24
Finished Aug 18 05:02:38 PM PDT 24
Peak memory 289484 kb
Host smart-92f874e0-a445-4600-963e-2f50a49c604f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010531630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2010531630
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.211175316
Short name T379
Test name
Test status
Simulation time 155803405870 ps
CPU time 2396.94 seconds
Started Aug 18 04:31:21 PM PDT 24
Finished Aug 18 05:11:18 PM PDT 24
Peak memory 281456 kb
Host smart-571ec339-ad41-4573-8eac-926d5ee36b56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211175316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.211175316
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.296490805
Short name T658
Test name
Test status
Simulation time 11881394966 ps
CPU time 128.69 seconds
Started Aug 18 04:31:21 PM PDT 24
Finished Aug 18 04:33:30 PM PDT 24
Peak memory 256504 kb
Host smart-f5180531-ac18-4625-8b1e-43b7f93b0d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29649
0805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.296490805
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2397475105
Short name T23
Test name
Test status
Simulation time 1094274318 ps
CPU time 26.89 seconds
Started Aug 18 04:31:29 PM PDT 24
Finished Aug 18 04:31:56 PM PDT 24
Peak memory 248368 kb
Host smart-43af8a7f-27d1-4258-bfed-bcd4b5b89ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23974
75105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2397475105
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.148463311
Short name T326
Test name
Test status
Simulation time 165433751887 ps
CPU time 1822.98 seconds
Started Aug 18 04:31:24 PM PDT 24
Finished Aug 18 05:01:48 PM PDT 24
Peak memory 282448 kb
Host smart-64fc779a-6bf2-47d7-a67b-8cb17e3f2117
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148463311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.148463311
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1131872410
Short name T19
Test name
Test status
Simulation time 32721169624 ps
CPU time 885.08 seconds
Started Aug 18 04:31:28 PM PDT 24
Finished Aug 18 04:46:13 PM PDT 24
Peak memory 268220 kb
Host smart-52f4defd-5948-4e68-a588-1a09896aa7fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131872410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1131872410
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3346223630
Short name T635
Test name
Test status
Simulation time 10672879389 ps
CPU time 447.12 seconds
Started Aug 18 04:31:22 PM PDT 24
Finished Aug 18 04:38:50 PM PDT 24
Peak memory 248720 kb
Host smart-7dad26ff-42c9-4bfa-8aa8-ba9e58e6cda5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346223630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3346223630
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4007978546
Short name T386
Test name
Test status
Simulation time 414401185 ps
CPU time 32.49 seconds
Started Aug 18 04:31:28 PM PDT 24
Finished Aug 18 04:32:01 PM PDT 24
Peak memory 248724 kb
Host smart-a2fe327e-acfb-40e7-b646-8f66f10ba205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40079
78546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4007978546
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.533504495
Short name T15
Test name
Test status
Simulation time 567437972 ps
CPU time 19.1 seconds
Started Aug 18 04:31:29 PM PDT 24
Finished Aug 18 04:31:48 PM PDT 24
Peak memory 255224 kb
Host smart-f4be7f36-1753-4333-a98e-5c071d214403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53350
4495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.533504495
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.907655415
Short name T581
Test name
Test status
Simulation time 202204834 ps
CPU time 13.9 seconds
Started Aug 18 04:31:21 PM PDT 24
Finished Aug 18 04:31:35 PM PDT 24
Peak memory 248680 kb
Host smart-010ec5e8-4320-4486-969d-bec04a245502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90765
5415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.907655415
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.504848935
Short name T634
Test name
Test status
Simulation time 1077367889 ps
CPU time 33.96 seconds
Started Aug 18 04:31:25 PM PDT 24
Finished Aug 18 04:31:59 PM PDT 24
Peak memory 256860 kb
Host smart-e7445c8e-10ff-42c6-ba30-af32779554d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50484
8935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.504848935
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1958363292
Short name T97
Test name
Test status
Simulation time 69442859863 ps
CPU time 1494.19 seconds
Started Aug 18 04:31:22 PM PDT 24
Finished Aug 18 04:56:17 PM PDT 24
Peak memory 289428 kb
Host smart-a106d669-0f3e-455f-b87f-415c2805eecc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958363292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1958363292
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3026471679
Short name T496
Test name
Test status
Simulation time 8269389423 ps
CPU time 149.27 seconds
Started Aug 18 04:31:22 PM PDT 24
Finished Aug 18 04:33:52 PM PDT 24
Peak memory 272108 kb
Host smart-cf011965-35bc-4c74-a537-40311d08026a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026471679 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3026471679
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3857560497
Short name T529
Test name
Test status
Simulation time 51113988787 ps
CPU time 3032.87 seconds
Started Aug 18 04:31:23 PM PDT 24
Finished Aug 18 05:21:56 PM PDT 24
Peak memory 289168 kb
Host smart-e77e6ab3-cb73-4b64-b8f3-a1d310fc9c23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857560497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3857560497
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.928761876
Short name T212
Test name
Test status
Simulation time 1532511002 ps
CPU time 127.21 seconds
Started Aug 18 04:31:23 PM PDT 24
Finished Aug 18 04:33:31 PM PDT 24
Peak memory 256816 kb
Host smart-31c7d290-4cd6-4842-8a02-d519cb417db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92876
1876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.928761876
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2072723832
Short name T636
Test name
Test status
Simulation time 1531329242 ps
CPU time 27.56 seconds
Started Aug 18 04:31:28 PM PDT 24
Finished Aug 18 04:31:56 PM PDT 24
Peak memory 248520 kb
Host smart-1672202e-343e-4f95-8e07-c3cb3395ca86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20727
23832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2072723832
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.43441153
Short name T230
Test name
Test status
Simulation time 96632520237 ps
CPU time 1547.12 seconds
Started Aug 18 04:31:34 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 265032 kb
Host smart-6a94e892-bee2-4302-a023-3f79005019f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43441153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.43441153
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2922073945
Short name T596
Test name
Test status
Simulation time 11036275469 ps
CPU time 1198.43 seconds
Started Aug 18 04:31:39 PM PDT 24
Finished Aug 18 04:51:38 PM PDT 24
Peak memory 287332 kb
Host smart-43901e19-9f54-4a1b-a693-4f4f1a8dc774
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922073945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2922073945
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2190178718
Short name T297
Test name
Test status
Simulation time 31325126560 ps
CPU time 328.67 seconds
Started Aug 18 04:31:38 PM PDT 24
Finished Aug 18 04:37:06 PM PDT 24
Peak memory 256876 kb
Host smart-2f565aec-e3d5-4171-a126-d5c5450009ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190178718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2190178718
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3228093303
Short name T42
Test name
Test status
Simulation time 501441117 ps
CPU time 13.86 seconds
Started Aug 18 04:31:26 PM PDT 24
Finished Aug 18 04:31:40 PM PDT 24
Peak memory 256144 kb
Host smart-3e69734a-ab61-407f-8bba-eebc2800fbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32280
93303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3228093303
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3785880411
Short name T414
Test name
Test status
Simulation time 226573925 ps
CPU time 18.17 seconds
Started Aug 18 04:31:21 PM PDT 24
Finished Aug 18 04:31:39 PM PDT 24
Peak memory 255992 kb
Host smart-ea61428c-aa70-4832-9090-beec48bef11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37858
80411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3785880411
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2769251433
Short name T72
Test name
Test status
Simulation time 397265287 ps
CPU time 44.22 seconds
Started Aug 18 04:31:27 PM PDT 24
Finished Aug 18 04:32:12 PM PDT 24
Peak memory 256996 kb
Host smart-f465de8b-75f9-49d8-aca4-7db43a0ec19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27692
51433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2769251433
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2362655240
Short name T273
Test name
Test status
Simulation time 636179616 ps
CPU time 14.69 seconds
Started Aug 18 04:31:29 PM PDT 24
Finished Aug 18 04:31:44 PM PDT 24
Peak memory 256560 kb
Host smart-965a44af-b458-4848-8988-0bb79822b543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23626
55240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2362655240
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1963926839
Short name T499
Test name
Test status
Simulation time 15979224234 ps
CPU time 1106.23 seconds
Started Aug 18 04:31:31 PM PDT 24
Finished Aug 18 04:49:58 PM PDT 24
Peak memory 289724 kb
Host smart-43be8d5d-fc4c-4d29-ad60-6009b69b9c71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963926839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1963926839
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2514803269
Short name T235
Test name
Test status
Simulation time 4699951262 ps
CPU time 156.47 seconds
Started Aug 18 04:31:38 PM PDT 24
Finished Aug 18 04:34:14 PM PDT 24
Peak memory 265428 kb
Host smart-4bb52ae8-47bf-4ec6-abbf-ced4a06b668c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514803269 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2514803269
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2070143390
Short name T545
Test name
Test status
Simulation time 37303672977 ps
CPU time 2005.39 seconds
Started Aug 18 04:31:31 PM PDT 24
Finished Aug 18 05:04:57 PM PDT 24
Peak memory 283532 kb
Host smart-c7a31483-8011-4bbf-8abf-e213de20a5c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070143390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2070143390
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2212862350
Short name T462
Test name
Test status
Simulation time 556646876 ps
CPU time 29.86 seconds
Started Aug 18 04:31:32 PM PDT 24
Finished Aug 18 04:32:02 PM PDT 24
Peak memory 256428 kb
Host smart-c0301ff4-c82d-4d60-a7d8-81527ff1d396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22128
62350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2212862350
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.668772346
Short name T404
Test name
Test status
Simulation time 1179051335 ps
CPU time 19.87 seconds
Started Aug 18 04:31:38 PM PDT 24
Finished Aug 18 04:31:58 PM PDT 24
Peak memory 248644 kb
Host smart-29b0197c-71b4-4525-92da-0ebe4519a110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66877
2346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.668772346
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3150222046
Short name T12
Test name
Test status
Simulation time 122686859879 ps
CPU time 1346.44 seconds
Started Aug 18 04:31:37 PM PDT 24
Finished Aug 18 04:54:04 PM PDT 24
Peak memory 270228 kb
Host smart-434a9662-4a65-4a5b-a080-eea5c0f119fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150222046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3150222046
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.165985272
Short name T308
Test name
Test status
Simulation time 44089582043 ps
CPU time 475.6 seconds
Started Aug 18 04:31:37 PM PDT 24
Finished Aug 18 04:39:33 PM PDT 24
Peak memory 248540 kb
Host smart-bf1cd789-94d6-4c43-bc19-a82fb07ce53a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165985272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.165985272
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2220196321
Short name T278
Test name
Test status
Simulation time 363939748 ps
CPU time 17.64 seconds
Started Aug 18 04:31:37 PM PDT 24
Finished Aug 18 04:31:55 PM PDT 24
Peak memory 248708 kb
Host smart-02c50ea2-d283-4ce7-a354-c0b98630f828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22201
96321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2220196321
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.355755079
Short name T1
Test name
Test status
Simulation time 404260012 ps
CPU time 13.74 seconds
Started Aug 18 04:31:37 PM PDT 24
Finished Aug 18 04:31:51 PM PDT 24
Peak memory 256320 kb
Host smart-664e1a84-3ed5-4828-ae84-5272d07eba93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35575
5079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.355755079
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1087512049
Short name T399
Test name
Test status
Simulation time 2028065855 ps
CPU time 51.64 seconds
Started Aug 18 04:31:32 PM PDT 24
Finished Aug 18 04:32:24 PM PDT 24
Peak memory 256064 kb
Host smart-4cb06bbc-03be-4f5b-ae3c-27f6e84c9048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10875
12049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1087512049
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1930256359
Short name T604
Test name
Test status
Simulation time 171414005413 ps
CPU time 2020.06 seconds
Started Aug 18 04:31:37 PM PDT 24
Finished Aug 18 05:05:18 PM PDT 24
Peak memory 273280 kb
Host smart-87cd457c-10b0-4545-b719-e6b015171d2e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930256359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1930256359
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3246909252
Short name T204
Test name
Test status
Simulation time 31900336 ps
CPU time 3.37 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:31:10 PM PDT 24
Peak memory 246288 kb
Host smart-0b525312-fb2f-411e-9c2d-f5dc48a2dc10
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3246909252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3246909252
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2336527204
Short name T53
Test name
Test status
Simulation time 150334277183 ps
CPU time 2138.53 seconds
Started Aug 18 04:30:01 PM PDT 24
Finished Aug 18 05:05:40 PM PDT 24
Peak memory 288628 kb
Host smart-5de073ca-4000-4582-8b4e-a5378be555cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336527204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2336527204
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4004287832
Short name T583
Test name
Test status
Simulation time 8879527878 ps
CPU time 161.2 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 04:32:44 PM PDT 24
Peak memory 256508 kb
Host smart-dd933efe-ad5e-444f-a3f1-991d15984837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042
87832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4004287832
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1433285802
Short name T362
Test name
Test status
Simulation time 1665708931 ps
CPU time 35.44 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 04:30:39 PM PDT 24
Peak memory 248504 kb
Host smart-3c7635fa-56be-4b24-972b-92beae0123c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14332
85802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1433285802
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.799331073
Short name T310
Test name
Test status
Simulation time 588844736071 ps
CPU time 3188.82 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 05:23:20 PM PDT 24
Peak memory 288460 kb
Host smart-1e3f309e-180c-4ca2-9c0c-edf61ae76c3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799331073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.799331073
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2012156949
Short name T651
Test name
Test status
Simulation time 40628450628 ps
CPU time 2073.51 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 05:05:41 PM PDT 24
Peak memory 284448 kb
Host smart-64122a97-5da7-461d-a52c-d7fc67a30e1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012156949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2012156949
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3223825370
Short name T616
Test name
Test status
Simulation time 10288832865 ps
CPU time 397 seconds
Started Aug 18 04:30:09 PM PDT 24
Finished Aug 18 04:36:46 PM PDT 24
Peak memory 248700 kb
Host smart-279589d3-6a74-47b3-870e-9479a55e9f68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223825370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3223825370
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3631953693
Short name T537
Test name
Test status
Simulation time 930283118 ps
CPU time 14.89 seconds
Started Aug 18 04:30:22 PM PDT 24
Finished Aug 18 04:30:37 PM PDT 24
Peak memory 248668 kb
Host smart-0ca2398e-2210-4b12-86ad-6894bc1d83a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36319
53693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3631953693
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1243760144
Short name T495
Test name
Test status
Simulation time 1991021623 ps
CPU time 56.65 seconds
Started Aug 18 04:30:01 PM PDT 24
Finished Aug 18 04:30:58 PM PDT 24
Peak memory 256944 kb
Host smart-877f6527-5714-48e1-aa7b-ffd2891e527f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12437
60144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1243760144
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1186409124
Short name T523
Test name
Test status
Simulation time 130691145 ps
CPU time 12.09 seconds
Started Aug 18 04:30:00 PM PDT 24
Finished Aug 18 04:30:12 PM PDT 24
Peak memory 256096 kb
Host smart-1f437d63-ba1d-4b0e-8bef-811f9681c3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11864
09124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1186409124
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.667693972
Short name T218
Test name
Test status
Simulation time 23168807314 ps
CPU time 1076.24 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:47:56 PM PDT 24
Peak memory 287760 kb
Host smart-0cb2f1b6-caf9-45b7-ab42-4374a8b3ce08
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667693972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.667693972
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2166358932
Short name T239
Test name
Test status
Simulation time 5076653899 ps
CPU time 88.4 seconds
Started Aug 18 04:29:57 PM PDT 24
Finished Aug 18 04:31:26 PM PDT 24
Peak memory 269964 kb
Host smart-ff4a5426-48f5-4a06-b314-185b1f4c25b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166358932 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2166358932
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4267109872
Short name T198
Test name
Test status
Simulation time 24578384 ps
CPU time 2.3 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 04:31:10 PM PDT 24
Peak memory 248452 kb
Host smart-0607f8bf-a617-4922-84c8-f5d237d393db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4267109872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4267109872
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2229583980
Short name T586
Test name
Test status
Simulation time 52564847684 ps
CPU time 2657.56 seconds
Started Aug 18 04:29:56 PM PDT 24
Finished Aug 18 05:14:14 PM PDT 24
Peak memory 281536 kb
Host smart-fbcd6331-1483-47d4-b050-c502c002640a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229583980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2229583980
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3018473999
Short name T378
Test name
Test status
Simulation time 405952459 ps
CPU time 11.17 seconds
Started Aug 18 04:30:07 PM PDT 24
Finished Aug 18 04:30:18 PM PDT 24
Peak memory 248560 kb
Host smart-77d7e129-fb0c-40dd-a17f-6bf5cee8705b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3018473999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3018473999
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.530382952
Short name T461
Test name
Test status
Simulation time 14533157985 ps
CPU time 225.65 seconds
Started Aug 18 04:30:16 PM PDT 24
Finished Aug 18 04:34:02 PM PDT 24
Peak memory 256944 kb
Host smart-60b5242a-306c-4915-83c1-ed6797f6ab2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53038
2952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.530382952
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.4121939054
Short name T363
Test name
Test status
Simulation time 1031257005 ps
CPU time 33.79 seconds
Started Aug 18 04:31:13 PM PDT 24
Finished Aug 18 04:31:47 PM PDT 24
Peak memory 255080 kb
Host smart-a4da3f40-7c0c-4290-9e10-30af48613f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41219
39054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.4121939054
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1722487185
Short name T666
Test name
Test status
Simulation time 222528258297 ps
CPU time 1178.47 seconds
Started Aug 18 04:31:04 PM PDT 24
Finished Aug 18 04:50:43 PM PDT 24
Peak memory 266112 kb
Host smart-5804f0b0-cd67-4758-96ad-49a02f485bc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722487185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1722487185
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1371465026
Short name T309
Test name
Test status
Simulation time 12427066343 ps
CPU time 293.54 seconds
Started Aug 18 04:30:07 PM PDT 24
Finished Aug 18 04:35:01 PM PDT 24
Peak memory 247404 kb
Host smart-a2d7533c-48a6-4b79-80d5-cc8b963d6ec8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371465026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1371465026
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2200392218
Short name T114
Test name
Test status
Simulation time 600536154 ps
CPU time 32.39 seconds
Started Aug 18 04:31:13 PM PDT 24
Finished Aug 18 04:31:46 PM PDT 24
Peak memory 254268 kb
Host smart-1b8f7f95-1836-4612-9e64-91ca5b1a2c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
92218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2200392218
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2219583962
Short name T341
Test name
Test status
Simulation time 132448087 ps
CPU time 16.1 seconds
Started Aug 18 04:31:05 PM PDT 24
Finished Aug 18 04:31:21 PM PDT 24
Peak memory 247656 kb
Host smart-1d3e7fa8-8487-4cc1-941d-e8aeac5de8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22195
83962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2219583962
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1243632978
Short name T86
Test name
Test status
Simulation time 729811276 ps
CPU time 52.15 seconds
Started Aug 18 04:31:04 PM PDT 24
Finished Aug 18 04:31:57 PM PDT 24
Peak memory 247172 kb
Host smart-1c56b599-e944-4a26-a75b-71950b7f2ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12436
32978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1243632978
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3499102806
Short name T509
Test name
Test status
Simulation time 3516732598 ps
CPU time 50.97 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 04:30:54 PM PDT 24
Peak memory 256916 kb
Host smart-8ef8a7c9-991e-4b71-b54d-5a53aadf65d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34991
02806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3499102806
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3445787875
Short name T425
Test name
Test status
Simulation time 9242419680 ps
CPU time 475.59 seconds
Started Aug 18 04:29:56 PM PDT 24
Finished Aug 18 04:37:52 PM PDT 24
Peak memory 265380 kb
Host smart-f3e0e6f3-7652-4ecf-9840-dc4f97389926
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445787875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3445787875
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1008770501
Short name T194
Test name
Test status
Simulation time 46277950 ps
CPU time 4.3 seconds
Started Aug 18 04:31:13 PM PDT 24
Finished Aug 18 04:31:18 PM PDT 24
Peak memory 247040 kb
Host smart-79d8d845-e346-4659-87a4-4345ed32ddad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1008770501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1008770501
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1689810050
Short name T116
Test name
Test status
Simulation time 36917909512 ps
CPU time 862.31 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:45:30 PM PDT 24
Peak memory 284020 kb
Host smart-20da9fdc-dfb5-4a91-aff6-c24469013be6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689810050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1689810050
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.188184956
Short name T571
Test name
Test status
Simulation time 262344005 ps
CPU time 13.38 seconds
Started Aug 18 04:29:56 PM PDT 24
Finished Aug 18 04:30:13 PM PDT 24
Peak memory 248668 kb
Host smart-9473ccfc-a511-4948-a839-4b57449b3b5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=188184956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.188184956
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3878495877
Short name T558
Test name
Test status
Simulation time 5830690563 ps
CPU time 167.76 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:33:55 PM PDT 24
Peak memory 255848 kb
Host smart-ea377d8d-0091-43cd-9d7c-b03fbc3b06ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38784
95877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3878495877
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.791136224
Short name T390
Test name
Test status
Simulation time 515153761 ps
CPU time 34.25 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:31:41 PM PDT 24
Peak memory 246736 kb
Host smart-52875e75-07c3-4079-a01c-0cc1e9dbd47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79113
6224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.791136224
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1603736514
Short name T65
Test name
Test status
Simulation time 18041591383 ps
CPU time 1458.91 seconds
Started Aug 18 04:30:00 PM PDT 24
Finished Aug 18 04:54:19 PM PDT 24
Peak memory 288980 kb
Host smart-74d7b072-c6c6-4f99-b43f-8679f7904477
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603736514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1603736514
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.572915563
Short name T544
Test name
Test status
Simulation time 26854949436 ps
CPU time 1051.56 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:48:39 PM PDT 24
Peak memory 286008 kb
Host smart-1ca8c96a-8bd2-45ea-b3c6-5a3c801d4f40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572915563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.572915563
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.492067946
Short name T301
Test name
Test status
Simulation time 8683523542 ps
CPU time 368.15 seconds
Started Aug 18 04:31:07 PM PDT 24
Finished Aug 18 04:37:15 PM PDT 24
Peak memory 246204 kb
Host smart-ba2b804c-0603-4577-8876-b9f71d947733
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492067946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.492067946
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3681496568
Short name T617
Test name
Test status
Simulation time 151104151 ps
CPU time 7.58 seconds
Started Aug 18 04:30:05 PM PDT 24
Finished Aug 18 04:30:13 PM PDT 24
Peak memory 251480 kb
Host smart-73f3a488-5705-45e6-b6fe-e61175235b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36814
96568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3681496568
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2621760053
Short name T344
Test name
Test status
Simulation time 177555513 ps
CPU time 14.03 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:31:21 PM PDT 24
Peak memory 254092 kb
Host smart-da38c6ce-1b68-4c05-9288-264073e5aeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26217
60053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2621760053
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3520268613
Short name T566
Test name
Test status
Simulation time 216540865 ps
CPU time 16.13 seconds
Started Aug 18 04:31:06 PM PDT 24
Finished Aug 18 04:31:23 PM PDT 24
Peak memory 246464 kb
Host smart-c72aa4b4-15d3-430d-be23-2e1df02bd376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35202
68613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3520268613
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3458633171
Short name T546
Test name
Test status
Simulation time 698656111 ps
CPU time 42.73 seconds
Started Aug 18 04:30:06 PM PDT 24
Finished Aug 18 04:30:49 PM PDT 24
Peak memory 256788 kb
Host smart-cba6a564-aab0-498b-af6e-0d777fea14a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
33171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3458633171
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1950292329
Short name T555
Test name
Test status
Simulation time 26396127986 ps
CPU time 1321.81 seconds
Started Aug 18 04:31:08 PM PDT 24
Finished Aug 18 04:53:10 PM PDT 24
Peak memory 272940 kb
Host smart-e81cb146-6701-4a6d-9651-4062276935d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950292329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1950292329
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1441228077
Short name T210
Test name
Test status
Simulation time 35371413 ps
CPU time 2.29 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:30:01 PM PDT 24
Peak memory 248712 kb
Host smart-ea7666c6-281f-4a2a-9c2e-0d08258e6eb6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1441228077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1441228077
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3119451559
Short name T676
Test name
Test status
Simulation time 72409770589 ps
CPU time 3104.99 seconds
Started Aug 18 04:30:09 PM PDT 24
Finished Aug 18 05:21:54 PM PDT 24
Peak memory 288816 kb
Host smart-145caa8a-3547-477b-a09a-6e6f54d848e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119451559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3119451559
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.647709450
Short name T438
Test name
Test status
Simulation time 3056571412 ps
CPU time 10.74 seconds
Started Aug 18 04:30:17 PM PDT 24
Finished Aug 18 04:30:28 PM PDT 24
Peak memory 248696 kb
Host smart-955eed1f-7cf0-4c08-ae0f-8e6f21a5a486
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=647709450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.647709450
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1783747926
Short name T565
Test name
Test status
Simulation time 9352944534 ps
CPU time 189.13 seconds
Started Aug 18 04:31:04 PM PDT 24
Finished Aug 18 04:34:14 PM PDT 24
Peak memory 254348 kb
Host smart-ee870dcc-cfe9-409c-9c9d-52e558bae0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17837
47926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1783747926
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.4287804063
Short name T216
Test name
Test status
Simulation time 7253077331 ps
CPU time 44.63 seconds
Started Aug 18 04:31:04 PM PDT 24
Finished Aug 18 04:31:49 PM PDT 24
Peak memory 254412 kb
Host smart-ea98417a-6a0f-45aa-9990-1b3318a1ca6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42878
04063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.4287804063
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.87701504
Short name T641
Test name
Test status
Simulation time 83352842254 ps
CPU time 1195.7 seconds
Started Aug 18 04:30:05 PM PDT 24
Finished Aug 18 04:50:01 PM PDT 24
Peak memory 272740 kb
Host smart-d0ff8734-8b66-48a1-8823-b8876f399b56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87701504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.87701504
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3462062558
Short name T492
Test name
Test status
Simulation time 76709455743 ps
CPU time 2237.26 seconds
Started Aug 18 04:30:11 PM PDT 24
Finished Aug 18 05:07:29 PM PDT 24
Peak memory 281484 kb
Host smart-6cd97598-4957-46f0-88fc-a63c94452975
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462062558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3462062558
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2846778194
Short name T100
Test name
Test status
Simulation time 104629488985 ps
CPU time 519.63 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:38:43 PM PDT 24
Peak memory 248836 kb
Host smart-75eb7325-7e10-42a5-81d2-362e23415deb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846778194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2846778194
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3476838492
Short name T215
Test name
Test status
Simulation time 1084339478 ps
CPU time 22.67 seconds
Started Aug 18 04:31:04 PM PDT 24
Finished Aug 18 04:31:27 PM PDT 24
Peak memory 247084 kb
Host smart-23d1c2c7-b3cf-49c9-8426-f3124848ac31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34768
38492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3476838492
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1854728620
Short name T54
Test name
Test status
Simulation time 1871278495 ps
CPU time 27.02 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 04:30:30 PM PDT 24
Peak memory 256772 kb
Host smart-99a6c3a3-3699-4a53-a5c0-c3bd930fb219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
28620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1854728620
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1814086841
Short name T245
Test name
Test status
Simulation time 2092554119 ps
CPU time 25.24 seconds
Started Aug 18 04:31:14 PM PDT 24
Finished Aug 18 04:31:39 PM PDT 24
Peak memory 248280 kb
Host smart-a1dd935b-d9c8-4fde-8ffa-5797cc206db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18140
86841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1814086841
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.159880252
Short name T64
Test name
Test status
Simulation time 260854135 ps
CPU time 29.34 seconds
Started Aug 18 04:31:05 PM PDT 24
Finished Aug 18 04:31:34 PM PDT 24
Peak memory 256136 kb
Host smart-bfe95501-3d9d-4974-a6b5-0aad120cc632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15988
0252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.159880252
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1677169113
Short name T450
Test name
Test status
Simulation time 2562681057 ps
CPU time 312.1 seconds
Started Aug 18 04:29:59 PM PDT 24
Finished Aug 18 04:35:11 PM PDT 24
Peak memory 266396 kb
Host smart-a737a93b-9e47-4c75-aea8-9a51fa2c4abb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677169113 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1677169113
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2060352612
Short name T199
Test name
Test status
Simulation time 71111183 ps
CPU time 3.62 seconds
Started Aug 18 04:30:08 PM PDT 24
Finished Aug 18 04:30:12 PM PDT 24
Peak memory 248768 kb
Host smart-cbf987af-a3bf-4a68-ab58-00eb3d31b9ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2060352612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2060352612
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2299281385
Short name T409
Test name
Test status
Simulation time 42435555882 ps
CPU time 897.06 seconds
Started Aug 18 04:30:01 PM PDT 24
Finished Aug 18 04:44:58 PM PDT 24
Peak memory 271952 kb
Host smart-2d3cc69b-265c-49c9-873f-e714b2a62141
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299281385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2299281385
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3522816539
Short name T570
Test name
Test status
Simulation time 4203377879 ps
CPU time 39.8 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 04:30:44 PM PDT 24
Peak memory 248764 kb
Host smart-867a73d4-fe40-4568-9793-e1a03acdb9ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3522816539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3522816539
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.851946418
Short name T48
Test name
Test status
Simulation time 337402780 ps
CPU time 6.55 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:30:05 PM PDT 24
Peak memory 251692 kb
Host smart-820b1b3c-6f24-4d02-995f-7959d2d6a2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85194
6418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.851946418
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3169628101
Short name T579
Test name
Test status
Simulation time 146407361 ps
CPU time 13.73 seconds
Started Aug 18 04:29:58 PM PDT 24
Finished Aug 18 04:30:12 PM PDT 24
Peak memory 256092 kb
Host smart-9f954239-57eb-41ae-9f43-524de29eb952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31696
28101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3169628101
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.500977961
Short name T66
Test name
Test status
Simulation time 59178036295 ps
CPU time 1375.3 seconds
Started Aug 18 04:30:20 PM PDT 24
Finished Aug 18 04:53:15 PM PDT 24
Peak memory 281408 kb
Host smart-74a93ac8-064a-4264-b70e-0592f04125a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500977961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.500977961
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1126233935
Short name T87
Test name
Test status
Simulation time 76637032853 ps
CPU time 2506.94 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 05:12:02 PM PDT 24
Peak memory 288716 kb
Host smart-06dcff41-6441-4105-a614-708d560021d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126233935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1126233935
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.314392327
Short name T677
Test name
Test status
Simulation time 4378695128 ps
CPU time 65.05 seconds
Started Aug 18 04:30:03 PM PDT 24
Finished Aug 18 04:31:08 PM PDT 24
Peak memory 256784 kb
Host smart-01bfcebb-3c7f-417f-9bd2-39b7d4c7e7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31439
2327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.314392327
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.762024753
Short name T652
Test name
Test status
Simulation time 1250549132 ps
CPU time 65.63 seconds
Started Aug 18 04:30:00 PM PDT 24
Finished Aug 18 04:31:05 PM PDT 24
Peak memory 256128 kb
Host smart-5313c09c-b011-4c87-99b3-8eaca7d7f457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76202
4753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.762024753
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1981221352
Short name T692
Test name
Test status
Simulation time 1108963761 ps
CPU time 28.72 seconds
Started Aug 18 04:30:12 PM PDT 24
Finished Aug 18 04:30:41 PM PDT 24
Peak memory 255600 kb
Host smart-00f3c4d8-fa51-4de9-a160-2e71825d5d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19812
21352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1981221352
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2374370810
Short name T485
Test name
Test status
Simulation time 1634256384 ps
CPU time 35.74 seconds
Started Aug 18 04:30:04 PM PDT 24
Finished Aug 18 04:30:40 PM PDT 24
Peak memory 248660 kb
Host smart-57279ccd-85b0-40ae-a91b-695586597e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743
70810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2374370810
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2028677005
Short name T489
Test name
Test status
Simulation time 10338357332 ps
CPU time 336.03 seconds
Started Aug 18 04:30:15 PM PDT 24
Finished Aug 18 04:35:52 PM PDT 24
Peak memory 256928 kb
Host smart-9de48e13-d1a8-4363-963c-ae90f5cff351
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028677005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2028677005
Directory /workspace/9.alert_handler_stress_all/latest
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