Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
class_index_cp 4 0 4 100.00 100 1 1 0
esc_index_cp 4 0 4 100.00 100 1 1 0
loc_alert_cause_cp 2 0 2 100.00 100 1 1 0


Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
loc_alert_cause_cross_alert_index 8 0 8 100.00 100 1 1 0
loc_alert_cause_cross_class_index 8 0 8 100.00 100 1 1 0


Summary for Variable class_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for class_index_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
class_i[0x0] 46043 1 T13 5 T6 2 T34 3489
class_i[0x1] 69597 1 T13 8 T23 14 T24 386
class_i[0x2] 25569 1 T13 12 T4 2585 T23 3719
class_i[0x3] 39987 1 T13 23 T6 8 T23 3



Summary for Variable esc_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for esc_index_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
alert[0x0] 43982 1 T13 10 T4 690 T6 2
alert[0x1] 45921 1 T13 15 T4 597 T6 4
alert[0x2] 46655 1 T13 16 T4 601 T23 972
alert[0x3] 44638 1 T13 7 T4 697 T6 4



Summary for Variable loc_alert_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail 180920 1 T13 48 T4 2585 T6 10
esc_ping_fail 276 1 T18 1 T19 3 T20 1



Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins
loc_alert_cause_cpesc_index_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail alert[0x0] 43903 1 T13 10 T4 690 T6 2
esc_integrity_fail alert[0x1] 45848 1 T13 15 T4 597 T6 4
esc_integrity_fail alert[0x2] 46590 1 T13 16 T4 601 T23 972
esc_integrity_fail alert[0x3] 44579 1 T13 7 T4 697 T6 4
esc_ping_fail alert[0x0] 79 1 T19 2 T115 2 T277 1
esc_ping_fail alert[0x1] 73 1 T19 1 T79 2 T277 1
esc_ping_fail alert[0x2] 65 1 T18 1 T20 1 T79 1
esc_ping_fail alert[0x3] 59 1 T115 1 T277 3 T279 1



Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins
loc_alert_cause_cpclass_index_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail class_i[0x0] 45966 1 T13 5 T6 2 T34 3489
esc_integrity_fail class_i[0x1] 69516 1 T13 8 T23 14 T24 386
esc_integrity_fail class_i[0x2] 25497 1 T13 12 T4 2585 T23 3719
esc_integrity_fail class_i[0x3] 39941 1 T13 23 T6 8 T23 3
esc_ping_fail class_i[0x0] 77 1 T19 2 T79 3 T115 2
esc_ping_fail class_i[0x1] 81 1 T18 1 T20 1 T115 1
esc_ping_fail class_i[0x2] 72 1 T280 1 T282 1 T287 4
esc_ping_fail class_i[0x3] 46 1 T19 1 T280 2 T287 1

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