Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	0	44	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	0	44	100.00	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	187	1			T4	1		T7	3		T6	2
index[0x1]	203	1			T16	1		T23	8		T24	1
index[0x2]	193	1			T6	1		T22	1		T24	1
index[0x3]	184	1			T1	1		T2	1		T23	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	225	1			T4	1		T6	1		T22	1
lens_less_than_1000[1]	125	1			T16	1		T23	1		T112	1
lens_less_than_1000[2]	128	1			T2	1		T7	3		T6	1
lens_less_than_1000[3]	104	1			T16	1		T53	1		T96	1
lens_less_than_1000[4]	58	1			T1	1		T6	1		T30	1
lens_less_than_1000[5]	47	1			T26	1		T80	1		T30	2
lens_less_than_1000[6]	28	1			T71	1		T238	1		T47	1
lens_less_than_1000[7]	20	1			T95	1		T97	1		T55	1
lens_less_than_1000[8]	16	1			T74	1		T101	1		T301	2
lens_less_than_1000[9]	5	1			T302	1		T286	1		T63	1
len_2	11	1			T28	1		T237	1		T281	3

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	0	44	100.00

Automatically Generated Cross Bins for len_per_esc_sig

Bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	55	1			T4	1		T22	1		T95	1
index[0x0]	lens_less_than_1000[1]	26	1			T16	1		T23	1		T56	1
index[0x0]	lens_less_than_1000[2]	33	1			T7	3		T6	1		T21	2
index[0x0]	lens_less_than_1000[3]	30	1			T38	1		T302	1		T303	1
index[0x0]	lens_less_than_1000[4]	15	1			T6	1		T30	1		T215	1
index[0x0]	lens_less_than_1000[5]	17	1			T26	1		T80	1		T103	6
index[0x0]	lens_less_than_1000[6]	1	1			T304	1		-	-		-	-
index[0x0]	lens_less_than_1000[7]	3	1			T95	1		T225	1		T305	1
index[0x0]	lens_less_than_1000[8]	5	1			T258	1		T248	4		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T63	1		-	-		-	-
index[0x0]	len_2	1	1			T306	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	62	1			T27	1		T30	1		T82	1
index[0x1]	lens_less_than_1000[1]	37	1			T55	1		T38	1		T113	1
index[0x1]	lens_less_than_1000[2]	32	1			T23	8		T24	1		T98	1
index[0x1]	lens_less_than_1000[3]	21	1			T16	1		T307	1		T188	1
index[0x1]	lens_less_than_1000[4]	18	1			T87	1		T89	1		T281	1
index[0x1]	lens_less_than_1000[5]	7	1			T32	1		T108	1		T308	1
index[0x1]	lens_less_than_1000[6]	13	1			T71	1		T309	1		T310	1
index[0x1]	lens_less_than_1000[7]	5	1			T90	1		T311	1		T312	1
index[0x1]	lens_less_than_1000[8]	4	1			T101	1		T251	1		T313	1
index[0x1]	lens_less_than_1000[9]	1	1			T314	1		-	-		-	-
index[0x1]	len_2	3	1			T237	1		T315	1		T261	1
index[0x2]	lens_less_than_1000[0]	57	1			T6	1		T24	1		T29	2
index[0x2]	lens_less_than_1000[1]	25	1			T112	1		T75	1		T101	1
index[0x2]	lens_less_than_1000[2]	31	1			T22	1		T25	1		T79	1
index[0x2]	lens_less_than_1000[3]	39	1			T53	1		T74	1		T55	5
index[0x2]	lens_less_than_1000[4]	10	1			T215	1		T216	1		T106	1
index[0x2]	lens_less_than_1000[5]	12	1			T30	2		T78	1		T100	1
index[0x2]	lens_less_than_1000[6]	6	1			T238	1		T47	1		T316	1
index[0x2]	lens_less_than_1000[7]	5	1			T317	1		T126	1		T117	1
index[0x2]	lens_less_than_1000[8]	2	1			T74	1		T301	1		-	-
index[0x2]	lens_less_than_1000[9]	2	1			T302	1		T314	1		-	-
index[0x2]	len_2	4	1			T281	3		T318	1		-	-
index[0x3]	lens_less_than_1000[0]	51	1			T23	1		T34	1		T38	1
index[0x3]	lens_less_than_1000[1]	37	1			T32	1		T101	1		T36	1
index[0x3]	lens_less_than_1000[2]	32	1			T2	1		T97	1		T73	1
index[0x3]	lens_less_than_1000[3]	14	1			T96	1		T97	1		T32	1
index[0x3]	lens_less_than_1000[4]	15	1			T1	1		T100	1		T319	1
index[0x3]	lens_less_than_1000[5]	11	1			T32	1		T188	1		T88	1
index[0x3]	lens_less_than_1000[6]	8	1			T124	1		T320	1		T321	1
index[0x3]	lens_less_than_1000[7]	7	1			T97	1		T55	1		T90	1
index[0x3]	lens_less_than_1000[8]	5	1			T301	1		T322	1		T258	1
index[0x3]	lens_less_than_1000[9]	1	1			T286	1		-	-		-	-
index[0x3]	len_2	3	1			T28	1		T230	1		T323	1