Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg
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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00
Crosses 40 5 35 87.50


Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
class_index_cp 4 0 4 100.00 100 1 1 0
intr_timeout_cnt_cp 10 0 10 100.00 100 1 1 0


Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
class_cnt_cross 40 5 35 87.50 100 1 1 0


Summary for Variable class_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for class_index_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
class_index[0x0] 68 1 T27 1 T30 2 T55 2
class_index[0x1] 54 1 T24 2 T28 5 T30 1
class_index[0x2] 58 1 T80 1 T55 1 T86 3
class_index[0x3] 47 1 T13 1 T24 1 T28 1



Summary for Variable intr_timeout_cnt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for intr_timeout_cnt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
intr_timeout_cnt[0] 97 1 T24 1 T27 1 T28 6
intr_timeout_cnt[1] 39 1 T24 1 T30 2 T87 1
intr_timeout_cnt[2] 34 1 T55 1 T86 3 T36 2
intr_timeout_cnt[3] 9 1 T62 1 T122 1 T245 1
intr_timeout_cnt[4] 13 1 T24 1 T30 2 T49 2
intr_timeout_cnt[5] 13 1 T13 1 T86 1 T88 1
intr_timeout_cnt[6] 8 1 T89 1 T90 1 T67 1
intr_timeout_cnt[7] 6 1 T30 1 T36 1 T246 1
intr_timeout_cnt[8] 5 1 T55 2 T247 1 T248 1
intr_timeout_cnt[9] 3 1 T249 1 T250 1 T251 1



Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 40 5 35 87.50 5


Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins
class_index_cpintr_timeout_cnt_cpCOUNTAT LEASTNUMBERSTATUS
[class_index[0x1]] [intr_timeout_cnt[6]] 0 1 1
[class_index[0x2]] [intr_timeout_cnt[3]] 0 1 1
[class_index[0x2]] [intr_timeout_cnt[9]] 0 1 1
[class_index[0x3]] [intr_timeout_cnt[3]] 0 1 1
[class_index[0x3]] [intr_timeout_cnt[8]] 0 1 1


Covered bins
class_index_cpintr_timeout_cnt_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
class_index[0x0] intr_timeout_cnt[0] 25 1 T27 1 T85 1 T83 1
class_index[0x0] intr_timeout_cnt[1] 15 1 T30 2 T91 1 T252 1
class_index[0x0] intr_timeout_cnt[2] 10 1 T87 1 T90 1 T62 1
class_index[0x0] intr_timeout_cnt[3] 4 1 T253 2 T254 1 T255 1
class_index[0x0] intr_timeout_cnt[4] 2 1 T66 1 T256 1 - -
class_index[0x0] intr_timeout_cnt[5] 4 1 T88 1 T249 1 T250 1
class_index[0x0] intr_timeout_cnt[6] 3 1 T89 1 T250 1 T257 1
class_index[0x0] intr_timeout_cnt[7] 1 1 T36 1 - - - -
class_index[0x0] intr_timeout_cnt[8] 3 1 T55 2 T248 1 - -
class_index[0x0] intr_timeout_cnt[9] 1 1 T251 1 - - - -
class_index[0x1] intr_timeout_cnt[0] 23 1 T24 1 T28 5 T91 1
class_index[0x1] intr_timeout_cnt[1] 10 1 T24 1 T87 1 T117 1
class_index[0x1] intr_timeout_cnt[2] 2 1 T258 1 T31 1 - -
class_index[0x1] intr_timeout_cnt[3] 5 1 T62 1 T122 1 T245 1
class_index[0x1] intr_timeout_cnt[4] 6 1 T49 2 T259 1 T260 2
class_index[0x1] intr_timeout_cnt[5] 3 1 T93 1 T63 1 T253 1
class_index[0x1] intr_timeout_cnt[7] 3 1 T30 1 T246 1 T261 1
class_index[0x1] intr_timeout_cnt[8] 1 1 T262 1 - - - -
class_index[0x1] intr_timeout_cnt[9] 1 1 T249 1 - - - -
class_index[0x2] intr_timeout_cnt[0] 23 1 T80 1 T88 1 T90 1
class_index[0x2] intr_timeout_cnt[1] 11 1 T122 1 T117 1 T64 1
class_index[0x2] intr_timeout_cnt[2] 14 1 T55 1 T86 3 T93 1
class_index[0x2] intr_timeout_cnt[4] 2 1 T87 1 T263 1 - -
class_index[0x2] intr_timeout_cnt[5] 3 1 T253 1 T261 2 - -
class_index[0x2] intr_timeout_cnt[6] 3 1 T264 2 T265 1 - -
class_index[0x2] intr_timeout_cnt[7] 1 1 T266 1 - - - -
class_index[0x2] intr_timeout_cnt[8] 1 1 T247 1 - - - -
class_index[0x3] intr_timeout_cnt[0] 26 1 T28 1 T36 2 T87 3
class_index[0x3] intr_timeout_cnt[1] 3 1 T252 1 T254 1 T267 1
class_index[0x3] intr_timeout_cnt[2] 8 1 T36 2 T93 1 T268 1
class_index[0x3] intr_timeout_cnt[4] 3 1 T24 1 T30 2 - -
class_index[0x3] intr_timeout_cnt[5] 3 1 T13 1 T86 1 T124 1
class_index[0x3] intr_timeout_cnt[6] 2 1 T90 1 T67 1 - -
class_index[0x3] intr_timeout_cnt[7] 1 1 T269 1 - - - -
class_index[0x3] intr_timeout_cnt[9] 1 1 T250 1 - - - -

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