Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287927	1			T1	1489		T2	31		T3	41
all_values[1]	287927	1			T1	1489		T2	31		T3	41
all_values[2]	287927	1			T1	1489		T2	31		T3	41
all_values[3]	287927	1			T1	1489		T2	31		T3	41

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

573040

1

T1

3061

T2

48

T3

85

auto[1]

578668

1

T1

2895

T2

76

T3

79

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

674491

1

T1

4636

T2

109

T3

84

auto[1]

477217

1

T1

1320

T2

15

T3

80

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	82019	1			T1	583		T2	5		T3	11
all_values[0]	auto[0]	auto[1]	62063	1			T1	199		T2	4		T3	11
all_values[0]	auto[1]	auto[0]	82376	1			T1	522		T2	11		T3	10
all_values[0]	auto[1]	auto[1]	61469	1			T1	185		T2	11		T3	9
all_values[1]	auto[0]	auto[0]	84681	1			T1	578		T2	12		T3	11
all_values[1]	auto[0]	auto[1]	58132	1			T1	198		T3	10		T13	7
all_values[1]	auto[1]	auto[0]	86287	1			T1	534		T2	19		T3	10
all_values[1]	auto[1]	auto[1]	58827	1			T1	179		T3	10		T13	5
all_values[2]	auto[0]	auto[0]	84157	1			T1	727		T2	17		T3	10
all_values[2]	auto[0]	auto[1]	58900	1			T1	4		T3	9		T13	5
all_values[2]	auto[1]	auto[0]	85684	1			T1	757		T2	14		T3	11
all_values[2]	auto[1]	auto[1]	59186	1			T1	1		T3	11		T13	5
all_values[3]	auto[0]	auto[0]	83878	1			T1	494		T2	10		T3	12
all_values[3]	auto[0]	auto[1]	59210	1			T1	278		T3	11		T13	4
all_values[3]	auto[1]	auto[0]	85409	1			T1	441		T2	21		T3	9
all_values[3]	auto[1]	auto[1]	59430	1			T1	276		T3	9		T13	10