Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	287927	1			T1	1489		T2	31		T3	41
all_pins[1]	287927	1			T1	1489		T2	31		T3	41
all_pins[2]	287927	1			T1	1489		T2	31		T3	41
all_pins[3]	287927	1			T1	1489		T2	31		T3	41

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	912796	1			T1	5315		T2	113		T3	125
values[0x1]	238912	1			T1	641		T2	11		T3	39
transitions[0x0=>0x1]	157813	1			T1	592		T2	10		T3	23
transitions[0x1=>0x0]	158068	1			T1	592		T2	11		T3	24

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	226458	1			T1	1304		T2	20		T3	32
all_pins[0]	values[0x1]	61469	1			T1	185		T2	11		T3	9
all_pins[0]	transitions[0x0=>0x1]	60930	1			T1	185		T2	10		T3	8
all_pins[0]	transitions[0x1=>0x0]	59146	1			T1	276		T3	9		T13	8
all_pins[1]	values[0x0]	229100	1			T1	1310		T2	31		T3	31
all_pins[1]	values[0x1]	58827	1			T1	179		T3	10		T13	5
all_pins[1]	transitions[0x0=>0x1]	32050	1			T1	130		T3	6		T13	4
all_pins[1]	transitions[0x1=>0x0]	34692	1			T1	136		T2	11		T3	5
all_pins[2]	values[0x0]	228741	1			T1	1488		T2	31		T3	30
all_pins[2]	values[0x1]	59186	1			T1	1		T3	11		T13	5
all_pins[2]	transitions[0x0=>0x1]	32406	1			T1	1		T3	4		T13	3
all_pins[2]	transitions[0x1=>0x0]	32047	1			T1	179		T3	3		T13	3
all_pins[3]	values[0x0]	228497	1			T1	1213		T2	31		T3	32
all_pins[3]	values[0x1]	59430	1			T1	276		T3	9		T13	10
all_pins[3]	transitions[0x0=>0x1]	32427	1			T1	276		T3	5		T13	7
all_pins[3]	transitions[0x1=>0x0]	32183	1			T1	1		T3	7		T13	2