Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90951	1			T7	951		T21	1252		T22	1705
accum_cnt_1000	193045	1			T1	838		T14	88		T4	827
accum_cnt_100	22230	1			T1	128		T2	6		T3	5
accum_cnt_50	64022	1			T1	120		T2	10		T3	17
accum_cnt_10	138639	1			T1	19		T2	5		T3	5
accum_cnt_0	307020	1			T1	3355		T2	67		T3	89

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	213307	1			T1	1115		T2	22		T3	29
class_index[0x1]	213307	1			T1	1115		T2	22		T3	29
class_index[0x2]	213307	1			T1	1115		T2	22		T3	29
class_index[0x3]	213307	1			T1	1115		T2	22		T3	29

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	21254	1			T7	537		T22	609		T23	544
class_index[0x0]	accum_cnt_1000	45555	1			T14	38		T7	481		T22	758
class_index[0x0]	accum_cnt_100	5190	1			T2	6		T3	5		T11	7
class_index[0x0]	accum_cnt_50	13975	1			T2	10		T3	17		T11	11
class_index[0x0]	accum_cnt_10	37043	1			T2	5		T3	5		T11	1
class_index[0x0]	accum_cnt_0	80552	1			T1	1115		T2	1		T3	2
class_index[0x1]	accum_cnt_2000	23811	1			T21	509		T23	527		T24	722
class_index[0x1]	accum_cnt_1000	49328	1			T1	838		T4	827		T21	605
class_index[0x1]	accum_cnt_100	6973	1			T1	128		T4	20		T21	33
class_index[0x1]	accum_cnt_50	19190	1			T1	120		T4	19		T6	9
class_index[0x1]	accum_cnt_10	34091	1			T1	19		T4	5		T15	7
class_index[0x1]	accum_cnt_0	69763	1			T1	10		T2	22		T3	29
class_index[0x2]	accum_cnt_2000	23633	1			T7	414		T21	276		T22	510
class_index[0x2]	accum_cnt_1000	50488	1			T14	50		T7	915		T21	813
class_index[0x2]	accum_cnt_100	4522	1			T14	23		T7	52		T21	48
class_index[0x2]	accum_cnt_50	18326	1			T14	18		T7	38		T6	5
class_index[0x2]	accum_cnt_10	35037	1			T13	5		T14	6		T15	7
class_index[0x2]	accum_cnt_0	70199	1			T1	1115		T2	22		T3	29
class_index[0x3]	accum_cnt_2000	22253	1			T21	467		T22	586		T24	693
class_index[0x3]	accum_cnt_1000	47674	1			T21	638		T22	513		T23	49
class_index[0x3]	accum_cnt_100	5545	1			T21	35		T22	27		T23	19
class_index[0x3]	accum_cnt_50	12531	1			T6	3		T16	14		T21	28
class_index[0x3]	accum_cnt_10	32468	1			T13	7		T6	27		T16	6
class_index[0x3]	accum_cnt_0	86506	1			T1	1115		T2	22		T3	29