Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3040	1			T23	178		T53	12		T40	31
alert[0x1]	2714	1			T53	406		T30	7		T19	1
alert[0x2]	2898	1			T53	14		T30	16		T114	1
alert[0x3]	6494	1			T13	2		T24	7		T40	2415
alert[0x4]	10976	1			T30	2450		T97	6		T33	34
alert[0x5]	4888	1			T53	41		T33	111		T56	45
alert[0x6]	5472	1			T1	1		T13	4		T23	99
alert[0x7]	3576	1			T23	28		T24	188		T30	32
alert[0x8]	5330	1			T23	1155		T53	11		T74	5
alert[0x9]	2991	1			T53	31		T30	21		T40	73
alert[0xa]	6876	1			T23	363		T17	2		T30	3056
alert[0xb]	4386	1			T23	251		T24	1		T30	2
alert[0xc]	10760	1			T23	1433		T24	1		T18	1
alert[0xd]	4167	1			T23	316		T30	7		T71	1
alert[0xe]	5266	1			T23	103		T30	16		T40	320
alert[0xf]	6380	1			T18	2		T79	1		T40	1422
alert[0x10]	4770	1			T32	3		T33	213		T40	227
alert[0x11]	5926	1			T53	35		T30	19		T115	1
alert[0x12]	11069	1			T30	7		T33	44		T277	1
alert[0x13]	4677	1			T13	1		T53	213		T79	1
alert[0x14]	9120	1			T23	3		T24	4		T53	231
alert[0x15]	2867	1			T30	853		T74	63		T33	261
alert[0x16]	3230	1			T6	1		T53	49		T97	3
alert[0x17]	12930	1			T24	7		T74	2		T33	3
alert[0x18]	7615	1			T24	8		T56	1		T88	2
alert[0x19]	4595	1			T71	2		T79	1		T40	969
alert[0x1a]	2861	1			T53	443		T278	1		T58	1
alert[0x1b]	3561	1			T30	22		T19	1		T33	235
alert[0x1c]	3088	1			T23	9		T30	8		T277	1
alert[0x1d]	4866	1			T6	18		T23	80		T24	9
alert[0x1e]	3087	1			T23	26		T53	141		T19	1
alert[0x1f]	11708	1			T23	762		T30	52		T234	1
alert[0x20]	877	1			T53	360		T55	3		T40	73
alert[0x21]	4127	1			T23	16		T30	244		T19	1
alert[0x22]	11929	1			T13	3		T23	22		T29	1
alert[0x23]	10919	1			T23	268		T53	97		T30	234
alert[0x24]	3195	1			T29	3		T33	452		T277	1
alert[0x25]	3830	1			T33	12		T279	1		T278	1
alert[0x26]	3120	1			T13	2		T23	89		T30	151
alert[0x27]	2931	1			T18	1		T74	3		T33	386
alert[0x28]	9191	1			T24	1		T53	18		T74	3
alert[0x29]	2165	1			T23	5		T53	118		T30	65
alert[0x2a]	3342	1			T23	16		T53	1002		T32	1
alert[0x2b]	5257	1			T23	17		T30	8		T33	706
alert[0x2c]	5209	1			T1	1		T23	31		T53	32
alert[0x2d]	4339	1			T23	22		T24	13		T30	3197
alert[0x2e]	3109	1			T1	2		T32	1		T279	1
alert[0x2f]	8488	1			T23	211		T53	44		T30	210
alert[0x30]	5199	1			T30	93		T56	243		T280	1
alert[0x31]	4996	1			T30	4		T33	52		T56	335
alert[0x32]	6287	1			T23	6		T32	3		T20	1
alert[0x33]	6925	1			T23	3818		T30	41		T74	50
alert[0x34]	1975	1			T53	7		T74	13		T279	1
alert[0x35]	2985	1			T23	81		T30	453		T74	7
alert[0x36]	2714	1			T6	2		T53	41		T19	1
alert[0x37]	4609	1			T6	2		T53	25		T32	2
alert[0x38]	8281	1			T278	2		T88	17		T61	219
alert[0x39]	8769	1			T23	435		T55	2		T40	113
alert[0x3a]	6463	1			T23	33		T29	1		T19	1
alert[0x3b]	3212	1			T53	75		T30	124		T33	16
alert[0x3c]	2459	1			T24	3		T33	54		T79	2
alert[0x3d]	4146	1			T23	38		T34	281		T53	87
alert[0x3e]	3527	1			T23	50		T33	35		T279	1
alert[0x3f]	4688	1			T53	226		T30	7		T33	30
alert[0x40]	2981	1			T53	50		T30	230		T40	8

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	111003	1			T13	3		T24	243		T34	281
class_i[0x1]	96061	1			T6	22		T30	11829		T18	2
class_i[0x2]	73373	1			T1	4		T23	2		T30	239
class_i[0x3]	63991	1			T13	9		T6	1		T23	9962

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

343729

1

T13

12

T6

23

T23

9964

alert_ping_fail

699

1

T1

4

T17

2

T18

5

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3018	1			T23	178		T53	12		T40	31
alert_integrity_fail	alert[0x1]	2704	1			T53	406		T30	7		T40	82
alert_integrity_fail	alert[0x2]	2883	1			T53	14		T30	16		T114	1
alert_integrity_fail	alert[0x3]	6490	1			T13	2		T24	7		T40	2415
alert_integrity_fail	alert[0x4]	10967	1			T30	2450		T97	6		T33	34
alert_integrity_fail	alert[0x5]	4878	1			T53	41		T33	111		T56	45
alert_integrity_fail	alert[0x6]	5456	1			T13	4		T23	99		T24	1
alert_integrity_fail	alert[0x7]	3560	1			T23	28		T24	188		T30	32
alert_integrity_fail	alert[0x8]	5314	1			T23	1155		T53	11		T74	5
alert_integrity_fail	alert[0x9]	2982	1			T53	31		T30	21		T40	73
alert_integrity_fail	alert[0xa]	6860	1			T23	363		T30	3056		T74	18
alert_integrity_fail	alert[0xb]	4382	1			T23	251		T24	1		T30	2
alert_integrity_fail	alert[0xc]	10740	1			T23	1433		T24	1		T33	91
alert_integrity_fail	alert[0xd]	4157	1			T23	316		T30	7		T71	1
alert_integrity_fail	alert[0xe]	5255	1			T23	103		T30	16		T40	320
alert_integrity_fail	alert[0xf]	6367	1			T40	1422		T56	400		T88	1
alert_integrity_fail	alert[0x10]	4761	1			T32	3		T33	213		T40	227
alert_integrity_fail	alert[0x11]	5916	1			T53	35		T30	19		T36	2
alert_integrity_fail	alert[0x12]	11060	1			T30	7		T33	44		T58	87
alert_integrity_fail	alert[0x13]	4661	1			T13	1		T53	213		T40	95
alert_integrity_fail	alert[0x14]	9107	1			T23	3		T24	4		T53	231
alert_integrity_fail	alert[0x15]	2854	1			T30	853		T74	63		T33	261
alert_integrity_fail	alert[0x16]	3219	1			T6	1		T53	49		T97	3
alert_integrity_fail	alert[0x17]	12921	1			T24	7		T74	2		T33	3
alert_integrity_fail	alert[0x18]	7602	1			T24	8		T56	1		T88	2
alert_integrity_fail	alert[0x19]	4589	1			T71	2		T40	969		T56	109
alert_integrity_fail	alert[0x1a]	2855	1			T53	443		T58	1		T89	1
alert_integrity_fail	alert[0x1b]	3550	1			T30	22		T33	235		T58	178
alert_integrity_fail	alert[0x1c]	3071	1			T23	9		T30	8		T58	169
alert_integrity_fail	alert[0x1d]	4858	1			T6	18		T23	80		T24	9
alert_integrity_fail	alert[0x1e]	3077	1			T23	26		T53	141		T33	545
alert_integrity_fail	alert[0x1f]	11696	1			T23	762		T30	52		T40	602
alert_integrity_fail	alert[0x20]	869	1			T53	360		T55	3		T40	73
alert_integrity_fail	alert[0x21]	4117	1			T23	16		T30	244		T33	67
alert_integrity_fail	alert[0x22]	11910	1			T13	3		T23	22		T29	1
alert_integrity_fail	alert[0x23]	10908	1			T23	268		T53	97		T30	234
alert_integrity_fail	alert[0x24]	3187	1			T29	3		T33	452		T61	12
alert_integrity_fail	alert[0x25]	3819	1			T33	12		T61	8		T281	12
alert_integrity_fail	alert[0x26]	3110	1			T13	2		T23	89		T30	151
alert_integrity_fail	alert[0x27]	2928	1			T74	3		T33	386		T40	232
alert_integrity_fail	alert[0x28]	9180	1			T24	1		T53	18		T74	3
alert_integrity_fail	alert[0x29]	2154	1			T23	5		T53	118		T30	65
alert_integrity_fail	alert[0x2a]	3325	1			T23	16		T53	1002		T32	1
alert_integrity_fail	alert[0x2b]	5240	1			T23	17		T30	8		T33	706
alert_integrity_fail	alert[0x2c]	5199	1			T23	31		T53	32		T30	202
alert_integrity_fail	alert[0x2d]	4326	1			T23	22		T24	13		T30	3197
alert_integrity_fail	alert[0x2e]	3101	1			T32	1		T88	16		T61	5
alert_integrity_fail	alert[0x2f]	8475	1			T23	211		T53	44		T30	210
alert_integrity_fail	alert[0x30]	5187	1			T30	93		T56	243		T88	44
alert_integrity_fail	alert[0x31]	4988	1			T30	4		T33	52		T56	335
alert_integrity_fail	alert[0x32]	6277	1			T23	6		T32	3		T40	79
alert_integrity_fail	alert[0x33]	6911	1			T23	3818		T30	41		T74	50
alert_integrity_fail	alert[0x34]	1968	1			T53	7		T74	13		T88	115
alert_integrity_fail	alert[0x35]	2978	1			T23	81		T30	453		T74	7
alert_integrity_fail	alert[0x36]	2707	1			T6	2		T53	41		T40	839
alert_integrity_fail	alert[0x37]	4599	1			T6	2		T53	25		T32	2
alert_integrity_fail	alert[0x38]	8270	1			T88	17		T61	219		T230	42
alert_integrity_fail	alert[0x39]	8762	1			T23	435		T55	2		T40	113
alert_integrity_fail	alert[0x3a]	6454	1			T23	33		T29	1		T33	285
alert_integrity_fail	alert[0x3b]	3208	1			T53	75		T30	124		T33	16
alert_integrity_fail	alert[0x3c]	2449	1			T24	3		T33	54		T56	301
alert_integrity_fail	alert[0x3d]	4138	1			T23	38		T34	281		T53	87
alert_integrity_fail	alert[0x3e]	3521	1			T23	50		T33	35		T88	5
alert_integrity_fail	alert[0x3f]	4681	1			T53	226		T30	7		T33	30
alert_integrity_fail	alert[0x40]	2973	1			T53	50		T30	230		T40	8
alert_ping_fail	alert[0x0]	22	1			T282	1		T283	1		T284	1
alert_ping_fail	alert[0x1]	10	1			T19	1		T285	1		T286	1
alert_ping_fail	alert[0x2]	15	1			T285	1		T287	2		T283	1
alert_ping_fail	alert[0x3]	4	1			T285	1		T288	2		T289	1
alert_ping_fail	alert[0x4]	9	1			T115	1		T285	1		T226	1
alert_ping_fail	alert[0x5]	10	1			T280	1		T278	1		T222	1
alert_ping_fail	alert[0x6]	16	1			T1	1		T19	1		T234	3
alert_ping_fail	alert[0x7]	16	1			T18	1		T282	1		T278	1
alert_ping_fail	alert[0x8]	16	1			T290	1		T222	1		T102	3
alert_ping_fail	alert[0x9]	9	1			T283	1		T290	1		T227	1
alert_ping_fail	alert[0xa]	16	1			T17	2		T277	1		T283	1
alert_ping_fail	alert[0xb]	4	1			T226	1		T291	1		T292	1
alert_ping_fail	alert[0xc]	20	1			T18	1		T277	1		T279	1
alert_ping_fail	alert[0xd]	10	1			T278	1		T287	1		T286	1
alert_ping_fail	alert[0xe]	11	1			T287	1		T283	1		T284	1
alert_ping_fail	alert[0xf]	13	1			T18	2		T79	1		T287	1
alert_ping_fail	alert[0x10]	9	1			T285	1		T283	1		T290	1
alert_ping_fail	alert[0x11]	10	1			T115	1		T277	1		T286	2
alert_ping_fail	alert[0x12]	9	1			T277	1		T278	1		T293	1
alert_ping_fail	alert[0x13]	16	1			T79	1		T279	1		T44	1
alert_ping_fail	alert[0x14]	13	1			T79	1		T273	1		T275	1
alert_ping_fail	alert[0x15]	13	1			T79	1		T115	1		T286	1
alert_ping_fail	alert[0x16]	11	1			T79	1		T279	1		T280	1
alert_ping_fail	alert[0x17]	9	1			T79	1		T279	3		T102	1
alert_ping_fail	alert[0x18]	13	1			T283	2		T225	1		T226	1
alert_ping_fail	alert[0x19]	6	1			T79	1		T284	1		T225	1
alert_ping_fail	alert[0x1a]	6	1			T278	1		T291	1		T294	1
alert_ping_fail	alert[0x1b]	11	1			T19	1		T75	1		T115	1
alert_ping_fail	alert[0x1c]	17	1			T277	1		T280	1		T283	1
alert_ping_fail	alert[0x1d]	8	1			T285	1		T287	1		T283	1
alert_ping_fail	alert[0x1e]	10	1			T19	1		T279	1		T280	1
alert_ping_fail	alert[0x1f]	12	1			T234	1		T273	1		T278	1
alert_ping_fail	alert[0x20]	8	1			T286	1		T293	1		T226	2
alert_ping_fail	alert[0x21]	10	1			T19	1		T277	1		T290	2
alert_ping_fail	alert[0x22]	19	1			T277	1		T282	1		T276	1
alert_ping_fail	alert[0x23]	11	1			T284	1		T295	1		T296	2
alert_ping_fail	alert[0x24]	8	1			T277	1		T293	2		T226	1
alert_ping_fail	alert[0x25]	11	1			T279	1		T278	1		T283	1
alert_ping_fail	alert[0x26]	10	1			T293	1		T102	2		T297	1
alert_ping_fail	alert[0x27]	3	1			T18	1		T290	1		T102	1
alert_ping_fail	alert[0x28]	11	1			T279	1		T287	1		T284	2
alert_ping_fail	alert[0x29]	11	1			T20	1		T277	1		T293	1
alert_ping_fail	alert[0x2a]	17	1			T44	1		T287	1		T290	2
alert_ping_fail	alert[0x2b]	17	1			T293	1		T225	1		T227	1
alert_ping_fail	alert[0x2c]	10	1			T1	1		T75	1		T115	1
alert_ping_fail	alert[0x2d]	13	1			T293	1		T226	1		T102	1
alert_ping_fail	alert[0x2e]	8	1			T1	2		T279	1		T283	1
alert_ping_fail	alert[0x2f]	13	1			T277	1		T285	2		T286	1
alert_ping_fail	alert[0x30]	12	1			T280	1		T278	1		T293	1
alert_ping_fail	alert[0x31]	8	1			T279	1		T298	1		T292	1
alert_ping_fail	alert[0x32]	10	1			T20	1		T277	1		T284	1
alert_ping_fail	alert[0x33]	14	1			T277	1		T286	1		T298	1
alert_ping_fail	alert[0x34]	7	1			T279	1		T287	3		T296	1
alert_ping_fail	alert[0x35]	7	1			T20	1		T283	1		T299	1
alert_ping_fail	alert[0x36]	7	1			T19	1		T102	1		T296	1
alert_ping_fail	alert[0x37]	10	1			T284	1		T226	1		T298	1
alert_ping_fail	alert[0x38]	11	1			T278	2		T297	1		T295	1
alert_ping_fail	alert[0x39]	7	1			T284	1		T222	1		T102	1
alert_ping_fail	alert[0x3a]	9	1			T19	1		T20	1		T283	1
alert_ping_fail	alert[0x3b]	4	1			T277	1		T280	1		T298	1
alert_ping_fail	alert[0x3c]	10	1			T79	2		T280	1		T284	1
alert_ping_fail	alert[0x3d]	8	1			T19	1		T277	1		T225	1
alert_ping_fail	alert[0x3e]	6	1			T279	1		T284	1		T225	1
alert_ping_fail	alert[0x3f]	7	1			T285	1		T284	1		T299	1
alert_ping_fail	alert[0x40]	8	1			T290	1		T298	1		T300	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	110842	1			T13	3		T24	243		T34	281
alert_integrity_fail	class_i[0x1]	95867	1			T6	22		T30	11829		T32	6
alert_integrity_fail	class_i[0x2]	73173	1			T23	2		T30	239		T32	6
alert_integrity_fail	class_i[0x3]	63847	1			T13	9		T6	1		T23	9962
alert_ping_fail	class_i[0x0]	161	1			T17	2		T234	4		T20	1
alert_ping_fail	class_i[0x1]	194	1			T18	2		T19	1		T20	3
alert_ping_fail	class_i[0x2]	200	1			T1	4		T18	1		T19	1
alert_ping_fail	class_i[0x3]	144	1			T18	2		T19	6		T75	2