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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.99 98.72 97.09 100.00 100.00 99.38 99.60


Total test records in report: 833
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T776 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.392607275 Aug 19 04:32:20 PM PDT 24 Aug 19 04:32:25 PM PDT 24 36445837 ps
T777 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.245033573 Aug 19 04:32:40 PM PDT 24 Aug 19 04:33:05 PM PDT 24 906595724 ps
T138 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2482077029 Aug 19 04:32:22 PM PDT 24 Aug 19 04:50:38 PM PDT 24 16104883964 ps
T187 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2427844756 Aug 19 04:32:41 PM PDT 24 Aug 19 04:33:04 PM PDT 24 223144648 ps
T778 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3338155947 Aug 19 04:32:23 PM PDT 24 Aug 19 04:32:29 PM PDT 24 176671406 ps
T779 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3807719145 Aug 19 04:32:44 PM PDT 24 Aug 19 04:32:46 PM PDT 24 53130214 ps
T780 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4145659506 Aug 19 04:32:22 PM PDT 24 Aug 19 04:32:30 PM PDT 24 122141278 ps
T781 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4075641543 Aug 19 04:32:22 PM PDT 24 Aug 19 04:32:24 PM PDT 24 14646879 ps
T171 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3473429709 Aug 19 04:32:43 PM PDT 24 Aug 19 04:33:54 PM PDT 24 3674483842 ps
T782 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2493442795 Aug 19 04:32:20 PM PDT 24 Aug 19 04:32:28 PM PDT 24 399503756 ps
T158 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4065945706 Aug 19 04:32:28 PM PDT 24 Aug 19 04:36:58 PM PDT 24 15772403036 ps
T783 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3419023472 Aug 19 04:32:33 PM PDT 24 Aug 19 04:32:38 PM PDT 24 108904189 ps
T784 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1727922629 Aug 19 04:32:32 PM PDT 24 Aug 19 04:32:40 PM PDT 24 355495784 ps
T154 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3840549936 Aug 19 04:32:24 PM PDT 24 Aug 19 04:35:05 PM PDT 24 2596592402 ps
T785 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.769305482 Aug 19 04:32:25 PM PDT 24 Aug 19 04:32:31 PM PDT 24 239531233 ps
T786 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.250692240 Aug 19 04:32:35 PM PDT 24 Aug 19 04:32:36 PM PDT 24 13899452 ps
T787 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3383765483 Aug 19 04:32:26 PM PDT 24 Aug 19 04:33:04 PM PDT 24 500741100 ps
T179 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2651009187 Aug 19 04:32:21 PM PDT 24 Aug 19 04:33:02 PM PDT 24 600822463 ps
T788 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.226907303 Aug 19 04:32:46 PM PDT 24 Aug 19 04:32:47 PM PDT 24 9388938 ps
T789 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1650901587 Aug 19 04:32:38 PM PDT 24 Aug 19 04:32:46 PM PDT 24 155387493 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.603642186 Aug 19 04:32:39 PM PDT 24 Aug 19 04:32:51 PM PDT 24 174607016 ps
T791 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3801041689 Aug 19 04:32:36 PM PDT 24 Aug 19 04:32:38 PM PDT 24 10059883 ps
T143 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3150237976 Aug 19 04:32:23 PM PDT 24 Aug 19 04:37:58 PM PDT 24 6365193404 ps
T150 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.8432610 Aug 19 04:32:26 PM PDT 24 Aug 19 04:48:00 PM PDT 24 23001393411 ps
T161 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2786488713 Aug 19 04:32:25 PM PDT 24 Aug 19 04:48:28 PM PDT 24 11933070830 ps
T792 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2637403165 Aug 19 04:32:39 PM PDT 24 Aug 19 04:32:40 PM PDT 24 6715808 ps
T793 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2144825445 Aug 19 04:32:40 PM PDT 24 Aug 19 04:32:41 PM PDT 24 8666981 ps
T794 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3947153343 Aug 19 04:32:44 PM PDT 24 Aug 19 04:32:45 PM PDT 24 22817525 ps
T172 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2865410890 Aug 19 04:32:20 PM PDT 24 Aug 19 04:32:23 PM PDT 24 122980800 ps
T795 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1853357505 Aug 19 04:32:39 PM PDT 24 Aug 19 04:35:55 PM PDT 24 1696562293 ps
T796 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1881869741 Aug 19 04:32:42 PM PDT 24 Aug 19 04:33:20 PM PDT 24 483585335 ps
T797 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3802777624 Aug 19 04:32:33 PM PDT 24 Aug 19 04:32:35 PM PDT 24 28223494 ps
T798 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2969415204 Aug 19 04:32:37 PM PDT 24 Aug 19 04:32:55 PM PDT 24 937631076 ps
T799 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2387628388 Aug 19 04:32:32 PM PDT 24 Aug 19 04:32:38 PM PDT 24 96580625 ps
T800 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2071053157 Aug 19 04:32:36 PM PDT 24 Aug 19 04:32:57 PM PDT 24 320997448 ps
T801 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2109485633 Aug 19 04:32:35 PM PDT 24 Aug 19 04:32:37 PM PDT 24 14437768 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1676803315 Aug 19 04:32:41 PM PDT 24 Aug 19 04:33:22 PM PDT 24 1026115864 ps
T803 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2934703952 Aug 19 04:32:40 PM PDT 24 Aug 19 04:32:42 PM PDT 24 7554009 ps
T804 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.788069839 Aug 19 04:32:26 PM PDT 24 Aug 19 04:32:35 PM PDT 24 116930622 ps
T134 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1378814279 Aug 19 04:32:21 PM PDT 24 Aug 19 04:37:36 PM PDT 24 4895573308 ps
T180 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2181908876 Aug 19 04:32:30 PM PDT 24 Aug 19 04:33:05 PM PDT 24 449480535 ps
T805 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2566862516 Aug 19 04:32:36 PM PDT 24 Aug 19 04:32:41 PM PDT 24 169591165 ps
T164 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3286794112 Aug 19 04:32:44 PM PDT 24 Aug 19 04:37:47 PM PDT 24 2457315303 ps
T162 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.4254769878 Aug 19 04:32:20 PM PDT 24 Aug 19 04:34:05 PM PDT 24 856265905 ps
T806 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1461089047 Aug 19 04:32:14 PM PDT 24 Aug 19 04:32:19 PM PDT 24 47470324 ps
T807 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3530231223 Aug 19 04:32:44 PM PDT 24 Aug 19 04:32:46 PM PDT 24 6244447 ps
T163 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.315241202 Aug 19 04:32:16 PM PDT 24 Aug 19 04:35:06 PM PDT 24 20448119557 ps
T151 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2890607554 Aug 19 04:32:47 PM PDT 24 Aug 19 04:37:58 PM PDT 24 4646690426 ps
T808 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3312945785 Aug 19 04:32:39 PM PDT 24 Aug 19 04:32:52 PM PDT 24 383386410 ps
T809 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3368648238 Aug 19 04:32:47 PM PDT 24 Aug 19 04:32:48 PM PDT 24 8585611 ps
T810 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2052223681 Aug 19 04:32:31 PM PDT 24 Aug 19 04:33:43 PM PDT 24 2248039718 ps
T811 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3563917412 Aug 19 04:32:36 PM PDT 24 Aug 19 04:32:48 PM PDT 24 237249103 ps
T812 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1004563956 Aug 19 04:32:34 PM PDT 24 Aug 19 04:32:39 PM PDT 24 66443508 ps
T152 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1763554354 Aug 19 04:32:43 PM PDT 24 Aug 19 04:37:43 PM PDT 24 35969416168 ps
T813 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3720937745 Aug 19 04:32:18 PM PDT 24 Aug 19 04:32:43 PM PDT 24 191270383 ps
T178 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1812541454 Aug 19 04:32:44 PM PDT 24 Aug 19 04:32:47 PM PDT 24 187060728 ps
T814 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.564636278 Aug 19 04:32:40 PM PDT 24 Aug 19 04:32:41 PM PDT 24 28417525 ps
T815 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1735143620 Aug 19 04:32:13 PM PDT 24 Aug 19 04:32:20 PM PDT 24 107586133 ps
T816 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1159597004 Aug 19 04:32:12 PM PDT 24 Aug 19 04:32:21 PM PDT 24 99136662 ps
T817 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3487324548 Aug 19 04:32:36 PM PDT 24 Aug 19 04:33:03 PM PDT 24 1807583967 ps
T818 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2820953048 Aug 19 04:32:36 PM PDT 24 Aug 19 04:32:46 PM PDT 24 126586907 ps
T819 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1793933026 Aug 19 04:32:21 PM PDT 24 Aug 19 04:32:29 PM PDT 24 59378770 ps
T174 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1455356847 Aug 19 04:32:41 PM PDT 24 Aug 19 04:33:53 PM PDT 24 4420686668 ps
T820 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.128539317 Aug 19 04:32:27 PM PDT 24 Aug 19 04:32:32 PM PDT 24 56071594 ps
T821 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4027242940 Aug 19 04:32:36 PM PDT 24 Aug 19 04:32:41 PM PDT 24 152637833 ps
T822 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3967845244 Aug 19 04:32:15 PM PDT 24 Aug 19 04:39:10 PM PDT 24 16090716236 ps
T823 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3664029551 Aug 19 04:32:38 PM PDT 24 Aug 19 04:32:39 PM PDT 24 7675206 ps
T824 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2148538042 Aug 19 04:32:32 PM PDT 24 Aug 19 04:32:36 PM PDT 24 73494046 ps
T825 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.493697330 Aug 19 04:32:37 PM PDT 24 Aug 19 04:32:42 PM PDT 24 286518405 ps
T826 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.919322906 Aug 19 04:32:31 PM PDT 24 Aug 19 04:32:35 PM PDT 24 28802573 ps
T827 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3620284871 Aug 19 04:32:44 PM PDT 24 Aug 19 04:32:51 PM PDT 24 191940923 ps
T156 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.310766118 Aug 19 04:32:45 PM PDT 24 Aug 19 04:34:25 PM PDT 24 4699682501 ps
T135 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1523211607 Aug 19 04:32:41 PM PDT 24 Aug 19 04:39:10 PM PDT 24 7870666430 ps
T828 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4105469279 Aug 19 04:32:38 PM PDT 24 Aug 19 04:37:16 PM PDT 24 17926207577 ps
T829 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1065075546 Aug 19 04:32:32 PM PDT 24 Aug 19 04:33:07 PM PDT 24 521183841 ps
T358 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2054851164 Aug 19 04:32:19 PM PDT 24 Aug 19 04:40:39 PM PDT 24 85657348800 ps
T830 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1393613703 Aug 19 04:32:35 PM PDT 24 Aug 19 04:32:45 PM PDT 24 62972177 ps
T155 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2212315974 Aug 19 04:32:40 PM PDT 24 Aug 19 04:35:34 PM PDT 24 6168951775 ps
T831 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4184431808 Aug 19 04:32:22 PM PDT 24 Aug 19 04:32:23 PM PDT 24 45271647 ps
T832 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.245779509 Aug 19 04:32:33 PM PDT 24 Aug 19 04:32:36 PM PDT 24 20235002 ps
T833 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3952282257 Aug 19 04:32:34 PM PDT 24 Aug 19 04:34:42 PM PDT 24 1860821851 ps
T181 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.218610556 Aug 19 04:32:36 PM PDT 24 Aug 19 04:33:20 PM PDT 24 358575369 ps
T177 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3326764415 Aug 19 04:32:43 PM PDT 24 Aug 19 04:32:46 PM PDT 24 64326307 ps

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1753804269
Short name T7
Test name
Test status
Simulation time 171162880956 ps
CPU time 2544.28 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:37:39 PM PDT 24
Peak memory 289016 kb
Host smart-b17a8d34-9b1c-4289-a0ed-c48aa4b791ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753804269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1753804269
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2765008573
Short name T24
Test name
Test status
Simulation time 173264504996 ps
CPU time 3360.07 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 05:50:23 PM PDT 24
Peak memory 298036 kb
Host smart-be9ae3f6-889c-4088-a3f5-64e751664d60
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765008573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2765008573
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.311936426
Short name T74
Test name
Test status
Simulation time 5077853212 ps
CPU time 318.28 seconds
Started Aug 19 04:56:07 PM PDT 24
Finished Aug 19 05:01:26 PM PDT 24
Peak memory 265312 kb
Host smart-b16e85ff-cf52-43d9-95d1-d25e9bec74dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311936426 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.311936426
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3052813432
Short name T9
Test name
Test status
Simulation time 439546751 ps
CPU time 12.82 seconds
Started Aug 19 04:54:13 PM PDT 24
Finished Aug 19 04:54:26 PM PDT 24
Peak memory 269756 kb
Host smart-8c40213b-00d6-429d-95ac-371c3d1d8829
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3052813432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3052813432
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.4099568004
Short name T165
Test name
Test status
Simulation time 341772630 ps
CPU time 39.67 seconds
Started Aug 19 04:32:22 PM PDT 24
Finished Aug 19 04:33:02 PM PDT 24
Peak memory 246012 kb
Host smart-ad3b80cd-9a7c-47c5-83e2-9239e2e55d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4099568004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.4099568004
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3702809807
Short name T5
Test name
Test status
Simulation time 170620264 ps
CPU time 10.64 seconds
Started Aug 19 04:54:36 PM PDT 24
Finished Aug 19 04:54:47 PM PDT 24
Peak memory 248692 kb
Host smart-27e66e5c-c067-4194-b93d-f6df10494ec6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3702809807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3702809807
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2144386848
Short name T318
Test name
Test status
Simulation time 6174077403 ps
CPU time 572.58 seconds
Started Aug 19 04:56:36 PM PDT 24
Finished Aug 19 05:06:09 PM PDT 24
Peak memory 272524 kb
Host smart-eb7fe23e-c5e4-4460-a3f2-cf40cbb95831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144386848 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2144386848
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.833617998
Short name T30
Test name
Test status
Simulation time 105396978226 ps
CPU time 1577.58 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 05:20:50 PM PDT 24
Peak memory 282720 kb
Host smart-9b6fb7af-2bd6-4204-863e-514be5067ff0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833617998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.833617998
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.633305023
Short name T6
Test name
Test status
Simulation time 1467555144 ps
CPU time 202.67 seconds
Started Aug 19 04:54:16 PM PDT 24
Finished Aug 19 04:57:39 PM PDT 24
Peak memory 265060 kb
Host smart-39bdcd9f-8c82-4ad6-9b83-ada725204aa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633305023 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.633305023
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1782659800
Short name T140
Test name
Test status
Simulation time 5775762469 ps
CPU time 351.27 seconds
Started Aug 19 04:32:19 PM PDT 24
Finished Aug 19 04:38:11 PM PDT 24
Peak memory 265720 kb
Host smart-ce80745a-4375-433d-8140-3dc07c045961
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1782659800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1782659800
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4167955814
Short name T1
Test name
Test status
Simulation time 91983432841 ps
CPU time 2797.08 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 05:42:54 PM PDT 24
Peak memory 284040 kb
Host smart-546dc3c5-3bea-4b97-8468-4238b22aaa27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167955814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4167955814
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3912428668
Short name T106
Test name
Test status
Simulation time 3367248015 ps
CPU time 113.74 seconds
Started Aug 19 04:55:55 PM PDT 24
Finished Aug 19 04:57:49 PM PDT 24
Peak memory 265452 kb
Host smart-eed47be1-a975-46f4-b3f8-6df19a046801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912428668 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3912428668
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.565490871
Short name T697
Test name
Test status
Simulation time 483855457 ps
CPU time 10.35 seconds
Started Aug 19 04:55:56 PM PDT 24
Finished Aug 19 04:56:06 PM PDT 24
Peak memory 253724 kb
Host smart-5037d6a4-b0b8-4a11-84be-ec8ed900f3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56549
0871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.565490871
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1514339520
Short name T146
Test name
Test status
Simulation time 13765371627 ps
CPU time 1012.23 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:49:37 PM PDT 24
Peak memory 273360 kb
Host smart-cac5e95e-5da8-467f-b040-859c53700083
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514339520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1514339520
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3674155945
Short name T102
Test name
Test status
Simulation time 54186719337 ps
CPU time 544.79 seconds
Started Aug 19 04:54:19 PM PDT 24
Finished Aug 19 05:03:24 PM PDT 24
Peak memory 248876 kb
Host smart-6c30941e-3b33-4e4d-90df-884b2dd8124f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674155945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3674155945
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4114158500
Short name T148
Test name
Test status
Simulation time 9341308929 ps
CPU time 322.8 seconds
Started Aug 19 04:32:20 PM PDT 24
Finished Aug 19 04:37:43 PM PDT 24
Peak memory 270892 kb
Host smart-1ebd6873-cc60-4ad2-87bb-b5eb0deb7737
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114158500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4114158500
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.912641796
Short name T145
Test name
Test status
Simulation time 3554778173 ps
CPU time 258.83 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:36:33 PM PDT 24
Peak memory 265532 kb
Host smart-14996b1d-002b-4029-95b9-59591d392777
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=912641796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.912641796
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2742286200
Short name T307
Test name
Test status
Simulation time 222840982386 ps
CPU time 3116.26 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 05:46:27 PM PDT 24
Peak memory 289028 kb
Host smart-1334a2d0-d4ef-4efc-b790-319530c54916
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742286200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2742286200
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3847107838
Short name T277
Test name
Test status
Simulation time 38073601952 ps
CPU time 406.86 seconds
Started Aug 19 04:55:16 PM PDT 24
Finished Aug 19 05:02:03 PM PDT 24
Peak memory 248844 kb
Host smart-ec4707dd-b715-4a22-8641-79ff36dc7b28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847107838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3847107838
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1631196152
Short name T168
Test name
Test status
Simulation time 24862493 ps
CPU time 1.35 seconds
Started Aug 19 04:32:41 PM PDT 24
Finished Aug 19 04:32:43 PM PDT 24
Peak memory 236960 kb
Host smart-6214f218-eb35-4bb0-9e45-0250f44e76fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1631196152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1631196152
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1463054491
Short name T97
Test name
Test status
Simulation time 52988224785 ps
CPU time 3263.52 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 05:50:29 PM PDT 24
Peak memory 289488 kb
Host smart-153804f4-f1ea-41be-b916-64f1c7154004
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463054491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1463054491
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2786488713
Short name T161
Test name
Test status
Simulation time 11933070830 ps
CPU time 962.82 seconds
Started Aug 19 04:32:25 PM PDT 24
Finished Aug 19 04:48:28 PM PDT 24
Peak memory 273704 kb
Host smart-d04d3792-fae6-4741-a1c2-dd1bd4860fc9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786488713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2786488713
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.943848077
Short name T283
Test name
Test status
Simulation time 57048919560 ps
CPU time 582.72 seconds
Started Aug 19 04:55:33 PM PDT 24
Finished Aug 19 05:05:16 PM PDT 24
Peak memory 248836 kb
Host smart-4fbaf2a9-ff80-49cb-9189-edcb4e7f4db9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943848077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.943848077
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.209560395
Short name T23
Test name
Test status
Simulation time 18812201579 ps
CPU time 1756.68 seconds
Started Aug 19 04:56:50 PM PDT 24
Finished Aug 19 05:26:07 PM PDT 24
Peak memory 289316 kb
Host smart-672c570e-5389-442d-b577-a7f4996f3e3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209560395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.209560395
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1523211607
Short name T135
Test name
Test status
Simulation time 7870666430 ps
CPU time 388.39 seconds
Started Aug 19 04:32:41 PM PDT 24
Finished Aug 19 04:39:10 PM PDT 24
Peak memory 273160 kb
Host smart-b3010cd1-e22b-42b7-af42-d6fa805a1591
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1523211607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1523211607
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.4114604947
Short name T63
Test name
Test status
Simulation time 7692114172 ps
CPU time 435.02 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 05:02:23 PM PDT 24
Peak memory 272324 kb
Host smart-9723b40a-3da3-418c-8acd-c19399164795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114604947 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.4114604947
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.861859367
Short name T126
Test name
Test status
Simulation time 35557048696 ps
CPU time 2098.27 seconds
Started Aug 19 04:54:51 PM PDT 24
Finished Aug 19 05:29:50 PM PDT 24
Peak memory 287040 kb
Host smart-2ce4c36d-f2ef-4f8e-9d23-ebe39bf79ef0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861859367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.861859367
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3393340515
Short name T132
Test name
Test status
Simulation time 4357471188 ps
CPU time 273.44 seconds
Started Aug 19 04:32:35 PM PDT 24
Finished Aug 19 04:37:09 PM PDT 24
Peak memory 270836 kb
Host smart-63b12e21-9fd6-41df-b4a9-56917eaa1bac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393340515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3393340515
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3793796852
Short name T75
Test name
Test status
Simulation time 322517873312 ps
CPU time 2544.68 seconds
Started Aug 19 04:55:21 PM PDT 24
Finished Aug 19 05:37:46 PM PDT 24
Peak memory 289084 kb
Host smart-ad78fadb-549f-406d-9a55-2f1d80296906
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793796852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3793796852
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3891514210
Short name T284
Test name
Test status
Simulation time 52017836014 ps
CPU time 548.56 seconds
Started Aug 19 04:56:36 PM PDT 24
Finished Aug 19 05:05:44 PM PDT 24
Peak memory 248520 kb
Host smart-4a5302c7-70a8-41b1-9a8f-dc0c827a0354
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891514210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3891514210
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3286794112
Short name T164
Test name
Test status
Simulation time 2457315303 ps
CPU time 303.61 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:37:47 PM PDT 24
Peak memory 270052 kb
Host smart-b273c11f-6fa2-4fce-bf32-59fbdfe3f45d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286794112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3286794112
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1842654776
Short name T55
Test name
Test status
Simulation time 191401804565 ps
CPU time 3289.53 seconds
Started Aug 19 04:55:54 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 289236 kb
Host smart-6c10ec27-5113-4169-ac3d-e2eda87b0f6b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842654776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1842654776
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1378814279
Short name T134
Test name
Test status
Simulation time 4895573308 ps
CPU time 314.34 seconds
Started Aug 19 04:32:21 PM PDT 24
Finished Aug 19 04:37:36 PM PDT 24
Peak memory 266136 kb
Host smart-ebf4b9e4-446a-4a28-aa4b-8ca19c978599
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1378814279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1378814279
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.4195931006
Short name T612
Test name
Test status
Simulation time 635004711759 ps
CPU time 2185.24 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 05:31:32 PM PDT 24
Peak memory 273424 kb
Host smart-7ea9046e-90d6-4576-81dc-2598c34b83d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195931006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4195931006
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2732031037
Short name T62
Test name
Test status
Simulation time 11957961727 ps
CPU time 192.96 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:58:20 PM PDT 24
Peak memory 257000 kb
Host smart-c8cec5be-3547-46fd-920c-29d1091960d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732031037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2732031037
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.566750858
Short name T136
Test name
Test status
Simulation time 7283383915 ps
CPU time 524.47 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:40:58 PM PDT 24
Peak memory 265836 kb
Host smart-11af4dd0-25f3-425d-8822-af60cae2ba42
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566750858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.566750858
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2209598403
Short name T278
Test name
Test status
Simulation time 22043003741 ps
CPU time 445.1 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 05:03:08 PM PDT 24
Peak memory 248804 kb
Host smart-03f35b0b-7d57-44c9-acad-3b49d83641ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209598403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2209598403
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.97056233
Short name T330
Test name
Test status
Simulation time 38731091893 ps
CPU time 2270.33 seconds
Started Aug 19 04:54:52 PM PDT 24
Finished Aug 19 05:32:43 PM PDT 24
Peak memory 273340 kb
Host smart-4cb280a6-a1e7-40a7-8591-dae02c3d57c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97056233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.97056233
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3462769869
Short name T258
Test name
Test status
Simulation time 16748253169 ps
CPU time 381.64 seconds
Started Aug 19 04:55:19 PM PDT 24
Finished Aug 19 05:01:40 PM PDT 24
Peak memory 265204 kb
Host smart-aaf33249-ac82-4883-a153-91589f70e436
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462769869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3462769869
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3330241511
Short name T250
Test name
Test status
Simulation time 5485212417 ps
CPU time 36.66 seconds
Started Aug 19 04:55:44 PM PDT 24
Finished Aug 19 04:56:21 PM PDT 24
Peak memory 256004 kb
Host smart-d9978b3f-1130-42d2-8e5b-c6947af59897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33302
41511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3330241511
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2212315974
Short name T155
Test name
Test status
Simulation time 6168951775 ps
CPU time 173.82 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 266756 kb
Host smart-1865e278-88c6-4525-8558-48cfcf9473b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2212315974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2212315974
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2666128616
Short name T349
Test name
Test status
Simulation time 11228926 ps
CPU time 1.51 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:37 PM PDT 24
Peak memory 236620 kb
Host smart-65e65399-507c-46cf-85da-179f9f9d734d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2666128616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2666128616
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.318871038
Short name T288
Test name
Test status
Simulation time 9238271171 ps
CPU time 364.74 seconds
Started Aug 19 04:55:00 PM PDT 24
Finished Aug 19 05:01:05 PM PDT 24
Peak memory 247528 kb
Host smart-e143000e-d194-447d-a21d-fb5a427c432c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318871038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.318871038
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2835535129
Short name T329
Test name
Test status
Simulation time 120778073647 ps
CPU time 1742.43 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 05:24:09 PM PDT 24
Peak memory 273468 kb
Host smart-939b94d3-fbdb-46f7-8a9e-5b08a8938f36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835535129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2835535129
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2482077029
Short name T138
Test name
Test status
Simulation time 16104883964 ps
CPU time 1096.03 seconds
Started Aug 19 04:32:22 PM PDT 24
Finished Aug 19 04:50:38 PM PDT 24
Peak memory 271620 kb
Host smart-be9c6ec2-a28d-421f-a736-947e1b0c4c06
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482077029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2482077029
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1797471864
Short name T173
Test name
Test status
Simulation time 1020677775 ps
CPU time 64.6 seconds
Started Aug 19 04:32:21 PM PDT 24
Finished Aug 19 04:33:26 PM PDT 24
Peak memory 240616 kb
Host smart-3450661d-3d83-44d3-a3c5-c52bf7bce971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1797471864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1797471864
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3633049042
Short name T226
Test name
Test status
Simulation time 48520249864 ps
CPU time 484.48 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:03:19 PM PDT 24
Peak memory 248840 kb
Host smart-c5637a45-0895-4b76-ac34-1ddfec3f8215
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633049042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3633049042
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1866208640
Short name T325
Test name
Test status
Simulation time 137359813391 ps
CPU time 1996.99 seconds
Started Aug 19 04:55:10 PM PDT 24
Finished Aug 19 05:28:28 PM PDT 24
Peak memory 289752 kb
Host smart-6e4805ed-02ed-4328-8969-a9dbfa23bee3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866208640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1866208640
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.969854905
Short name T90
Test name
Test status
Simulation time 192059719076 ps
CPU time 1899.6 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 05:26:55 PM PDT 24
Peak memory 281692 kb
Host smart-93a041bc-1958-488b-9dcf-32180d5a0d72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969854905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.969854905
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1243061296
Short name T254
Test name
Test status
Simulation time 16853879668 ps
CPU time 313.63 seconds
Started Aug 19 04:55:31 PM PDT 24
Finished Aug 19 05:00:45 PM PDT 24
Peak memory 266432 kb
Host smart-30788897-2f23-4093-a620-f3438e445602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243061296 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1243061296
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.620255087
Short name T124
Test name
Test status
Simulation time 533984512 ps
CPU time 9.85 seconds
Started Aug 19 04:55:34 PM PDT 24
Finished Aug 19 04:55:44 PM PDT 24
Peak memory 248812 kb
Host smart-e5aa65bc-b6f0-445c-b163-84a2bfb6e6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62025
5087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.620255087
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3581615252
Short name T336
Test name
Test status
Simulation time 16389400919 ps
CPU time 1134.58 seconds
Started Aug 19 04:56:32 PM PDT 24
Finished Aug 19 05:15:27 PM PDT 24
Peak memory 287432 kb
Host smart-0265af47-db88-4c88-916b-932ec88287ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581615252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3581615252
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.577662712
Short name T36
Test name
Test status
Simulation time 2964221741 ps
CPU time 302.66 seconds
Started Aug 19 04:56:48 PM PDT 24
Finished Aug 19 05:01:51 PM PDT 24
Peak memory 273576 kb
Host smart-ab16e916-bbf9-4f3e-9591-1d342ea9545f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577662712 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.577662712
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2890607554
Short name T151
Test name
Test status
Simulation time 4646690426 ps
CPU time 310.76 seconds
Started Aug 19 04:32:47 PM PDT 24
Finished Aug 19 04:37:58 PM PDT 24
Peak memory 265688 kb
Host smart-14d00259-1e5f-486f-8f31-8b13a59d5115
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2890607554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2890607554
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2270922139
Short name T197
Test name
Test status
Simulation time 46781504 ps
CPU time 3.64 seconds
Started Aug 19 04:54:10 PM PDT 24
Finished Aug 19 04:54:13 PM PDT 24
Peak memory 248912 kb
Host smart-645aeabb-ac17-434d-934d-0e27da0b4422
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2270922139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2270922139
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.248282327
Short name T199
Test name
Test status
Simulation time 82309039 ps
CPU time 2.16 seconds
Started Aug 19 04:54:13 PM PDT 24
Finished Aug 19 04:54:15 PM PDT 24
Peak memory 249016 kb
Host smart-406d08e0-6143-4ea3-ad4e-584f03a6896b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=248282327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.248282327
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4217142918
Short name T213
Test name
Test status
Simulation time 99414105 ps
CPU time 2.75 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 04:54:36 PM PDT 24
Peak memory 248896 kb
Host smart-64c77462-08a3-4151-ad5a-8a3bfb00b1b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4217142918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4217142918
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3639126779
Short name T208
Test name
Test status
Simulation time 90646259 ps
CPU time 4.1 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 04:54:25 PM PDT 24
Peak memory 249020 kb
Host smart-ff38f27e-e8b4-4f25-9708-ff87da563e7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3639126779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3639126779
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1217525323
Short name T230
Test name
Test status
Simulation time 357977260299 ps
CPU time 2208.42 seconds
Started Aug 19 04:55:06 PM PDT 24
Finished Aug 19 05:31:55 PM PDT 24
Peak memory 288596 kb
Host smart-7a0fd3d8-dabe-4e57-8684-43e57ac6245b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217525323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1217525323
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.752792686
Short name T298
Test name
Test status
Simulation time 28205152719 ps
CPU time 535.56 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 247708 kb
Host smart-65b76716-e6f3-4ce8-b912-54652ca8ee6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752792686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.752792686
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.977746010
Short name T263
Test name
Test status
Simulation time 2179699075 ps
CPU time 61.01 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 04:56:12 PM PDT 24
Peak memory 257048 kb
Host smart-ad7eeac9-358d-43ac-ba44-2bf7f52f5cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97774
6010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.977746010
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.4198694319
Short name T251
Test name
Test status
Simulation time 54062244019 ps
CPU time 3163.77 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 05:47:51 PM PDT 24
Peak memory 289228 kb
Host smart-0a1ecbf3-713c-472c-87a3-0ce31dac8139
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198694319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.4198694319
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.940089078
Short name T314
Test name
Test status
Simulation time 42868608687 ps
CPU time 2565.87 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 05:38:28 PM PDT 24
Peak memory 289508 kb
Host smart-f2b44e57-09ce-4fc6-9e08-d3179967845e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940089078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.940089078
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2638331545
Short name T261
Test name
Test status
Simulation time 17103075711 ps
CPU time 271.11 seconds
Started Aug 19 04:56:14 PM PDT 24
Finished Aug 19 05:00:46 PM PDT 24
Peak memory 257056 kb
Host smart-fd1dbecb-126a-430b-b3e6-628eb3bf1129
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638331545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2638331545
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2886430158
Short name T166
Test name
Test status
Simulation time 65952075 ps
CPU time 4.75 seconds
Started Aug 19 04:32:41 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 237676 kb
Host smart-d8f079a8-6ff6-40d8-95a9-dd3fc3dc1710
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2886430158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2886430158
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1577802696
Short name T49
Test name
Test status
Simulation time 70513332 ps
CPU time 9.89 seconds
Started Aug 19 04:54:51 PM PDT 24
Finished Aug 19 04:55:01 PM PDT 24
Peak memory 255476 kb
Host smart-a7450ddd-473f-43ce-bbbe-33d2b814f57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15778
02696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1577802696
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.178546680
Short name T66
Test name
Test status
Simulation time 18726371045 ps
CPU time 329.83 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 05:00:37 PM PDT 24
Peak memory 253824 kb
Host smart-54c0de3c-fe6f-4d73-ac64-055771649c95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178546680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.178546680
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3369434594
Short name T133
Test name
Test status
Simulation time 1542761911 ps
CPU time 168.23 seconds
Started Aug 19 04:32:47 PM PDT 24
Finished Aug 19 04:35:35 PM PDT 24
Peak memory 265128 kb
Host smart-ddcc045b-add2-4352-bbd6-197c0a8b0df1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3369434594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3369434594
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1179708353
Short name T95
Test name
Test status
Simulation time 18465418093 ps
CPU time 1493.68 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 05:20:03 PM PDT 24
Peak memory 289616 kb
Host smart-7caa9a89-cdcd-410c-9eda-a89d0f4b4422
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179708353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1179708353
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.521750475
Short name T729
Test name
Test status
Simulation time 60820028 ps
CPU time 5.11 seconds
Started Aug 19 04:32:25 PM PDT 24
Finished Aug 19 04:32:30 PM PDT 24
Peak memory 252392 kb
Host smart-4f9a6375-5a81-4ba5-ab19-91956aa54393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521750475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.521750475
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.199077477
Short name T733
Test name
Test status
Simulation time 17182731 ps
CPU time 1.24 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:16 PM PDT 24
Peak memory 237776 kb
Host smart-19c3da53-a8e0-4d81-8880-a3be1464ae4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=199077477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.199077477
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3406575739
Short name T160
Test name
Test status
Simulation time 61324919334 ps
CPU time 504.06 seconds
Started Aug 19 04:32:18 PM PDT 24
Finished Aug 19 04:40:42 PM PDT 24
Peak memory 273524 kb
Host smart-0693a131-b672-4a1a-8cd7-685a3382cd06
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406575739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3406575739
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.8432610
Short name T150
Test name
Test status
Simulation time 23001393411 ps
CPU time 934.04 seconds
Started Aug 19 04:32:26 PM PDT 24
Finished Aug 19 04:48:00 PM PDT 24
Peak memory 270912 kb
Host smart-84931536-74fe-43ad-b356-f4422f54fe5e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8432610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_shadow_reg_errors_with_csr_rw.8432610
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.557664501
Short name T678
Test name
Test status
Simulation time 70633122415 ps
CPU time 1593.23 seconds
Started Aug 19 04:54:09 PM PDT 24
Finished Aug 19 05:20:42 PM PDT 24
Peak memory 289784 kb
Host smart-25c6cda4-fa61-4072-bf9f-d77ffe7ad782
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557664501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.557664501
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3839271975
Short name T525
Test name
Test status
Simulation time 2250934834 ps
CPU time 135.6 seconds
Started Aug 19 04:54:49 PM PDT 24
Finished Aug 19 04:57:05 PM PDT 24
Peak memory 257072 kb
Host smart-e6b67505-9ce8-48fa-8041-bad5fa9a5db5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839271975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3839271975
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3315428505
Short name T247
Test name
Test status
Simulation time 243580867 ps
CPU time 28.68 seconds
Started Aug 19 04:54:49 PM PDT 24
Finished Aug 19 04:55:18 PM PDT 24
Peak memory 256544 kb
Host smart-82dcb662-79bc-4046-b213-fd97811e04ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33154
28505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3315428505
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4202585704
Short name T249
Test name
Test status
Simulation time 4140282137 ps
CPU time 61.74 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 04:56:11 PM PDT 24
Peak memory 256920 kb
Host smart-da46ebe5-2f4c-4f43-af5d-f7cb8d230e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42025
85704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4202585704
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2087130015
Short name T304
Test name
Test status
Simulation time 3243648841 ps
CPU time 37.09 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 04:55:51 PM PDT 24
Peak memory 256296 kb
Host smart-8b365ee7-9d99-4a57-948d-8ba30a8c1ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20871
30015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2087130015
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2459688636
Short name T269
Test name
Test status
Simulation time 4054000542 ps
CPU time 296.71 seconds
Started Aug 19 04:55:31 PM PDT 24
Finished Aug 19 05:00:28 PM PDT 24
Peak memory 257004 kb
Host smart-b047d45b-90da-4a32-a513-0ebf12f86a89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459688636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2459688636
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1813588848
Short name T266
Test name
Test status
Simulation time 1062950397 ps
CPU time 36.17 seconds
Started Aug 19 04:55:31 PM PDT 24
Finished Aug 19 04:56:07 PM PDT 24
Peak memory 256008 kb
Host smart-f1542c7e-5b71-49bc-a6ef-98d964fdd744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18135
88848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1813588848
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2047942892
Short name T265
Test name
Test status
Simulation time 230095940 ps
CPU time 14.79 seconds
Started Aug 19 04:55:51 PM PDT 24
Finished Aug 19 04:56:06 PM PDT 24
Peak memory 248232 kb
Host smart-9ba75bc3-375d-4b28-bd6e-ef7b6e45f0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20479
42892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2047942892
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.238742647
Short name T262
Test name
Test status
Simulation time 538159882 ps
CPU time 35.71 seconds
Started Aug 19 04:56:33 PM PDT 24
Finished Aug 19 04:57:09 PM PDT 24
Peak memory 256108 kb
Host smart-ccca2f1b-01d1-4afa-b8f5-a05dbb3687f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23874
2647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.238742647
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3281073027
Short name T306
Test name
Test status
Simulation time 48329094356 ps
CPU time 813.52 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 05:07:56 PM PDT 24
Peak memory 273008 kb
Host smart-7579a8c5-9830-4034-81fe-b8d46554e4cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281073027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3281073027
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1125164433
Short name T286
Test name
Test status
Simulation time 12225631420 ps
CPU time 253.63 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:58:43 PM PDT 24
Peak memory 248800 kb
Host smart-477d902a-151a-4b9d-9223-153e52e1d17f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125164433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1125164433
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1455356847
Short name T174
Test name
Test status
Simulation time 4420686668 ps
CPU time 72.07 seconds
Started Aug 19 04:32:41 PM PDT 24
Finished Aug 19 04:33:53 PM PDT 24
Peak memory 247148 kb
Host smart-eb8fa734-8b3d-4ef9-9dbb-6e9ddf99db6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1455356847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1455356847
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3473429709
Short name T171
Test name
Test status
Simulation time 3674483842 ps
CPU time 70.11 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:33:54 PM PDT 24
Peak memory 240736 kb
Host smart-4935ee5b-85c5-47d0-84b2-4789b5c9177a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3473429709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3473429709
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3326764415
Short name T177
Test name
Test status
Simulation time 64326307 ps
CPU time 2.99 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 237776 kb
Host smart-4c8d67a4-db1b-417e-8a2c-cb34d88ba05c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3326764415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3326764415
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3150237976
Short name T143
Test name
Test status
Simulation time 6365193404 ps
CPU time 334.78 seconds
Started Aug 19 04:32:23 PM PDT 24
Finished Aug 19 04:37:58 PM PDT 24
Peak memory 265764 kb
Host smart-4639f4f5-7803-47d6-8978-225016aa9ed4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150237976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3150237976
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.218610556
Short name T181
Test name
Test status
Simulation time 358575369 ps
CPU time 44.25 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:33:20 PM PDT 24
Peak memory 240708 kb
Host smart-9c15401f-518e-4525-97f8-02a24a43ab8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=218610556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.218610556
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2651009187
Short name T179
Test name
Test status
Simulation time 600822463 ps
CPU time 41.52 seconds
Started Aug 19 04:32:21 PM PDT 24
Finished Aug 19 04:33:02 PM PDT 24
Peak memory 240660 kb
Host smart-66f5a8c2-3c97-4278-be2f-52742e8892c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2651009187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2651009187
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2176955084
Short name T176
Test name
Test status
Simulation time 5466165362 ps
CPU time 63.69 seconds
Started Aug 19 04:32:35 PM PDT 24
Finished Aug 19 04:33:39 PM PDT 24
Peak memory 248992 kb
Host smart-bfa59d5b-70e8-45e9-b28d-7d941388cffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2176955084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2176955084
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1774823664
Short name T182
Test name
Test status
Simulation time 3521474147 ps
CPU time 61.48 seconds
Started Aug 19 04:32:31 PM PDT 24
Finished Aug 19 04:33:33 PM PDT 24
Peak memory 240768 kb
Host smart-83601e2f-d979-46b2-a519-246add1566a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1774823664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1774823664
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3795752116
Short name T175
Test name
Test status
Simulation time 466088674 ps
CPU time 30.5 seconds
Started Aug 19 04:32:16 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 237968 kb
Host smart-dd916219-6161-4b47-b205-c14b435ec841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3795752116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3795752116
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2865410890
Short name T172
Test name
Test status
Simulation time 122980800 ps
CPU time 2.74 seconds
Started Aug 19 04:32:20 PM PDT 24
Finished Aug 19 04:32:23 PM PDT 24
Peak memory 237772 kb
Host smart-1135c66c-7416-40ad-b6a1-837d1e5cdfea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2865410890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2865410890
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2181908876
Short name T180
Test name
Test status
Simulation time 449480535 ps
CPU time 34.54 seconds
Started Aug 19 04:32:30 PM PDT 24
Finished Aug 19 04:33:05 PM PDT 24
Peak memory 237732 kb
Host smart-4f7bc0c7-03af-4188-b811-5106f680886c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2181908876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2181908876
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1812541454
Short name T178
Test name
Test status
Simulation time 187060728 ps
CPU time 2.85 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:32:47 PM PDT 24
Peak memory 237776 kb
Host smart-4065279c-e104-4bd3-8570-c9be805073c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1812541454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1812541454
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2427844756
Short name T187
Test name
Test status
Simulation time 223144648 ps
CPU time 23.16 seconds
Started Aug 19 04:32:41 PM PDT 24
Finished Aug 19 04:33:04 PM PDT 24
Peak memory 237760 kb
Host smart-c024005c-14d8-4817-9a5a-0053dd59e322
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2427844756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2427844756
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2023192191
Short name T167
Test name
Test status
Simulation time 1028740774 ps
CPU time 34.93 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:33:11 PM PDT 24
Peak memory 240636 kb
Host smart-e0cafa64-273d-4972-af8c-bdc5739fbf2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2023192191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2023192191
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.169943569
Short name T185
Test name
Test status
Simulation time 33116609 ps
CPU time 2.69 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:32:17 PM PDT 24
Peak memory 236880 kb
Host smart-5b19041c-324d-444f-ac43-1dcebf016554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=169943569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.169943569
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1976490869
Short name T17
Test name
Test status
Simulation time 13666339665 ps
CPU time 1201.84 seconds
Started Aug 19 04:54:14 PM PDT 24
Finished Aug 19 05:14:16 PM PDT 24
Peak memory 284656 kb
Host smart-4a77a88c-301f-4456-823d-93ead6da2180
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976490869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1976490869
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.295837140
Short name T31
Test name
Test status
Simulation time 150426569276 ps
CPU time 4543.85 seconds
Started Aug 19 04:56:04 PM PDT 24
Finished Aug 19 06:11:49 PM PDT 24
Peak memory 303896 kb
Host smart-bd2574a3-9a2f-4204-8fe2-bc438046566c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295837140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.295837140
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2052223681
Short name T810
Test name
Test status
Simulation time 2248039718 ps
CPU time 72.63 seconds
Started Aug 19 04:32:31 PM PDT 24
Finished Aug 19 04:33:43 PM PDT 24
Peak memory 237840 kb
Host smart-874da073-f599-471b-b7da-680f6b1a5cdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2052223681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2052223681
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3769705705
Short name T743
Test name
Test status
Simulation time 3270002334 ps
CPU time 105.66 seconds
Started Aug 19 04:32:24 PM PDT 24
Finished Aug 19 04:34:10 PM PDT 24
Peak memory 240652 kb
Host smart-a0de0d8c-cecd-4ae4-9bd2-c75523e0dc29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3769705705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3769705705
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1159597004
Short name T816
Test name
Test status
Simulation time 99136662 ps
CPU time 8.2 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:21 PM PDT 24
Peak memory 249376 kb
Host smart-79159b2d-3b0e-4ad7-bac5-51b2ef459663
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1159597004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1159597004
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1830559233
Short name T753
Test name
Test status
Simulation time 100091311 ps
CPU time 7.18 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:43 PM PDT 24
Peak memory 236920 kb
Host smart-5725bdfe-2503-42fc-a72a-415c99bd7f60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1830559233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1830559233
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1364701562
Short name T774
Test name
Test status
Simulation time 24386057 ps
CPU time 1.46 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:32:16 PM PDT 24
Peak memory 236748 kb
Host smart-2a05558d-4d77-4404-a58f-1c226f56e71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1364701562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1364701562
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3364487674
Short name T760
Test name
Test status
Simulation time 188912694 ps
CPU time 20.03 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:56 PM PDT 24
Peak memory 248928 kb
Host smart-95c52762-7c05-4067-b0f6-2a98a59605ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3364487674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3364487674
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2566255780
Short name T139
Test name
Test status
Simulation time 4800391347 ps
CPU time 329.12 seconds
Started Aug 19 04:32:21 PM PDT 24
Finished Aug 19 04:37:51 PM PDT 24
Peak memory 265684 kb
Host smart-615c0c12-8b62-4d8c-9cd3-41411ae8d7c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2566255780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2566255780
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.779808409
Short name T715
Test name
Test status
Simulation time 266273563 ps
CPU time 5.06 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 249108 kb
Host smart-41aa9fb7-cfac-4192-9071-9724c6a51cef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=779808409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.779808409
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3427687688
Short name T772
Test name
Test status
Simulation time 14267570521 ps
CPU time 138.59 seconds
Started Aug 19 04:32:29 PM PDT 24
Finished Aug 19 04:34:47 PM PDT 24
Peak memory 239552 kb
Host smart-ab3e64b7-a16a-4fb7-8575-ba629d7cc0a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3427687688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3427687688
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3967845244
Short name T822
Test name
Test status
Simulation time 16090716236 ps
CPU time 414.94 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:39:10 PM PDT 24
Peak memory 236808 kb
Host smart-7b2c58cd-d274-4e7e-9951-b931e64c5f1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3967845244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3967845244
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1626772477
Short name T737
Test name
Test status
Simulation time 37595823 ps
CPU time 5.38 seconds
Started Aug 19 04:32:25 PM PDT 24
Finished Aug 19 04:32:31 PM PDT 24
Peak memory 249324 kb
Host smart-e216d86c-8a8b-4cd9-a176-887e209fa33d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1626772477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1626772477
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.313875980
Short name T356
Test name
Test status
Simulation time 327028611 ps
CPU time 6.83 seconds
Started Aug 19 04:32:29 PM PDT 24
Finished Aug 19 04:32:36 PM PDT 24
Peak memory 240904 kb
Host smart-9bbc785e-8dfd-4875-ae70-d154fb18a80d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313875980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.313875980
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1461089047
Short name T806
Test name
Test status
Simulation time 47470324 ps
CPU time 4.23 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:19 PM PDT 24
Peak memory 237756 kb
Host smart-d96eda62-2351-4873-b58e-48f13b3f01f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1461089047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1461089047
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2824502483
Short name T766
Test name
Test status
Simulation time 352586967 ps
CPU time 20.55 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:33 PM PDT 24
Peak memory 248912 kb
Host smart-deb94739-1109-43ba-ac92-7a89ec0e9f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2824502483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2824502483
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.186214169
Short name T142
Test name
Test status
Simulation time 1887850743 ps
CPU time 129.79 seconds
Started Aug 19 04:32:20 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 265768 kb
Host smart-a4833238-6e85-485d-8b65-747a576ef313
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=186214169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.186214169
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3338155947
Short name T778
Test name
Test status
Simulation time 176671406 ps
CPU time 6.16 seconds
Started Aug 19 04:32:23 PM PDT 24
Finished Aug 19 04:32:29 PM PDT 24
Peak memory 248060 kb
Host smart-256a5fc0-2018-464b-8d53-4322217d89fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3338155947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3338155947
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.951337011
Short name T361
Test name
Test status
Simulation time 53641507 ps
CPU time 7 seconds
Started Aug 19 04:32:33 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 257156 kb
Host smart-1b29e899-43be-4efe-9abc-baf1e5186765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951337011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.951337011
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3810186416
Short name T183
Test name
Test status
Simulation time 497113293 ps
CPU time 9.71 seconds
Started Aug 19 04:32:38 PM PDT 24
Finished Aug 19 04:32:47 PM PDT 24
Peak memory 240732 kb
Host smart-7f453ba6-fc36-4894-a9e1-7d0f090f9c8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3810186416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3810186416
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3801041689
Short name T791
Test name
Test status
Simulation time 10059883 ps
CPU time 1.6 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:38 PM PDT 24
Peak memory 237796 kb
Host smart-726924b7-45fa-4547-b898-031499f4c2d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3801041689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3801041689
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2071053157
Short name T800
Test name
Test status
Simulation time 320997448 ps
CPU time 21.04 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:57 PM PDT 24
Peak memory 245980 kb
Host smart-80acd2b7-2d3c-414e-b7e0-8dae953cd328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2071053157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2071053157
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1693359789
Short name T130
Test name
Test status
Simulation time 2817448199 ps
CPU time 180.62 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:35:40 PM PDT 24
Peak memory 265728 kb
Host smart-b616c5fa-5d19-4e02-8930-0350e51f39a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1693359789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1693359789
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.652070198
Short name T759
Test name
Test status
Simulation time 220914839 ps
CPU time 15.07 seconds
Started Aug 19 04:32:41 PM PDT 24
Finished Aug 19 04:32:56 PM PDT 24
Peak memory 248960 kb
Host smart-65096c4e-0a3e-4faf-bf1a-8d6480c50f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=652070198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.652070198
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1772644909
Short name T742
Test name
Test status
Simulation time 65799829 ps
CPU time 4.48 seconds
Started Aug 19 04:32:47 PM PDT 24
Finished Aug 19 04:32:51 PM PDT 24
Peak memory 240796 kb
Host smart-eef15694-bdee-43fa-9e11-43792ad1128e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772644909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1772644909
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1487889201
Short name T355
Test name
Test status
Simulation time 519410036 ps
CPU time 9.04 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:52 PM PDT 24
Peak memory 240632 kb
Host smart-6b5b28d7-608c-4cae-a8ea-e2c48cb51d68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1487889201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1487889201
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1532408204
Short name T746
Test name
Test status
Simulation time 35409015 ps
CPU time 1.51 seconds
Started Aug 19 04:32:41 PM PDT 24
Finished Aug 19 04:32:42 PM PDT 24
Peak memory 235780 kb
Host smart-9cd4dd9b-96ee-421f-b050-3dea24e40abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1532408204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1532408204
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3312945785
Short name T808
Test name
Test status
Simulation time 383386410 ps
CPU time 13.12 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:32:52 PM PDT 24
Peak memory 248820 kb
Host smart-6ed11dc8-a35d-40fb-8758-cbd23f3ac530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3312945785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3312945785
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.4254769878
Short name T162
Test name
Test status
Simulation time 856265905 ps
CPU time 104.65 seconds
Started Aug 19 04:32:20 PM PDT 24
Finished Aug 19 04:34:05 PM PDT 24
Peak memory 257412 kb
Host smart-f1e8bd7f-e35f-4412-b189-c3233e1a8da0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4254769878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.4254769878
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3399915026
Short name T129
Test name
Test status
Simulation time 6015841859 ps
CPU time 409.87 seconds
Started Aug 19 04:32:21 PM PDT 24
Finished Aug 19 04:39:11 PM PDT 24
Peak memory 265732 kb
Host smart-fd651cef-6faa-44c0-a8cd-f80e484aa58d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399915026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3399915026
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4145659506
Short name T780
Test name
Test status
Simulation time 122141278 ps
CPU time 7.79 seconds
Started Aug 19 04:32:22 PM PDT 24
Finished Aug 19 04:32:30 PM PDT 24
Peak memory 248024 kb
Host smart-738b04e0-5052-4657-9051-fbff3869b312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145659506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.4145659506
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3563917412
Short name T811
Test name
Test status
Simulation time 237249103 ps
CPU time 12.43 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:48 PM PDT 24
Peak memory 242784 kb
Host smart-f5ea0695-50ca-4a1e-b11b-added815b3b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563917412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3563917412
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1695372928
Short name T751
Test name
Test status
Simulation time 212788361 ps
CPU time 4.38 seconds
Started Aug 19 04:33:30 PM PDT 24
Finished Aug 19 04:33:35 PM PDT 24
Peak memory 236824 kb
Host smart-77f36a40-40af-4c11-b324-b0013e4b38b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1695372928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1695372928
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3137553654
Short name T748
Test name
Test status
Simulation time 11178997 ps
CPU time 1.6 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 236880 kb
Host smart-e4594f97-92c3-43cc-8dc6-68918c38e47e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3137553654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3137553654
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2971037300
Short name T752
Test name
Test status
Simulation time 316736741 ps
CPU time 18.58 seconds
Started Aug 19 04:32:48 PM PDT 24
Finished Aug 19 04:33:06 PM PDT 24
Peak memory 244644 kb
Host smart-788ba9e1-c31f-4b53-ad7b-370d453f844b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2971037300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2971037300
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.310766118
Short name T156
Test name
Test status
Simulation time 4699682501 ps
CPU time 99.61 seconds
Started Aug 19 04:32:45 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 265688 kb
Host smart-10341451-a909-4818-ba12-8dde6887cba8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=310766118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.310766118
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1349064369
Short name T727
Test name
Test status
Simulation time 336087793 ps
CPU time 23.98 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:33:00 PM PDT 24
Peak memory 254760 kb
Host smart-e2b03fcf-fa43-4f10-9231-28b8fc4be687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1349064369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1349064369
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2762073602
Short name T352
Test name
Test status
Simulation time 188274564 ps
CPU time 5.59 seconds
Started Aug 19 04:32:46 PM PDT 24
Finished Aug 19 04:32:52 PM PDT 24
Peak memory 239780 kb
Host smart-4ed600c9-b8c3-4719-9a3e-618ef8933d22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762073602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2762073602
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2866002339
Short name T731
Test name
Test status
Simulation time 357271985 ps
CPU time 6.97 seconds
Started Aug 19 04:32:48 PM PDT 24
Finished Aug 19 04:32:55 PM PDT 24
Peak memory 237336 kb
Host smart-359f6f16-4c54-49d6-86aa-9e2e0fb82115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2866002339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2866002339
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3891694357
Short name T771
Test name
Test status
Simulation time 11183473 ps
CPU time 1.33 seconds
Started Aug 19 04:32:42 PM PDT 24
Finished Aug 19 04:32:43 PM PDT 24
Peak memory 236916 kb
Host smart-1657de45-7fb6-431a-a525-4dfe1e3e197a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3891694357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3891694357
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1676803315
Short name T802
Test name
Test status
Simulation time 1026115864 ps
CPU time 40.15 seconds
Started Aug 19 04:32:41 PM PDT 24
Finished Aug 19 04:33:22 PM PDT 24
Peak memory 245820 kb
Host smart-fed9212d-e9c1-426e-a298-711896f0cd94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1676803315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1676803315
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.769305482
Short name T785
Test name
Test status
Simulation time 239531233 ps
CPU time 6.02 seconds
Started Aug 19 04:32:25 PM PDT 24
Finished Aug 19 04:32:31 PM PDT 24
Peak memory 253596 kb
Host smart-208fb00a-7d3c-426e-bd12-24a11b08931b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=769305482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.769305482
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2566862516
Short name T805
Test name
Test status
Simulation time 169591165 ps
CPU time 5.17 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 257016 kb
Host smart-a99752a8-4953-4ce8-b546-697ddc147054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566862516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2566862516
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4027242940
Short name T821
Test name
Test status
Simulation time 152637833 ps
CPU time 4.71 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 236864 kb
Host smart-ec65075d-e458-4919-a2ec-15fe3abbdffe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4027242940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4027242940
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3920270794
Short name T763
Test name
Test status
Simulation time 10746591 ps
CPU time 1.34 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 236824 kb
Host smart-11ab9ba7-11af-4580-a0ab-f888c783438f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3920270794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3920270794
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.825750911
Short name T194
Test name
Test status
Simulation time 1345806417 ps
CPU time 22.15 seconds
Started Aug 19 04:32:48 PM PDT 24
Finished Aug 19 04:33:10 PM PDT 24
Peak memory 245624 kb
Host smart-601c2e8a-c2d2-4d50-9c51-8bcdb168b7cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=825750911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.825750911
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3952282257
Short name T833
Test name
Test status
Simulation time 1860821851 ps
CPU time 127.7 seconds
Started Aug 19 04:32:34 PM PDT 24
Finished Aug 19 04:34:42 PM PDT 24
Peak memory 266780 kb
Host smart-6573346d-d0b2-4ca1-83e6-a6c97e68626d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3952282257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3952282257
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4065945706
Short name T158
Test name
Test status
Simulation time 15772403036 ps
CPU time 269.63 seconds
Started Aug 19 04:32:28 PM PDT 24
Finished Aug 19 04:36:58 PM PDT 24
Peak memory 265764 kb
Host smart-77a1f3b0-694d-432f-827d-17487660a45d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065945706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.4065945706
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.603642186
Short name T790
Test name
Test status
Simulation time 174607016 ps
CPU time 12.34 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:32:51 PM PDT 24
Peak memory 248760 kb
Host smart-2f13e6bb-fe94-4eb0-bb86-7a18d2f4bf5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=603642186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.603642186
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1249150532
Short name T757
Test name
Test status
Simulation time 90737796 ps
CPU time 6.55 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:49 PM PDT 24
Peak memory 240144 kb
Host smart-e5b2f242-19f0-402a-94c0-3c7ab8ff60ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249150532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1249150532
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.128539317
Short name T820
Test name
Test status
Simulation time 56071594 ps
CPU time 4.47 seconds
Started Aug 19 04:32:27 PM PDT 24
Finished Aug 19 04:32:32 PM PDT 24
Peak memory 237628 kb
Host smart-12db6399-ec09-41c1-8131-724f3c2a13c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=128539317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.128539317
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1736236748
Short name T745
Test name
Test status
Simulation time 11464381 ps
CPU time 1.69 seconds
Started Aug 19 04:32:45 PM PDT 24
Finished Aug 19 04:32:47 PM PDT 24
Peak memory 237804 kb
Host smart-92bc8ea4-c23c-4237-86fd-eb3e126de97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1736236748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1736236748
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3026086511
Short name T747
Test name
Test status
Simulation time 329729691 ps
CPU time 21.86 seconds
Started Aug 19 04:32:32 PM PDT 24
Finished Aug 19 04:32:53 PM PDT 24
Peak memory 245964 kb
Host smart-48992dd5-d5ef-47bb-a4b0-584033e188c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3026086511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3026086511
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.600973859
Short name T127
Test name
Test status
Simulation time 15120499593 ps
CPU time 249.31 seconds
Started Aug 19 04:33:29 PM PDT 24
Finished Aug 19 04:37:39 PM PDT 24
Peak memory 272220 kb
Host smart-935a31e2-3ee6-48b2-b301-4115b0f29d8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=600973859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.600973859
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3164163098
Short name T159
Test name
Test status
Simulation time 4419058558 ps
CPU time 282.76 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:37:19 PM PDT 24
Peak memory 265640 kb
Host smart-fa490428-75a4-4bfd-a2b5-24c0970d59d4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164163098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3164163098
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.405034459
Short name T726
Test name
Test status
Simulation time 780931375 ps
CPU time 20.3 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:33:00 PM PDT 24
Peak memory 255804 kb
Host smart-3c6bfab3-9223-4a1d-b5ab-834730961fca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=405034459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.405034459
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1155330466
Short name T186
Test name
Test status
Simulation time 475819420 ps
CPU time 36.35 seconds
Started Aug 19 04:32:34 PM PDT 24
Finished Aug 19 04:33:11 PM PDT 24
Peak memory 237896 kb
Host smart-e8890d64-9033-4802-88cc-417fa600ae93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1155330466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1155330466
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1848041622
Short name T755
Test name
Test status
Simulation time 214006234 ps
CPU time 8.43 seconds
Started Aug 19 04:33:30 PM PDT 24
Finished Aug 19 04:33:39 PM PDT 24
Peak memory 252000 kb
Host smart-6702bcab-93b8-4d6f-9b49-c2085ef98eac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848041622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1848041622
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1727922629
Short name T784
Test name
Test status
Simulation time 355495784 ps
CPU time 7.87 seconds
Started Aug 19 04:32:32 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 240704 kb
Host smart-67ae149c-9e48-46c7-9f6d-a085bcd62b80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1727922629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1727922629
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1108156755
Short name T169
Test name
Test status
Simulation time 8779975 ps
CPU time 1.39 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:37 PM PDT 24
Peak memory 237780 kb
Host smart-495af1a6-7e6b-44d3-92ad-775c5f49e208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1108156755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1108156755
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1036387389
Short name T741
Test name
Test status
Simulation time 2070517835 ps
CPU time 37.97 seconds
Started Aug 19 04:32:30 PM PDT 24
Finished Aug 19 04:33:08 PM PDT 24
Peak memory 245956 kb
Host smart-fbc13bd2-4b0f-4497-b33c-d21caaa84640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1036387389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1036387389
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.919322906
Short name T826
Test name
Test status
Simulation time 28802573 ps
CPU time 3.65 seconds
Started Aug 19 04:32:31 PM PDT 24
Finished Aug 19 04:32:35 PM PDT 24
Peak memory 248936 kb
Host smart-636afafc-b641-4088-9c10-5fb2dbf1e17e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=919322906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.919322906
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4169109006
Short name T767
Test name
Test status
Simulation time 283225153 ps
CPU time 7.36 seconds
Started Aug 19 04:32:42 PM PDT 24
Finished Aug 19 04:32:50 PM PDT 24
Peak memory 241032 kb
Host smart-6b28b5cb-82d7-4838-b22d-974ff8c85e14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169109006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.4169109006
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2812312197
Short name T735
Test name
Test status
Simulation time 110301357 ps
CPU time 4.87 seconds
Started Aug 19 04:32:28 PM PDT 24
Finished Aug 19 04:32:33 PM PDT 24
Peak memory 236772 kb
Host smart-e362962c-8a5e-4c8e-99f1-23a33732dc02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2812312197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2812312197
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.815544862
Short name T761
Test name
Test status
Simulation time 10698489 ps
CPU time 1.41 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 235792 kb
Host smart-d5cf7a51-9faf-4fb5-8ace-04dabbd8eada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=815544862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.815544862
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2612191835
Short name T195
Test name
Test status
Simulation time 660569954 ps
CPU time 23.76 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:33:03 PM PDT 24
Peak memory 248880 kb
Host smart-b3a0125a-8e26-47d8-b70c-88b874f4141b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2612191835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2612191835
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2076195409
Short name T157
Test name
Test status
Simulation time 1762516765 ps
CPU time 101.8 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 265844 kb
Host smart-75f99a07-db55-4586-905b-2b3a66fd33fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2076195409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2076195409
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2302711636
Short name T717
Test name
Test status
Simulation time 152366645 ps
CPU time 10.37 seconds
Started Aug 19 04:32:42 PM PDT 24
Finished Aug 19 04:32:52 PM PDT 24
Peak memory 248676 kb
Host smart-6a856148-93be-490f-8645-2d55a8ed68a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2302711636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2302711636
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3620284871
Short name T827
Test name
Test status
Simulation time 191940923 ps
CPU time 7.22 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:32:51 PM PDT 24
Peak memory 239436 kb
Host smart-e811cb1c-00d6-4e61-a4fd-c54ee74ed9d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620284871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3620284871
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.788069839
Short name T804
Test name
Test status
Simulation time 116930622 ps
CPU time 8.13 seconds
Started Aug 19 04:32:26 PM PDT 24
Finished Aug 19 04:32:35 PM PDT 24
Peak memory 240708 kb
Host smart-a14f378e-c7ff-4280-bb00-1b6e260acc8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=788069839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.788069839
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4079436903
Short name T720
Test name
Test status
Simulation time 11071223 ps
CPU time 1.61 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 235780 kb
Host smart-9b97c9f8-a496-4b92-9f17-816d89d6780b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4079436903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.4079436903
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3393913824
Short name T749
Test name
Test status
Simulation time 179262462 ps
CPU time 19.08 seconds
Started Aug 19 04:32:34 PM PDT 24
Finished Aug 19 04:32:54 PM PDT 24
Peak memory 245076 kb
Host smart-7283f11e-61de-4d4e-9a4c-f818c2332eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3393913824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3393913824
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4276081668
Short name T131
Test name
Test status
Simulation time 2791723623 ps
CPU time 81.18 seconds
Started Aug 19 04:32:41 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 265684 kb
Host smart-1f23faf1-1c2f-49af-a46c-452064bab6d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4276081668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4276081668
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2580376464
Short name T137
Test name
Test status
Simulation time 57710344228 ps
CPU time 991.21 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:49:14 PM PDT 24
Peak memory 266680 kb
Host smart-4f672f40-f7aa-403f-b77b-94391bc09ec4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580376464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2580376464
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2387628388
Short name T799
Test name
Test status
Simulation time 96580625 ps
CPU time 6.51 seconds
Started Aug 19 04:32:32 PM PDT 24
Finished Aug 19 04:32:38 PM PDT 24
Peak memory 254228 kb
Host smart-f8291abd-5363-4bc7-8c03-324ccb49e469
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2387628388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2387628388
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3855466037
Short name T769
Test name
Test status
Simulation time 113960649 ps
CPU time 5.18 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:32:44 PM PDT 24
Peak memory 240748 kb
Host smart-a2cf2567-cb8d-4d3a-a639-17154fb21813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855466037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3855466037
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2820953048
Short name T818
Test name
Test status
Simulation time 126586907 ps
CPU time 9.5 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 240624 kb
Host smart-9af7214f-a600-485b-935f-cd7f5ac69b5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2820953048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2820953048
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2399865562
Short name T758
Test name
Test status
Simulation time 2205939294 ps
CPU time 44.88 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:33:28 PM PDT 24
Peak memory 248864 kb
Host smart-3052bfb8-981f-42d1-8c61-8abef42cacae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2399865562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2399865562
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1966630121
Short name T149
Test name
Test status
Simulation time 8418127470 ps
CPU time 286.91 seconds
Started Aug 19 04:32:37 PM PDT 24
Finished Aug 19 04:37:24 PM PDT 24
Peak memory 271744 kb
Host smart-a0610f18-e5bc-46de-987f-9eb193f24654
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966630121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1966630121
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2958486888
Short name T722
Test name
Test status
Simulation time 540691926 ps
CPU time 4.37 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:32:44 PM PDT 24
Peak memory 250016 kb
Host smart-ee0b920a-8db6-4d9f-899a-8de8105f12c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2958486888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2958486888
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3347188909
Short name T190
Test name
Test status
Simulation time 2093427090 ps
CPU time 158.3 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:34:53 PM PDT 24
Peak memory 241620 kb
Host smart-53a71f3e-0cf0-499e-b5a8-f6c541892a9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3347188909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3347188909
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3896913163
Short name T353
Test name
Test status
Simulation time 3269065474 ps
CPU time 106.22 seconds
Started Aug 19 04:32:11 PM PDT 24
Finished Aug 19 04:33:58 PM PDT 24
Peak memory 240796 kb
Host smart-9ba592f5-b33f-4bd6-ad09-c2a09ff506ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3896913163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3896913163
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2148538042
Short name T824
Test name
Test status
Simulation time 73494046 ps
CPU time 3.65 seconds
Started Aug 19 04:32:32 PM PDT 24
Finished Aug 19 04:32:36 PM PDT 24
Peak memory 240764 kb
Host smart-700a2bc7-3822-4bec-a1e9-f02d3c7e8473
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2148538042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2148538042
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1793933026
Short name T819
Test name
Test status
Simulation time 59378770 ps
CPU time 8.49 seconds
Started Aug 19 04:32:21 PM PDT 24
Finished Aug 19 04:32:29 PM PDT 24
Peak memory 248912 kb
Host smart-863de793-032f-4af0-bdff-41dc9940bac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793933026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1793933026
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3189905345
Short name T357
Test name
Test status
Simulation time 35928267 ps
CPU time 2.98 seconds
Started Aug 19 04:32:28 PM PDT 24
Finished Aug 19 04:32:31 PM PDT 24
Peak memory 236784 kb
Host smart-761a96ef-e50b-4f98-95bd-48e787cc2066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3189905345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3189905345
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4075641543
Short name T781
Test name
Test status
Simulation time 14646879 ps
CPU time 1.49 seconds
Started Aug 19 04:32:22 PM PDT 24
Finished Aug 19 04:32:24 PM PDT 24
Peak memory 237796 kb
Host smart-eb9dbf5e-097a-48f5-9795-caec0ce6b0ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4075641543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4075641543
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3417634777
Short name T736
Test name
Test status
Simulation time 3419774904 ps
CPU time 18.79 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:32:34 PM PDT 24
Peak memory 246020 kb
Host smart-9136d832-ad44-4498-836a-a4ca08f51c47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3417634777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3417634777
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.615602407
Short name T128
Test name
Test status
Simulation time 12704839345 ps
CPU time 455.51 seconds
Started Aug 19 04:32:27 PM PDT 24
Finished Aug 19 04:40:03 PM PDT 24
Peak memory 265572 kb
Host smart-c52119d1-7bed-45b8-bf55-9822ac5fc854
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615602407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.615602407
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2032475570
Short name T716
Test name
Test status
Simulation time 89454644 ps
CPU time 10.91 seconds
Started Aug 19 04:32:26 PM PDT 24
Finished Aug 19 04:32:37 PM PDT 24
Peak memory 240740 kb
Host smart-2cd39f62-a88d-40c9-a55d-1f46de8acd69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2032475570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2032475570
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3104937768
Short name T350
Test name
Test status
Simulation time 9993220 ps
CPU time 1.25 seconds
Started Aug 19 04:32:48 PM PDT 24
Finished Aug 19 04:32:49 PM PDT 24
Peak memory 236508 kb
Host smart-c56d6a20-3a02-4237-a4c8-db1b612b288e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104937768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3104937768
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.117973015
Short name T756
Test name
Test status
Simulation time 17577730 ps
CPU time 1.5 seconds
Started Aug 19 04:32:46 PM PDT 24
Finished Aug 19 04:32:48 PM PDT 24
Peak memory 237796 kb
Host smart-4fdc5282-0388-471d-abc4-5ae11dfb73f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=117973015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.117973015
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3502125901
Short name T730
Test name
Test status
Simulation time 6303978 ps
CPU time 1.4 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:32:42 PM PDT 24
Peak memory 236916 kb
Host smart-3c2f682c-5da6-41c6-ac7c-dbc5d377203d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3502125901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3502125901
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3947153343
Short name T794
Test name
Test status
Simulation time 22817525 ps
CPU time 1.51 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 237672 kb
Host smart-73adb5d3-e8eb-47ed-899d-517f7be1a2ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3947153343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3947153343
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3664029551
Short name T823
Test name
Test status
Simulation time 7675206 ps
CPU time 1.27 seconds
Started Aug 19 04:32:38 PM PDT 24
Finished Aug 19 04:32:39 PM PDT 24
Peak memory 237700 kb
Host smart-b9b16374-a84b-4477-b5e7-a4d9abf2f018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3664029551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3664029551
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3530231223
Short name T807
Test name
Test status
Simulation time 6244447 ps
CPU time 1.61 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 237760 kb
Host smart-433f5df4-391f-4048-98f3-6552aecfde0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3530231223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3530231223
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2678614356
Short name T719
Test name
Test status
Simulation time 11737517 ps
CPU time 1.6 seconds
Started Aug 19 04:32:34 PM PDT 24
Finished Aug 19 04:32:36 PM PDT 24
Peak memory 237788 kb
Host smart-40cbdb1e-2f48-49cb-82f8-34e746b09109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2678614356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2678614356
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2181991496
Short name T744
Test name
Test status
Simulation time 15021041 ps
CPU time 1.35 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 236756 kb
Host smart-c7959563-8277-48f8-b9cb-f5ca42136839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2181991496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2181991496
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2317147452
Short name T768
Test name
Test status
Simulation time 13521744 ps
CPU time 1.32 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 237748 kb
Host smart-ca65c1f4-02ec-4170-9f39-187eba45c66e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2317147452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2317147452
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1011728895
Short name T770
Test name
Test status
Simulation time 12263177 ps
CPU time 1.69 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 236748 kb
Host smart-44c1fd79-534d-4835-adbf-464e18acf64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1011728895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1011728895
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4105469279
Short name T828
Test name
Test status
Simulation time 17926207577 ps
CPU time 277.39 seconds
Started Aug 19 04:32:38 PM PDT 24
Finished Aug 19 04:37:16 PM PDT 24
Peak memory 240804 kb
Host smart-17498cd2-e408-4db8-8bd6-71ba62cbf75f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4105469279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.4105469279
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1837719949
Short name T775
Test name
Test status
Simulation time 2977825307 ps
CPU time 193.21 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:35:29 PM PDT 24
Peak memory 240644 kb
Host smart-c0e83bb7-8b3c-47b6-8f08-4f73e63593ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1837719949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1837719949
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1696182738
Short name T170
Test name
Test status
Simulation time 247085666 ps
CPU time 5.29 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 248796 kb
Host smart-42055aa9-168f-4b2e-951b-826b6c8fb955
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1696182738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1696182738
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2493442795
Short name T782
Test name
Test status
Simulation time 399503756 ps
CPU time 8.09 seconds
Started Aug 19 04:32:20 PM PDT 24
Finished Aug 19 04:32:28 PM PDT 24
Peak memory 240736 kb
Host smart-0aec3ccb-fab3-4cc1-b592-7c9ddd1e7e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493442795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2493442795
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.813636835
Short name T191
Test name
Test status
Simulation time 249771727 ps
CPU time 4.56 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:17 PM PDT 24
Peak memory 240512 kb
Host smart-9212fff3-8b87-4200-9c22-0af331c66e5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=813636835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.813636835
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2109485633
Short name T801
Test name
Test status
Simulation time 14437768 ps
CPU time 1.29 seconds
Started Aug 19 04:32:35 PM PDT 24
Finished Aug 19 04:32:37 PM PDT 24
Peak memory 237684 kb
Host smart-7f6f7263-8968-4e37-b153-1139c160b151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2109485633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2109485633
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1810428037
Short name T192
Test name
Test status
Simulation time 3288716230 ps
CPU time 24.22 seconds
Started Aug 19 04:32:38 PM PDT 24
Finished Aug 19 04:33:02 PM PDT 24
Peak memory 245880 kb
Host smart-1e7f862f-89b1-48cd-9f9d-a47cfd62e225
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1810428037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1810428037
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1735143620
Short name T815
Test name
Test status
Simulation time 107586133 ps
CPU time 6.44 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:20 PM PDT 24
Peak memory 248868 kb
Host smart-f9592892-978d-4a63-ab63-cd8f0455a33d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1735143620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1735143620
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.504412494
Short name T270
Test name
Test status
Simulation time 3646303534 ps
CPU time 59.94 seconds
Started Aug 19 04:32:22 PM PDT 24
Finished Aug 19 04:33:23 PM PDT 24
Peak memory 247176 kb
Host smart-4d45dcce-9451-4449-ac3c-86e812c80ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=504412494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.504412494
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3837885116
Short name T754
Test name
Test status
Simulation time 7861123 ps
CPU time 1.42 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:44 PM PDT 24
Peak memory 237740 kb
Host smart-fb29458a-22ef-457f-b8ae-c253f2bd1d4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3837885116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3837885116
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2411216014
Short name T739
Test name
Test status
Simulation time 33240414 ps
CPU time 1.44 seconds
Started Aug 19 04:32:38 PM PDT 24
Finished Aug 19 04:32:39 PM PDT 24
Peak memory 237804 kb
Host smart-9e2f8f2c-edff-4e6f-b722-04198073d3b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2411216014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2411216014
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4058525346
Short name T750
Test name
Test status
Simulation time 9021046 ps
CPU time 1.45 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 235876 kb
Host smart-c8280bdc-644c-432d-814d-d5d3ebde1158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4058525346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4058525346
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3859210082
Short name T728
Test name
Test status
Simulation time 12911163 ps
CPU time 1.59 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 236696 kb
Host smart-7369fe15-8071-4f3d-9684-82562340a55f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3859210082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3859210082
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.250692240
Short name T786
Test name
Test status
Simulation time 13899452 ps
CPU time 1.53 seconds
Started Aug 19 04:32:35 PM PDT 24
Finished Aug 19 04:32:36 PM PDT 24
Peak memory 236780 kb
Host smart-603ca917-285d-4503-b13b-e2bae63fa4ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=250692240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.250692240
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3412838251
Short name T734
Test name
Test status
Simulation time 15834060 ps
CPU time 1.85 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 236900 kb
Host smart-2d00e5b5-7ff1-45db-8525-87022725cec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412838251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3412838251
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.328194283
Short name T732
Test name
Test status
Simulation time 6366847 ps
CPU time 1.36 seconds
Started Aug 19 04:32:50 PM PDT 24
Finished Aug 19 04:32:51 PM PDT 24
Peak memory 237764 kb
Host smart-4d9a5318-10a7-48b1-b5a6-26f4a97bc4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=328194283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.328194283
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1789028494
Short name T347
Test name
Test status
Simulation time 24034074 ps
CPU time 1.47 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 236748 kb
Host smart-2cd49a46-6201-4cf7-9c47-5b8dcdbb7b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1789028494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1789028494
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3014208927
Short name T738
Test name
Test status
Simulation time 15227861 ps
CPU time 1.28 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 236724 kb
Host smart-0bc0b298-ce8c-44be-90ce-1128ee96cb99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3014208927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3014208927
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4261156681
Short name T765
Test name
Test status
Simulation time 3360838690 ps
CPU time 232.81 seconds
Started Aug 19 04:32:37 PM PDT 24
Finished Aug 19 04:36:30 PM PDT 24
Peak memory 241816 kb
Host smart-9fd077a6-6c1e-4d7f-b26a-aa795d68b34c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4261156681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4261156681
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1853357505
Short name T795
Test name
Test status
Simulation time 1696562293 ps
CPU time 196.06 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:35:55 PM PDT 24
Peak memory 237684 kb
Host smart-91479423-a370-4c8f-96d1-da2f50bf2b30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1853357505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1853357505
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3167508351
Short name T725
Test name
Test status
Simulation time 196179792 ps
CPU time 8.51 seconds
Started Aug 19 04:32:35 PM PDT 24
Finished Aug 19 04:32:44 PM PDT 24
Peak memory 249340 kb
Host smart-91f84691-565b-4240-9780-97e5c02f008d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3167508351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3167508351
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3942368880
Short name T351
Test name
Test status
Simulation time 291240221 ps
CPU time 6.38 seconds
Started Aug 19 04:32:38 PM PDT 24
Finished Aug 19 04:32:44 PM PDT 24
Peak memory 240760 kb
Host smart-0e22055d-c058-4970-859f-d5248a3d2d9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942368880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3942368880
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1004563956
Short name T812
Test name
Test status
Simulation time 66443508 ps
CPU time 4.95 seconds
Started Aug 19 04:32:34 PM PDT 24
Finished Aug 19 04:32:39 PM PDT 24
Peak memory 240708 kb
Host smart-424ccc39-00a3-478b-991e-a5689b2c9682
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1004563956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1004563956
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4184431808
Short name T831
Test name
Test status
Simulation time 45271647 ps
CPU time 1.27 seconds
Started Aug 19 04:32:22 PM PDT 24
Finished Aug 19 04:32:23 PM PDT 24
Peak memory 236824 kb
Host smart-f21125c1-1f33-4527-a117-1bbf2a803515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4184431808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4184431808
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3720937745
Short name T813
Test name
Test status
Simulation time 191270383 ps
CPU time 25.17 seconds
Started Aug 19 04:32:18 PM PDT 24
Finished Aug 19 04:32:43 PM PDT 24
Peak memory 245868 kb
Host smart-9d008256-67e6-45d4-97cf-46b4ab6c3521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3720937745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3720937745
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1377866198
Short name T141
Test name
Test status
Simulation time 1727235705 ps
CPU time 199.61 seconds
Started Aug 19 04:32:34 PM PDT 24
Finished Aug 19 04:35:53 PM PDT 24
Peak memory 265684 kb
Host smart-4405d430-d477-409f-b8b9-b4208c17737b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1377866198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1377866198
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2969415204
Short name T798
Test name
Test status
Simulation time 937631076 ps
CPU time 17.82 seconds
Started Aug 19 04:32:37 PM PDT 24
Finished Aug 19 04:32:55 PM PDT 24
Peak memory 248892 kb
Host smart-ba492f96-bd45-46a2-849f-1ae1438d5de9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2969415204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2969415204
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.226907303
Short name T788
Test name
Test status
Simulation time 9388938 ps
CPU time 1.35 seconds
Started Aug 19 04:32:46 PM PDT 24
Finished Aug 19 04:32:47 PM PDT 24
Peak memory 237812 kb
Host smart-7d71d046-b90b-42ed-b16e-2e807a037fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=226907303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.226907303
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3807719145
Short name T779
Test name
Test status
Simulation time 53130214 ps
CPU time 1.3 seconds
Started Aug 19 04:32:44 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 235696 kb
Host smart-e2b1fcec-a01b-40df-9dbc-3b74f580484e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3807719145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3807719145
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3742041111
Short name T724
Test name
Test status
Simulation time 8419547 ps
CPU time 1.4 seconds
Started Aug 19 04:32:47 PM PDT 24
Finished Aug 19 04:32:48 PM PDT 24
Peak memory 235360 kb
Host smart-669cc19e-9bb8-4d52-abdb-74064483ffd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3742041111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3742041111
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3368648238
Short name T809
Test name
Test status
Simulation time 8585611 ps
CPU time 1.48 seconds
Started Aug 19 04:32:47 PM PDT 24
Finished Aug 19 04:32:48 PM PDT 24
Peak memory 236440 kb
Host smart-b41b633a-3df1-46bd-9b23-fda99a677658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3368648238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3368648238
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.564636278
Short name T814
Test name
Test status
Simulation time 28417525 ps
CPU time 1.34 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 236724 kb
Host smart-2ef0c1aa-d357-4ced-82d9-376c8afd3739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=564636278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.564636278
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3802777624
Short name T797
Test name
Test status
Simulation time 28223494 ps
CPU time 1.51 seconds
Started Aug 19 04:32:33 PM PDT 24
Finished Aug 19 04:32:35 PM PDT 24
Peak memory 237640 kb
Host smart-2d547773-dfb0-4c50-9dbf-5939659b2c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3802777624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3802777624
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.580349501
Short name T762
Test name
Test status
Simulation time 21841435 ps
CPU time 1.37 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 235800 kb
Host smart-0f5d16fc-cdcd-4fc9-821b-a53eb1f0b7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=580349501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.580349501
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3963828400
Short name T718
Test name
Test status
Simulation time 16505827 ps
CPU time 1.3 seconds
Started Aug 19 04:32:45 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 235632 kb
Host smart-62c2c7df-53ca-485d-ba26-1feb10f7d071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3963828400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3963828400
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2863346671
Short name T232
Test name
Test status
Simulation time 25734652 ps
CPU time 1.5 seconds
Started Aug 19 04:32:37 PM PDT 24
Finished Aug 19 04:32:39 PM PDT 24
Peak memory 236820 kb
Host smart-9871f392-2d06-43d6-adc3-5c151f993dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2863346671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2863346671
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1659484357
Short name T348
Test name
Test status
Simulation time 15244513 ps
CPU time 1.78 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 237788 kb
Host smart-532b0fcc-1715-446b-a2f9-f881060f8c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1659484357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1659484357
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2359499055
Short name T184
Test name
Test status
Simulation time 534132456 ps
CPU time 10.99 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:25 PM PDT 24
Peak memory 252904 kb
Host smart-42fda3da-ba0d-4496-9883-a7fc2f75c4e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359499055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2359499055
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.493697330
Short name T825
Test name
Test status
Simulation time 286518405 ps
CPU time 4.7 seconds
Started Aug 19 04:32:37 PM PDT 24
Finished Aug 19 04:32:42 PM PDT 24
Peak memory 237780 kb
Host smart-5ad9c0d4-bfb3-4b27-9900-b78684fdbfbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=493697330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.493697330
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2144825445
Short name T793
Test name
Test status
Simulation time 8666981 ps
CPU time 1.41 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 236760 kb
Host smart-62a25ee0-008f-4afe-ac70-f70aa5f23c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2144825445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2144825445
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3412045319
Short name T189
Test name
Test status
Simulation time 1455622704 ps
CPU time 20.85 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:32:36 PM PDT 24
Peak memory 245876 kb
Host smart-8b8d67bd-1b44-4f46-a427-ab06b35b0e26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3412045319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3412045319
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1622617288
Short name T773
Test name
Test status
Simulation time 170041679 ps
CPU time 10.98 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:25 PM PDT 24
Peak memory 254836 kb
Host smart-22802605-e8d8-4bdb-ad3d-3debb9da40cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1622617288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1622617288
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3419023472
Short name T783
Test name
Test status
Simulation time 108904189 ps
CPU time 4.53 seconds
Started Aug 19 04:32:33 PM PDT 24
Finished Aug 19 04:32:38 PM PDT 24
Peak memory 239780 kb
Host smart-48656596-0efc-486a-aaf1-54ea824fc55e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419023472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3419023472
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.392607275
Short name T776
Test name
Test status
Simulation time 36445837 ps
CPU time 5.45 seconds
Started Aug 19 04:32:20 PM PDT 24
Finished Aug 19 04:32:25 PM PDT 24
Peak memory 236864 kb
Host smart-5d032196-a24e-4ef1-9369-3ad8804ff8eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=392607275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.392607275
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2934703952
Short name T803
Test name
Test status
Simulation time 7554009 ps
CPU time 1.41 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:32:42 PM PDT 24
Peak memory 236772 kb
Host smart-46760aff-3229-4381-b52b-745b4bd47907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2934703952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2934703952
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1881869741
Short name T796
Test name
Test status
Simulation time 483585335 ps
CPU time 37.61 seconds
Started Aug 19 04:32:42 PM PDT 24
Finished Aug 19 04:33:20 PM PDT 24
Peak memory 245984 kb
Host smart-7ee970a7-b649-4f55-86b6-a7cc749a7f63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1881869741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1881869741
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.315241202
Short name T163
Test name
Test status
Simulation time 20448119557 ps
CPU time 169.28 seconds
Started Aug 19 04:32:16 PM PDT 24
Finished Aug 19 04:35:06 PM PDT 24
Peak memory 257356 kb
Host smart-e38d4d8a-54c1-4965-9f5b-23dc00d0a84c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=315241202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.315241202
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1763554354
Short name T152
Test name
Test status
Simulation time 35969416168 ps
CPU time 299.77 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:37:43 PM PDT 24
Peak memory 268488 kb
Host smart-168e40d1-b43f-4df7-81e8-d262e5e2cbfb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763554354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1763554354
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3487324548
Short name T817
Test name
Test status
Simulation time 1807583967 ps
CPU time 26.35 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:33:03 PM PDT 24
Peak memory 249032 kb
Host smart-41327df5-baba-4ab9-a384-47df5da3b0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3487324548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3487324548
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1393613703
Short name T830
Test name
Test status
Simulation time 62972177 ps
CPU time 9.37 seconds
Started Aug 19 04:32:35 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 248952 kb
Host smart-237cc2f9-5420-4d90-8116-3397b2a70fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393613703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1393613703
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2797491927
Short name T354
Test name
Test status
Simulation time 368353847 ps
CPU time 4.74 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 240688 kb
Host smart-c59942fe-53d7-4f03-99cd-819736c629a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2797491927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2797491927
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2637403165
Short name T792
Test name
Test status
Simulation time 6715808 ps
CPU time 1.41 seconds
Started Aug 19 04:32:39 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 237796 kb
Host smart-96a8d097-e690-4d00-aba5-27098ddf7d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2637403165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2637403165
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3383765483
Short name T787
Test name
Test status
Simulation time 500741100 ps
CPU time 38.02 seconds
Started Aug 19 04:32:26 PM PDT 24
Finished Aug 19 04:33:04 PM PDT 24
Peak memory 245960 kb
Host smart-75648af1-4aaf-402c-8cc9-46bb6e68e8c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3383765483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3383765483
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3840549936
Short name T154
Test name
Test status
Simulation time 2596592402 ps
CPU time 161.43 seconds
Started Aug 19 04:32:24 PM PDT 24
Finished Aug 19 04:35:05 PM PDT 24
Peak memory 265576 kb
Host smart-081bbc51-3dad-4d0c-b800-85f7e39295b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3840549936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3840549936
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2054851164
Short name T358
Test name
Test status
Simulation time 85657348800 ps
CPU time 499.61 seconds
Started Aug 19 04:32:19 PM PDT 24
Finished Aug 19 04:40:39 PM PDT 24
Peak memory 265532 kb
Host smart-9bd39ee6-5ab4-4ab4-8015-c5baff2acb69
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054851164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2054851164
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1116222033
Short name T721
Test name
Test status
Simulation time 57153476 ps
CPU time 6.38 seconds
Started Aug 19 04:32:34 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 248640 kb
Host smart-d391714e-0383-485e-9959-24fc1a5d3d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1116222033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1116222033
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3889400588
Short name T359
Test name
Test status
Simulation time 2616388785 ps
CPU time 9.99 seconds
Started Aug 19 04:32:42 PM PDT 24
Finished Aug 19 04:32:52 PM PDT 24
Peak memory 240836 kb
Host smart-1e451db8-cb04-4568-b68f-e7f14cf9ed3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889400588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3889400588
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.245779509
Short name T832
Test name
Test status
Simulation time 20235002 ps
CPU time 3.33 seconds
Started Aug 19 04:32:33 PM PDT 24
Finished Aug 19 04:32:36 PM PDT 24
Peak memory 236792 kb
Host smart-cfa5ad2b-6a20-4f5c-9863-fe9d5d82708f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=245779509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.245779509
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1637789254
Short name T723
Test name
Test status
Simulation time 8553759 ps
CPU time 1.44 seconds
Started Aug 19 04:32:38 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 237700 kb
Host smart-c994b001-646b-43d3-81d2-c1229c5a7454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1637789254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1637789254
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1984203279
Short name T193
Test name
Test status
Simulation time 726035124 ps
CPU time 23.19 seconds
Started Aug 19 04:32:18 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 248796 kb
Host smart-997f2a05-a66d-4f21-845b-ca64109c61f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1984203279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1984203279
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2014288677
Short name T144
Test name
Test status
Simulation time 2000959559 ps
CPU time 144.77 seconds
Started Aug 19 04:32:18 PM PDT 24
Finished Aug 19 04:34:43 PM PDT 24
Peak memory 265476 kb
Host smart-9bd988c9-756f-4dba-ab13-e0c7f4fbb4f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2014288677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2014288677
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2475296220
Short name T147
Test name
Test status
Simulation time 35392648810 ps
CPU time 529.13 seconds
Started Aug 19 04:32:16 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 265620 kb
Host smart-7f386793-90a7-497c-b18e-b7fa501e627b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475296220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2475296220
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.245033573
Short name T777
Test name
Test status
Simulation time 906595724 ps
CPU time 24.57 seconds
Started Aug 19 04:32:40 PM PDT 24
Finished Aug 19 04:33:05 PM PDT 24
Peak memory 256512 kb
Host smart-4c5eae37-4940-4509-84a1-02877bd90c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=245033573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.245033573
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1650901587
Short name T789
Test name
Test status
Simulation time 155387493 ps
CPU time 7.48 seconds
Started Aug 19 04:32:38 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 257116 kb
Host smart-6ea63a17-a9fe-4e15-b4b5-2ec646b0dcf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650901587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1650901587
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.714312917
Short name T360
Test name
Test status
Simulation time 143459299 ps
CPU time 5.03 seconds
Started Aug 19 04:32:45 PM PDT 24
Finished Aug 19 04:32:50 PM PDT 24
Peak memory 237776 kb
Host smart-6e063d9b-bd1b-4098-8071-8d3ba35cf4a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=714312917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.714312917
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1830419976
Short name T740
Test name
Test status
Simulation time 17759579 ps
CPU time 1.85 seconds
Started Aug 19 04:32:37 PM PDT 24
Finished Aug 19 04:32:39 PM PDT 24
Peak memory 237800 kb
Host smart-0bc27a5c-9ea4-4abf-b1b1-ec60290a2167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1830419976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1830419976
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1065075546
Short name T829
Test name
Test status
Simulation time 521183841 ps
CPU time 34.37 seconds
Started Aug 19 04:32:32 PM PDT 24
Finished Aug 19 04:33:07 PM PDT 24
Peak memory 245096 kb
Host smart-276ea93d-b2cc-453e-950c-00eeca3b70ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1065075546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1065075546
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3772099315
Short name T153
Test name
Test status
Simulation time 14474396962 ps
CPU time 993.8 seconds
Started Aug 19 04:32:37 PM PDT 24
Finished Aug 19 04:49:11 PM PDT 24
Peak memory 265668 kb
Host smart-58541c1d-8ca2-4d46-93fd-b91c7ceced4a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772099315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3772099315
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1646299325
Short name T764
Test name
Test status
Simulation time 176888152 ps
CPU time 5.77 seconds
Started Aug 19 04:32:34 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 253056 kb
Host smart-765a68d3-d3a1-41b8-9cf4-de5d19646642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1646299325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1646299325
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3979818664
Short name T271
Test name
Test status
Simulation time 922201970 ps
CPU time 31.85 seconds
Started Aug 19 04:32:36 PM PDT 24
Finished Aug 19 04:33:08 PM PDT 24
Peak memory 240700 kb
Host smart-3fa87a4e-5ab1-4495-8b45-c89b386a1fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3979818664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3979818664
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2712788491
Short name T580
Test name
Test status
Simulation time 14486663596 ps
CPU time 847.39 seconds
Started Aug 19 04:54:08 PM PDT 24
Finished Aug 19 05:08:16 PM PDT 24
Peak memory 273124 kb
Host smart-7d0b7247-83aa-4444-bc3e-793612e79bd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712788491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2712788491
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1122190204
Short name T381
Test name
Test status
Simulation time 20763968648 ps
CPU time 66.69 seconds
Started Aug 19 04:54:16 PM PDT 24
Finished Aug 19 04:55:23 PM PDT 24
Peak memory 248524 kb
Host smart-d7108944-924f-455b-b9fe-c4d649635b8a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1122190204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1122190204
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3571025427
Short name T710
Test name
Test status
Simulation time 5635733923 ps
CPU time 129.73 seconds
Started Aug 19 04:54:16 PM PDT 24
Finished Aug 19 04:56:26 PM PDT 24
Peak memory 256600 kb
Host smart-b9b8e33a-a331-4965-97af-206fc4841e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35710
25427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3571025427
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3732395596
Short name T694
Test name
Test status
Simulation time 562536930 ps
CPU time 38.15 seconds
Started Aug 19 04:54:13 PM PDT 24
Finished Aug 19 04:54:51 PM PDT 24
Peak memory 248824 kb
Host smart-f4bab758-225d-4b4d-9145-7652aaf5a7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323
95596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3732395596
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1791581822
Short name T340
Test name
Test status
Simulation time 42772689955 ps
CPU time 977.32 seconds
Started Aug 19 04:54:14 PM PDT 24
Finished Aug 19 05:10:32 PM PDT 24
Peak memory 272832 kb
Host smart-3fee80ef-8668-4c6c-a6d0-2c00ee971978
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791581822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1791581822
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.123147136
Short name T216
Test name
Test status
Simulation time 33922802053 ps
CPU time 2188.58 seconds
Started Aug 19 04:54:16 PM PDT 24
Finished Aug 19 05:30:45 PM PDT 24
Peak memory 289608 kb
Host smart-11709fb5-b9f6-46c6-85f3-a857f520ab43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123147136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.123147136
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.673037306
Short name T292
Test name
Test status
Simulation time 9886694436 ps
CPU time 413.69 seconds
Started Aug 19 04:54:12 PM PDT 24
Finished Aug 19 05:01:06 PM PDT 24
Peak memory 247608 kb
Host smart-cd6fd854-04f8-421e-badd-a3bca62372dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673037306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.673037306
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.92601311
Short name T54
Test name
Test status
Simulation time 478168603 ps
CPU time 7.76 seconds
Started Aug 19 04:54:14 PM PDT 24
Finished Aug 19 04:54:22 PM PDT 24
Peak memory 251376 kb
Host smart-e0abb61a-51e7-4159-8777-f0fbd42d38cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92601
311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.92601311
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.717401062
Short name T596
Test name
Test status
Simulation time 723906358 ps
CPU time 44.72 seconds
Started Aug 19 04:54:12 PM PDT 24
Finished Aug 19 04:54:57 PM PDT 24
Peak memory 248376 kb
Host smart-1f6d8aa0-8404-40cd-a1d3-b34fcfb06d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71740
1062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.717401062
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1957675595
Short name T42
Test name
Test status
Simulation time 682805876 ps
CPU time 20.58 seconds
Started Aug 19 04:54:11 PM PDT 24
Finished Aug 19 04:54:31 PM PDT 24
Peak memory 269960 kb
Host smart-87a2c48a-5221-4154-aafa-904f501341ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1957675595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1957675595
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.116864435
Short name T473
Test name
Test status
Simulation time 911233257 ps
CPU time 8.87 seconds
Started Aug 19 04:54:08 PM PDT 24
Finished Aug 19 04:54:16 PM PDT 24
Peak memory 248160 kb
Host smart-4696aace-6aa2-4f1b-9c53-75445f0f3a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11686
4435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.116864435
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3136770873
Short name T574
Test name
Test status
Simulation time 641581969 ps
CPU time 38.03 seconds
Started Aug 19 04:54:16 PM PDT 24
Finished Aug 19 04:54:54 PM PDT 24
Peak memory 256924 kb
Host smart-951e15bb-0738-41c7-ba93-ed68a97f84ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31367
70873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3136770873
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.902535743
Short name T497
Test name
Test status
Simulation time 17870543718 ps
CPU time 1332.35 seconds
Started Aug 19 04:54:12 PM PDT 24
Finished Aug 19 05:16:25 PM PDT 24
Peak memory 287484 kb
Host smart-d5897e31-10da-494e-890e-d17d4aace176
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902535743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.902535743
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.771396153
Short name T233
Test name
Test status
Simulation time 192180716 ps
CPU time 11.44 seconds
Started Aug 19 04:54:10 PM PDT 24
Finished Aug 19 04:54:22 PM PDT 24
Peak memory 248764 kb
Host smart-ba1202ba-f740-4cee-833a-52e65bbf5752
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=771396153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.771396153
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1343079005
Short name T377
Test name
Test status
Simulation time 6110809769 ps
CPU time 91.83 seconds
Started Aug 19 04:54:16 PM PDT 24
Finished Aug 19 04:55:48 PM PDT 24
Peak memory 257100 kb
Host smart-e730f0ee-0a40-45a1-bdd8-53cba232cc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13430
79005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1343079005
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.125411966
Short name T252
Test name
Test status
Simulation time 1642669026 ps
CPU time 28.15 seconds
Started Aug 19 04:54:12 PM PDT 24
Finished Aug 19 04:54:40 PM PDT 24
Peak memory 248324 kb
Host smart-459d4034-6a1e-4b08-bd27-508416650cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12541
1966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.125411966
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1614842162
Short name T450
Test name
Test status
Simulation time 7357106054 ps
CPU time 790.38 seconds
Started Aug 19 04:54:10 PM PDT 24
Finished Aug 19 05:07:20 PM PDT 24
Peak memory 272852 kb
Host smart-0a7b3f27-40d2-4b67-95de-1641e5961356
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614842162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1614842162
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2742008857
Short name T519
Test name
Test status
Simulation time 12548531476 ps
CPU time 273.89 seconds
Started Aug 19 04:54:10 PM PDT 24
Finished Aug 19 04:58:44 PM PDT 24
Peak memory 247720 kb
Host smart-7d2c0da7-eff3-47b2-ae76-fa447d4351be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742008857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2742008857
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.903192362
Short name T68
Test name
Test status
Simulation time 310020974 ps
CPU time 16.87 seconds
Started Aug 19 04:54:12 PM PDT 24
Finished Aug 19 04:54:29 PM PDT 24
Peak memory 248744 kb
Host smart-6570e8bc-af0d-4fc7-a58e-f1241eb34da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90319
2362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.903192362
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1244720414
Short name T389
Test name
Test status
Simulation time 17887364940 ps
CPU time 70.13 seconds
Started Aug 19 04:54:12 PM PDT 24
Finished Aug 19 04:55:22 PM PDT 24
Peak memory 256384 kb
Host smart-7e1fafc4-6c3e-4ec6-8cc7-3f572980d9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12447
20414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1244720414
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.52251832
Short name T593
Test name
Test status
Simulation time 102501683 ps
CPU time 12.48 seconds
Started Aug 19 04:54:11 PM PDT 24
Finished Aug 19 04:54:24 PM PDT 24
Peak memory 248316 kb
Host smart-f67fa23e-63d6-4428-8e8f-38ec40ff12e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52251
832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.52251832
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2977734517
Short name T468
Test name
Test status
Simulation time 694647640 ps
CPU time 38.52 seconds
Started Aug 19 04:54:14 PM PDT 24
Finished Aug 19 04:54:53 PM PDT 24
Peak memory 256892 kb
Host smart-68cc03be-318f-4972-a2e1-11f041a72566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29777
34517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2977734517
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4245012372
Short name T483
Test name
Test status
Simulation time 3939489762 ps
CPU time 233.99 seconds
Started Aug 19 04:54:13 PM PDT 24
Finished Aug 19 04:58:08 PM PDT 24
Peak memory 257052 kb
Host smart-9e5daf1f-304b-49d5-8cc5-cf9d85b489ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245012372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4245012372
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.592780382
Short name T614
Test name
Test status
Simulation time 2292652951 ps
CPU time 263.79 seconds
Started Aug 19 04:54:11 PM PDT 24
Finished Aug 19 04:58:35 PM PDT 24
Peak memory 267008 kb
Host smart-df3f251a-6f6e-4162-98ce-a46ed4454265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592780382 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.592780382
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2203152380
Short name T672
Test name
Test status
Simulation time 36609924067 ps
CPU time 954.87 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 05:10:27 PM PDT 24
Peak memory 271344 kb
Host smart-15d3e14a-e764-4ddf-b2af-af1023aba2cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203152380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2203152380
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2603292379
Short name T303
Test name
Test status
Simulation time 3443743979 ps
CPU time 209.52 seconds
Started Aug 19 04:54:34 PM PDT 24
Finished Aug 19 04:58:04 PM PDT 24
Peak memory 256328 kb
Host smart-64476138-b1ba-4031-b1bd-ee85f58a2364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26032
92379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2603292379
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2228136422
Short name T649
Test name
Test status
Simulation time 1386323943 ps
CPU time 40.04 seconds
Started Aug 19 04:54:29 PM PDT 24
Finished Aug 19 04:55:09 PM PDT 24
Peak memory 248752 kb
Host smart-1a5deb61-8511-4d64-8fd7-67a85ac40f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22281
36422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2228136422
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.782989023
Short name T272
Test name
Test status
Simulation time 17671417544 ps
CPU time 862.41 seconds
Started Aug 19 04:54:28 PM PDT 24
Finished Aug 19 05:08:50 PM PDT 24
Peak memory 273404 kb
Host smart-67db6205-91e4-4aeb-90cf-35536be5b974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782989023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.782989023
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.526706178
Short name T113
Test name
Test status
Simulation time 12995570076 ps
CPU time 1196.69 seconds
Started Aug 19 04:54:29 PM PDT 24
Finished Aug 19 05:14:26 PM PDT 24
Peak memory 288888 kb
Host smart-7e883a42-09aa-4bc9-b1eb-ac964023a317
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526706178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.526706178
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1968790633
Short name T594
Test name
Test status
Simulation time 7309529464 ps
CPU time 319.03 seconds
Started Aug 19 04:54:29 PM PDT 24
Finished Aug 19 04:59:48 PM PDT 24
Peak memory 255520 kb
Host smart-7ec70558-97c1-4cb8-9273-d64ed7b40040
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968790633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1968790633
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2098830344
Short name T454
Test name
Test status
Simulation time 262011307 ps
CPU time 3.95 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 04:54:37 PM PDT 24
Peak memory 248828 kb
Host smart-91b9a842-d17a-41fe-b005-b82c1bc3e0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20988
30344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2098830344
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1117560112
Short name T121
Test name
Test status
Simulation time 402864321 ps
CPU time 33.02 seconds
Started Aug 19 04:54:29 PM PDT 24
Finished Aug 19 04:55:02 PM PDT 24
Peak memory 248372 kb
Host smart-5d64e36d-06ef-4510-a357-58a5fe92889e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11175
60112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1117560112
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.822685092
Short name T659
Test name
Test status
Simulation time 197945028 ps
CPU time 14.47 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:54:45 PM PDT 24
Peak memory 248368 kb
Host smart-acbf39c2-fb63-4d59-ac9e-48779ff5a75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82268
5092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.822685092
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1403705224
Short name T475
Test name
Test status
Simulation time 1918664703 ps
CPU time 29.61 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 04:55:02 PM PDT 24
Peak memory 256952 kb
Host smart-b4d6bf5b-c294-4114-a5e2-8c8f3664f3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14037
05224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1403705224
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1970488551
Short name T34
Test name
Test status
Simulation time 178720929867 ps
CPU time 1991.36 seconds
Started Aug 19 04:54:41 PM PDT 24
Finished Aug 19 05:27:52 PM PDT 24
Peak memory 281656 kb
Host smart-eb2ad15d-9dba-44d2-8b2e-3a3ec7c03278
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970488551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1970488551
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3553103140
Short name T239
Test name
Test status
Simulation time 7460314379 ps
CPU time 138 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 04:56:51 PM PDT 24
Peak memory 265336 kb
Host smart-a7d3e835-51fe-47ec-916b-5ac992a11ba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553103140 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3553103140
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1627835512
Short name T203
Test name
Test status
Simulation time 153775398 ps
CPU time 3.86 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:54:35 PM PDT 24
Peak memory 248992 kb
Host smart-212deba1-8d5e-4851-bcad-32d44517d2aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1627835512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1627835512
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3724327430
Short name T391
Test name
Test status
Simulation time 30134899112 ps
CPU time 2155.48 seconds
Started Aug 19 04:54:29 PM PDT 24
Finished Aug 19 05:30:25 PM PDT 24
Peak memory 289556 kb
Host smart-ad44b1f9-e316-4352-962a-e217ae7abb0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724327430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3724327430
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2957871071
Short name T634
Test name
Test status
Simulation time 451209406 ps
CPU time 8.14 seconds
Started Aug 19 04:54:34 PM PDT 24
Finished Aug 19 04:54:43 PM PDT 24
Peak memory 248780 kb
Host smart-954781a7-b2b2-4dce-8b3c-71022ff1f028
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2957871071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2957871071
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3291045211
Short name T368
Test name
Test status
Simulation time 1135667637 ps
CPU time 98.69 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:56:09 PM PDT 24
Peak memory 256892 kb
Host smart-ff921774-66a4-4d28-9087-a08446e7d2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32910
45211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3291045211
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1285584501
Short name T81
Test name
Test status
Simulation time 2694433288 ps
CPU time 39.03 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:55:10 PM PDT 24
Peak memory 256372 kb
Host smart-7e58602b-8a13-4082-8241-15692bebf113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12855
84501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1285584501
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.840363709
Short name T565
Test name
Test status
Simulation time 13088795813 ps
CPU time 1030.99 seconds
Started Aug 19 04:54:42 PM PDT 24
Finished Aug 19 05:11:53 PM PDT 24
Peak memory 273368 kb
Host smart-c1d162e9-b4b4-4324-9543-26c63762fca1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840363709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.840363709
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1745857370
Short name T419
Test name
Test status
Simulation time 21040017286 ps
CPU time 620.64 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 05:04:54 PM PDT 24
Peak memory 273320 kb
Host smart-7915448d-ec65-463f-8b71-fc29c182a02f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745857370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1745857370
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1747612395
Short name T564
Test name
Test status
Simulation time 13099310844 ps
CPU time 284.17 seconds
Started Aug 19 04:54:41 PM PDT 24
Finished Aug 19 04:59:25 PM PDT 24
Peak memory 255528 kb
Host smart-22fa9525-a8b8-41e4-bbbf-110d0feb3577
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747612395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1747612395
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3606303245
Short name T409
Test name
Test status
Simulation time 1098304783 ps
CPU time 22.67 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 04:54:56 PM PDT 24
Peak memory 256220 kb
Host smart-4c3adaf0-8a00-4f01-bae7-fd8eb7e8e38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36063
03245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3606303245
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3967646848
Short name T559
Test name
Test status
Simulation time 1908408224 ps
CPU time 26.82 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 04:54:59 PM PDT 24
Peak memory 248304 kb
Host smart-d00a0813-ac39-47c9-a888-6c1977566d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39676
46848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3967646848
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.188537673
Short name T645
Test name
Test status
Simulation time 525344041 ps
CPU time 13.88 seconds
Started Aug 19 04:54:40 PM PDT 24
Finished Aug 19 04:54:54 PM PDT 24
Peak memory 256976 kb
Host smart-28ef00f0-3b8a-431c-b621-5774caf2374f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18853
7673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.188537673
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3946026954
Short name T4
Test name
Test status
Simulation time 24067041290 ps
CPU time 991.24 seconds
Started Aug 19 04:54:41 PM PDT 24
Finished Aug 19 05:11:12 PM PDT 24
Peak memory 273408 kb
Host smart-34fba858-d270-4466-b935-f4dc82041d59
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946026954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3946026954
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1424534461
Short name T88
Test name
Test status
Simulation time 25239378991 ps
CPU time 791.48 seconds
Started Aug 19 04:54:42 PM PDT 24
Finished Aug 19 05:07:53 PM PDT 24
Peak memory 283648 kb
Host smart-bc2725a6-50cb-4853-b4d8-4f8671faa455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424534461 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1424534461
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3611474421
Short name T204
Test name
Test status
Simulation time 56467749 ps
CPU time 3.01 seconds
Started Aug 19 04:54:36 PM PDT 24
Finished Aug 19 04:54:39 PM PDT 24
Peak memory 249004 kb
Host smart-41aee911-02e2-46fb-b9c2-a2488578f72f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3611474421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3611474421
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1347529986
Short name T413
Test name
Test status
Simulation time 150914611386 ps
CPU time 2424.33 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 05:34:56 PM PDT 24
Peak memory 281356 kb
Host smart-8d183e5d-93ae-4aef-9014-59cf3ec644fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347529986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1347529986
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.991916380
Short name T375
Test name
Test status
Simulation time 935037627 ps
CPU time 42.15 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:55:13 PM PDT 24
Peak memory 248796 kb
Host smart-012a757c-a4e1-4bc3-a5b3-06d37545ddff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=991916380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.991916380
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2139269286
Short name T421
Test name
Test status
Simulation time 2890803549 ps
CPU time 119.81 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 04:56:32 PM PDT 24
Peak memory 250892 kb
Host smart-ed54e7a7-1216-496e-89ec-eb0a6d07af63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21392
69286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2139269286
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1082081381
Short name T692
Test name
Test status
Simulation time 1155518765 ps
CPU time 46.2 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:55:17 PM PDT 24
Peak memory 256376 kb
Host smart-32c89824-a2e3-42c2-a671-950f50c859e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10820
81381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1082081381
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3059907444
Short name T590
Test name
Test status
Simulation time 88244699209 ps
CPU time 2147.63 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 05:30:22 PM PDT 24
Peak memory 289832 kb
Host smart-f056fca0-34bf-4782-b9b3-475c346af87f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059907444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3059907444
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1147658392
Short name T709
Test name
Test status
Simulation time 123138266627 ps
CPU time 2277.78 seconds
Started Aug 19 04:54:41 PM PDT 24
Finished Aug 19 05:32:39 PM PDT 24
Peak memory 287404 kb
Host smart-2e30fb0c-5db8-477c-9051-94b85c0403cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147658392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1147658392
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2193580605
Short name T641
Test name
Test status
Simulation time 6291883851 ps
CPU time 242.02 seconds
Started Aug 19 04:54:42 PM PDT 24
Finished Aug 19 04:58:44 PM PDT 24
Peak memory 248744 kb
Host smart-efdb5ceb-1964-442e-bc4b-42c3e52efaed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193580605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2193580605
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2422296547
Short name T2
Test name
Test status
Simulation time 2393617049 ps
CPU time 37.65 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:55:09 PM PDT 24
Peak memory 256332 kb
Host smart-cab599d2-e40f-462a-9295-1263d495eda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24222
96547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2422296547
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4096834510
Short name T78
Test name
Test status
Simulation time 2706460323 ps
CPU time 40 seconds
Started Aug 19 04:54:42 PM PDT 24
Finished Aug 19 04:55:22 PM PDT 24
Peak memory 255964 kb
Host smart-c57b1491-429d-4f2a-be2e-be0dfbd69c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40968
34510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4096834510
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1401294860
Short name T479
Test name
Test status
Simulation time 1341982543 ps
CPU time 50.13 seconds
Started Aug 19 04:54:36 PM PDT 24
Finished Aug 19 04:55:26 PM PDT 24
Peak memory 248496 kb
Host smart-7a027088-2f2a-44a9-a567-bb4db1c6b5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14012
94860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1401294860
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1235381031
Short name T400
Test name
Test status
Simulation time 1082915668 ps
CPU time 19.04 seconds
Started Aug 19 04:54:42 PM PDT 24
Finished Aug 19 04:55:01 PM PDT 24
Peak memory 256732 kb
Host smart-b9b2aa54-6471-4ebd-b7ba-6e57d5c0fe9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12353
81031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1235381031
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1602529723
Short name T93
Test name
Test status
Simulation time 938151715659 ps
CPU time 3093.89 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 05:46:07 PM PDT 24
Peak memory 305332 kb
Host smart-bebeadf1-e480-4cbf-949d-898cf2c2561e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602529723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1602529723
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1972018534
Short name T620
Test name
Test status
Simulation time 4035677017 ps
CPU time 445.63 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 05:01:58 PM PDT 24
Peak memory 271304 kb
Host smart-048cd081-5165-44d2-a206-7427e0cf78a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972018534 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1972018534
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3821280913
Short name T196
Test name
Test status
Simulation time 115134450 ps
CPU time 3.64 seconds
Started Aug 19 04:54:48 PM PDT 24
Finished Aug 19 04:54:52 PM PDT 24
Peak memory 248992 kb
Host smart-17f47e46-0114-4fae-935c-78ebceec0e07
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3821280913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3821280913
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.374543498
Short name T25
Test name
Test status
Simulation time 179568525501 ps
CPU time 966.08 seconds
Started Aug 19 04:54:49 PM PDT 24
Finished Aug 19 05:10:55 PM PDT 24
Peak memory 272864 kb
Host smart-22490f93-3aec-4adc-8914-2df4b786a16a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374543498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.374543498
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.458158397
Short name T448
Test name
Test status
Simulation time 1007071082 ps
CPU time 9.31 seconds
Started Aug 19 04:54:49 PM PDT 24
Finished Aug 19 04:54:59 PM PDT 24
Peak memory 248792 kb
Host smart-c22c9f5e-8f87-4977-8dd1-9f3047c1a8f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=458158397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.458158397
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1910695107
Short name T393
Test name
Test status
Simulation time 668533847 ps
CPU time 43.99 seconds
Started Aug 19 04:54:52 PM PDT 24
Finished Aug 19 04:55:36 PM PDT 24
Peak memory 256420 kb
Host smart-595d8ab8-939f-4480-b1dd-49e91047c7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19106
95107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1910695107
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3765337719
Short name T27
Test name
Test status
Simulation time 385524713 ps
CPU time 27.91 seconds
Started Aug 19 04:54:55 PM PDT 24
Finished Aug 19 04:55:22 PM PDT 24
Peak memory 255876 kb
Host smart-7ffea059-b5e8-49f1-9aed-5af180038afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37653
37719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3765337719
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.4234491257
Short name T112
Test name
Test status
Simulation time 11132592340 ps
CPU time 1011.55 seconds
Started Aug 19 04:54:50 PM PDT 24
Finished Aug 19 05:11:41 PM PDT 24
Peak memory 289140 kb
Host smart-8be35c2f-0a03-46e9-ad8f-23b7cc0218f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234491257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.4234491257
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.620132052
Short name T714
Test name
Test status
Simulation time 17452155055 ps
CPU time 320.4 seconds
Started Aug 19 04:54:49 PM PDT 24
Finished Aug 19 05:00:10 PM PDT 24
Peak memory 248680 kb
Host smart-ca4a528d-17b1-4e94-a110-12a33f8bb44a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620132052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.620132052
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2011685285
Short name T215
Test name
Test status
Simulation time 419575878 ps
CPU time 14.05 seconds
Started Aug 19 04:54:34 PM PDT 24
Finished Aug 19 04:54:48 PM PDT 24
Peak memory 248752 kb
Host smart-e8c9435a-766a-41fc-b535-4c2175bfae95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20116
85285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2011685285
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.917558896
Short name T101
Test name
Test status
Simulation time 369822275 ps
CPU time 10.81 seconds
Started Aug 19 04:54:37 PM PDT 24
Finished Aug 19 04:54:48 PM PDT 24
Peak memory 248380 kb
Host smart-b711e0f0-6178-43e7-825e-de640258b8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91755
8896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.917558896
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.979377406
Short name T533
Test name
Test status
Simulation time 606901698 ps
CPU time 13.94 seconds
Started Aug 19 04:54:53 PM PDT 24
Finished Aug 19 04:55:07 PM PDT 24
Peak memory 248304 kb
Host smart-b90f7992-07b0-46f3-821b-9d97dac0ae4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97937
7406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.979377406
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2721321103
Short name T630
Test name
Test status
Simulation time 744604698 ps
CPU time 23.77 seconds
Started Aug 19 04:54:36 PM PDT 24
Finished Aug 19 04:55:00 PM PDT 24
Peak memory 248748 kb
Host smart-7502f6e8-e00f-49cf-bdb6-0b9caffbf13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27213
21103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2721321103
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2171435276
Short name T12
Test name
Test status
Simulation time 39210427 ps
CPU time 2.27 seconds
Started Aug 19 04:54:50 PM PDT 24
Finished Aug 19 04:54:52 PM PDT 24
Peak memory 249000 kb
Host smart-95c7885c-2863-410d-97e4-422bb64806f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2171435276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2171435276
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3694092629
Short name T405
Test name
Test status
Simulation time 5618633460 ps
CPU time 627.44 seconds
Started Aug 19 04:54:53 PM PDT 24
Finished Aug 19 05:05:20 PM PDT 24
Peak memory 273324 kb
Host smart-b0aed8c1-c196-4286-92dc-4cf18c97cc6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694092629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3694092629
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1745179647
Short name T549
Test name
Test status
Simulation time 1674261457 ps
CPU time 69.52 seconds
Started Aug 19 04:54:50 PM PDT 24
Finished Aug 19 04:55:59 PM PDT 24
Peak memory 248772 kb
Host smart-22650702-ebe0-4342-a434-271e5603a62f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1745179647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1745179647
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1240877410
Short name T365
Test name
Test status
Simulation time 1540873241 ps
CPU time 124.73 seconds
Started Aug 19 04:54:52 PM PDT 24
Finished Aug 19 04:56:57 PM PDT 24
Peak memory 256820 kb
Host smart-f3ac2719-51ad-4cef-9080-4e8a17e0fbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12408
77410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1240877410
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1681550043
Short name T439
Test name
Test status
Simulation time 411734816 ps
CPU time 27.66 seconds
Started Aug 19 04:54:50 PM PDT 24
Finished Aug 19 04:55:17 PM PDT 24
Peak memory 256916 kb
Host smart-2822c77a-694c-4f1a-8c3e-3c24dc98a582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16815
50043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1681550043
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1964952248
Short name T469
Test name
Test status
Simulation time 64996309129 ps
CPU time 2415.1 seconds
Started Aug 19 04:54:52 PM PDT 24
Finished Aug 19 05:35:07 PM PDT 24
Peak memory 289404 kb
Host smart-45918b89-708f-4822-8b0f-318948272c7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964952248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1964952248
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3736328458
Short name T115
Test name
Test status
Simulation time 8574962885 ps
CPU time 91.06 seconds
Started Aug 19 04:54:53 PM PDT 24
Finished Aug 19 04:56:24 PM PDT 24
Peak memory 248840 kb
Host smart-b2d1fffb-320c-4a91-8a76-687e3c65b8e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736328458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3736328458
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2973344496
Short name T374
Test name
Test status
Simulation time 4588259364 ps
CPU time 59.32 seconds
Started Aug 19 04:54:54 PM PDT 24
Finished Aug 19 04:55:53 PM PDT 24
Peak memory 256244 kb
Host smart-1eb0913b-c0d7-440e-bbe2-015feb4b201c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29733
44496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2973344496
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.206805478
Short name T397
Test name
Test status
Simulation time 152996320 ps
CPU time 14.89 seconds
Started Aug 19 04:54:53 PM PDT 24
Finished Aug 19 04:55:08 PM PDT 24
Peak memory 256388 kb
Host smart-cd02afa4-3922-46d1-8cb9-d7e0b0e00b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20680
5478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.206805478
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2090229337
Short name T700
Test name
Test status
Simulation time 318532639 ps
CPU time 15.18 seconds
Started Aug 19 04:54:52 PM PDT 24
Finished Aug 19 04:55:07 PM PDT 24
Peak memory 255928 kb
Host smart-9b4cc87c-61aa-47d5-a815-36cc163fb2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20902
29337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2090229337
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2652183653
Short name T33
Test name
Test status
Simulation time 28531745937 ps
CPU time 1226.13 seconds
Started Aug 19 04:54:53 PM PDT 24
Finished Aug 19 05:15:19 PM PDT 24
Peak memory 289388 kb
Host smart-b99cdbb9-878e-432f-99a8-4331dbcb8bf6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652183653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2652183653
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3297103045
Short name T200
Test name
Test status
Simulation time 518826957 ps
CPU time 3.21 seconds
Started Aug 19 04:55:01 PM PDT 24
Finished Aug 19 04:55:05 PM PDT 24
Peak memory 248996 kb
Host smart-1d8f0335-469c-4772-a43c-8bbc6a63bbdd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3297103045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3297103045
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1019038711
Short name T40
Test name
Test status
Simulation time 73693959741 ps
CPU time 1318.43 seconds
Started Aug 19 04:54:50 PM PDT 24
Finished Aug 19 05:16:48 PM PDT 24
Peak memory 289504 kb
Host smart-f03fa28a-0931-4671-b026-a2c68e641c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019038711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1019038711
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.942352622
Short name T395
Test name
Test status
Simulation time 1329330360 ps
CPU time 55.41 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:56:03 PM PDT 24
Peak memory 248724 kb
Host smart-84bb03dd-97d1-4824-ab82-2a27d886e21d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=942352622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.942352622
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3195567204
Short name T14
Test name
Test status
Simulation time 22546670526 ps
CPU time 180.88 seconds
Started Aug 19 04:54:53 PM PDT 24
Finished Aug 19 04:57:54 PM PDT 24
Peak memory 256528 kb
Host smart-cd33332e-7f8b-40ae-993d-e7dc32708160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31955
67204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3195567204
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1855004377
Short name T370
Test name
Test status
Simulation time 57958315 ps
CPU time 7.96 seconds
Started Aug 19 04:54:49 PM PDT 24
Finished Aug 19 04:54:57 PM PDT 24
Peak memory 248360 kb
Host smart-00bb6b8d-a474-4737-ac97-418fce330594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18550
04377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1855004377
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.513354852
Short name T26
Test name
Test status
Simulation time 22463861095 ps
CPU time 1184.85 seconds
Started Aug 19 04:55:01 PM PDT 24
Finished Aug 19 05:14:47 PM PDT 24
Peak memory 288820 kb
Host smart-55c74021-963e-4de9-9c70-85069b9854c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513354852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.513354852
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.4121055182
Short name T282
Test name
Test status
Simulation time 1941736559 ps
CPU time 81.69 seconds
Started Aug 19 04:54:48 PM PDT 24
Finished Aug 19 04:56:10 PM PDT 24
Peak memory 248608 kb
Host smart-73567339-b0a6-4d29-b629-af52c269445a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121055182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.4121055182
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.502827221
Short name T387
Test name
Test status
Simulation time 1089216871 ps
CPU time 25.17 seconds
Started Aug 19 04:54:48 PM PDT 24
Finished Aug 19 04:55:13 PM PDT 24
Peak memory 248812 kb
Host smart-bd417cf0-9296-44dc-b05e-d29ce6113566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50282
7221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.502827221
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3752789063
Short name T3
Test name
Test status
Simulation time 5000480104 ps
CPU time 83.67 seconds
Started Aug 19 04:54:53 PM PDT 24
Finished Aug 19 04:56:17 PM PDT 24
Peak memory 256484 kb
Host smart-53812406-e8ae-4d32-9bd0-6fcde09f54b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37527
89063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3752789063
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2318614022
Short name T708
Test name
Test status
Simulation time 215072199 ps
CPU time 23.01 seconds
Started Aug 19 04:54:50 PM PDT 24
Finished Aug 19 04:55:13 PM PDT 24
Peak memory 256992 kb
Host smart-aa8de98c-027f-433e-8ee0-664e4fe91f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186
14022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2318614022
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2933840687
Short name T688
Test name
Test status
Simulation time 37844586578 ps
CPU time 2022.12 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 05:28:47 PM PDT 24
Peak memory 283932 kb
Host smart-c260997c-226d-4379-b514-382257987dbb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933840687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2933840687
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2972737152
Short name T100
Test name
Test status
Simulation time 10710597067 ps
CPU time 208.33 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:58:35 PM PDT 24
Peak memory 273268 kb
Host smart-0f96d4bb-9248-47ba-bb50-33d29cac790a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972737152 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2972737152
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3156786608
Short name T211
Test name
Test status
Simulation time 73174928 ps
CPU time 2.8 seconds
Started Aug 19 04:55:05 PM PDT 24
Finished Aug 19 04:55:08 PM PDT 24
Peak memory 249012 kb
Host smart-02ed7375-0271-4599-af2b-dfcf8ec23f09
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3156786608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3156786608
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1323191452
Short name T104
Test name
Test status
Simulation time 25067659416 ps
CPU time 1355.75 seconds
Started Aug 19 04:55:02 PM PDT 24
Finished Aug 19 05:17:38 PM PDT 24
Peak memory 273432 kb
Host smart-d3559260-2ac5-47cd-9299-e668200a88cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323191452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1323191452
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1688972726
Short name T435
Test name
Test status
Simulation time 1615059110 ps
CPU time 20.02 seconds
Started Aug 19 04:55:05 PM PDT 24
Finished Aug 19 04:55:26 PM PDT 24
Peak memory 248812 kb
Host smart-df8cb732-8013-4299-a37c-2709304ad35d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1688972726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1688972726
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3953230808
Short name T698
Test name
Test status
Simulation time 1585260958 ps
CPU time 67.91 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 04:56:11 PM PDT 24
Peak memory 256468 kb
Host smart-4e03461d-40e9-4f78-ac45-11721c56ca22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39532
30808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3953230808
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.4061990129
Short name T83
Test name
Test status
Simulation time 491147046 ps
CPU time 35.23 seconds
Started Aug 19 04:55:05 PM PDT 24
Finished Aug 19 04:55:41 PM PDT 24
Peak memory 256908 kb
Host smart-5c57d1fd-3cf1-4b28-bb35-804488f0ea37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40619
90129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.4061990129
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3648509272
Short name T707
Test name
Test status
Simulation time 15703943948 ps
CPU time 1065.48 seconds
Started Aug 19 04:55:02 PM PDT 24
Finished Aug 19 05:12:48 PM PDT 24
Peak memory 282964 kb
Host smart-60410583-1c01-4e86-87ed-b62f70880790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648509272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3648509272
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1513668950
Short name T495
Test name
Test status
Simulation time 7438981290 ps
CPU time 900.33 seconds
Started Aug 19 04:55:06 PM PDT 24
Finished Aug 19 05:10:06 PM PDT 24
Peak memory 270380 kb
Host smart-e30ff6cf-a1f2-4ebd-ac43-0d43e4fba598
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513668950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1513668950
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2246701907
Short name T632
Test name
Test status
Simulation time 284668307 ps
CPU time 25.26 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 04:55:29 PM PDT 24
Peak memory 248824 kb
Host smart-3bb28c1e-c4e0-4a6d-8c7b-3dfc0c00f5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22467
01907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2246701907
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1818379658
Short name T704
Test name
Test status
Simulation time 2447178919 ps
CPU time 34.99 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 04:55:39 PM PDT 24
Peak memory 256108 kb
Host smart-ff304a7d-f2f1-4588-ac88-520dd21328ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18183
79658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1818379658
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1104543601
Short name T586
Test name
Test status
Simulation time 667740222 ps
CPU time 41.14 seconds
Started Aug 19 04:55:02 PM PDT 24
Finished Aug 19 04:55:43 PM PDT 24
Peak memory 248780 kb
Host smart-d9cc2337-9e22-4edd-8904-1186df7f384c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11045
43601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1104543601
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.377576499
Short name T371
Test name
Test status
Simulation time 1306801684 ps
CPU time 20.89 seconds
Started Aug 19 04:55:01 PM PDT 24
Finished Aug 19 04:55:22 PM PDT 24
Peak memory 256516 kb
Host smart-793b4198-f398-4384-9f5a-f67a1096179b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37757
6499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.377576499
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3300079228
Short name T188
Test name
Test status
Simulation time 12948522040 ps
CPU time 373.89 seconds
Started Aug 19 04:55:02 PM PDT 24
Finished Aug 19 05:01:16 PM PDT 24
Peak memory 273572 kb
Host smart-4cf1f461-d517-4126-9790-e0eb1c9fd08a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300079228 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3300079228
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1801251549
Short name T210
Test name
Test status
Simulation time 19528605 ps
CPU time 2.67 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 04:55:06 PM PDT 24
Peak memory 248908 kb
Host smart-950befc7-80ae-4b1f-ac4f-cb2f584fb192
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1801251549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1801251549
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1358399716
Short name T415
Test name
Test status
Simulation time 166760656519 ps
CPU time 2876.74 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 05:43:00 PM PDT 24
Peak memory 281548 kb
Host smart-df7e1ad5-5448-45e8-9696-8c63af85a2e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358399716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1358399716
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1989818246
Short name T437
Test name
Test status
Simulation time 956384653 ps
CPU time 12.72 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 04:55:17 PM PDT 24
Peak memory 248812 kb
Host smart-45e3537a-3be9-4426-a235-e907d8e67652
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1989818246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1989818246
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3774988241
Short name T301
Test name
Test status
Simulation time 678070836 ps
CPU time 63.41 seconds
Started Aug 19 04:55:02 PM PDT 24
Finished Aug 19 04:56:06 PM PDT 24
Peak memory 256472 kb
Host smart-486ebd73-ed22-458c-8fb9-3fe34e1c643e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37749
88241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3774988241
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3562648348
Short name T520
Test name
Test status
Simulation time 214034333 ps
CPU time 10.68 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 04:55:15 PM PDT 24
Peak memory 248780 kb
Host smart-ee98d630-db0b-42a2-9d07-e49c5b59eaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35626
48348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3562648348
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3838413179
Short name T674
Test name
Test status
Simulation time 148183696079 ps
CPU time 2353.62 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 05:34:23 PM PDT 24
Peak memory 289756 kb
Host smart-507896dd-88c6-490b-8b45-1d114af08953
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838413179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3838413179
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3388386339
Short name T503
Test name
Test status
Simulation time 23831238994 ps
CPU time 1619.42 seconds
Started Aug 19 04:55:06 PM PDT 24
Finished Aug 19 05:22:06 PM PDT 24
Peak memory 288688 kb
Host smart-be0610a4-bfce-462c-8d38-36e1acfa4b9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388386339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3388386339
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.4152616128
Short name T290
Test name
Test status
Simulation time 8844568970 ps
CPU time 358 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 05:01:05 PM PDT 24
Peak memory 247720 kb
Host smart-8b346e02-68e8-4157-beae-16141efb7615
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152616128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.4152616128
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.884560092
Short name T323
Test name
Test status
Simulation time 2223492142 ps
CPU time 30.31 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 04:55:34 PM PDT 24
Peak memory 256844 kb
Host smart-e3d01d4a-7e2c-403b-bf4d-03e980483d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88456
0092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.884560092
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3860259690
Short name T637
Test name
Test status
Simulation time 2058989155 ps
CPU time 30.24 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:55:38 PM PDT 24
Peak memory 248540 kb
Host smart-5c4c2c9b-ec4c-42d2-91d5-589015d9d96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602
59690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3860259690
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3841262920
Short name T508
Test name
Test status
Simulation time 774176704 ps
CPU time 37.21 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:55:45 PM PDT 24
Peak memory 247996 kb
Host smart-65d76f71-5f77-4a01-9199-80586a2423bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38412
62920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3841262920
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1198988766
Short name T364
Test name
Test status
Simulation time 47611381 ps
CPU time 5.21 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 04:55:09 PM PDT 24
Peak memory 250796 kb
Host smart-8c34088a-9158-4de4-a9fc-d6f87c38ba2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11989
88766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1198988766
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1347570788
Short name T608
Test name
Test status
Simulation time 2560514518 ps
CPU time 201.16 seconds
Started Aug 19 04:55:05 PM PDT 24
Finished Aug 19 04:58:26 PM PDT 24
Peak memory 256968 kb
Host smart-9c4bda43-1566-4d6e-8476-a35089b27250
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347570788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1347570788
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.4022929253
Short name T109
Test name
Test status
Simulation time 14297726554 ps
CPU time 255.61 seconds
Started Aug 19 04:55:02 PM PDT 24
Finished Aug 19 04:59:18 PM PDT 24
Peak memory 265464 kb
Host smart-f336bf7d-ba7b-451a-9fa4-02b342439b0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022929253 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.4022929253
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3743756409
Short name T206
Test name
Test status
Simulation time 39468571 ps
CPU time 4.13 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 04:55:07 PM PDT 24
Peak memory 249052 kb
Host smart-52ee65c2-4698-47f2-87db-f0f348e167f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3743756409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3743756409
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2161373857
Short name T591
Test name
Test status
Simulation time 30689815977 ps
CPU time 1913.74 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 05:26:59 PM PDT 24
Peak memory 273228 kb
Host smart-486c1ef3-783b-4678-a535-fb800ad1a548
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161373857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2161373857
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1857234216
Short name T218
Test name
Test status
Simulation time 231379103 ps
CPU time 12.45 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 04:55:16 PM PDT 24
Peak memory 248844 kb
Host smart-dfcf6bfc-7128-4a30-ab9a-0398ac3b2044
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1857234216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1857234216
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3362701989
Short name T587
Test name
Test status
Simulation time 3007353330 ps
CPU time 123.03 seconds
Started Aug 19 04:55:01 PM PDT 24
Finished Aug 19 04:57:05 PM PDT 24
Peak memory 257044 kb
Host smart-516c0635-9b4e-41bb-bc13-734eecd1d772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33627
01989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3362701989
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3620386984
Short name T619
Test name
Test status
Simulation time 386234095 ps
CPU time 25.1 seconds
Started Aug 19 04:55:02 PM PDT 24
Finished Aug 19 04:55:27 PM PDT 24
Peak memory 248832 kb
Host smart-713c658c-7288-4f82-800e-84082cc2959d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36203
86984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3620386984
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.254346683
Short name T655
Test name
Test status
Simulation time 162923218174 ps
CPU time 1394.17 seconds
Started Aug 19 04:55:05 PM PDT 24
Finished Aug 19 05:18:20 PM PDT 24
Peak memory 272548 kb
Host smart-06701432-5d84-4ecd-9aca-b91082d5e7a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254346683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.254346683
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1873238493
Short name T527
Test name
Test status
Simulation time 83167964995 ps
CPU time 1090.26 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 05:13:17 PM PDT 24
Peak memory 281560 kb
Host smart-b8299bc9-abaa-4541-bea5-45fe07f89295
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873238493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1873238493
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1093745584
Short name T640
Test name
Test status
Simulation time 2887992267 ps
CPU time 47.64 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 04:55:50 PM PDT 24
Peak memory 247692 kb
Host smart-236e3fe5-f546-4a4d-9566-1cb03ef75588
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093745584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1093745584
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4044124859
Short name T687
Test name
Test status
Simulation time 1031407342 ps
CPU time 60.79 seconds
Started Aug 19 04:55:06 PM PDT 24
Finished Aug 19 04:56:07 PM PDT 24
Peak memory 248820 kb
Host smart-13d557c7-779c-4d28-9bd2-3380c7789385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40441
24859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4044124859
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.394053683
Short name T311
Test name
Test status
Simulation time 100901580 ps
CPU time 12.21 seconds
Started Aug 19 04:55:01 PM PDT 24
Finished Aug 19 04:55:13 PM PDT 24
Peak memory 248304 kb
Host smart-ba774058-e18d-4913-aa0e-bdeb1d46f63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39405
3683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.394053683
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.829947305
Short name T246
Test name
Test status
Simulation time 2197441900 ps
CPU time 34.81 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 04:55:39 PM PDT 24
Peak memory 248180 kb
Host smart-9138ac3e-ddf9-4df6-a15e-3eebd2885b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82994
7305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.829947305
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.281713009
Short name T98
Test name
Test status
Simulation time 4348587183 ps
CPU time 61.94 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 04:56:06 PM PDT 24
Peak memory 248884 kb
Host smart-083f446b-c0dc-4ffe-8c60-8d23b06bf046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
3009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.281713009
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.363563358
Short name T315
Test name
Test status
Simulation time 2131470214 ps
CPU time 117.23 seconds
Started Aug 19 04:55:06 PM PDT 24
Finished Aug 19 04:57:03 PM PDT 24
Peak memory 265304 kb
Host smart-f0ffc36e-bb59-4b94-9f27-7522df144798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363563358 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.363563358
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.117987573
Short name T205
Test name
Test status
Simulation time 16344078 ps
CPU time 2.42 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 04:55:12 PM PDT 24
Peak memory 249020 kb
Host smart-c77459a0-8645-49a9-86c8-461ac6bb84bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=117987573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.117987573
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2293675113
Short name T417
Test name
Test status
Simulation time 97185523846 ps
CPU time 3040.38 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 05:45:44 PM PDT 24
Peak memory 289776 kb
Host smart-fd50de33-b334-4d8b-8f83-63d80a63a77f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293675113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2293675113
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3698513975
Short name T45
Test name
Test status
Simulation time 970533435 ps
CPU time 12.9 seconds
Started Aug 19 04:55:05 PM PDT 24
Finished Aug 19 04:55:18 PM PDT 24
Peak memory 248804 kb
Host smart-0258dc0e-f0a9-420b-afa8-e0e52dbbd4ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3698513975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3698513975
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1141122750
Short name T662
Test name
Test status
Simulation time 1976698455 ps
CPU time 34.21 seconds
Started Aug 19 04:55:06 PM PDT 24
Finished Aug 19 04:55:40 PM PDT 24
Peak memory 256256 kb
Host smart-54f8cc81-c622-49af-91cd-0c74ae0703c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11411
22750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1141122750
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.274430531
Short name T80
Test name
Test status
Simulation time 1352338052 ps
CPU time 36.04 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:55:43 PM PDT 24
Peak memory 248596 kb
Host smart-c533aa4f-3ea1-4f0d-83de-9e89752d8944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27443
0531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.274430531
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2534767127
Short name T599
Test name
Test status
Simulation time 39807185059 ps
CPU time 416.39 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 05:02:04 PM PDT 24
Peak memory 255368 kb
Host smart-43a51bd8-f455-47b3-b971-395857374deb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534767127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2534767127
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3844841838
Short name T57
Test name
Test status
Simulation time 4255114440 ps
CPU time 39.77 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:55:48 PM PDT 24
Peak memory 256916 kb
Host smart-861c4541-4961-4b81-a8cb-431a7277f37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38448
41838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3844841838
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.211860530
Short name T231
Test name
Test status
Simulation time 991434741 ps
CPU time 16.34 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:55:23 PM PDT 24
Peak memory 248384 kb
Host smart-c4cc8a6f-2d14-4f72-92e3-79fd1c5c50f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21186
0530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.211860530
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1024846515
Short name T13
Test name
Test status
Simulation time 5596098893 ps
CPU time 43.92 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:55:52 PM PDT 24
Peak memory 256540 kb
Host smart-14debf07-a85e-4160-aabe-78a045478e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10248
46515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1024846515
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2123186643
Short name T399
Test name
Test status
Simulation time 306598561 ps
CPU time 29.83 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:55:38 PM PDT 24
Peak memory 256976 kb
Host smart-da43e5a6-9da3-422b-9566-757b8f2ff42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21231
86643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2123186643
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.197525622
Short name T535
Test name
Test status
Simulation time 7612184705 ps
CPU time 440.88 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 05:02:30 PM PDT 24
Peak memory 269208 kb
Host smart-4452e481-6331-4ce3-a754-b7ad729402cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197525622 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.197525622
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.4274065805
Short name T198
Test name
Test status
Simulation time 13288525 ps
CPU time 2.21 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 04:54:23 PM PDT 24
Peak memory 249176 kb
Host smart-5b7f8ae7-28c1-4aa4-812e-9115f2233d51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4274065805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.4274065805
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.776444490
Short name T482
Test name
Test status
Simulation time 36173478559 ps
CPU time 1763.1 seconds
Started Aug 19 04:54:23 PM PDT 24
Finished Aug 19 05:23:47 PM PDT 24
Peak memory 273372 kb
Host smart-a948c32b-d294-4001-938b-c72bf7e71f2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776444490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.776444490
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3656705642
Short name T445
Test name
Test status
Simulation time 581827169 ps
CPU time 15.14 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:54:36 PM PDT 24
Peak memory 248788 kb
Host smart-7f154c93-223c-40b2-8e6f-3175d9505b0e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3656705642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3656705642
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2579165274
Short name T656
Test name
Test status
Simulation time 2429014784 ps
CPU time 104.67 seconds
Started Aug 19 04:54:17 PM PDT 24
Finished Aug 19 04:56:02 PM PDT 24
Peak memory 250888 kb
Host smart-a26e0991-19f5-44e1-98d4-44aa6320bf97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25791
65274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2579165274
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.4188176404
Short name T452
Test name
Test status
Simulation time 1868717799 ps
CPU time 54.54 seconds
Started Aug 19 04:54:12 PM PDT 24
Finished Aug 19 04:55:07 PM PDT 24
Peak memory 249296 kb
Host smart-cb08ad6b-d853-4174-b4ea-acc89c53ef54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41881
76404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4188176404
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1596781753
Short name T274
Test name
Test status
Simulation time 8534708351 ps
CPU time 883.93 seconds
Started Aug 19 04:54:18 PM PDT 24
Finished Aug 19 05:09:02 PM PDT 24
Peak memory 273052 kb
Host smart-3cd204d0-8dd5-458f-8f64-91b8714be90d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596781753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1596781753
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2831006863
Short name T595
Test name
Test status
Simulation time 30237269329 ps
CPU time 1884.42 seconds
Started Aug 19 04:54:19 PM PDT 24
Finished Aug 19 05:25:43 PM PDT 24
Peak memory 287664 kb
Host smart-0a9a59cb-49e4-4e86-8819-d7a8ff11dbaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831006863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2831006863
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2962028089
Short name T295
Test name
Test status
Simulation time 3155103538 ps
CPU time 141.29 seconds
Started Aug 19 04:54:23 PM PDT 24
Finished Aug 19 04:56:44 PM PDT 24
Peak memory 247712 kb
Host smart-1bc9e058-580c-46c4-8364-80c201ae98eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962028089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2962028089
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1297945094
Short name T712
Test name
Test status
Simulation time 1528663280 ps
CPU time 32.42 seconds
Started Aug 19 04:54:12 PM PDT 24
Finished Aug 19 04:54:45 PM PDT 24
Peak memory 256000 kb
Host smart-6419b480-d244-467f-9120-ad8bdf2d22f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12979
45094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1297945094
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2517279249
Short name T684
Test name
Test status
Simulation time 1070749324 ps
CPU time 57.71 seconds
Started Aug 19 04:54:13 PM PDT 24
Finished Aug 19 04:55:10 PM PDT 24
Peak memory 256912 kb
Host smart-ab4099e7-ea2d-420f-b6f7-f7f4c579fed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25172
79249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2517279249
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3305244696
Short name T8
Test name
Test status
Simulation time 523058153 ps
CPU time 26.17 seconds
Started Aug 19 04:54:23 PM PDT 24
Finished Aug 19 04:54:49 PM PDT 24
Peak memory 271356 kb
Host smart-573669fb-7c51-4338-88aa-01560af28870
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3305244696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3305244696
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2595175636
Short name T411
Test name
Test status
Simulation time 358145844 ps
CPU time 5.3 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 04:54:27 PM PDT 24
Peak memory 239728 kb
Host smart-0fc76ccf-0501-4717-824b-2b074d8685c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25951
75636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2595175636
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4158570154
Short name T494
Test name
Test status
Simulation time 451825576 ps
CPU time 9.4 seconds
Started Aug 19 04:54:14 PM PDT 24
Finished Aug 19 04:54:23 PM PDT 24
Peak memory 255052 kb
Host smart-880c116f-0408-4741-a755-4026e2e645c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41585
70154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4158570154
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1627337463
Short name T571
Test name
Test status
Simulation time 194525571112 ps
CPU time 3027.67 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 05:44:59 PM PDT 24
Peak memory 296740 kb
Host smart-53d987f7-983c-49c9-9f0e-23d0a6838057
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627337463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1627337463
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3703921041
Short name T29
Test name
Test status
Simulation time 3384396391 ps
CPU time 209.14 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:57:49 PM PDT 24
Peak memory 267892 kb
Host smart-284eed7b-9e93-4cff-86aa-d3eccc96cbba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703921041 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3703921041
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.170750777
Short name T426
Test name
Test status
Simulation time 14317541137 ps
CPU time 1248.75 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 05:15:52 PM PDT 24
Peak memory 287836 kb
Host smart-21430647-e275-4fa0-bea7-9e2aa8593252
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170750777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.170750777
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2202529128
Short name T455
Test name
Test status
Simulation time 67603198 ps
CPU time 6.73 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 04:55:16 PM PDT 24
Peak memory 254076 kb
Host smart-633e424f-889e-48bc-aac8-928832bc625c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22025
29128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2202529128
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3540050722
Short name T434
Test name
Test status
Simulation time 96950716 ps
CPU time 8.13 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:55:17 PM PDT 24
Peak memory 248748 kb
Host smart-023591d7-fb6e-4852-b319-e7bd59ad9e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35400
50722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3540050722
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.4173323306
Short name T327
Test name
Test status
Simulation time 125160787962 ps
CPU time 1787.54 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 05:24:55 PM PDT 24
Peak memory 282760 kb
Host smart-92db1a4b-b342-4d38-bf98-20c204e7e07a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173323306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.4173323306
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3906086524
Short name T491
Test name
Test status
Simulation time 11881659414 ps
CPU time 907.39 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 05:10:18 PM PDT 24
Peak memory 288968 kb
Host smart-76f28e39-4f5a-442a-8661-8aa551038c9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906086524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3906086524
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1481610226
Short name T536
Test name
Test status
Simulation time 1746842678 ps
CPU time 49.19 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:55:58 PM PDT 24
Peak memory 256368 kb
Host smart-bb8e9e11-c6c6-419b-bfaf-fa3ea61c64b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14816
10226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1481610226
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1116949571
Short name T220
Test name
Test status
Simulation time 1761366566 ps
CPU time 58.79 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 04:56:01 PM PDT 24
Peak memory 256468 kb
Host smart-2eadba23-66de-4496-b66c-1bbc675af56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11169
49571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1116949571
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2265244184
Short name T433
Test name
Test status
Simulation time 1319600174 ps
CPU time 69.18 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:56:18 PM PDT 24
Peak memory 256376 kb
Host smart-4184679f-9973-44c0-8081-689bbefb0049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22652
44184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2265244184
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1311612695
Short name T598
Test name
Test status
Simulation time 10234804118 ps
CPU time 1179.68 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 05:14:51 PM PDT 24
Peak memory 289484 kb
Host smart-3afd07b9-869b-4157-9976-8342054eff1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311612695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1311612695
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.248698785
Short name T241
Test name
Test status
Simulation time 5074692722 ps
CPU time 351.33 seconds
Started Aug 19 04:55:16 PM PDT 24
Finished Aug 19 05:01:07 PM PDT 24
Peak memory 273588 kb
Host smart-188d37b8-2d5f-4007-b5bb-0df193567b79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248698785 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.248698785
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1969907836
Short name T70
Test name
Test status
Simulation time 156476008859 ps
CPU time 1751.8 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 05:24:27 PM PDT 24
Peak memory 273320 kb
Host smart-f2665e94-22cc-48ae-93b2-90bd3704ba03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969907836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1969907836
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2960209902
Short name T372
Test name
Test status
Simulation time 4017508821 ps
CPU time 158.22 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:57:47 PM PDT 24
Peak memory 257076 kb
Host smart-2b62394c-b3f0-4fd8-9648-9ae769a0062b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29602
09902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2960209902
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.4223941645
Short name T701
Test name
Test status
Simulation time 4905175092 ps
CPU time 16.49 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 04:55:28 PM PDT 24
Peak memory 248048 kb
Host smart-c2f57b64-80a5-4d4b-93b9-9c452b9e2d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42239
41645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.4223941645
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2969137888
Short name T583
Test name
Test status
Simulation time 28715060457 ps
CPU time 697.38 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:06:51 PM PDT 24
Peak memory 271860 kb
Host smart-e79d5a04-5a35-41e7-8d01-38f3819f0916
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969137888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2969137888
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.197739235
Short name T677
Test name
Test status
Simulation time 60747161507 ps
CPU time 2069.33 seconds
Started Aug 19 04:55:12 PM PDT 24
Finished Aug 19 05:29:42 PM PDT 24
Peak memory 285176 kb
Host smart-31e361e5-fb00-4725-a4b2-f79c4b6b60c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197739235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.197739235
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1575776441
Short name T296
Test name
Test status
Simulation time 21408925502 ps
CPU time 417.23 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:02:12 PM PDT 24
Peak memory 248716 kb
Host smart-d51cdad1-4ead-44af-a112-6b4dd09201ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575776441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1575776441
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3156043031
Short name T418
Test name
Test status
Simulation time 870041574 ps
CPU time 40.51 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 04:55:52 PM PDT 24
Peak memory 256148 kb
Host smart-ee30acfd-4961-4eb0-851c-089c3547f8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31560
43031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3156043031
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3631874141
Short name T652
Test name
Test status
Simulation time 209562644 ps
CPU time 18.91 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 04:55:30 PM PDT 24
Peak memory 248756 kb
Host smart-2196defb-1332-4495-a91d-416f34b53d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318
74141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3631874141
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1525513640
Short name T321
Test name
Test status
Simulation time 1102925337 ps
CPU time 30.12 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 04:55:39 PM PDT 24
Peak memory 256332 kb
Host smart-3004a2bb-fd3b-493c-88cb-15baccdb0172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15255
13640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1525513640
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.832525062
Short name T379
Test name
Test status
Simulation time 3989123990 ps
CPU time 50.87 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 04:56:02 PM PDT 24
Peak memory 257028 kb
Host smart-45bc9e73-0086-4651-91fd-3032624f7997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83252
5062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.832525062
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2119085515
Short name T440
Test name
Test status
Simulation time 19988606704 ps
CPU time 906.81 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:10:21 PM PDT 24
Peak memory 273388 kb
Host smart-7d0640d2-ef64-4947-9d38-fb44077657f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119085515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2119085515
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3554881300
Short name T610
Test name
Test status
Simulation time 36467910 ps
CPU time 5.36 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 04:55:19 PM PDT 24
Peak memory 251832 kb
Host smart-b4e268b8-cffd-44b0-8231-c1a8f4430bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35548
81300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3554881300
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2715111866
Short name T466
Test name
Test status
Simulation time 511817644 ps
CPU time 31.84 seconds
Started Aug 19 04:55:16 PM PDT 24
Finished Aug 19 04:55:48 PM PDT 24
Peak memory 248408 kb
Host smart-29b63068-db05-4ddc-b968-4eebde31f8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27151
11866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2715111866
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2788774310
Short name T337
Test name
Test status
Simulation time 40544335063 ps
CPU time 2654.38 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:39:29 PM PDT 24
Peak memory 289672 kb
Host smart-13cdcc9e-afd3-474f-8295-1439a9129d3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788774310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2788774310
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.410376794
Short name T367
Test name
Test status
Simulation time 40036950126 ps
CPU time 1206.16 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:15:20 PM PDT 24
Peak memory 283988 kb
Host smart-15662072-2b3b-4322-8b84-7cf9e0817377
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410376794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.410376794
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1280859214
Short name T627
Test name
Test status
Simulation time 950698110 ps
CPU time 51.69 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 04:55:56 PM PDT 24
Peak memory 256248 kb
Host smart-258b88a7-2c9c-4f76-aed0-74ffbbf172f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12808
59214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1280859214
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3965654208
Short name T644
Test name
Test status
Simulation time 135057333 ps
CPU time 9.68 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 04:55:21 PM PDT 24
Peak memory 248304 kb
Host smart-afbb24c4-a076-44f7-9bfd-cecb6e07aef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39656
54208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3965654208
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2333227751
Short name T47
Test name
Test status
Simulation time 463247810 ps
CPU time 27.47 seconds
Started Aug 19 04:55:17 PM PDT 24
Finished Aug 19 04:55:44 PM PDT 24
Peak memory 257000 kb
Host smart-8386e04e-4192-421d-8a76-b02e5ecc9f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23332
27751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2333227751
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3428120226
Short name T703
Test name
Test status
Simulation time 302516848 ps
CPU time 12.47 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:55:20 PM PDT 24
Peak memory 248812 kb
Host smart-99b4ebe8-48be-484c-b67b-f3f10049baff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
20226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3428120226
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2950738329
Short name T638
Test name
Test status
Simulation time 27711191926 ps
CPU time 596.41 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:05:11 PM PDT 24
Peak memory 265272 kb
Host smart-18c49d7e-b5d2-4e72-a027-c8b6c7b0ff73
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950738329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2950738329
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4012127951
Short name T467
Test name
Test status
Simulation time 4041618297 ps
CPU time 255.42 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:59:22 PM PDT 24
Peak memory 267780 kb
Host smart-89783ca0-cd3d-429a-88a1-ca1099d33e5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012127951 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4012127951
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.330860221
Short name T320
Test name
Test status
Simulation time 55864033388 ps
CPU time 1961.4 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 05:27:49 PM PDT 24
Peak memory 273600 kb
Host smart-9f4cb0a8-d2c9-48e0-8bd0-9bd080a11c85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330860221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.330860221
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3955995310
Short name T654
Test name
Test status
Simulation time 4962772652 ps
CPU time 135.06 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:57:23 PM PDT 24
Peak memory 257016 kb
Host smart-94f86811-2dbd-47c7-b300-126867a05944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39559
95310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3955995310
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1530777166
Short name T646
Test name
Test status
Simulation time 1424495516 ps
CPU time 29.12 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:55:36 PM PDT 24
Peak memory 256224 kb
Host smart-2a5e8288-81c6-426f-8058-22955ac67ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15307
77166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1530777166
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3627239195
Short name T346
Test name
Test status
Simulation time 11404113311 ps
CPU time 1301.96 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 05:16:50 PM PDT 24
Peak memory 287424 kb
Host smart-6048c74c-83c0-44ab-b74f-d0540a934a4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627239195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3627239195
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2797069710
Short name T464
Test name
Test status
Simulation time 202545657978 ps
CPU time 1358.38 seconds
Started Aug 19 04:55:03 PM PDT 24
Finished Aug 19 05:17:42 PM PDT 24
Peak memory 267472 kb
Host smart-74e4bbf8-8c85-466a-b09d-d68bf382ed37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797069710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2797069710
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2825114134
Short name T291
Test name
Test status
Simulation time 49714504744 ps
CPU time 506.49 seconds
Started Aug 19 04:55:10 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 247860 kb
Host smart-8ec64264-7913-4db3-b704-bc2c4c83703b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825114134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2825114134
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2767566158
Short name T11
Test name
Test status
Simulation time 249840369 ps
CPU time 35.07 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 04:55:50 PM PDT 24
Peak memory 256204 kb
Host smart-bb7b21a9-0f0f-4c19-a18c-ad0858c5e129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
66158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2767566158
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3330335251
Short name T38
Test name
Test status
Simulation time 1457461044 ps
CPU time 27.86 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:55:36 PM PDT 24
Peak memory 248628 kb
Host smart-481d6a30-a195-49d6-a15e-915eac623092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303
35251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3330335251
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1576937485
Short name T488
Test name
Test status
Simulation time 160356608 ps
CPU time 15.19 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:55:23 PM PDT 24
Peak memory 255284 kb
Host smart-e34a2680-b524-41a6-9ab9-a1de24084b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15769
37485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1576937485
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3940663861
Short name T48
Test name
Test status
Simulation time 813199920 ps
CPU time 15.01 seconds
Started Aug 19 04:55:07 PM PDT 24
Finished Aug 19 04:55:22 PM PDT 24
Peak memory 248824 kb
Host smart-41eeb326-c73d-45cd-940e-24553e9c6835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39406
63861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3940663861
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2373236378
Short name T116
Test name
Test status
Simulation time 76434051169 ps
CPU time 1543.64 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 05:20:53 PM PDT 24
Peak memory 289376 kb
Host smart-491a696b-5475-45a9-b629-502e1d2021d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373236378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2373236378
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3379501502
Short name T540
Test name
Test status
Simulation time 56668102108 ps
CPU time 1782 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 05:24:53 PM PDT 24
Peak memory 289136 kb
Host smart-1edf1477-f041-4dc5-9757-41c17a82bd13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379501502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3379501502
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.8067658
Short name T617
Test name
Test status
Simulation time 6988223284 ps
CPU time 190.44 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 04:58:19 PM PDT 24
Peak memory 256608 kb
Host smart-40d4688c-ba2d-42a1-8bce-241740a7e96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80676
58 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.8067658
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.334146075
Short name T589
Test name
Test status
Simulation time 2352628792 ps
CPU time 38.44 seconds
Started Aug 19 04:55:10 PM PDT 24
Finished Aug 19 04:55:48 PM PDT 24
Peak memory 248812 kb
Host smart-16d7171a-1c2c-4540-9ee0-52ed7987536a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33414
6075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.334146075
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2333595187
Short name T414
Test name
Test status
Simulation time 159841716425 ps
CPU time 1785.58 seconds
Started Aug 19 04:55:11 PM PDT 24
Finished Aug 19 05:24:57 PM PDT 24
Peak memory 273380 kb
Host smart-36165693-7540-47b6-a903-0219d7fd4710
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333595187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2333595187
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1507115361
Short name T289
Test name
Test status
Simulation time 8193643810 ps
CPU time 160.5 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:57:49 PM PDT 24
Peak memory 248804 kb
Host smart-84b73800-e5a8-49d3-a88d-7b132c73e870
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507115361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1507115361
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3537585620
Short name T373
Test name
Test status
Simulation time 321786451 ps
CPU time 9.86 seconds
Started Aug 19 04:55:10 PM PDT 24
Finished Aug 19 04:55:20 PM PDT 24
Peak memory 248844 kb
Host smart-fbe3b303-29e8-4fbc-9e65-a8d721448534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35375
85620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3537585620
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2101890119
Short name T622
Test name
Test status
Simulation time 288610157 ps
CPU time 17.12 seconds
Started Aug 19 04:55:08 PM PDT 24
Finished Aug 19 04:55:26 PM PDT 24
Peak memory 248336 kb
Host smart-40e3acb6-765b-4b24-b783-bc6efac73e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21018
90119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2101890119
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.251537454
Short name T451
Test name
Test status
Simulation time 597717402 ps
CPU time 37.48 seconds
Started Aug 19 04:55:09 PM PDT 24
Finished Aug 19 04:55:47 PM PDT 24
Peak memory 256896 kb
Host smart-5fea3729-4448-41b4-b851-d3820020dcfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25153
7454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.251537454
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.437043579
Short name T396
Test name
Test status
Simulation time 261165843999 ps
CPU time 1748.79 seconds
Started Aug 19 04:55:21 PM PDT 24
Finished Aug 19 05:24:30 PM PDT 24
Peak memory 273312 kb
Host smart-97a3dddf-6df3-4cab-a65b-306571f442ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437043579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.437043579
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.994644978
Short name T602
Test name
Test status
Simulation time 11466673489 ps
CPU time 183.15 seconds
Started Aug 19 04:55:16 PM PDT 24
Finished Aug 19 04:58:19 PM PDT 24
Peak memory 256964 kb
Host smart-fdb3b8d1-e987-41b3-b570-241c3eb45714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99464
4978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.994644978
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2140594257
Short name T579
Test name
Test status
Simulation time 2263551321 ps
CPU time 68.47 seconds
Started Aug 19 04:55:16 PM PDT 24
Finished Aug 19 04:56:25 PM PDT 24
Peak memory 256624 kb
Host smart-f3432a14-e06a-49b9-b871-759515a20c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21405
94257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2140594257
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2313435864
Short name T328
Test name
Test status
Simulation time 10906221991 ps
CPU time 1182.95 seconds
Started Aug 19 04:55:22 PM PDT 24
Finished Aug 19 05:15:05 PM PDT 24
Peak memory 285364 kb
Host smart-040bf9d2-4d10-47ff-92bd-359fc3e91a89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313435864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2313435864
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.355760811
Short name T673
Test name
Test status
Simulation time 57179498281 ps
CPU time 516.67 seconds
Started Aug 19 04:55:19 PM PDT 24
Finished Aug 19 05:03:56 PM PDT 24
Peak memory 249036 kb
Host smart-15e45061-e45b-4687-a904-4a85c8ff6169
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355760811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.355760811
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1113804010
Short name T507
Test name
Test status
Simulation time 1503371916 ps
CPU time 25.69 seconds
Started Aug 19 04:55:16 PM PDT 24
Finished Aug 19 04:55:41 PM PDT 24
Peak memory 248748 kb
Host smart-9d9c6065-7aed-4d85-ae14-89ce3a33b07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11138
04010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1113804010
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1982224539
Short name T51
Test name
Test status
Simulation time 793381918 ps
CPU time 27.21 seconds
Started Aug 19 04:55:04 PM PDT 24
Finished Aug 19 04:55:31 PM PDT 24
Peak memory 248796 kb
Host smart-b18d7dfc-2366-4186-a864-cb6e31d836c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
24539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1982224539
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1608978248
Short name T71
Test name
Test status
Simulation time 203197239 ps
CPU time 23.25 seconds
Started Aug 19 04:55:13 PM PDT 24
Finished Aug 19 04:55:37 PM PDT 24
Peak memory 248792 kb
Host smart-a1d74584-c386-40db-a417-318217392cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16089
78248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1608978248
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3825846899
Short name T380
Test name
Test status
Simulation time 897340107 ps
CPU time 35.91 seconds
Started Aug 19 04:55:10 PM PDT 24
Finished Aug 19 04:55:46 PM PDT 24
Peak memory 256024 kb
Host smart-2162b076-bcc4-4efe-8823-9dcb0c93552a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38258
46899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3825846899
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.274372495
Short name T89
Test name
Test status
Simulation time 49086367515 ps
CPU time 270.65 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 04:59:45 PM PDT 24
Peak memory 265260 kb
Host smart-1b93b6dc-7482-4ad2-bcfe-6fe4ad76346d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274372495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.274372495
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.37189377
Short name T317
Test name
Test status
Simulation time 7778023638 ps
CPU time 472.42 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 05:03:08 PM PDT 24
Peak memory 270272 kb
Host smart-135d20f6-09d9-48fb-b748-1801c4f204e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37189377 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.37189377
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.38598372
Short name T538
Test name
Test status
Simulation time 30545813307 ps
CPU time 1797.72 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 05:25:13 PM PDT 24
Peak memory 272468 kb
Host smart-ab4429df-84f0-4378-971e-6bce67105ca4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38598372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.38598372
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.259662230
Short name T534
Test name
Test status
Simulation time 242307846 ps
CPU time 10.78 seconds
Started Aug 19 04:55:18 PM PDT 24
Finished Aug 19 04:55:29 PM PDT 24
Peak memory 253932 kb
Host smart-ea1c781e-bb5c-4f15-8ebd-a29aec8f568d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25966
2230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.259662230
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.599050831
Short name T392
Test name
Test status
Simulation time 1799148948 ps
CPU time 32.12 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 04:55:47 PM PDT 24
Peak memory 248752 kb
Host smart-38c8e2b3-4e6e-44fc-8436-9d6d72bf97ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59905
0831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.599050831
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1070707658
Short name T711
Test name
Test status
Simulation time 168159967898 ps
CPU time 2238.68 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 05:32:34 PM PDT 24
Peak memory 289148 kb
Host smart-74cc36fa-d370-43d6-a511-8873a783083a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070707658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1070707658
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.4012144983
Short name T661
Test name
Test status
Simulation time 44554333302 ps
CPU time 1311.73 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 05:17:07 PM PDT 24
Peak memory 272164 kb
Host smart-e0e1d077-4ceb-459d-b8e6-c6daefe2fa8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012144983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4012144983
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.118278416
Short name T537
Test name
Test status
Simulation time 16448012135 ps
CPU time 332.85 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 05:00:48 PM PDT 24
Peak memory 249028 kb
Host smart-b1b9bf90-9598-4a24-a638-1d01c339e1f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118278416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.118278416
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3646115156
Short name T663
Test name
Test status
Simulation time 2197859058 ps
CPU time 64.24 seconds
Started Aug 19 04:55:22 PM PDT 24
Finished Aug 19 04:56:26 PM PDT 24
Peak memory 256132 kb
Host smart-7a346ee5-f468-4edf-b791-a8e4fa570a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36461
15156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3646115156
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4122955843
Short name T510
Test name
Test status
Simulation time 1608212729 ps
CPU time 42.77 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 04:55:57 PM PDT 24
Peak memory 256512 kb
Host smart-897af4a7-7aee-4126-94ef-00c10cf7221b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41229
55843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4122955843
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.855441893
Short name T686
Test name
Test status
Simulation time 823799634 ps
CPU time 54.39 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 04:56:09 PM PDT 24
Peak memory 248124 kb
Host smart-2346b27c-8ff5-4d2d-ad55-0793c8b21dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85544
1893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.855441893
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4046268295
Short name T582
Test name
Test status
Simulation time 1093287173 ps
CPU time 66.13 seconds
Started Aug 19 04:55:22 PM PDT 24
Finished Aug 19 04:56:29 PM PDT 24
Peak memory 256440 kb
Host smart-cd4ad1f7-43dd-4c8a-a60b-cd6072411977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40462
68295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4046268295
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2726009449
Short name T428
Test name
Test status
Simulation time 9389325596 ps
CPU time 211.98 seconds
Started Aug 19 04:55:17 PM PDT 24
Finished Aug 19 04:58:50 PM PDT 24
Peak memory 265396 kb
Host smart-c1c6721f-fe0b-40d6-bb23-90edc5372e9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726009449 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2726009449
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2607923946
Short name T237
Test name
Test status
Simulation time 44289434994 ps
CPU time 1227.99 seconds
Started Aug 19 04:55:22 PM PDT 24
Finished Aug 19 05:15:50 PM PDT 24
Peak memory 288808 kb
Host smart-3a4cd32d-6050-489b-9ccf-ecb9d4c8f78e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607923946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2607923946
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1841078610
Short name T485
Test name
Test status
Simulation time 4024207046 ps
CPU time 88.89 seconds
Started Aug 19 04:55:18 PM PDT 24
Finished Aug 19 04:56:47 PM PDT 24
Peak memory 249900 kb
Host smart-b6baf1d7-be5d-4656-a708-aaf60ab8f6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18410
78610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1841078610
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2387639675
Short name T568
Test name
Test status
Simulation time 344549451 ps
CPU time 34.29 seconds
Started Aug 19 04:55:15 PM PDT 24
Finished Aug 19 04:55:49 PM PDT 24
Peak memory 248788 kb
Host smart-6d8ecc49-ec78-40d5-af72-65543bcaa1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23876
39675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2387639675
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.255392211
Short name T319
Test name
Test status
Simulation time 55926414468 ps
CPU time 730.57 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:07:25 PM PDT 24
Peak memory 288992 kb
Host smart-809de54c-d577-4e30-8158-4c4a8017442d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255392211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.255392211
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2516643855
Short name T73
Test name
Test status
Simulation time 210893223 ps
CPU time 24.18 seconds
Started Aug 19 04:55:22 PM PDT 24
Finished Aug 19 04:55:47 PM PDT 24
Peak memory 256284 kb
Host smart-06de1579-71a7-4f82-a400-2e0b9ffa99c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25166
43855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2516643855
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3811863220
Short name T114
Test name
Test status
Simulation time 1984530118 ps
CPU time 9.1 seconds
Started Aug 19 04:55:19 PM PDT 24
Finished Aug 19 04:55:28 PM PDT 24
Peak memory 248824 kb
Host smart-43205e4d-33c2-4e3c-8c42-034c1f504dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38118
63220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3811863220
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3499164744
Short name T228
Test name
Test status
Simulation time 1676982527 ps
CPU time 18.91 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 04:55:33 PM PDT 24
Peak memory 248820 kb
Host smart-920b9765-710a-48de-aa2c-7973c3007639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34991
64744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3499164744
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3003970434
Short name T521
Test name
Test status
Simulation time 114338778299 ps
CPU time 1787.97 seconds
Started Aug 19 04:55:14 PM PDT 24
Finished Aug 19 05:25:02 PM PDT 24
Peak memory 272660 kb
Host smart-a33e83e8-73e3-4416-adf2-ab2af70215ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003970434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3003970434
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1667086871
Short name T689
Test name
Test status
Simulation time 10434751429 ps
CPU time 374.05 seconds
Started Aug 19 04:55:16 PM PDT 24
Finished Aug 19 05:01:30 PM PDT 24
Peak memory 268112 kb
Host smart-82bfe458-1474-4709-bddd-b0f58ae9e5c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667086871 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1667086871
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2159030125
Short name T584
Test name
Test status
Simulation time 8744241278 ps
CPU time 767.49 seconds
Started Aug 19 04:55:29 PM PDT 24
Finished Aug 19 05:08:17 PM PDT 24
Peak memory 272976 kb
Host smart-69af7474-935c-4cb5-824d-4f9fdcd31e03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159030125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2159030125
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2429892432
Short name T705
Test name
Test status
Simulation time 499918206 ps
CPU time 35.22 seconds
Started Aug 19 04:55:32 PM PDT 24
Finished Aug 19 04:56:07 PM PDT 24
Peak memory 256496 kb
Host smart-65b6cd69-9cf2-44dc-b1f6-0d673efe586a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24298
92432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2429892432
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.214390837
Short name T404
Test name
Test status
Simulation time 647801010 ps
CPU time 26.67 seconds
Started Aug 19 04:55:31 PM PDT 24
Finished Aug 19 04:55:58 PM PDT 24
Peak memory 255632 kb
Host smart-36bd57f4-f7a4-4336-9847-411dcf098211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21439
0837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.214390837
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1645706958
Short name T275
Test name
Test status
Simulation time 8153466675 ps
CPU time 701.9 seconds
Started Aug 19 04:55:29 PM PDT 24
Finished Aug 19 05:07:11 PM PDT 24
Peak memory 273108 kb
Host smart-46f92627-078c-421a-9273-dbdd99e1d197
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645706958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1645706958
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3822191975
Short name T600
Test name
Test status
Simulation time 166266367815 ps
CPU time 978.29 seconds
Started Aug 19 04:55:32 PM PDT 24
Finished Aug 19 05:11:50 PM PDT 24
Peak memory 284192 kb
Host smart-5dde367f-ff05-4e2b-adc1-2d1befce2b10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822191975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3822191975
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3362291472
Short name T225
Test name
Test status
Simulation time 6877723890 ps
CPU time 276.51 seconds
Started Aug 19 04:55:28 PM PDT 24
Finished Aug 19 05:00:05 PM PDT 24
Peak memory 248840 kb
Host smart-b6fc70ac-ac39-4eea-8bd6-d5d83bc5cce1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362291472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3362291472
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2814154191
Short name T618
Test name
Test status
Simulation time 233482235 ps
CPU time 21.46 seconds
Started Aug 19 04:55:30 PM PDT 24
Finished Aug 19 04:55:52 PM PDT 24
Peak memory 248836 kb
Host smart-2a708f70-3760-46bd-af41-1f7a343f8a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28141
54191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2814154191
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.606679623
Short name T125
Test name
Test status
Simulation time 2952287923 ps
CPU time 26 seconds
Started Aug 19 04:55:29 PM PDT 24
Finished Aug 19 04:55:55 PM PDT 24
Peak memory 248104 kb
Host smart-41349e7f-1bf5-41b1-bce6-cde3f74e2f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60667
9623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.606679623
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3958959749
Short name T699
Test name
Test status
Simulation time 6475976872 ps
CPU time 23.5 seconds
Started Aug 19 04:55:29 PM PDT 24
Finished Aug 19 04:55:53 PM PDT 24
Peak memory 248912 kb
Host smart-4e273bf1-2a33-4762-8433-f5d475b90da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39589
59749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3958959749
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2449616453
Short name T498
Test name
Test status
Simulation time 520501177 ps
CPU time 31.08 seconds
Started Aug 19 04:55:30 PM PDT 24
Finished Aug 19 04:56:01 PM PDT 24
Peak memory 255608 kb
Host smart-9b68989f-4e56-4ee0-88a9-adf6282334cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24496
16453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2449616453
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3941247148
Short name T312
Test name
Test status
Simulation time 4547702650 ps
CPU time 578.34 seconds
Started Aug 19 04:55:28 PM PDT 24
Finished Aug 19 05:05:07 PM PDT 24
Peak memory 273516 kb
Host smart-ab213fd7-4b8a-4cd0-a1b4-e6caadf186fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941247148 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3941247148
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.4125813744
Short name T555
Test name
Test status
Simulation time 32171863636 ps
CPU time 823.74 seconds
Started Aug 19 04:55:33 PM PDT 24
Finished Aug 19 05:09:17 PM PDT 24
Peak memory 282368 kb
Host smart-81cbf966-327c-4e75-b350-c48cd67740a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125813744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.4125813744
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.242472935
Short name T604
Test name
Test status
Simulation time 1747128746 ps
CPU time 166.31 seconds
Started Aug 19 04:55:31 PM PDT 24
Finished Aug 19 04:58:18 PM PDT 24
Peak memory 256988 kb
Host smart-e6ee0eec-485b-4db1-b670-78b3c44ece44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24247
2935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.242472935
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2318144167
Short name T506
Test name
Test status
Simulation time 1206128083 ps
CPU time 71.37 seconds
Started Aug 19 04:55:29 PM PDT 24
Finished Aug 19 04:56:41 PM PDT 24
Peak memory 256936 kb
Host smart-1c810642-1b00-498c-a7df-9b0da0a6749f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181
44167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2318144167
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1849223788
Short name T338
Test name
Test status
Simulation time 89843367706 ps
CPU time 1306.45 seconds
Started Aug 19 04:55:32 PM PDT 24
Finished Aug 19 05:17:19 PM PDT 24
Peak memory 273376 kb
Host smart-6767cd9c-ff76-4710-b6a6-0c35719dd307
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849223788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1849223788
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2530155438
Short name T236
Test name
Test status
Simulation time 45488059080 ps
CPU time 1380.9 seconds
Started Aug 19 04:55:31 PM PDT 24
Finished Aug 19 05:18:32 PM PDT 24
Peak memory 273128 kb
Host smart-f06ff7bf-804a-4648-98d3-2ba3e1fddc23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530155438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2530155438
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.460419422
Short name T561
Test name
Test status
Simulation time 36538394026 ps
CPU time 215.8 seconds
Started Aug 19 04:55:29 PM PDT 24
Finished Aug 19 04:59:05 PM PDT 24
Peak memory 247924 kb
Host smart-d0541094-2094-40a8-8b38-3acd63e3b6d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460419422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.460419422
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1801219935
Short name T484
Test name
Test status
Simulation time 859169928 ps
CPU time 48.04 seconds
Started Aug 19 04:55:31 PM PDT 24
Finished Aug 19 04:56:19 PM PDT 24
Peak memory 255572 kb
Host smart-3dd7b5be-99f6-4f76-8872-6505515f1066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18012
19935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1801219935
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3828796333
Short name T322
Test name
Test status
Simulation time 68960921 ps
CPU time 4.56 seconds
Started Aug 19 04:55:31 PM PDT 24
Finished Aug 19 04:55:36 PM PDT 24
Peak memory 240036 kb
Host smart-7aad174a-ddc0-4332-8d7c-caef9182f4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38287
96333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3828796333
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2473163455
Short name T407
Test name
Test status
Simulation time 103280788 ps
CPU time 13.25 seconds
Started Aug 19 04:55:33 PM PDT 24
Finished Aug 19 04:55:47 PM PDT 24
Peak memory 256940 kb
Host smart-31993e8a-261d-4080-abf7-6321178150c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24731
63455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2473163455
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.398746465
Short name T248
Test name
Test status
Simulation time 559252638072 ps
CPU time 3205.49 seconds
Started Aug 19 04:55:33 PM PDT 24
Finished Aug 19 05:48:59 PM PDT 24
Peak memory 297872 kb
Host smart-eb02dfbe-7f4d-4410-abc8-bb308d824276
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398746465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.398746465
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2444770322
Short name T58
Test name
Test status
Simulation time 54059774302 ps
CPU time 1801.6 seconds
Started Aug 19 04:54:27 PM PDT 24
Finished Aug 19 05:24:29 PM PDT 24
Peak memory 273364 kb
Host smart-506d36c4-97f7-495b-a21b-190381fd9057
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444770322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2444770322
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1952346867
Short name T573
Test name
Test status
Simulation time 510368326 ps
CPU time 14.3 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:54:44 PM PDT 24
Peak memory 248764 kb
Host smart-33549171-07ff-458e-bb7f-62819a64c9a0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1952346867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1952346867
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3713329715
Short name T118
Test name
Test status
Simulation time 1418790414 ps
CPU time 68.69 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:55:28 PM PDT 24
Peak memory 249836 kb
Host smart-4762e1a0-5957-4617-91c2-ce8a4d285aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37133
29715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3713329715
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2193827533
Short name T668
Test name
Test status
Simulation time 183954609 ps
CPU time 9.7 seconds
Started Aug 19 04:54:19 PM PDT 24
Finished Aug 19 04:54:29 PM PDT 24
Peak memory 248364 kb
Host smart-8d706d4f-1e11-49d5-b33b-46e4b8ed6a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21938
27533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2193827533
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.514864513
Short name T332
Test name
Test status
Simulation time 72478851964 ps
CPU time 1141.06 seconds
Started Aug 19 04:54:18 PM PDT 24
Finished Aug 19 05:13:19 PM PDT 24
Peak memory 273460 kb
Host smart-e900802a-acaa-443a-a8bc-0acd6c416589
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514864513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.514864513
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1685313080
Short name T671
Test name
Test status
Simulation time 121488304059 ps
CPU time 2054.23 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 05:28:36 PM PDT 24
Peak memory 283976 kb
Host smart-5066acad-6391-4ac8-90af-6aa85bf2aefa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685313080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1685313080
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3696091086
Short name T280
Test name
Test status
Simulation time 16670052523 ps
CPU time 184.64 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 04:57:26 PM PDT 24
Peak memory 248600 kb
Host smart-969d9b7e-1000-4d2b-a5bf-ab431ac895ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696091086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3696091086
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1458935318
Short name T447
Test name
Test status
Simulation time 9840432876 ps
CPU time 57.14 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:55:17 PM PDT 24
Peak memory 248768 kb
Host smart-566767b6-6cec-40cc-a330-8116ef584af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14589
35318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1458935318
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2410760093
Short name T382
Test name
Test status
Simulation time 1590199639 ps
CPU time 14.32 seconds
Started Aug 19 04:54:23 PM PDT 24
Finished Aug 19 04:54:37 PM PDT 24
Peak memory 253840 kb
Host smart-061f69d6-c709-40ae-87ff-e860ad24505c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24107
60093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2410760093
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.11956858
Short name T10
Test name
Test status
Simulation time 1830654405 ps
CPU time 24.05 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:54:54 PM PDT 24
Peak memory 275764 kb
Host smart-536ee765-93ed-4f97-a862-0e5c0e3faf54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=11956858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.11956858
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.33249500
Short name T669
Test name
Test status
Simulation time 648632349 ps
CPU time 39.43 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:54:59 PM PDT 24
Peak memory 256460 kb
Host smart-6eb76680-5a9a-4177-9bed-97e9821cbad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33249
500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.33249500
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.4104400379
Short name T547
Test name
Test status
Simulation time 675098787 ps
CPU time 48.43 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 04:55:10 PM PDT 24
Peak memory 256364 kb
Host smart-35bc86e1-7fc4-44c1-bad9-3f7c70a0b816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41044
00379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.4104400379
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2377733042
Short name T616
Test name
Test status
Simulation time 173712278963 ps
CPU time 2642.22 seconds
Started Aug 19 04:55:33 PM PDT 24
Finished Aug 19 05:39:36 PM PDT 24
Peak memory 289028 kb
Host smart-b7aae861-e1fc-43eb-956c-b8774bd2d419
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377733042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2377733042
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.4190003091
Short name T402
Test name
Test status
Simulation time 1319471563 ps
CPU time 73.44 seconds
Started Aug 19 04:55:31 PM PDT 24
Finished Aug 19 04:56:45 PM PDT 24
Peak memory 256100 kb
Host smart-e3480a7b-351d-403d-b715-eade375f855f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41900
03091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4190003091
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2582093837
Short name T84
Test name
Test status
Simulation time 771667300 ps
CPU time 20.66 seconds
Started Aug 19 04:55:34 PM PDT 24
Finished Aug 19 04:55:55 PM PDT 24
Peak memory 248204 kb
Host smart-c9afae96-166a-4efd-90cb-701f185470d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820
93837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2582093837
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3824114104
Short name T333
Test name
Test status
Simulation time 54050298186 ps
CPU time 2993.66 seconds
Started Aug 19 04:55:34 PM PDT 24
Finished Aug 19 05:45:28 PM PDT 24
Peak memory 287580 kb
Host smart-f881dc61-6b1c-46f9-8b62-e96d18283ad8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824114104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3824114104
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4248068157
Short name T463
Test name
Test status
Simulation time 278209796853 ps
CPU time 1117.95 seconds
Started Aug 19 04:55:34 PM PDT 24
Finished Aug 19 05:14:13 PM PDT 24
Peak memory 288808 kb
Host smart-7571d4ea-a483-4730-b394-e9ea66de174d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248068157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4248068157
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1956789579
Short name T486
Test name
Test status
Simulation time 390486044 ps
CPU time 23.28 seconds
Started Aug 19 04:55:34 PM PDT 24
Finished Aug 19 04:55:58 PM PDT 24
Peak memory 256880 kb
Host smart-926d9556-fbfb-43ce-b0f0-a639de04e2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19567
89579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1956789579
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3057412386
Short name T16
Test name
Test status
Simulation time 272720036 ps
CPU time 31.7 seconds
Started Aug 19 04:55:30 PM PDT 24
Finished Aug 19 04:56:02 PM PDT 24
Peak memory 248300 kb
Host smart-d9725c34-d41f-467a-af83-4db04fbb19d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30574
12386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3057412386
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.228766839
Short name T460
Test name
Test status
Simulation time 386310927 ps
CPU time 12.39 seconds
Started Aug 19 04:55:32 PM PDT 24
Finished Aug 19 04:55:45 PM PDT 24
Peak memory 248716 kb
Host smart-15b56277-9761-4de9-937e-3c779a16a161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22876
6839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.228766839
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1323300771
Short name T477
Test name
Test status
Simulation time 329061201486 ps
CPU time 1719.23 seconds
Started Aug 19 04:55:36 PM PDT 24
Finished Aug 19 05:24:15 PM PDT 24
Peak memory 284220 kb
Host smart-68c58029-e197-4b8a-a6ff-3169d62bf2d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323300771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1323300771
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1974967675
Short name T32
Test name
Test status
Simulation time 10532569813 ps
CPU time 345.87 seconds
Started Aug 19 04:55:32 PM PDT 24
Finished Aug 19 05:01:18 PM PDT 24
Peak memory 270480 kb
Host smart-78bb9a2c-d898-49f1-a820-3087c0d8e649
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974967675 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1974967675
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.268329418
Short name T529
Test name
Test status
Simulation time 98718810101 ps
CPU time 3317.26 seconds
Started Aug 19 04:55:44 PM PDT 24
Finished Aug 19 05:51:02 PM PDT 24
Peak memory 289528 kb
Host smart-6f1a2821-fdaf-4a53-9fe3-10634f8e1246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268329418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.268329418
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3964249046
Short name T384
Test name
Test status
Simulation time 3271703513 ps
CPU time 212.54 seconds
Started Aug 19 04:55:41 PM PDT 24
Finished Aug 19 04:59:14 PM PDT 24
Peak memory 256424 kb
Host smart-9589c99d-aace-4369-8b4d-02b7e0c4a22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39642
49046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3964249046
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1267048291
Short name T502
Test name
Test status
Simulation time 653236197 ps
CPU time 45.12 seconds
Started Aug 19 04:55:34 PM PDT 24
Finished Aug 19 04:56:20 PM PDT 24
Peak memory 248248 kb
Host smart-833cda70-7fe0-4c95-a4f0-0f3f5bbbee33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
48291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1267048291
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1283217422
Short name T576
Test name
Test status
Simulation time 42777595427 ps
CPU time 973.51 seconds
Started Aug 19 04:55:45 PM PDT 24
Finished Aug 19 05:11:58 PM PDT 24
Peak memory 289736 kb
Host smart-3bddcc96-8f90-4fbc-9880-04c3aaab6aa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283217422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1283217422
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2962225731
Short name T691
Test name
Test status
Simulation time 6320825020 ps
CPU time 582.5 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 05:05:25 PM PDT 24
Peak memory 265248 kb
Host smart-2d662dfe-c648-4404-8ec3-4d9fdd050ded
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962225731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2962225731
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.663766984
Short name T606
Test name
Test status
Simulation time 51268272226 ps
CPU time 498.26 seconds
Started Aug 19 04:55:41 PM PDT 24
Finished Aug 19 05:03:59 PM PDT 24
Peak memory 248844 kb
Host smart-fde14fcc-b15f-4fe6-a3d9-7e863ee191ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663766984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.663766984
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.935159847
Short name T592
Test name
Test status
Simulation time 1183622018 ps
CPU time 40.99 seconds
Started Aug 19 04:55:36 PM PDT 24
Finished Aug 19 04:56:17 PM PDT 24
Peak memory 256284 kb
Host smart-3023cf52-ce49-46b9-8f42-db3a42171e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93515
9847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.935159847
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3878471951
Short name T681
Test name
Test status
Simulation time 89295682 ps
CPU time 10.49 seconds
Started Aug 19 04:55:33 PM PDT 24
Finished Aug 19 04:55:43 PM PDT 24
Peak memory 255288 kb
Host smart-86e4aa20-5fb8-4e81-9578-04f73e553994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38784
71951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3878471951
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2258304093
Short name T505
Test name
Test status
Simulation time 428279416 ps
CPU time 25.7 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 04:56:07 PM PDT 24
Peak memory 248248 kb
Host smart-b8559bae-bbe1-41d8-8749-4f3a9c8c9a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22583
04093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2258304093
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2487360585
Short name T401
Test name
Test status
Simulation time 691828854 ps
CPU time 23.11 seconds
Started Aug 19 04:55:34 PM PDT 24
Finished Aug 19 04:55:57 PM PDT 24
Peak memory 256096 kb
Host smart-78700fcc-00cb-4399-89dd-861cc074e631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24873
60585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2487360585
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1937180446
Short name T386
Test name
Test status
Simulation time 24763474843 ps
CPU time 1640.77 seconds
Started Aug 19 04:55:43 PM PDT 24
Finished Aug 19 05:23:04 PM PDT 24
Peak memory 282388 kb
Host smart-6c8c8f41-49a0-455b-aed2-34adfbb2c285
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937180446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1937180446
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1631275724
Short name T244
Test name
Test status
Simulation time 11131154035 ps
CPU time 362.64 seconds
Started Aug 19 04:55:45 PM PDT 24
Finished Aug 19 05:01:48 PM PDT 24
Peak memory 256368 kb
Host smart-93a44579-8c0b-4e86-9657-0cf6f4520271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16312
75724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1631275724
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1426687113
Short name T500
Test name
Test status
Simulation time 997675806 ps
CPU time 28.57 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 04:56:10 PM PDT 24
Peak memory 248516 kb
Host smart-d61dac3c-4910-4b0e-997d-85435e86e2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14266
87113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1426687113
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3931300302
Short name T334
Test name
Test status
Simulation time 243338435953 ps
CPU time 1950.87 seconds
Started Aug 19 04:55:43 PM PDT 24
Finished Aug 19 05:28:14 PM PDT 24
Peak memory 289308 kb
Host smart-adf981d4-dab1-4147-8b35-6e55547569bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931300302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3931300302
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2632535591
Short name T18
Test name
Test status
Simulation time 10231348634 ps
CPU time 113.62 seconds
Started Aug 19 04:55:40 PM PDT 24
Finished Aug 19 04:57:33 PM PDT 24
Peak memory 255512 kb
Host smart-34d33cea-8829-4cb6-8ed6-cb415650fc26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632535591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2632535591
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.530633724
Short name T523
Test name
Test status
Simulation time 1147742345 ps
CPU time 36.93 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 04:56:19 PM PDT 24
Peak memory 256288 kb
Host smart-b3b67817-f2f6-4a07-ac82-b2bbef164a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53063
3724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.530633724
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1698273621
Short name T406
Test name
Test status
Simulation time 1181757773 ps
CPU time 26.02 seconds
Started Aug 19 04:55:41 PM PDT 24
Finished Aug 19 04:56:07 PM PDT 24
Peak memory 256228 kb
Host smart-7c4361dd-d3ba-4d7c-8b4e-eb0d7dae0bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16982
73621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1698273621
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1365545052
Short name T515
Test name
Test status
Simulation time 2294932090 ps
CPU time 29.3 seconds
Started Aug 19 04:55:41 PM PDT 24
Finished Aug 19 04:56:11 PM PDT 24
Peak memory 248168 kb
Host smart-c9352cdc-0908-48e8-bb45-0994f59c7918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13655
45052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1365545052
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2658411691
Short name T481
Test name
Test status
Simulation time 1391346107 ps
CPU time 42.29 seconds
Started Aug 19 04:55:43 PM PDT 24
Finished Aug 19 04:56:25 PM PDT 24
Peak memory 248836 kb
Host smart-0cb7ebc1-4945-4f58-a470-6d944bfc6005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26584
11691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2658411691
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3016837390
Short name T69
Test name
Test status
Simulation time 1577340520 ps
CPU time 110.72 seconds
Started Aug 19 04:55:41 PM PDT 24
Finished Aug 19 04:57:32 PM PDT 24
Peak memory 249836 kb
Host smart-37dba5fb-3498-42e4-892d-b1002e62f19c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016837390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3016837390
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3085246037
Short name T110
Test name
Test status
Simulation time 2952228871 ps
CPU time 201.16 seconds
Started Aug 19 04:55:43 PM PDT 24
Finished Aug 19 04:59:04 PM PDT 24
Peak memory 265400 kb
Host smart-47323649-dad1-4ea1-aa6b-0c42fe5edb7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085246037 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3085246037
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2018011943
Short name T682
Test name
Test status
Simulation time 219437161142 ps
CPU time 2110.8 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 05:30:53 PM PDT 24
Peak memory 284232 kb
Host smart-ebabda35-2113-4e4e-a23d-c13713273e9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018011943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2018011943
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.4213047080
Short name T50
Test name
Test status
Simulation time 3914632734 ps
CPU time 70.2 seconds
Started Aug 19 04:55:44 PM PDT 24
Finished Aug 19 04:56:54 PM PDT 24
Peak memory 256560 kb
Host smart-422d089b-54ef-4ec9-b2ce-370dffe14099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42130
47080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4213047080
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3142115074
Short name T446
Test name
Test status
Simulation time 2247571342 ps
CPU time 33.1 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 04:56:15 PM PDT 24
Peak memory 248264 kb
Host smart-54306a9c-31af-47f8-84e5-eb7d8f2b9670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31421
15074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3142115074
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3102643488
Short name T342
Test name
Test status
Simulation time 171984096221 ps
CPU time 2895.43 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 05:43:58 PM PDT 24
Peak memory 283132 kb
Host smart-065d117d-452f-447e-aa43-57e761c6b565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102643488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3102643488
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1089184815
Short name T339
Test name
Test status
Simulation time 69207886855 ps
CPU time 924.69 seconds
Started Aug 19 04:55:46 PM PDT 24
Finished Aug 19 05:11:10 PM PDT 24
Peak memory 282560 kb
Host smart-9647df8a-a304-4171-9dde-ef613142fafd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089184815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1089184815
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.123788831
Short name T531
Test name
Test status
Simulation time 7040669577 ps
CPU time 293.02 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 05:00:35 PM PDT 24
Peak memory 248628 kb
Host smart-a761b9c6-31a1-4f50-8b3a-c3563655c9a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123788831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.123788831
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.4203192147
Short name T683
Test name
Test status
Simulation time 2894097117 ps
CPU time 50.66 seconds
Started Aug 19 04:55:45 PM PDT 24
Finished Aug 19 04:56:36 PM PDT 24
Peak memory 256420 kb
Host smart-68242f8f-0ce4-4c30-a91f-d3a2f2ac4c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42031
92147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4203192147
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2714012956
Short name T65
Test name
Test status
Simulation time 191781223 ps
CPU time 12.9 seconds
Started Aug 19 04:55:44 PM PDT 24
Finished Aug 19 04:55:57 PM PDT 24
Peak memory 248252 kb
Host smart-835aa9b2-0b38-448e-b31e-c4fe20b3572a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27140
12956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2714012956
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1912297250
Short name T35
Test name
Test status
Simulation time 2190742288 ps
CPU time 41.46 seconds
Started Aug 19 04:55:43 PM PDT 24
Finished Aug 19 04:56:25 PM PDT 24
Peak memory 257036 kb
Host smart-7f5f273d-471d-42ba-9fe6-a2ff1203e590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19122
97250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1912297250
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3986526975
Short name T281
Test name
Test status
Simulation time 13873572967 ps
CPU time 1308.9 seconds
Started Aug 19 04:55:44 PM PDT 24
Finished Aug 19 05:17:33 PM PDT 24
Peak memory 289644 kb
Host smart-a0a62690-e069-458b-93b2-5cbf99e81a2e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986526975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3986526975
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3959256730
Short name T257
Test name
Test status
Simulation time 4725353575 ps
CPU time 578.66 seconds
Started Aug 19 04:55:43 PM PDT 24
Finished Aug 19 05:05:22 PM PDT 24
Peak memory 273576 kb
Host smart-719f83d5-9fab-4ff6-bc39-3e9ef8ae405f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959256730 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3959256730
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1253226268
Short name T660
Test name
Test status
Simulation time 17461165780 ps
CPU time 637.09 seconds
Started Aug 19 04:55:44 PM PDT 24
Finished Aug 19 05:06:21 PM PDT 24
Peak memory 265224 kb
Host smart-73a3f892-4bad-4778-ad30-fd4cbcdd22cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253226268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1253226268
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2792299924
Short name T541
Test name
Test status
Simulation time 769051785 ps
CPU time 46.88 seconds
Started Aug 19 04:55:41 PM PDT 24
Finished Aug 19 04:56:28 PM PDT 24
Peak memory 256564 kb
Host smart-c42a8bb3-a691-4eb8-a33a-842f5e5a6f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27922
99924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2792299924
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2880721464
Short name T28
Test name
Test status
Simulation time 1056062940 ps
CPU time 22.1 seconds
Started Aug 19 04:55:44 PM PDT 24
Finished Aug 19 04:56:06 PM PDT 24
Peak memory 256812 kb
Host smart-5cbf2f5d-2fb9-431e-ba9d-cf185e0a4b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28807
21464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2880721464
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.249449888
Short name T335
Test name
Test status
Simulation time 104199601908 ps
CPU time 1677.34 seconds
Started Aug 19 04:55:55 PM PDT 24
Finished Aug 19 05:23:53 PM PDT 24
Peak memory 272604 kb
Host smart-54852e43-5a1a-4183-98eb-249533e69e29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249449888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.249449888
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1606677910
Short name T613
Test name
Test status
Simulation time 327862862779 ps
CPU time 2825.02 seconds
Started Aug 19 04:55:51 PM PDT 24
Finished Aug 19 05:42:56 PM PDT 24
Peak memory 287300 kb
Host smart-bd663c72-48b8-4d1c-a281-7824236a0bf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606677910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1606677910
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2563507557
Short name T623
Test name
Test status
Simulation time 1647517079 ps
CPU time 37.7 seconds
Started Aug 19 04:55:43 PM PDT 24
Finished Aug 19 04:56:21 PM PDT 24
Peak memory 248820 kb
Host smart-ba36f243-6ed1-4fd9-b7ec-d91af56cf30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25635
07557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2563507557
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1430744608
Short name T524
Test name
Test status
Simulation time 267397574 ps
CPU time 27.6 seconds
Started Aug 19 04:55:43 PM PDT 24
Finished Aug 19 04:56:11 PM PDT 24
Peak memory 248224 kb
Host smart-e3a50327-ea3b-4a7d-81fe-7634ecd26ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14307
44608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1430744608
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2917240656
Short name T260
Test name
Test status
Simulation time 1193181190 ps
CPU time 34.56 seconds
Started Aug 19 04:55:42 PM PDT 24
Finished Aug 19 04:56:17 PM PDT 24
Peak memory 248764 kb
Host smart-096486f7-2a34-4d47-8943-1f90800fef89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29172
40656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2917240656
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1862553390
Short name T557
Test name
Test status
Simulation time 1093981479 ps
CPU time 20.67 seconds
Started Aug 19 04:55:45 PM PDT 24
Finished Aug 19 04:56:06 PM PDT 24
Peak memory 248796 kb
Host smart-0f45be75-53e3-49ac-ac3a-2350d4903756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18625
53390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1862553390
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3331779248
Short name T61
Test name
Test status
Simulation time 23012893837 ps
CPU time 288.92 seconds
Started Aug 19 04:55:52 PM PDT 24
Finished Aug 19 05:00:41 PM PDT 24
Peak memory 268748 kb
Host smart-404321d4-4789-4214-aee6-3853878513eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331779248 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3331779248
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2357446736
Short name T105
Test name
Test status
Simulation time 44739231130 ps
CPU time 2614.7 seconds
Started Aug 19 04:55:56 PM PDT 24
Finished Aug 19 05:39:31 PM PDT 24
Peak memory 288872 kb
Host smart-a03a388c-6690-4c6f-9349-32cfa4140f07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357446736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2357446736
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2251384953
Short name T449
Test name
Test status
Simulation time 2556337474 ps
CPU time 140.9 seconds
Started Aug 19 04:55:54 PM PDT 24
Finished Aug 19 04:58:15 PM PDT 24
Peak memory 256204 kb
Host smart-5e1f12ef-694e-43b1-a5cd-d4676f673bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22513
84953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2251384953
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3032493539
Short name T493
Test name
Test status
Simulation time 512583384 ps
CPU time 32.03 seconds
Started Aug 19 04:55:55 PM PDT 24
Finished Aug 19 04:56:27 PM PDT 24
Peak memory 248604 kb
Host smart-b2200706-482f-492d-b1a8-1ae620139107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30324
93539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3032493539
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1906432967
Short name T316
Test name
Test status
Simulation time 32082681343 ps
CPU time 2059.32 seconds
Started Aug 19 04:55:52 PM PDT 24
Finished Aug 19 05:30:12 PM PDT 24
Peak memory 282816 kb
Host smart-77e3e611-77e0-49ea-9c51-736c640e9ac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906432967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1906432967
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4270077546
Short name T313
Test name
Test status
Simulation time 137523152716 ps
CPU time 2583.13 seconds
Started Aug 19 04:55:52 PM PDT 24
Finished Aug 19 05:38:55 PM PDT 24
Peak memory 289556 kb
Host smart-7b195a93-d960-473d-9736-e92213fad225
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270077546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4270077546
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1965544559
Short name T297
Test name
Test status
Simulation time 4490388700 ps
CPU time 183.58 seconds
Started Aug 19 04:55:51 PM PDT 24
Finished Aug 19 04:58:55 PM PDT 24
Peak memory 248844 kb
Host smart-69e7fe0e-fa0e-4397-9eb3-7dc7bd0950c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965544559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1965544559
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1914535700
Short name T431
Test name
Test status
Simulation time 409410996 ps
CPU time 14.25 seconds
Started Aug 19 04:55:54 PM PDT 24
Finished Aug 19 04:56:09 PM PDT 24
Peak memory 248712 kb
Host smart-fa95a86b-648e-49b2-a213-8e14837870de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19145
35700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1914535700
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.241427927
Short name T605
Test name
Test status
Simulation time 1766991556 ps
CPU time 38.54 seconds
Started Aug 19 04:55:54 PM PDT 24
Finished Aug 19 04:56:32 PM PDT 24
Peak memory 256936 kb
Host smart-4fe5a8a1-4ae6-428f-9441-8781a1424ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24142
7927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.241427927
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3543623311
Short name T224
Test name
Test status
Simulation time 161582514 ps
CPU time 10.22 seconds
Started Aug 19 04:55:51 PM PDT 24
Finished Aug 19 04:56:01 PM PDT 24
Peak memory 256260 kb
Host smart-d7ec3564-459f-4bfa-8b45-216d0a4cf66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35436
23311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3543623311
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2763746690
Short name T82
Test name
Test status
Simulation time 534261662 ps
CPU time 35.05 seconds
Started Aug 19 04:55:52 PM PDT 24
Finished Aug 19 04:56:27 PM PDT 24
Peak memory 256912 kb
Host smart-56bede2a-a431-4859-9a2c-30db38e4557d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27637
46690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2763746690
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3161357576
Short name T56
Test name
Test status
Simulation time 170834505217 ps
CPU time 3156.59 seconds
Started Aug 19 04:55:53 PM PDT 24
Finished Aug 19 05:48:30 PM PDT 24
Peak memory 289712 kb
Host smart-7fe9c7a1-753b-4447-a54f-0a5d954c9fdc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161357576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3161357576
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3904114378
Short name T615
Test name
Test status
Simulation time 99016271702 ps
CPU time 2920.21 seconds
Started Aug 19 04:55:56 PM PDT 24
Finished Aug 19 05:44:37 PM PDT 24
Peak memory 289724 kb
Host smart-43226295-b365-489d-a121-c92ac5730014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904114378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3904114378
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1304822999
Short name T363
Test name
Test status
Simulation time 8077575988 ps
CPU time 148.86 seconds
Started Aug 19 04:55:51 PM PDT 24
Finished Aug 19 04:58:20 PM PDT 24
Peak memory 255240 kb
Host smart-80179cbb-7883-495c-9edb-ab546f1bbfc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13048
22999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1304822999
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2802058501
Short name T713
Test name
Test status
Simulation time 299512806 ps
CPU time 20.41 seconds
Started Aug 19 04:55:52 PM PDT 24
Finished Aug 19 04:56:12 PM PDT 24
Peak memory 248268 kb
Host smart-4754a0ba-6037-465d-b560-e219bdaab4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28020
58501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2802058501
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1512845763
Short name T639
Test name
Test status
Simulation time 120598088846 ps
CPU time 1985.07 seconds
Started Aug 19 04:55:53 PM PDT 24
Finished Aug 19 05:28:59 PM PDT 24
Peak memory 273324 kb
Host smart-a25b0ad4-df38-45f1-89b5-d6ad2f2b4b63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512845763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1512845763
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2214426300
Short name T103
Test name
Test status
Simulation time 48559059292 ps
CPU time 1511.25 seconds
Started Aug 19 04:55:53 PM PDT 24
Finished Aug 19 05:21:05 PM PDT 24
Peak memory 273020 kb
Host smart-d4276a6d-4339-4684-baf6-210c5c7939c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214426300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2214426300
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2708317354
Short name T19
Test name
Test status
Simulation time 9976894998 ps
CPU time 226.65 seconds
Started Aug 19 04:55:51 PM PDT 24
Finished Aug 19 04:59:38 PM PDT 24
Peak memory 248832 kb
Host smart-e38f78b5-5ca2-439d-846f-be443bf91899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708317354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2708317354
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3310653421
Short name T462
Test name
Test status
Simulation time 813552823 ps
CPU time 28.5 seconds
Started Aug 19 04:55:53 PM PDT 24
Finished Aug 19 04:56:22 PM PDT 24
Peak memory 256224 kb
Host smart-d6ef6a3c-9f80-435e-b40b-5b5fdb037068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33106
53421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3310653421
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4279129456
Short name T86
Test name
Test status
Simulation time 1221219083 ps
CPU time 58.35 seconds
Started Aug 19 04:55:55 PM PDT 24
Finished Aug 19 04:56:54 PM PDT 24
Peak memory 248308 kb
Host smart-af59ab07-8ecf-47e8-b09f-894229e2889b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42791
29456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4279129456
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1836360003
Short name T412
Test name
Test status
Simulation time 1410934754 ps
CPU time 25.59 seconds
Started Aug 19 04:55:52 PM PDT 24
Finished Aug 19 04:56:18 PM PDT 24
Peak memory 256924 kb
Host smart-666ad5ac-6e24-4be4-93c3-4b050ca41deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18363
60003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1836360003
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.430060010
Short name T117
Test name
Test status
Simulation time 196608806231 ps
CPU time 2319.81 seconds
Started Aug 19 04:55:57 PM PDT 24
Finished Aug 19 05:34:37 PM PDT 24
Peak memory 285892 kb
Host smart-c6a2ed55-ff93-461c-9d5a-32181291cec1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430060010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.430060010
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2112501971
Short name T123
Test name
Test status
Simulation time 85383787077 ps
CPU time 2560.35 seconds
Started Aug 19 04:55:58 PM PDT 24
Finished Aug 19 05:38:38 PM PDT 24
Peak memory 289616 kb
Host smart-5bfdafbf-c788-4623-9f38-f1746c0ba2d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112501971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2112501971
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2962434187
Short name T625
Test name
Test status
Simulation time 28696596198 ps
CPU time 172.58 seconds
Started Aug 19 04:55:51 PM PDT 24
Finished Aug 19 04:58:44 PM PDT 24
Peak memory 256300 kb
Host smart-c2194cf8-2824-4803-8414-8cbe5c8ba8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29624
34187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2962434187
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.290498544
Short name T563
Test name
Test status
Simulation time 655220709 ps
CPU time 38.53 seconds
Started Aug 19 04:55:58 PM PDT 24
Finished Aug 19 04:56:37 PM PDT 24
Peak memory 256964 kb
Host smart-9a07486d-bc1d-4f41-9f7c-586f1926ff6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
8544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.290498544
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1771154752
Short name T234
Test name
Test status
Simulation time 33098843467 ps
CPU time 1927.52 seconds
Started Aug 19 04:55:52 PM PDT 24
Finished Aug 19 05:28:00 PM PDT 24
Peak memory 273428 kb
Host smart-8ea52d04-d5c1-4ba7-ab17-fee8d59cc10d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771154752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1771154752
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1171595637
Short name T567
Test name
Test status
Simulation time 28137753996 ps
CPU time 1613.34 seconds
Started Aug 19 04:55:53 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 273352 kb
Host smart-7cabc367-d479-45d4-a4a1-9723db128790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171595637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1171595637
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3031885543
Short name T299
Test name
Test status
Simulation time 40144966589 ps
CPU time 215.43 seconds
Started Aug 19 04:55:54 PM PDT 24
Finished Aug 19 04:59:30 PM PDT 24
Peak memory 248800 kb
Host smart-12a993fa-574c-499f-900d-a05c0b7bce49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031885543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3031885543
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1262599971
Short name T420
Test name
Test status
Simulation time 1299705616 ps
CPU time 76.74 seconds
Started Aug 19 04:55:54 PM PDT 24
Finished Aug 19 04:57:11 PM PDT 24
Peak memory 256868 kb
Host smart-20b9b516-50fa-468b-912d-efe463de4d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12625
99971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1262599971
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2770248787
Short name T676
Test name
Test status
Simulation time 72410270 ps
CPU time 9.78 seconds
Started Aug 19 04:55:56 PM PDT 24
Finished Aug 19 04:56:06 PM PDT 24
Peak memory 248128 kb
Host smart-34e9c3f9-b2d4-4bc9-9bef-237591680f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27702
48787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2770248787
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2759240484
Short name T653
Test name
Test status
Simulation time 448635659 ps
CPU time 33.1 seconds
Started Aug 19 04:55:55 PM PDT 24
Finished Aug 19 04:56:29 PM PDT 24
Peak memory 256960 kb
Host smart-ffe94cc5-577d-4b9b-9666-29d508ae330a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27592
40484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2759240484
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2520621120
Short name T76
Test name
Test status
Simulation time 13140600295 ps
CPU time 1314.22 seconds
Started Aug 19 04:55:57 PM PDT 24
Finished Aug 19 05:17:52 PM PDT 24
Peak memory 289240 kb
Host smart-cb7a0a8e-3a43-47a4-8158-09055cf0aef2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520621120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2520621120
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2004917625
Short name T240
Test name
Test status
Simulation time 11231024468 ps
CPU time 185.41 seconds
Started Aug 19 04:55:55 PM PDT 24
Finished Aug 19 04:59:01 PM PDT 24
Peak memory 265960 kb
Host smart-ac676120-8274-4480-adcd-891ac95d816b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004917625 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2004917625
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.295029653
Short name T558
Test name
Test status
Simulation time 25964964394 ps
CPU time 1640.29 seconds
Started Aug 19 04:56:04 PM PDT 24
Finished Aug 19 05:23:24 PM PDT 24
Peak memory 265248 kb
Host smart-e744fdf9-9924-4e6e-a39a-550b26061427
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295029653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.295029653
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2196183467
Short name T362
Test name
Test status
Simulation time 517282896 ps
CPU time 49.22 seconds
Started Aug 19 04:56:03 PM PDT 24
Finished Aug 19 04:56:52 PM PDT 24
Peak memory 256436 kb
Host smart-a7c1778c-e690-4c13-9326-39dc19c0ab1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
83467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2196183467
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.980933081
Short name T514
Test name
Test status
Simulation time 536620809 ps
CPU time 23.73 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 04:56:28 PM PDT 24
Peak memory 256880 kb
Host smart-f6ec0f70-840e-4e59-96ba-3495754408c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98093
3081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.980933081
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.926909220
Short name T343
Test name
Test status
Simulation time 149735631761 ps
CPU time 768.7 seconds
Started Aug 19 04:56:07 PM PDT 24
Finished Aug 19 05:08:55 PM PDT 24
Peak memory 273368 kb
Host smart-7e8f7add-b0f8-4884-96f5-09f2ed3cd9b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926909220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.926909220
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.128538516
Short name T119
Test name
Test status
Simulation time 211766402705 ps
CPU time 2099.14 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 05:31:05 PM PDT 24
Peak memory 273116 kb
Host smart-b2545dd1-2716-4cc0-863c-75761c1f4d2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128538516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.128538516
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3950489100
Short name T227
Test name
Test status
Simulation time 13672659905 ps
CPU time 147.95 seconds
Started Aug 19 04:56:03 PM PDT 24
Finished Aug 19 04:58:31 PM PDT 24
Peak memory 255512 kb
Host smart-0cd589e6-08e8-4b58-a11a-64faa300e620
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950489100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3950489100
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2648592006
Short name T96
Test name
Test status
Simulation time 3471331740 ps
CPU time 61.53 seconds
Started Aug 19 04:55:53 PM PDT 24
Finished Aug 19 04:56:55 PM PDT 24
Peak memory 256272 kb
Host smart-e983eeff-b87e-4b92-8e9a-5dce7fea70a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26485
92006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2648592006
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.495784691
Short name T383
Test name
Test status
Simulation time 599909158 ps
CPU time 13 seconds
Started Aug 19 04:56:03 PM PDT 24
Finished Aug 19 04:56:16 PM PDT 24
Peak memory 248340 kb
Host smart-40ee35ff-8805-4df7-8980-2ae80cacf1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49578
4691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.495784691
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.587509831
Short name T511
Test name
Test status
Simulation time 557051385 ps
CPU time 28.94 seconds
Started Aug 19 04:56:08 PM PDT 24
Finished Aug 19 04:56:37 PM PDT 24
Peak memory 248188 kb
Host smart-96568dec-262b-445f-b6e3-88ef16498439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58750
9831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.587509831
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2386460576
Short name T85
Test name
Test status
Simulation time 611584259 ps
CPU time 19.17 seconds
Started Aug 19 04:55:56 PM PDT 24
Finished Aug 19 04:56:15 PM PDT 24
Peak memory 255440 kb
Host smart-ffc2b942-ba52-4d5c-9bd5-d8f83aa389d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23864
60576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2386460576
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2046823414
Short name T542
Test name
Test status
Simulation time 165489836650 ps
CPU time 1188.19 seconds
Started Aug 19 04:56:07 PM PDT 24
Finished Aug 19 05:15:56 PM PDT 24
Peak memory 281576 kb
Host smart-4c3fd12d-fc05-4873-a3dd-ee4ae4d6afe6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046823414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2046823414
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1696458814
Short name T621
Test name
Test status
Simulation time 1539864678 ps
CPU time 50.74 seconds
Started Aug 19 04:56:02 PM PDT 24
Finished Aug 19 04:56:53 PM PDT 24
Peak memory 256276 kb
Host smart-b7be8445-5e34-4310-b7d7-a7768b37156a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16964
58814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1696458814
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4079307290
Short name T577
Test name
Test status
Simulation time 360825224 ps
CPU time 13.4 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 04:56:18 PM PDT 24
Peak memory 248356 kb
Host smart-f8ee4558-f578-4791-9ef2-162f70e51b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40793
07290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4079307290
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3917580967
Short name T331
Test name
Test status
Simulation time 105373919829 ps
CPU time 2868.02 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 05:43:54 PM PDT 24
Peak memory 281552 kb
Host smart-b832a5fb-8d99-44a9-a068-559531375ee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917580967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3917580967
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2703488662
Short name T235
Test name
Test status
Simulation time 39613086511 ps
CPU time 2267.3 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 05:33:53 PM PDT 24
Peak memory 286596 kb
Host smart-ffd49016-b5f5-441b-9682-48b9c5385605
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703488662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2703488662
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.596803888
Short name T300
Test name
Test status
Simulation time 2699906644 ps
CPU time 109.78 seconds
Started Aug 19 04:56:04 PM PDT 24
Finished Aug 19 04:57:54 PM PDT 24
Peak memory 248680 kb
Host smart-c1bdb984-ed27-4e6d-9f15-60d841676d52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596803888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.596803888
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3816057627
Short name T398
Test name
Test status
Simulation time 1815928408 ps
CPU time 27.19 seconds
Started Aug 19 04:56:04 PM PDT 24
Finished Aug 19 04:56:31 PM PDT 24
Peak memory 256588 kb
Host smart-18b6d4c3-28a9-4681-bffd-196640627ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38160
57627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3816057627
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1209625965
Short name T532
Test name
Test status
Simulation time 215241100 ps
CPU time 25.2 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 04:56:30 PM PDT 24
Peak memory 248188 kb
Host smart-6c17bc12-2426-49e9-b9fb-bb0674a1255e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12096
25965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1209625965
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1795881167
Short name T268
Test name
Test status
Simulation time 132075098 ps
CPU time 8.11 seconds
Started Aug 19 04:56:02 PM PDT 24
Finished Aug 19 04:56:11 PM PDT 24
Peak memory 248796 kb
Host smart-493960da-9181-450d-986c-5f932ded3244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17958
81167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1795881167
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2198898924
Short name T489
Test name
Test status
Simulation time 1134761469 ps
CPU time 18.62 seconds
Started Aug 19 04:56:06 PM PDT 24
Finished Aug 19 04:56:25 PM PDT 24
Peak memory 256776 kb
Host smart-e5b180b1-274b-441e-97c5-02da06fa5c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21988
98924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2198898924
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2420205002
Short name T64
Test name
Test status
Simulation time 7623825313 ps
CPU time 148.45 seconds
Started Aug 19 04:56:04 PM PDT 24
Finished Aug 19 04:58:33 PM PDT 24
Peak memory 273048 kb
Host smart-81c01528-f43e-4c16-a403-9910ee81e0a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420205002 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2420205002
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2135818745
Short name T207
Test name
Test status
Simulation time 77764738 ps
CPU time 3.56 seconds
Started Aug 19 04:54:19 PM PDT 24
Finished Aug 19 04:54:23 PM PDT 24
Peak memory 248996 kb
Host smart-a4e5547d-63bb-40bd-af71-59e4780d9f9c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2135818745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2135818745
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1245494557
Short name T569
Test name
Test status
Simulation time 17915169694 ps
CPU time 1380.82 seconds
Started Aug 19 04:54:27 PM PDT 24
Finished Aug 19 05:17:28 PM PDT 24
Peak memory 289280 kb
Host smart-a514b51e-a1c9-43eb-bf5f-c82effbb901b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245494557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1245494557
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2739907098
Short name T229
Test name
Test status
Simulation time 1998841611 ps
CPU time 40.81 seconds
Started Aug 19 04:54:17 PM PDT 24
Finished Aug 19 04:54:58 PM PDT 24
Peak memory 248784 kb
Host smart-9eb33b09-3e7d-46b3-b96b-ac9e16a1e585
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2739907098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2739907098
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.4206575727
Short name T390
Test name
Test status
Simulation time 4784539696 ps
CPU time 76.04 seconds
Started Aug 19 04:54:19 PM PDT 24
Finished Aug 19 04:55:35 PM PDT 24
Peak memory 257044 kb
Host smart-4035923d-2514-49a8-93f9-53c879597953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42065
75727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4206575727
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.4256965719
Short name T665
Test name
Test status
Simulation time 71606643 ps
CPU time 5.39 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 04:54:26 PM PDT 24
Peak memory 240708 kb
Host smart-7b9c0fbd-e5c2-4fda-8d38-0b31624cabf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42569
65719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.4256965719
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2284375862
Short name T326
Test name
Test status
Simulation time 35736992868 ps
CPU time 1083.67 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 05:12:25 PM PDT 24
Peak memory 265268 kb
Host smart-a6ee8cca-29b4-4c67-b67f-2133bd49bfd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284375862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2284375862
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1908381741
Short name T99
Test name
Test status
Simulation time 118596013433 ps
CPU time 1533.96 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 05:20:05 PM PDT 24
Peak memory 272672 kb
Host smart-a8e40e17-79cc-4306-8d14-8a8b1e977737
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908381741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1908381741
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3783789045
Short name T636
Test name
Test status
Simulation time 4797214063 ps
CPU time 188.05 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 04:57:29 PM PDT 24
Peak memory 247888 kb
Host smart-b07b2f3f-e99f-47c4-862c-6c18648349cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783789045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3783789045
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3042892650
Short name T666
Test name
Test status
Simulation time 601895428 ps
CPU time 36.85 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 04:54:59 PM PDT 24
Peak memory 256168 kb
Host smart-4405eb28-43dd-4a80-a7dd-230a1448b86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30428
92650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3042892650
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2772958443
Short name T60
Test name
Test status
Simulation time 504995025 ps
CPU time 36.75 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 04:54:59 PM PDT 24
Peak memory 256600 kb
Host smart-4150832d-1746-4de7-8e0d-692e74f871aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27729
58443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2772958443
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3325063401
Short name T41
Test name
Test status
Simulation time 579137222 ps
CPU time 29.43 seconds
Started Aug 19 04:54:19 PM PDT 24
Finished Aug 19 04:54:49 PM PDT 24
Peak memory 271072 kb
Host smart-eec7db8b-45e7-4cd8-88c9-2eeae1dfeccd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3325063401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3325063401
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2472046353
Short name T585
Test name
Test status
Simulation time 912176696 ps
CPU time 47.17 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:55:18 PM PDT 24
Peak memory 256024 kb
Host smart-c9083973-9b79-4665-8962-d58a32993639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24720
46353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2472046353
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.100088931
Short name T308
Test name
Test status
Simulation time 2959742419 ps
CPU time 46.15 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:55:06 PM PDT 24
Peak memory 256984 kb
Host smart-fd28ffac-da37-4c4a-8935-1a3079b0cbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10008
8931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.100088931
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3158369363
Short name T432
Test name
Test status
Simulation time 74106403546 ps
CPU time 1520.23 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 05:19:42 PM PDT 24
Peak memory 289668 kb
Host smart-13e4b09d-2784-43e1-b492-d1bea48d4ffa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158369363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3158369363
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1749821863
Short name T108
Test name
Test status
Simulation time 43885894092 ps
CPU time 223.66 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 04:58:05 PM PDT 24
Peak memory 268144 kb
Host smart-2929ea80-f42d-4e13-b41b-a8d0449fe785
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749821863 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1749821863
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2449071561
Short name T456
Test name
Test status
Simulation time 43702726667 ps
CPU time 1061.89 seconds
Started Aug 19 04:56:04 PM PDT 24
Finished Aug 19 05:13:47 PM PDT 24
Peak memory 273140 kb
Host smart-1834708c-005b-4f0a-809a-6ecff9cd94ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449071561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2449071561
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.53001800
Short name T309
Test name
Test status
Simulation time 3355372415 ps
CPU time 105.72 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 04:57:51 PM PDT 24
Peak memory 256384 kb
Host smart-dc63e36b-b18f-4145-86c7-97ec0263966d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53001
800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.53001800
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.4210198771
Short name T427
Test name
Test status
Simulation time 1850389097 ps
CPU time 43.18 seconds
Started Aug 19 04:56:03 PM PDT 24
Finished Aug 19 04:56:46 PM PDT 24
Peak memory 248716 kb
Host smart-f839d034-4f18-486a-93e6-52322e6a99eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42101
98771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4210198771
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.190204890
Short name T664
Test name
Test status
Simulation time 38799526928 ps
CPU time 2492.78 seconds
Started Aug 19 04:56:03 PM PDT 24
Finished Aug 19 05:37:36 PM PDT 24
Peak memory 289612 kb
Host smart-e587a44a-3588-45d0-935a-7ec7cac80e77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190204890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.190204890
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2454578364
Short name T21
Test name
Test status
Simulation time 21594054985 ps
CPU time 1389.92 seconds
Started Aug 19 04:56:04 PM PDT 24
Finished Aug 19 05:19:14 PM PDT 24
Peak memory 286700 kb
Host smart-9c2f0e66-c793-4119-a107-28ffbc785b30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454578364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2454578364
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2460843305
Short name T657
Test name
Test status
Simulation time 70546580536 ps
CPU time 441.52 seconds
Started Aug 19 04:56:08 PM PDT 24
Finished Aug 19 05:03:30 PM PDT 24
Peak memory 247752 kb
Host smart-baebf712-8f3a-4c9c-ae92-490b30361d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460843305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2460843305
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.532969565
Short name T679
Test name
Test status
Simulation time 892792105 ps
CPU time 51.47 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 04:56:57 PM PDT 24
Peak memory 256024 kb
Host smart-b8e6062a-dbd8-4f31-b2d1-3b2ae14ee1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53296
9565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.532969565
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2111301508
Short name T496
Test name
Test status
Simulation time 4415340164 ps
CPU time 70.38 seconds
Started Aug 19 04:56:03 PM PDT 24
Finished Aug 19 04:57:14 PM PDT 24
Peak memory 249920 kb
Host smart-34d39570-5ebb-4b99-b8fc-42482cca8ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21113
01508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2111301508
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3791682775
Short name T458
Test name
Test status
Simulation time 546950306 ps
CPU time 8.87 seconds
Started Aug 19 04:56:03 PM PDT 24
Finished Aug 19 04:56:12 PM PDT 24
Peak memory 255660 kb
Host smart-c3e5871b-5b49-4247-9994-03664a4ce6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916
82775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3791682775
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2894682775
Short name T631
Test name
Test status
Simulation time 2047772480 ps
CPU time 39.54 seconds
Started Aug 19 04:56:04 PM PDT 24
Finished Aug 19 04:56:44 PM PDT 24
Peak memory 248732 kb
Host smart-934835de-035e-4cfb-8e82-4f04ef8ee544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28946
82775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2894682775
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1627759698
Short name T120
Test name
Test status
Simulation time 10701099278 ps
CPU time 1025.31 seconds
Started Aug 19 04:56:03 PM PDT 24
Finished Aug 19 05:13:08 PM PDT 24
Peak memory 285128 kb
Host smart-685db0a3-a73c-4e9d-9cb4-2ae50414ef61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627759698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1627759698
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.684854230
Short name T543
Test name
Test status
Simulation time 6306535937 ps
CPU time 440.72 seconds
Started Aug 19 04:56:06 PM PDT 24
Finished Aug 19 05:03:27 PM PDT 24
Peak memory 267396 kb
Host smart-909e6a5c-3360-4b2c-b6d5-3ea0db9d6aac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684854230 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.684854230
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1855553334
Short name T562
Test name
Test status
Simulation time 9122249875 ps
CPU time 1255.7 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 05:17:12 PM PDT 24
Peak memory 289172 kb
Host smart-89ae81c0-c884-4706-a3c0-712e34224d96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855553334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1855553334
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1223348366
Short name T695
Test name
Test status
Simulation time 2645006862 ps
CPU time 141.17 seconds
Started Aug 19 04:56:06 PM PDT 24
Finished Aug 19 04:58:27 PM PDT 24
Peak memory 257072 kb
Host smart-0f5f3744-4732-4a7a-be98-dc01c91bc515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12233
48366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1223348366
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2050107966
Short name T626
Test name
Test status
Simulation time 1455400509 ps
CPU time 48.73 seconds
Started Aug 19 04:56:05 PM PDT 24
Finished Aug 19 04:56:54 PM PDT 24
Peak memory 256348 kb
Host smart-acbfd621-bd00-486f-9f87-767a876c1af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20501
07966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2050107966
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3126550931
Short name T273
Test name
Test status
Simulation time 22481333536 ps
CPU time 1761.92 seconds
Started Aug 19 04:56:15 PM PDT 24
Finished Aug 19 05:25:37 PM PDT 24
Peak memory 289836 kb
Host smart-eceb4de5-9113-4225-8693-5d883943382d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126550931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3126550931
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.4159538123
Short name T635
Test name
Test status
Simulation time 34185046980 ps
CPU time 475.12 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 05:04:11 PM PDT 24
Peak memory 255532 kb
Host smart-361e3b2f-b280-4870-b3ea-e1de68661113
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159538123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.4159538123
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.320325708
Short name T512
Test name
Test status
Simulation time 812116562 ps
CPU time 43.2 seconds
Started Aug 19 04:56:06 PM PDT 24
Finished Aug 19 04:56:49 PM PDT 24
Peak memory 256592 kb
Host smart-b53b7e40-f0e1-4d6d-aa5b-fc92e780d143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32032
5708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.320325708
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4014035642
Short name T702
Test name
Test status
Simulation time 742830234 ps
CPU time 49.73 seconds
Started Aug 19 04:56:04 PM PDT 24
Finished Aug 19 04:56:54 PM PDT 24
Peak memory 248336 kb
Host smart-206f6ff6-ad82-40b9-b74a-27ffbbc9588a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40140
35642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4014035642
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.428604747
Short name T550
Test name
Test status
Simulation time 205482295 ps
CPU time 14.44 seconds
Started Aug 19 04:56:03 PM PDT 24
Finished Aug 19 04:56:18 PM PDT 24
Peak memory 255416 kb
Host smart-66653425-5e07-4965-b345-d0e173fe53e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42860
4747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.428604747
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3858404254
Short name T667
Test name
Test status
Simulation time 26333441970 ps
CPU time 1484.67 seconds
Started Aug 19 04:56:15 PM PDT 24
Finished Aug 19 05:21:00 PM PDT 24
Peak memory 289768 kb
Host smart-59445f4d-04ad-44fb-9dc1-b72494ccc73e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858404254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3858404254
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1662645018
Short name T690
Test name
Test status
Simulation time 111224300377 ps
CPU time 1826.21 seconds
Started Aug 19 04:56:15 PM PDT 24
Finished Aug 19 05:26:42 PM PDT 24
Peak memory 272824 kb
Host smart-f565464a-8b6e-49ab-be29-7ec76f35809f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662645018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1662645018
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1168462457
Short name T366
Test name
Test status
Simulation time 4620714262 ps
CPU time 113.41 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 04:58:09 PM PDT 24
Peak memory 251048 kb
Host smart-028a6e1d-1baa-46f6-a4c4-2705c11aab05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11684
62457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1168462457
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3706344017
Short name T91
Test name
Test status
Simulation time 3387432393 ps
CPU time 50.31 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 04:57:06 PM PDT 24
Peak memory 248764 kb
Host smart-382a64e7-2418-45e7-ab7e-d1e6213ef683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37063
44017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3706344017
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2372454305
Short name T22
Test name
Test status
Simulation time 11597185490 ps
CPU time 1155.13 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 05:15:32 PM PDT 24
Peak memory 289148 kb
Host smart-081bc941-c40c-4556-942a-c8be4221067d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372454305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2372454305
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3483026254
Short name T20
Test name
Test status
Simulation time 15945567946 ps
CPU time 163.1 seconds
Started Aug 19 04:56:15 PM PDT 24
Finished Aug 19 04:58:58 PM PDT 24
Peak memory 248696 kb
Host smart-850f9867-281d-4f4e-9176-bae65fdcb53f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483026254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3483026254
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.448781836
Short name T552
Test name
Test status
Simulation time 326119028 ps
CPU time 32.58 seconds
Started Aug 19 04:56:19 PM PDT 24
Finished Aug 19 04:56:51 PM PDT 24
Peak memory 248784 kb
Host smart-978adb5c-ec2f-4e98-af12-be96bdaa7ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44878
1836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.448781836
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.570536955
Short name T15
Test name
Test status
Simulation time 419750859 ps
CPU time 24.86 seconds
Started Aug 19 04:56:18 PM PDT 24
Finished Aug 19 04:56:43 PM PDT 24
Peak memory 256440 kb
Host smart-e903df6b-1239-480a-a882-a82600be36c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57053
6955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.570536955
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2148778816
Short name T650
Test name
Test status
Simulation time 202478797 ps
CPU time 22.64 seconds
Started Aug 19 04:56:15 PM PDT 24
Finished Aug 19 04:56:38 PM PDT 24
Peak memory 248816 kb
Host smart-252fc986-c39d-47dd-9c20-31b22f2338a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21487
78816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2148778816
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3413180342
Short name T518
Test name
Test status
Simulation time 211305350 ps
CPU time 21.78 seconds
Started Aug 19 04:56:15 PM PDT 24
Finished Aug 19 04:56:37 PM PDT 24
Peak memory 256944 kb
Host smart-b0bda4b9-c302-46c6-af08-9b57d25f353d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34131
80342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3413180342
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2076304642
Short name T554
Test name
Test status
Simulation time 4404602190 ps
CPU time 546.7 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 05:05:23 PM PDT 24
Peak memory 270396 kb
Host smart-768c6e4d-4964-4916-89bc-b4c257ac66bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076304642 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2076304642
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2684438860
Short name T651
Test name
Test status
Simulation time 5723301296 ps
CPU time 527.66 seconds
Started Aug 19 04:56:32 PM PDT 24
Finished Aug 19 05:05:20 PM PDT 24
Peak memory 273428 kb
Host smart-8a3bf168-25b3-4ff8-9683-f110e55c4d86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684438860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2684438860
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.326288630
Short name T575
Test name
Test status
Simulation time 5076893897 ps
CPU time 64.06 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 04:57:20 PM PDT 24
Peak memory 256580 kb
Host smart-b3c2841e-871d-4040-a25e-64a29b364cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32628
8630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.326288630
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3981854158
Short name T526
Test name
Test status
Simulation time 1550783150 ps
CPU time 18.86 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 04:56:35 PM PDT 24
Peak memory 248748 kb
Host smart-d8f8e836-7815-49e5-abb1-fda94e5298fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
54158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3981854158
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1781383731
Short name T609
Test name
Test status
Simulation time 30878567060 ps
CPU time 1373.52 seconds
Started Aug 19 04:56:31 PM PDT 24
Finished Aug 19 05:19:25 PM PDT 24
Peak memory 288952 kb
Host smart-b3b0544c-94b1-465b-a1d0-ec4cc88872aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781383731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1781383731
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3595480322
Short name T293
Test name
Test status
Simulation time 46821685457 ps
CPU time 514.56 seconds
Started Aug 19 04:56:31 PM PDT 24
Finished Aug 19 05:05:06 PM PDT 24
Peak memory 248732 kb
Host smart-82046792-76b4-4865-b514-30ad9cb2a8ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595480322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3595480322
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2254337991
Short name T648
Test name
Test status
Simulation time 842861110 ps
CPU time 23.49 seconds
Started Aug 19 04:56:17 PM PDT 24
Finished Aug 19 04:56:41 PM PDT 24
Peak memory 248720 kb
Host smart-20e96885-ead4-439b-8527-60a12c10a1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22543
37991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2254337991
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2358848283
Short name T578
Test name
Test status
Simulation time 1200710112 ps
CPU time 39.62 seconds
Started Aug 19 04:56:15 PM PDT 24
Finished Aug 19 04:56:55 PM PDT 24
Peak memory 256496 kb
Host smart-34e29c46-2a54-4c77-942f-1b4b69d652bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23588
48283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2358848283
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.111109791
Short name T443
Test name
Test status
Simulation time 330143559 ps
CPU time 6.75 seconds
Started Aug 19 04:56:16 PM PDT 24
Finished Aug 19 04:56:23 PM PDT 24
Peak memory 251176 kb
Host smart-32b460f1-d7c4-40a5-9a45-33aa34f021ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11110
9791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.111109791
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4059678224
Short name T72
Test name
Test status
Simulation time 3105449590 ps
CPU time 47.05 seconds
Started Aug 19 04:56:15 PM PDT 24
Finished Aug 19 04:57:03 PM PDT 24
Peak memory 256988 kb
Host smart-f75a4f3d-9f29-4094-bc9a-359395ec59d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40596
78224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4059678224
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3910653068
Short name T472
Test name
Test status
Simulation time 1719892537 ps
CPU time 116.68 seconds
Started Aug 19 04:56:30 PM PDT 24
Finished Aug 19 04:58:27 PM PDT 24
Peak memory 257004 kb
Host smart-2aced573-e261-4396-9fb3-8fd502d7815a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910653068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3910653068
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.273800318
Short name T111
Test name
Test status
Simulation time 3712954963 ps
CPU time 443.01 seconds
Started Aug 19 04:56:33 PM PDT 24
Finished Aug 19 05:03:57 PM PDT 24
Peak memory 269852 kb
Host smart-72b29498-70e6-4b42-8d62-79bef1f7870e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273800318 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.273800318
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2721359103
Short name T548
Test name
Test status
Simulation time 34286956001 ps
CPU time 2074.21 seconds
Started Aug 19 04:56:33 PM PDT 24
Finished Aug 19 05:31:07 PM PDT 24
Peak memory 288988 kb
Host smart-83b6b857-04b1-4700-92b9-5adf54138fcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721359103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2721359103
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2204461795
Short name T403
Test name
Test status
Simulation time 1087539912 ps
CPU time 54.08 seconds
Started Aug 19 04:56:30 PM PDT 24
Finished Aug 19 04:57:24 PM PDT 24
Peak memory 256888 kb
Host smart-56751409-43d5-41b0-bc96-e80cd28c7114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044
61795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2204461795
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2693991587
Short name T410
Test name
Test status
Simulation time 2361970152 ps
CPU time 72.81 seconds
Started Aug 19 04:56:31 PM PDT 24
Finished Aug 19 04:57:44 PM PDT 24
Peak memory 248008 kb
Host smart-ecfabe16-df6f-4f2e-9839-49adabcd7356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26939
91587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2693991587
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2898336877
Short name T341
Test name
Test status
Simulation time 16063079156 ps
CPU time 1343.63 seconds
Started Aug 19 04:56:32 PM PDT 24
Finished Aug 19 05:18:55 PM PDT 24
Peak memory 289132 kb
Host smart-a0fb463f-40ef-4de2-a514-d0007aadda67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898336877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2898336877
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2927211818
Short name T480
Test name
Test status
Simulation time 167497950446 ps
CPU time 3006.76 seconds
Started Aug 19 04:56:32 PM PDT 24
Finished Aug 19 05:46:39 PM PDT 24
Peak memory 286620 kb
Host smart-99565708-88f2-408e-9e52-0c38a2c25e58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927211818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2927211818
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3519361320
Short name T285
Test name
Test status
Simulation time 20567016549 ps
CPU time 219.67 seconds
Started Aug 19 04:56:34 PM PDT 24
Finished Aug 19 05:00:14 PM PDT 24
Peak memory 255376 kb
Host smart-fff09308-b56c-43e6-8035-bb3d585ed3a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519361320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3519361320
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1763010646
Short name T487
Test name
Test status
Simulation time 271991499 ps
CPU time 5.16 seconds
Started Aug 19 04:56:31 PM PDT 24
Finished Aug 19 04:56:36 PM PDT 24
Peak memory 248792 kb
Host smart-1ed1b1e2-c1c5-406a-9e64-ea2ee93213bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17630
10646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1763010646
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.24528434
Short name T670
Test name
Test status
Simulation time 353927393 ps
CPU time 38.21 seconds
Started Aug 19 04:56:31 PM PDT 24
Finished Aug 19 04:57:09 PM PDT 24
Peak memory 248300 kb
Host smart-b66a4e55-bbce-4756-8b1a-24f44c509a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24528
434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.24528434
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3750950708
Short name T388
Test name
Test status
Simulation time 1206631747 ps
CPU time 32.42 seconds
Started Aug 19 04:56:32 PM PDT 24
Finished Aug 19 04:57:05 PM PDT 24
Peak memory 256928 kb
Host smart-e826f6ae-e4be-4bf7-9a34-5398630a2b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37509
50708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3750950708
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2980536505
Short name T545
Test name
Test status
Simulation time 18185458007 ps
CPU time 294.36 seconds
Started Aug 19 04:56:33 PM PDT 24
Finished Aug 19 05:01:28 PM PDT 24
Peak memory 257004 kb
Host smart-4752f678-6a30-48cb-a9e3-a3b1b74a9171
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980536505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2980536505
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3286331430
Short name T242
Test name
Test status
Simulation time 2425879343 ps
CPU time 161.22 seconds
Started Aug 19 04:56:34 PM PDT 24
Finished Aug 19 04:59:15 PM PDT 24
Peak memory 265788 kb
Host smart-45d06f6e-b1a1-4bea-8ff6-920230e36bb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286331430 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3286331430
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3266297235
Short name T560
Test name
Test status
Simulation time 57229402149 ps
CPU time 1389.18 seconds
Started Aug 19 04:56:34 PM PDT 24
Finished Aug 19 05:19:43 PM PDT 24
Peak memory 273048 kb
Host smart-433cf81e-109d-46f3-a53c-9a0551519d44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266297235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3266297235
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.4004313266
Short name T551
Test name
Test status
Simulation time 2389310531 ps
CPU time 60.16 seconds
Started Aug 19 04:56:33 PM PDT 24
Finished Aug 19 04:57:33 PM PDT 24
Peak memory 256564 kb
Host smart-974aad65-c09b-4567-9ede-038799932998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40043
13266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.4004313266
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3956565638
Short name T223
Test name
Test status
Simulation time 141580412 ps
CPU time 6.22 seconds
Started Aug 19 04:56:34 PM PDT 24
Finished Aug 19 04:56:41 PM PDT 24
Peak memory 254256 kb
Host smart-03d38060-86b2-4d3d-8b3b-ca9dae616f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39565
65638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3956565638
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.320600994
Short name T675
Test name
Test status
Simulation time 33043340672 ps
CPU time 1891.98 seconds
Started Aug 19 04:56:34 PM PDT 24
Finished Aug 19 05:28:06 PM PDT 24
Peak memory 273460 kb
Host smart-7e9940a9-2587-4df6-8920-59b42ad8a1a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320600994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.320600994
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3110957470
Short name T444
Test name
Test status
Simulation time 5817904767 ps
CPU time 564.79 seconds
Started Aug 19 04:56:36 PM PDT 24
Finished Aug 19 05:06:01 PM PDT 24
Peak memory 273320 kb
Host smart-cd263e62-d74b-49d7-aefd-819e336201f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110957470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3110957470
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3342018960
Short name T294
Test name
Test status
Simulation time 44712029543 ps
CPU time 452.96 seconds
Started Aug 19 04:56:34 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 248720 kb
Host smart-f797437d-4869-49f9-8b8c-9f3028f22816
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342018960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3342018960
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3732934114
Short name T436
Test name
Test status
Simulation time 2685020349 ps
CPU time 55.04 seconds
Started Aug 19 04:56:33 PM PDT 24
Finished Aug 19 04:57:28 PM PDT 24
Peak memory 256968 kb
Host smart-da182dce-d2b1-4869-8a73-53ba686a21e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37329
34114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3732934114
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2996991815
Short name T492
Test name
Test status
Simulation time 1411471279 ps
CPU time 35.58 seconds
Started Aug 19 04:56:31 PM PDT 24
Finished Aug 19 04:57:07 PM PDT 24
Peak memory 256404 kb
Host smart-67aea935-c186-4d21-8963-0be273bb7733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29969
91815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2996991815
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.776149084
Short name T122
Test name
Test status
Simulation time 292053567 ps
CPU time 31.33 seconds
Started Aug 19 04:56:36 PM PDT 24
Finished Aug 19 04:57:08 PM PDT 24
Peak memory 249876 kb
Host smart-e0208de6-fac3-4e10-ae35-bf325e109ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77614
9084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.776149084
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2875525511
Short name T77
Test name
Test status
Simulation time 839354738 ps
CPU time 60.77 seconds
Started Aug 19 04:56:32 PM PDT 24
Finished Aug 19 04:57:33 PM PDT 24
Peak memory 256936 kb
Host smart-cba79083-ebb2-49f5-86ae-4572654f4f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
25511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2875525511
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3007616326
Short name T581
Test name
Test status
Simulation time 31208845062 ps
CPU time 493.23 seconds
Started Aug 19 04:56:35 PM PDT 24
Finished Aug 19 05:04:49 PM PDT 24
Peak memory 256992 kb
Host smart-871536b7-71d3-4582-b9eb-230f6c53ab88
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007616326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3007616326
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1699730940
Short name T408
Test name
Test status
Simulation time 11578279273 ps
CPU time 1427.22 seconds
Started Aug 19 04:56:37 PM PDT 24
Finished Aug 19 05:20:25 PM PDT 24
Peak memory 289408 kb
Host smart-d95bb493-32aa-4d54-9ae3-b65023a9d37c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699730940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1699730940
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3462838728
Short name T385
Test name
Test status
Simulation time 3705397428 ps
CPU time 155.58 seconds
Started Aug 19 04:56:36 PM PDT 24
Finished Aug 19 04:59:12 PM PDT 24
Peak memory 257052 kb
Host smart-40715fd2-e85a-4204-98e6-23bb4dccdf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34628
38728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3462838728
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.481060322
Short name T94
Test name
Test status
Simulation time 1850429260 ps
CPU time 44.56 seconds
Started Aug 19 04:56:34 PM PDT 24
Finished Aug 19 04:57:19 PM PDT 24
Peak memory 255680 kb
Host smart-0b9d58d1-8e9a-4dfd-aa6c-63b3b92f75af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48106
0322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.481060322
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1722780402
Short name T345
Test name
Test status
Simulation time 38113835454 ps
CPU time 842.19 seconds
Started Aug 19 04:56:36 PM PDT 24
Finished Aug 19 05:10:38 PM PDT 24
Peak memory 272604 kb
Host smart-48e613bb-b58b-4356-8387-913ab9a27d0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722780402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1722780402
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3127872854
Short name T376
Test name
Test status
Simulation time 132256733864 ps
CPU time 2005.52 seconds
Started Aug 19 04:56:50 PM PDT 24
Finished Aug 19 05:30:15 PM PDT 24
Peak memory 273444 kb
Host smart-844da462-3779-458b-8e87-aaa5b0089cf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127872854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3127872854
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3545635489
Short name T696
Test name
Test status
Simulation time 216310280 ps
CPU time 22.87 seconds
Started Aug 19 04:56:36 PM PDT 24
Finished Aug 19 04:56:59 PM PDT 24
Peak memory 256268 kb
Host smart-7483e52a-b814-47f6-a5ee-0159fd37ccd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35456
35489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3545635489
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1841951229
Short name T539
Test name
Test status
Simulation time 117187521 ps
CPU time 4.77 seconds
Started Aug 19 04:56:35 PM PDT 24
Finished Aug 19 04:56:40 PM PDT 24
Peak memory 251296 kb
Host smart-60f301e9-39e8-4498-b87c-511b6037a81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18419
51229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1841951229
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3540904159
Short name T253
Test name
Test status
Simulation time 2035273159 ps
CPU time 69.92 seconds
Started Aug 19 04:56:36 PM PDT 24
Finished Aug 19 04:57:46 PM PDT 24
Peak memory 256940 kb
Host smart-28af04df-fb31-4cd9-911d-b5ec061efdbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35409
04159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3540904159
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2328640550
Short name T369
Test name
Test status
Simulation time 350106659 ps
CPU time 33.14 seconds
Started Aug 19 04:56:36 PM PDT 24
Finished Aug 19 04:57:09 PM PDT 24
Peak memory 256872 kb
Host smart-3e00aaa6-06fc-4e5c-9534-4572b46e3db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
40550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2328640550
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.869699246
Short name T67
Test name
Test status
Simulation time 182548829805 ps
CPU time 1714.63 seconds
Started Aug 19 04:56:43 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 289740 kb
Host smart-82e8bb5c-7f8f-4380-94a0-a0095c4b92f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869699246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.869699246
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3687032241
Short name T53
Test name
Test status
Simulation time 45635332061 ps
CPU time 1130.1 seconds
Started Aug 19 04:56:43 PM PDT 24
Finished Aug 19 05:15:33 PM PDT 24
Peak memory 288824 kb
Host smart-e71696d5-2936-492a-a60d-73ba4eadca1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687032241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3687032241
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2014915072
Short name T378
Test name
Test status
Simulation time 1504308881 ps
CPU time 57.42 seconds
Started Aug 19 04:56:51 PM PDT 24
Finished Aug 19 04:57:49 PM PDT 24
Peak memory 249680 kb
Host smart-8ebf49a0-d5ae-4288-b1be-a1f030fe7101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20149
15072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2014915072
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4009914154
Short name T37
Test name
Test status
Simulation time 364911808 ps
CPU time 11.79 seconds
Started Aug 19 04:56:43 PM PDT 24
Finished Aug 19 04:56:55 PM PDT 24
Peak memory 248428 kb
Host smart-8659ac37-7721-4e6e-b7cf-87bcb2f8d480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40099
14154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4009914154
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1039518583
Short name T706
Test name
Test status
Simulation time 67401071294 ps
CPU time 1312.06 seconds
Started Aug 19 04:56:41 PM PDT 24
Finished Aug 19 05:18:33 PM PDT 24
Peak memory 285296 kb
Host smart-07ea4d48-6132-459d-b273-4d21f1411751
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039518583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1039518583
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1349083035
Short name T546
Test name
Test status
Simulation time 22355520822 ps
CPU time 1584.07 seconds
Started Aug 19 04:56:42 PM PDT 24
Finished Aug 19 05:23:06 PM PDT 24
Peak memory 273364 kb
Host smart-6b487238-c5cc-46a8-9666-c2141ce806d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349083035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1349083035
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1069720692
Short name T287
Test name
Test status
Simulation time 8881333276 ps
CPU time 362.56 seconds
Started Aug 19 04:56:51 PM PDT 24
Finished Aug 19 05:02:54 PM PDT 24
Peak memory 247664 kb
Host smart-9c6da7b8-fbe8-41a0-805d-0ba79bc25cf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069720692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1069720692
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4203050790
Short name T556
Test name
Test status
Simulation time 71596762 ps
CPU time 5.53 seconds
Started Aug 19 04:56:43 PM PDT 24
Finished Aug 19 04:56:49 PM PDT 24
Peak memory 240540 kb
Host smart-7c5471c8-8343-4315-a18b-055a123ae26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42030
50790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4203050790
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2589345058
Short name T46
Test name
Test status
Simulation time 5872498260 ps
CPU time 48.62 seconds
Started Aug 19 04:56:44 PM PDT 24
Finished Aug 19 04:57:33 PM PDT 24
Peak memory 257052 kb
Host smart-e01994ec-42f7-4e61-b5a2-1f21479fff1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25893
45058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2589345058
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.664765625
Short name T628
Test name
Test status
Simulation time 233599711 ps
CPU time 18.35 seconds
Started Aug 19 04:56:48 PM PDT 24
Finished Aug 19 04:57:06 PM PDT 24
Peak memory 249292 kb
Host smart-84b4b2e0-0225-4196-8ed6-9d484cc066c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66476
5625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.664765625
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2765153017
Short name T522
Test name
Test status
Simulation time 98700271 ps
CPU time 15.36 seconds
Started Aug 19 04:56:48 PM PDT 24
Finished Aug 19 04:57:04 PM PDT 24
Peak memory 256544 kb
Host smart-e8f86c7f-e9d2-4024-a5a2-56cdd3f98e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27651
53017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2765153017
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2963097704
Short name T647
Test name
Test status
Simulation time 10459641805 ps
CPU time 1482.26 seconds
Started Aug 19 04:56:50 PM PDT 24
Finished Aug 19 05:21:33 PM PDT 24
Peak memory 289624 kb
Host smart-bea4ac01-01b4-4bfd-a86c-c9ae148d84bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963097704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2963097704
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2508782348
Short name T643
Test name
Test status
Simulation time 7062415589 ps
CPU time 691 seconds
Started Aug 19 04:56:51 PM PDT 24
Finished Aug 19 05:08:22 PM PDT 24
Peak memory 265192 kb
Host smart-544bfadf-a9ee-4fca-84db-a009bfe23527
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508782348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2508782348
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2126527161
Short name T416
Test name
Test status
Simulation time 6417096356 ps
CPU time 132.39 seconds
Started Aug 19 04:56:48 PM PDT 24
Finished Aug 19 04:59:01 PM PDT 24
Peak memory 256328 kb
Host smart-917ddd5a-319a-4ac4-bec6-fea79be60b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21265
27161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2126527161
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.612902599
Short name T92
Test name
Test status
Simulation time 4975966984 ps
CPU time 79.92 seconds
Started Aug 19 04:56:47 PM PDT 24
Finished Aug 19 04:58:07 PM PDT 24
Peak memory 248628 kb
Host smart-c430eba8-1c97-4a3a-8903-86abc2e478a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61290
2599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.612902599
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.4002189982
Short name T344
Test name
Test status
Simulation time 10142953187 ps
CPU time 953.61 seconds
Started Aug 19 04:56:42 PM PDT 24
Finished Aug 19 05:12:36 PM PDT 24
Peak memory 272772 kb
Host smart-ee6975fd-1e69-4a8c-b14b-6291a4388af8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002189982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.4002189982
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2628364802
Short name T302
Test name
Test status
Simulation time 38049931306 ps
CPU time 1413.23 seconds
Started Aug 19 04:56:47 PM PDT 24
Finished Aug 19 05:20:21 PM PDT 24
Peak memory 273440 kb
Host smart-f6d5446b-5302-486c-8b2f-a4e4def3d6b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628364802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2628364802
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3458635276
Short name T222
Test name
Test status
Simulation time 8558263942 ps
CPU time 359.73 seconds
Started Aug 19 04:56:43 PM PDT 24
Finished Aug 19 05:02:42 PM PDT 24
Peak memory 256772 kb
Host smart-759001f4-2372-429f-b16d-d6be4b96b510
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458635276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3458635276
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1279724076
Short name T459
Test name
Test status
Simulation time 1126113863 ps
CPU time 42.95 seconds
Started Aug 19 04:56:47 PM PDT 24
Finished Aug 19 04:57:30 PM PDT 24
Peak memory 256748 kb
Host smart-71e3c659-2b49-4900-9cc5-cdaecd17eeda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12797
24076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1279724076
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3286896115
Short name T570
Test name
Test status
Simulation time 1809340776 ps
CPU time 53.02 seconds
Started Aug 19 04:56:47 PM PDT 24
Finished Aug 19 04:57:40 PM PDT 24
Peak memory 256932 kb
Host smart-54b83f10-9d6a-4be0-8f43-3dbee27cccca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32868
96115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3286896115
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3185298167
Short name T221
Test name
Test status
Simulation time 1494154817 ps
CPU time 49.53 seconds
Started Aug 19 04:56:43 PM PDT 24
Finished Aug 19 04:57:33 PM PDT 24
Peak memory 249836 kb
Host smart-be72d3ff-02ac-4fc9-a3a4-be2076f259a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31852
98167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3185298167
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3155783615
Short name T629
Test name
Test status
Simulation time 199972316 ps
CPU time 4.32 seconds
Started Aug 19 04:56:42 PM PDT 24
Finished Aug 19 04:56:46 PM PDT 24
Peak memory 250968 kb
Host smart-55c7796c-3170-487f-80d2-314f4e6237f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31557
83615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3155783615
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.288572062
Short name T255
Test name
Test status
Simulation time 167687581161 ps
CPU time 1529.56 seconds
Started Aug 19 04:56:42 PM PDT 24
Finished Aug 19 05:22:11 PM PDT 24
Peak memory 297420 kb
Host smart-24bf1e34-b1da-4335-94af-3d2c4439341f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288572062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.288572062
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.557760942
Short name T256
Test name
Test status
Simulation time 10434449699 ps
CPU time 274.19 seconds
Started Aug 19 04:56:44 PM PDT 24
Finished Aug 19 05:01:18 PM PDT 24
Peak memory 273528 kb
Host smart-216db5d7-86c3-41f6-b04b-2ac803ac95f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557760942 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.557760942
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.963550314
Short name T501
Test name
Test status
Simulation time 233103114560 ps
CPU time 3382.02 seconds
Started Aug 19 04:56:50 PM PDT 24
Finished Aug 19 05:53:12 PM PDT 24
Peak memory 289024 kb
Host smart-a97d50dd-c8d2-40fb-9192-d942212f26ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963550314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.963550314
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1666399640
Short name T633
Test name
Test status
Simulation time 1620288684 ps
CPU time 26.52 seconds
Started Aug 19 04:58:11 PM PDT 24
Finished Aug 19 04:58:37 PM PDT 24
Peak memory 256528 kb
Host smart-78557b23-aae5-43c1-8426-db6e5eb59b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16663
99640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1666399640
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3012797229
Short name T597
Test name
Test status
Simulation time 513782005 ps
CPU time 7.41 seconds
Started Aug 19 04:56:50 PM PDT 24
Finished Aug 19 04:56:58 PM PDT 24
Peak memory 250984 kb
Host smart-8fe6ffb5-2bf9-4f01-a0b0-daab2b0e3014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30127
97229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3012797229
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.4187807887
Short name T624
Test name
Test status
Simulation time 54059141638 ps
CPU time 1637.46 seconds
Started Aug 19 04:56:42 PM PDT 24
Finished Aug 19 05:23:59 PM PDT 24
Peak memory 272700 kb
Host smart-d0c10afd-292e-42cc-a5b2-81b3199cde06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187807887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.4187807887
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.424702649
Short name T499
Test name
Test status
Simulation time 36201003731 ps
CPU time 2283.36 seconds
Started Aug 19 04:56:42 PM PDT 24
Finished Aug 19 05:34:46 PM PDT 24
Peak memory 273400 kb
Host smart-d67e5d09-cdea-47f7-93dd-519029608040
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424702649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.424702649
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1888199955
Short name T603
Test name
Test status
Simulation time 49355445792 ps
CPU time 533.07 seconds
Started Aug 19 04:56:43 PM PDT 24
Finished Aug 19 05:05:37 PM PDT 24
Peak memory 255528 kb
Host smart-16f90348-36b1-4dbe-8a9a-2da0f6ec8912
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888199955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1888199955
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.363142016
Short name T611
Test name
Test status
Simulation time 11067256868 ps
CPU time 59.37 seconds
Started Aug 19 04:56:51 PM PDT 24
Finished Aug 19 04:57:50 PM PDT 24
Peak memory 257080 kb
Host smart-74b1fd7c-7c53-4464-bb6c-4c86b978a45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36314
2016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.363142016
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.374842334
Short name T423
Test name
Test status
Simulation time 1399730233 ps
CPU time 46.14 seconds
Started Aug 19 04:56:51 PM PDT 24
Finished Aug 19 04:57:38 PM PDT 24
Peak memory 256464 kb
Host smart-deabccc1-afc8-49fc-aefd-94ef7d1f4447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37484
2334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.374842334
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1901391355
Short name T259
Test name
Test status
Simulation time 1403710296 ps
CPU time 49.81 seconds
Started Aug 19 04:56:45 PM PDT 24
Finished Aug 19 04:57:35 PM PDT 24
Peak memory 248200 kb
Host smart-91826d77-2fe5-485d-9b71-3d7477d45ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19013
91355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1901391355
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.974915176
Short name T424
Test name
Test status
Simulation time 1045453823 ps
CPU time 33.84 seconds
Started Aug 19 04:56:50 PM PDT 24
Finished Aug 19 04:57:23 PM PDT 24
Peak memory 256968 kb
Host smart-d3d9b6da-b7d9-47bc-b088-4bc7b653ea8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97491
5176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.974915176
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.468751509
Short name T52
Test name
Test status
Simulation time 193348166 ps
CPU time 3.27 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 04:54:25 PM PDT 24
Peak memory 248916 kb
Host smart-ab4b3a9c-b273-480d-87cc-33a2845d9d47
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=468751509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.468751509
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1503640483
Short name T470
Test name
Test status
Simulation time 970747711 ps
CPU time 12.93 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 04:54:34 PM PDT 24
Peak memory 248812 kb
Host smart-e123c2c5-edb8-4e88-be3f-00fc41c3917d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1503640483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1503640483
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4015910900
Short name T310
Test name
Test status
Simulation time 2276715058 ps
CPU time 74.49 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:55:35 PM PDT 24
Peak memory 257028 kb
Host smart-755a0cc4-d483-4dc5-970d-ac8709204f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40159
10900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4015910900
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3610026658
Short name T267
Test name
Test status
Simulation time 1720165243 ps
CPU time 18.53 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:54:38 PM PDT 24
Peak memory 248316 kb
Host smart-6b61e21c-e35e-4bf2-bb1b-6ae96cc24b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36100
26658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3610026658
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3181512544
Short name T276
Test name
Test status
Simulation time 74819221525 ps
CPU time 2477.99 seconds
Started Aug 19 04:54:23 PM PDT 24
Finished Aug 19 05:35:42 PM PDT 24
Peak memory 281584 kb
Host smart-69f75c48-d66c-49bc-9720-826be57be48d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181512544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3181512544
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3726731505
Short name T107
Test name
Test status
Simulation time 158194016519 ps
CPU time 2466.18 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 05:35:36 PM PDT 24
Peak memory 289084 kb
Host smart-11dc59b1-cc4d-49bb-aac6-1ba8e4d40745
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726731505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3726731505
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.640715984
Short name T279
Test name
Test status
Simulation time 35168436617 ps
CPU time 365.32 seconds
Started Aug 19 04:54:19 PM PDT 24
Finished Aug 19 05:00:25 PM PDT 24
Peak memory 248856 kb
Host smart-105568ac-9048-4e7c-b822-8898be1d357b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640715984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.640715984
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3811986088
Short name T509
Test name
Test status
Simulation time 2218469463 ps
CPU time 36.54 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:54:57 PM PDT 24
Peak memory 257028 kb
Host smart-d642128a-0303-4b57-95e4-c58c675f36da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38119
86088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3811986088
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2428464715
Short name T588
Test name
Test status
Simulation time 267600245 ps
CPU time 15.35 seconds
Started Aug 19 04:54:19 PM PDT 24
Finished Aug 19 04:54:35 PM PDT 24
Peak memory 256992 kb
Host smart-b3ca42fe-2cf9-42d6-a859-585c12c23227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24284
64715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2428464715
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.76523510
Short name T422
Test name
Test status
Simulation time 4078557813 ps
CPU time 48.89 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 04:55:11 PM PDT 24
Peak memory 249456 kb
Host smart-529eac4f-0ff8-432a-bd1e-d412c0c79b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76523
510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.76523510
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1427717041
Short name T243
Test name
Test status
Simulation time 143425277 ps
CPU time 20.76 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:54:52 PM PDT 24
Peak memory 255088 kb
Host smart-d4b74705-be81-4201-95f8-f3baaa98ef15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14277
17041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1427717041
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2390549362
Short name T530
Test name
Test status
Simulation time 65726912735 ps
CPU time 1974.75 seconds
Started Aug 19 04:54:19 PM PDT 24
Finished Aug 19 05:27:14 PM PDT 24
Peak memory 303544 kb
Host smart-d134cb5a-b81c-4d4c-b61a-940489cccf03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390549362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2390549362
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3636758741
Short name T209
Test name
Test status
Simulation time 31853085 ps
CPU time 2.41 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:54:34 PM PDT 24
Peak memory 249000 kb
Host smart-e015e1d1-32cd-4bbf-b309-8b7f17974cda
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3636758741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3636758741
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2155433407
Short name T438
Test name
Test status
Simulation time 5101921833 ps
CPU time 578.7 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 05:04:00 PM PDT 24
Peak memory 273136 kb
Host smart-cbb40618-9955-4835-a45c-182b6a89e175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155433407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2155433407
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2707677645
Short name T461
Test name
Test status
Simulation time 1877022818 ps
CPU time 24.2 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:54:56 PM PDT 24
Peak memory 248788 kb
Host smart-a9309e47-c686-4fd5-a1ce-635bae619e0b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2707677645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2707677645
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.213151361
Short name T474
Test name
Test status
Simulation time 255602455 ps
CPU time 30.32 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 04:54:53 PM PDT 24
Peak memory 256400 kb
Host smart-75581d53-65c0-4205-834c-f97362e9a579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21315
1361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.213151361
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.530627474
Short name T478
Test name
Test status
Simulation time 921424302 ps
CPU time 52.28 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:55:23 PM PDT 24
Peak memory 255716 kb
Host smart-09b1be0c-6aa9-4089-99b4-d46a17f027ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53062
7474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.530627474
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3429097467
Short name T572
Test name
Test status
Simulation time 8997094959 ps
CPU time 990.48 seconds
Started Aug 19 04:54:28 PM PDT 24
Finished Aug 19 05:10:58 PM PDT 24
Peak memory 281648 kb
Host smart-bb2cf9a2-a4df-44cd-a185-2a7f6d837fbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429097467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3429097467
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.576441962
Short name T79
Test name
Test status
Simulation time 23469156491 ps
CPU time 259.95 seconds
Started Aug 19 04:54:18 PM PDT 24
Finished Aug 19 04:58:38 PM PDT 24
Peak memory 248684 kb
Host smart-704916ef-a9c1-411a-a9c4-b13de1569362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576441962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.576441962
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3741875386
Short name T642
Test name
Test status
Simulation time 264814434 ps
CPU time 19.76 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 04:54:41 PM PDT 24
Peak memory 256372 kb
Host smart-358275ce-a115-4602-8a92-0b12ce3451b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37418
75386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3741875386
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.523405243
Short name T39
Test name
Test status
Simulation time 58034927 ps
CPU time 3.11 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 04:54:24 PM PDT 24
Peak memory 240064 kb
Host smart-bcb37d69-ea17-4053-aff1-8efcb90007df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52340
5243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.523405243
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4244881177
Short name T517
Test name
Test status
Simulation time 794579447 ps
CPU time 48.32 seconds
Started Aug 19 04:54:24 PM PDT 24
Finished Aug 19 04:55:12 PM PDT 24
Peak memory 249132 kb
Host smart-34b55b10-f14f-45d6-907a-c141aa1a36f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42448
81177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4244881177
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3754612086
Short name T43
Test name
Test status
Simulation time 1430802089 ps
CPU time 49.87 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:55:20 PM PDT 24
Peak memory 256944 kb
Host smart-77f6f52b-19c9-42dd-ad6c-8205f954c407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37546
12086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3754612086
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.201388188
Short name T202
Test name
Test status
Simulation time 737285203 ps
CPU time 4.1 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:54:35 PM PDT 24
Peak memory 248796 kb
Host smart-7ccbaac4-6a99-4731-b0b2-d8c4cf1dfd38
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=201388188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.201388188
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.124892034
Short name T394
Test name
Test status
Simulation time 26084101119 ps
CPU time 1834.95 seconds
Started Aug 19 04:54:21 PM PDT 24
Finished Aug 19 05:24:56 PM PDT 24
Peak memory 273448 kb
Host smart-d158c9da-ae3d-4b2b-87c8-b53a92237919
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124892034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.124892034
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1430078855
Short name T685
Test name
Test status
Simulation time 1171692683 ps
CPU time 15.98 seconds
Started Aug 19 04:54:20 PM PDT 24
Finished Aug 19 04:54:36 PM PDT 24
Peak memory 248720 kb
Host smart-e3a6e9c7-4ae7-4c10-ad18-78767766dbd9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1430078855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1430078855
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1067581945
Short name T219
Test name
Test status
Simulation time 9098029897 ps
CPU time 137.44 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:56:48 PM PDT 24
Peak memory 256240 kb
Host smart-3ddcc8fa-f7b3-49c1-b538-6d13153f4aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10675
81945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1067581945
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.318206790
Short name T553
Test name
Test status
Simulation time 160747826 ps
CPU time 7.99 seconds
Started Aug 19 04:54:24 PM PDT 24
Finished Aug 19 04:54:32 PM PDT 24
Peak memory 248344 kb
Host smart-711ce31c-1014-4c79-a8da-8a0913e608fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31820
6790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.318206790
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3252451162
Short name T44
Test name
Test status
Simulation time 118440136617 ps
CPU time 1661.55 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 05:22:03 PM PDT 24
Peak memory 273376 kb
Host smart-4bb41e72-0735-46ed-8119-2b7ae71b2c6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252451162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3252451162
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.219996303
Short name T425
Test name
Test status
Simulation time 41074739911 ps
CPU time 2442.49 seconds
Started Aug 19 04:54:22 PM PDT 24
Finished Aug 19 05:35:05 PM PDT 24
Peak memory 281608 kb
Host smart-36dbe666-ab76-468d-a4af-77aa09f14523
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219996303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.219996303
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1071139575
Short name T305
Test name
Test status
Simulation time 226460935 ps
CPU time 7.58 seconds
Started Aug 19 04:54:29 PM PDT 24
Finished Aug 19 04:54:36 PM PDT 24
Peak memory 248720 kb
Host smart-96435e59-ea01-4a06-ae0e-2c75ce786b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10711
39575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1071139575
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1758129955
Short name T516
Test name
Test status
Simulation time 74018703 ps
CPU time 8.1 seconds
Started Aug 19 04:54:28 PM PDT 24
Finished Aug 19 04:54:36 PM PDT 24
Peak memory 253420 kb
Host smart-18c7730e-78b0-4e87-aaa8-d34aa208e85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17581
29955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1758129955
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3132194012
Short name T513
Test name
Test status
Simulation time 1742215978 ps
CPU time 32.44 seconds
Started Aug 19 04:54:29 PM PDT 24
Finished Aug 19 04:55:01 PM PDT 24
Peak memory 248824 kb
Host smart-0e2f1eca-a4c5-430e-8730-77d65fd78b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31321
94012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3132194012
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1133267440
Short name T528
Test name
Test status
Simulation time 620350946 ps
CPU time 38.02 seconds
Started Aug 19 04:54:28 PM PDT 24
Finished Aug 19 04:55:06 PM PDT 24
Peak memory 248812 kb
Host smart-b636ecd8-c320-4fbc-abce-742154a24b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11332
67440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1133267440
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1896975876
Short name T59
Test name
Test status
Simulation time 36011603405 ps
CPU time 2033.06 seconds
Started Aug 19 04:54:28 PM PDT 24
Finished Aug 19 05:28:22 PM PDT 24
Peak memory 281088 kb
Host smart-483d5ef2-113b-4e9e-849b-4abaaa27a192
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896975876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1896975876
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3331048099
Short name T212
Test name
Test status
Simulation time 212712430 ps
CPU time 3.41 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:54:33 PM PDT 24
Peak memory 249000 kb
Host smart-fd8b3310-327d-45a4-830d-a2b420b51108
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3331048099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3331048099
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.4185109396
Short name T441
Test name
Test status
Simulation time 37718610216 ps
CPU time 829.7 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 05:08:20 PM PDT 24
Peak memory 268328 kb
Host smart-391b18fc-3694-4b29-8d67-0a179aa863c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185109396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.4185109396
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3622702339
Short name T457
Test name
Test status
Simulation time 1167447050 ps
CPU time 13.04 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 04:54:45 PM PDT 24
Peak memory 248768 kb
Host smart-566f7640-31e1-47d9-a804-573de339d5b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3622702339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3622702339
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4073650514
Short name T465
Test name
Test status
Simulation time 1285601862 ps
CPU time 117.3 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 04:56:31 PM PDT 24
Peak memory 256920 kb
Host smart-683956e6-41f8-4e71-90aa-453ea8d459e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40736
50514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4073650514
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3360710766
Short name T476
Test name
Test status
Simulation time 693880918 ps
CPU time 20.09 seconds
Started Aug 19 04:54:40 PM PDT 24
Finished Aug 19 04:55:00 PM PDT 24
Peak memory 248432 kb
Host smart-2e32873d-c910-4d75-9d72-83f9fdce2dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33607
10766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3360710766
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2546581750
Short name T607
Test name
Test status
Simulation time 268461127100 ps
CPU time 2210.62 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 05:31:23 PM PDT 24
Peak memory 285552 kb
Host smart-d50911f3-e931-4fa3-a268-5871dc515676
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546581750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2546581750
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.830706202
Short name T214
Test name
Test status
Simulation time 197599577954 ps
CPU time 2474.78 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 05:35:48 PM PDT 24
Peak memory 281636 kb
Host smart-840e5761-bc52-44ec-90ef-c613ebac9d04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830706202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.830706202
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.557839427
Short name T490
Test name
Test status
Simulation time 463303572 ps
CPU time 28.74 seconds
Started Aug 19 04:54:29 PM PDT 24
Finished Aug 19 04:54:58 PM PDT 24
Peak memory 248772 kb
Host smart-d82e2069-b7c1-44d4-b823-d2752f219f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55783
9427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.557839427
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.95919219
Short name T453
Test name
Test status
Simulation time 1282722698 ps
CPU time 23.13 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 04:54:54 PM PDT 24
Peak memory 248780 kb
Host smart-3c47b0f5-b3b9-4871-9aab-f0fb908a50dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95919
219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.95919219
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1798958328
Short name T264
Test name
Test status
Simulation time 1185857184 ps
CPU time 70.39 seconds
Started Aug 19 04:54:28 PM PDT 24
Finished Aug 19 04:55:38 PM PDT 24
Peak memory 256308 kb
Host smart-fc47aeea-b8e4-4034-a983-c7227d7e5a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17989
58328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1798958328
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.964615883
Short name T504
Test name
Test status
Simulation time 3424463898 ps
CPU time 52.4 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 04:55:25 PM PDT 24
Peak memory 248860 kb
Host smart-45a68766-5fa3-461c-b849-52b8934f3ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96461
5883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.964615883
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.814064364
Short name T245
Test name
Test status
Simulation time 47865263256 ps
CPU time 936.58 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 05:10:07 PM PDT 24
Peak memory 271864 kb
Host smart-aa2c6095-28f5-4d5d-aac8-9c07781883c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814064364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.814064364
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.4054129630
Short name T87
Test name
Test status
Simulation time 8419528679 ps
CPU time 444.01 seconds
Started Aug 19 04:54:34 PM PDT 24
Finished Aug 19 05:01:58 PM PDT 24
Peak memory 271356 kb
Host smart-31847073-902c-4c3f-9f1c-ad9cbbdbd47e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054129630 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.4054129630
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1120034211
Short name T201
Test name
Test status
Simulation time 77165952 ps
CPU time 3.86 seconds
Started Aug 19 04:54:34 PM PDT 24
Finished Aug 19 04:54:38 PM PDT 24
Peak memory 248988 kb
Host smart-ee81883f-ac00-4bc7-bd98-f7f4ff95955c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1120034211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1120034211
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.992120085
Short name T601
Test name
Test status
Simulation time 435862610680 ps
CPU time 1903.68 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 05:26:17 PM PDT 24
Peak memory 273348 kb
Host smart-f6a1fb46-2764-4603-93bc-e008144f620b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992120085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.992120085
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2072794295
Short name T544
Test name
Test status
Simulation time 557637869 ps
CPU time 8.02 seconds
Started Aug 19 04:54:32 PM PDT 24
Finished Aug 19 04:54:41 PM PDT 24
Peak memory 248712 kb
Host smart-97c6badc-00ae-4ba6-a7a3-b3c100e208ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2072794295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2072794295
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.830464310
Short name T680
Test name
Test status
Simulation time 9562437686 ps
CPU time 117.56 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 04:56:31 PM PDT 24
Peak memory 257060 kb
Host smart-e41c8370-c12b-4d64-827f-41aec35690b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83046
4310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.830464310
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4261940260
Short name T217
Test name
Test status
Simulation time 324872222 ps
CPU time 10.09 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 04:54:40 PM PDT 24
Peak memory 256032 kb
Host smart-bd96f180-d473-488e-aec5-8a08a076fced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42619
40260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4261940260
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.585040171
Short name T324
Test name
Test status
Simulation time 77753528928 ps
CPU time 1365.2 seconds
Started Aug 19 04:54:41 PM PDT 24
Finished Aug 19 05:17:26 PM PDT 24
Peak memory 289532 kb
Host smart-43477e2c-32cd-4778-81a6-a8bcc0925941
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585040171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.585040171
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2359561942
Short name T238
Test name
Test status
Simulation time 25091446386 ps
CPU time 1604.75 seconds
Started Aug 19 04:54:30 PM PDT 24
Finished Aug 19 05:21:15 PM PDT 24
Peak memory 283156 kb
Host smart-f2c2be84-7b86-4bf6-bb70-2c9426f0bfb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359561942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2359561942
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3856584943
Short name T658
Test name
Test status
Simulation time 8418501860 ps
CPU time 339.06 seconds
Started Aug 19 04:54:29 PM PDT 24
Finished Aug 19 05:00:08 PM PDT 24
Peak memory 248816 kb
Host smart-ac3f80a5-80b1-4c00-9610-8675106adfa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856584943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3856584943
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1619533548
Short name T442
Test name
Test status
Simulation time 2331200203 ps
CPU time 71.15 seconds
Started Aug 19 04:54:40 PM PDT 24
Finished Aug 19 04:55:51 PM PDT 24
Peak memory 256752 kb
Host smart-34cb9cac-b85f-4331-add3-6a6b7c2ddf2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16195
33548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1619533548
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.725127756
Short name T429
Test name
Test status
Simulation time 1894676702 ps
CPU time 25.25 seconds
Started Aug 19 04:54:39 PM PDT 24
Finished Aug 19 04:55:05 PM PDT 24
Peak memory 248432 kb
Host smart-b1d47579-6e2e-4450-93d6-db0cae305368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72512
7756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.725127756
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1182067583
Short name T471
Test name
Test status
Simulation time 1558101661 ps
CPU time 26.32 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 04:54:59 PM PDT 24
Peak memory 248796 kb
Host smart-119bd222-b819-40ae-acfd-1637445b3887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11820
67583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1182067583
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1655005375
Short name T566
Test name
Test status
Simulation time 1055778877 ps
CPU time 33.82 seconds
Started Aug 19 04:54:33 PM PDT 24
Finished Aug 19 04:55:07 PM PDT 24
Peak memory 256336 kb
Host smart-fd296cc1-9fbc-47eb-bdfc-f9b31452a588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16550
05375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1655005375
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.437171426
Short name T430
Test name
Test status
Simulation time 5060053235 ps
CPU time 422.14 seconds
Started Aug 19 04:54:31 PM PDT 24
Finished Aug 19 05:01:33 PM PDT 24
Peak memory 265276 kb
Host smart-a0966b20-11b1-4cb4-9c04-9058f507ede8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437171426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.437171426
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1396173240
Short name T693
Test name
Test status
Simulation time 10241100195 ps
CPU time 338.57 seconds
Started Aug 19 04:54:40 PM PDT 24
Finished Aug 19 05:00:19 PM PDT 24
Peak memory 269052 kb
Host smart-829b3367-4b0b-4d38-b8d5-7d04a2744abc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396173240 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1396173240
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%