Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	34774	1			T27	3		T18	6		T63	94
class_i[0x1]	39255	1			T60	22		T61	950		T19	1
class_i[0x2]	43500	1			T60	6		T18	3		T19	1
class_i[0x3]	54182	1			T27	9		T121	1106		T19	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	45907	1			T27	1		T60	10		T61	478
alert[0x1]	42091	1			T27	3		T60	10		T18	1
alert[0x2]	41256	1			T60	6		T61	472		T18	3
alert[0x3]	42457	1			T27	8		T60	2		T63	20

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

171430

1

T27

12

T60

28

T61

950

esc_ping_fail

281

1

T18

4

T19

2

T20

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	45825	1			T27	1		T60	10		T61	478
esc_integrity_fail	alert[0x1]	42019	1			T27	3		T60	10		T63	16
esc_integrity_fail	alert[0x2]	41195	1			T60	6		T61	472		T18	2
esc_integrity_fail	alert[0x3]	42391	1			T27	8		T60	2		T63	20
esc_ping_fail	alert[0x0]	82	1			T18	2		T19	2		T20	1
esc_ping_fail	alert[0x1]	72	1			T18	1		T20	1		T344	3
esc_ping_fail	alert[0x2]	61	1			T18	1		T228	1		T344	2
esc_ping_fail	alert[0x3]	66	1			T228	1		T344	1		T342	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	34686	1			T27	3		T18	5		T63	94
esc_integrity_fail	class_i[0x1]	39200	1			T60	22		T61	950		T64	15
esc_integrity_fail	class_i[0x2]	43437	1			T60	6		T146	81		T81	12
esc_integrity_fail	class_i[0x3]	54107	1			T27	9		T121	1106		T19	2
esc_ping_fail	class_i[0x0]	88	1			T18	1		T342	1		T343	8
esc_ping_fail	class_i[0x1]	55	1			T19	1		T20	1		T342	1
esc_ping_fail	class_i[0x2]	63	1			T18	3		T19	1		T20	1
esc_ping_fail	class_i[0x3]	75	1			T228	2		T344	7		T345	1