Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	60	1			T77	1		T99	1		T38	1
class_index[0x1]	47	1			T15	1		T16	1		T95	1
class_index[0x2]	57	1			T27	1		T61	2		T63	2
class_index[0x3]	42	1			T93	1		T88	1		T46	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	86	1			T15	1		T16	1		T77	1
intr_timeout_cnt[1]	42	1			T93	1		T95	1		T100	1
intr_timeout_cnt[2]	23	1			T88	1		T146	1		T81	1
intr_timeout_cnt[3]	11	1			T46	1		T67	1		T147	1
intr_timeout_cnt[4]	13	1			T100	1		T102	1		T113	1
intr_timeout_cnt[5]	5	1			T71	1		T43	1		T286	1
intr_timeout_cnt[6]	10	1			T27	1		T64	2		T105	1
intr_timeout_cnt[7]	7	1			T61	1		T40	1		T102	1
intr_timeout_cnt[8]	6	1			T63	2		T287	1		T288	1
intr_timeout_cnt[9]	3	1			T289	2		T290	1		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	25	1			T77	1		T99	1		T38	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T100	1		T66	2		T101	2
class_index[0x0]	intr_timeout_cnt[2]	6	1			T107	1		T74	1		T291	2
class_index[0x0]	intr_timeout_cnt[3]	3	1			T74	1		T110	1		T285	1
class_index[0x0]	intr_timeout_cnt[4]	7	1			T110	3		T292	1		T48	3
class_index[0x0]	intr_timeout_cnt[5]	1	1			T43	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T105	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T102	1		T136	1		T293	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T289	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	16	1			T15	1		T16	1		T89	2
class_index[0x1]	intr_timeout_cnt[1]	13	1			T95	1		T40	2		T103	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T263	1		T288	1		T285	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T104	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T113	1		T294	1		T285	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T71	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T64	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T40	1		T110	2		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T295	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T290	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	27	1			T61	1		T71	2		T74	1
class_index[0x2]	intr_timeout_cnt[1]	6	1			T296	1		T113	1		T130	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T146	1		T81	1		T101	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T67	1		T147	1		T71	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T100	1		T102	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	5	1			T27	1		T297	1		T298	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T61	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	4	1			T63	2		T288	1		T299	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T289	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	18	1			T158	1		T144	1		T101	1
class_index[0x3]	intr_timeout_cnt[1]	10	1			T93	1		T101	1		T289	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T88	1		T263	1		T43	2
class_index[0x3]	intr_timeout_cnt[3]	3	1			T46	1		T74	1		T293	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T300	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	3	1			T286	1		T136	2		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T113	1		T301	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T287	1		-	-		-	-