Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	246761	1			T1	3		T3	5		T10	13
all_values[1]	246761	1			T1	3		T3	5		T10	13
all_values[2]	246761	1			T1	3		T3	5		T10	13
all_values[3]	246761	1			T1	3		T3	5		T10	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

490328

1

T1

6

T3

7

T10

34

auto[1]

496716

1

T1

6

T3

13

T10

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

589236

1

T1

11

T3

18

T10

28

auto[1]

397808

1

T1

1

T3

2

T10

24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	70927	1			T10	6		T11	15		T13	5
all_values[0]	auto[0]	auto[1]	51620	1			T10	5		T13	4		T17	11
all_values[0]	auto[1]	auto[0]	72405	1			T1	2		T3	3		T10	1
all_values[0]	auto[1]	auto[1]	51809	1			T1	1		T3	2		T10	1
all_values[1]	auto[0]	auto[0]	72296	1			T1	3		T10	4		T11	15
all_values[1]	auto[0]	auto[1]	49951	1			T10	3		T13	5		T17	7
all_values[1]	auto[1]	auto[0]	74065	1			T3	5		T10	3		T11	14
all_values[1]	auto[1]	auto[1]	50449	1			T10	3		T13	4		T17	10
all_values[2]	auto[0]	auto[0]	74088	1			T3	5		T10	3		T11	14
all_values[2]	auto[0]	auto[1]	48681	1			T10	3		T13	4		T17	9
all_values[2]	auto[1]	auto[0]	75288	1			T1	3		T10	4		T11	15
all_values[2]	auto[1]	auto[1]	48704	1			T10	3		T13	5		T17	6
all_values[3]	auto[0]	auto[0]	74597	1			T1	3		T3	2		T10	5
all_values[3]	auto[0]	auto[1]	48168	1			T10	5		T13	4		T17	6
all_values[3]	auto[1]	auto[0]	75570	1			T3	3		T10	2		T11	14
all_values[3]	auto[1]	auto[1]	48426	1			T10	1		T13	5		T17	11